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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.48


Total test records in report: 1320
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T1253 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4293165327 Sep 01 06:58:14 AM UTC 24 Sep 01 06:58:16 AM UTC 24 65973232 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.1274806953 Sep 01 06:58:13 AM UTC 24 Sep 01 06:58:16 AM UTC 24 97613382 ps
T1254 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.2575848649 Sep 01 06:58:13 AM UTC 24 Sep 01 06:58:18 AM UTC 24 477211328 ps
T1255 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3542746066 Sep 01 06:58:14 AM UTC 24 Sep 01 06:58:18 AM UTC 24 252063047 ps
T1256 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1404727363 Sep 01 06:58:14 AM UTC 24 Sep 01 06:58:18 AM UTC 24 105842510 ps
T1257 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.3542167340 Sep 01 06:58:17 AM UTC 24 Sep 01 06:58:19 AM UTC 24 15335807 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3537868975 Sep 01 06:58:17 AM UTC 24 Sep 01 06:58:19 AM UTC 24 15008596 ps
T1258 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3797572664 Sep 01 06:58:17 AM UTC 24 Sep 01 06:58:19 AM UTC 24 49463396 ps
T1259 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2675028566 Sep 01 06:58:17 AM UTC 24 Sep 01 06:58:19 AM UTC 24 114004814 ps
T1260 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.4210167851 Sep 01 06:58:17 AM UTC 24 Sep 01 06:58:19 AM UTC 24 50995706 ps
T1261 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.482090392 Sep 01 06:58:18 AM UTC 24 Sep 01 06:58:19 AM UTC 24 13844714 ps
T1262 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1279343790 Sep 01 06:58:17 AM UTC 24 Sep 01 06:58:19 AM UTC 24 108507898 ps
T1263 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2825735118 Sep 01 06:58:18 AM UTC 24 Sep 01 06:58:20 AM UTC 24 18242558 ps
T1264 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3162938627 Sep 01 06:58:17 AM UTC 24 Sep 01 06:58:20 AM UTC 24 478410893 ps
T1265 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.2098570250 Sep 01 06:58:17 AM UTC 24 Sep 01 06:58:20 AM UTC 24 200212858 ps
T1266 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.2527002688 Sep 01 06:58:17 AM UTC 24 Sep 01 06:58:20 AM UTC 24 113964543 ps
T1267 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.323689503 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:24 AM UTC 24 115745268 ps
T1268 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.561460492 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:24 AM UTC 24 14265949 ps
T1269 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1942147687 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:24 AM UTC 24 43869658 ps
T1270 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2886967053 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:24 AM UTC 24 46931223 ps
T1271 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.19736248 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:24 AM UTC 24 78691983 ps
T1272 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.3487519921 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:24 AM UTC 24 52894768 ps
T1273 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.739208830 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:24 AM UTC 24 54848301 ps
T1274 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3434070958 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:24 AM UTC 24 41115354 ps
T1275 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2574640773 Sep 01 06:58:23 AM UTC 24 Sep 01 06:58:24 AM UTC 24 22027207 ps
T1276 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.4182530515 Sep 01 06:58:23 AM UTC 24 Sep 01 06:58:25 AM UTC 24 29766705 ps
T1277 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2268087878 Sep 01 06:58:23 AM UTC 24 Sep 01 06:58:25 AM UTC 24 20517544 ps
T1278 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3835272398 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:25 AM UTC 24 82013861 ps
T1279 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.302069343 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:25 AM UTC 24 68144336 ps
T1280 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.359844743 Sep 01 06:58:23 AM UTC 24 Sep 01 06:58:25 AM UTC 24 136154591 ps
T1281 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3173499121 Sep 01 06:58:23 AM UTC 24 Sep 01 06:58:25 AM UTC 24 16777636 ps
T1282 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1956078459 Sep 01 06:58:23 AM UTC 24 Sep 01 06:58:25 AM UTC 24 120446799 ps
T1283 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.639980650 Sep 01 06:58:23 AM UTC 24 Sep 01 06:58:26 AM UTC 24 233833129 ps
T1284 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.315874872 Sep 01 06:58:23 AM UTC 24 Sep 01 06:58:26 AM UTC 24 41958103 ps
T1285 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.950560976 Sep 01 06:58:22 AM UTC 24 Sep 01 06:58:27 AM UTC 24 344770145 ps
T1286 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.4023966797 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:28 AM UTC 24 80399270 ps
T1287 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.609920181 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 44894476 ps
T1288 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1930580563 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 25786985 ps
T1289 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2655071479 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 12368181 ps
T1290 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.3222246515 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 37537742 ps
T1291 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1089436167 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 29142166 ps
T1292 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2686401140 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 23469458 ps
T1293 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2319784604 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 23118158 ps
T1294 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.181002257 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 14411144 ps
T1295 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1858084999 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 15537004 ps
T1296 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.2282456420 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 37114801 ps
T1297 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2573373650 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 51767334 ps
T1298 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.4180268347 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 32049687 ps
T1299 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.108868169 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 64201508 ps
T1300 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2665794891 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 32027737 ps
T1301 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2610057222 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 46957633 ps
T1302 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.4286080791 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 28078123 ps
T1303 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.1583699475 Sep 01 06:58:27 AM UTC 24 Sep 01 06:58:29 AM UTC 24 108880721 ps
T1304 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3379110313 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 46628721 ps
T1305 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.358081572 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 25138055 ps
T1306 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2101346424 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 59926956 ps
T1307 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.2844565076 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 33722342 ps
T1308 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2245901431 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 17731054 ps
T1309 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1204134415 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 20510173 ps
T1310 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.183079951 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 108549637 ps
T1311 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2683464999 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 27748097 ps
T1312 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.90041994 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 56401747 ps
T1313 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1319484684 Sep 01 06:58:32 AM UTC 24 Sep 01 06:58:34 AM UTC 24 12363308 ps
T1314 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1707884908 Sep 01 06:58:33 AM UTC 24 Sep 01 06:58:34 AM UTC 24 36069919 ps
T1315 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.683994518 Sep 01 06:58:33 AM UTC 24 Sep 01 06:58:35 AM UTC 24 42415355 ps
T1316 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.4008632972 Sep 01 06:58:33 AM UTC 24 Sep 01 06:58:35 AM UTC 24 37194851 ps
T1317 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1485034482 Sep 01 06:58:33 AM UTC 24 Sep 01 06:58:35 AM UTC 24 187932211 ps
T1318 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2562416218 Sep 01 06:58:33 AM UTC 24 Sep 01 06:58:35 AM UTC 24 52571419 ps
T1319 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.951342891 Sep 01 06:58:33 AM UTC 24 Sep 01 06:58:35 AM UTC 24 20980921 ps
T1320 /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3690460524 Sep 01 06:58:33 AM UTC 24 Sep 01 06:58:35 AM UTC 24 51252964 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.421972816
Short name T4
Test name
Test status
Simulation time 642906500 ps
CPU time 2.73 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:25:19 AM UTC 24
Peak memory 204772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421972816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.421972816
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1372453501
Short name T11
Test name
Test status
Simulation time 4082595558 ps
CPU time 10.31 seconds
Started Sep 01 06:25:17 AM UTC 24
Finished Sep 01 06:25:28 AM UTC 24
Peak memory 217612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1372453501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_
with_rand_reset.1372453501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_stress_all.1927318818
Short name T23
Test name
Test status
Simulation time 122555881007 ps
CPU time 123.92 seconds
Started Sep 01 06:25:17 AM UTC 24
Finished Sep 01 06:27:23 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927318818 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1927318818
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_tx_rx.1979899070
Short name T32
Test name
Test status
Simulation time 74426112511 ps
CPU time 45.36 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:26:02 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979899070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.1979899070
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.2831719956
Short name T273
Test name
Test status
Simulation time 79109640205 ps
CPU time 219.93 seconds
Started Sep 01 06:25:27 AM UTC 24
Finished Sep 01 06:29:11 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831719956 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2831719956
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_stress_all.977487993
Short name T318
Test name
Test status
Simulation time 98714839314 ps
CPU time 204.93 seconds
Started Sep 01 06:25:28 AM UTC 24
Finished Sep 01 06:28:56 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977487993 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.977487993
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.2603342056
Short name T29
Test name
Test status
Simulation time 67704561835 ps
CPU time 56.49 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:26:13 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603342056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2603342056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_stress_all.1906245753
Short name T120
Test name
Test status
Simulation time 237319408749 ps
CPU time 125.9 seconds
Started Sep 01 06:27:20 AM UTC 24
Finished Sep 01 06:29:28 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906245753 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1906245753
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.1757286973
Short name T286
Test name
Test status
Simulation time 98097681312 ps
CPU time 270.5 seconds
Started Sep 01 06:26:51 AM UTC 24
Finished Sep 01 06:31:25 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757286973 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1757286973
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_fifo_full.1763768840
Short name T287
Test name
Test status
Simulation time 175178403202 ps
CPU time 102.91 seconds
Started Sep 01 06:26:55 AM UTC 24
Finished Sep 01 06:28:40 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763768840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1763768840
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3200570953
Short name T16
Test name
Test status
Simulation time 2366578755 ps
CPU time 3.98 seconds
Started Sep 01 06:25:23 AM UTC 24
Finished Sep 01 06:25:29 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200570953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3200570953
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_stress_all.3045193537
Short name T272
Test name
Test status
Simulation time 72104617775 ps
CPU time 173.42 seconds
Started Sep 01 06:25:41 AM UTC 24
Finished Sep 01 06:28:37 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045193537 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.3045193537
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_stress_all.4094163417
Short name T180
Test name
Test status
Simulation time 186479171728 ps
CPU time 145.76 seconds
Started Sep 01 06:29:07 AM UTC 24
Finished Sep 01 06:31:35 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094163417 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.4094163417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_sec_cm.3256444420
Short name T2
Test name
Test status
Simulation time 179655791 ps
CPU time 1.04 seconds
Started Sep 01 06:25:17 AM UTC 24
Finished Sep 01 06:25:19 AM UTC 24
Peak memory 240032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256444420 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3256444420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_perf.1415977901
Short name T356
Test name
Test status
Simulation time 22099654701 ps
CPU time 87.78 seconds
Started Sep 01 06:31:23 AM UTC 24
Finished Sep 01 06:32:53 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415977901 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1415977901
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_fifo_full.2397630661
Short name T111
Test name
Test status
Simulation time 263364428359 ps
CPU time 138.76 seconds
Started Sep 01 06:26:01 AM UTC 24
Finished Sep 01 06:28:22 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397630661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.2397630661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.3317730071
Short name T38
Test name
Test status
Simulation time 9464477125 ps
CPU time 40.21 seconds
Started Sep 01 06:26:32 AM UTC 24
Finished Sep 01 06:27:13 AM UTC 24
Peak memory 217844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3317730071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_
with_rand_reset.3317730071
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.3479188937
Short name T53
Test name
Test status
Simulation time 18406240 ps
CPU time 1.16 seconds
Started Sep 01 06:57:42 AM UTC 24
Finished Sep 01 06:57:44 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479188937 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3479188937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_stress_all.3966509334
Short name T197
Test name
Test status
Simulation time 373827535620 ps
CPU time 697.53 seconds
Started Sep 01 06:25:19 AM UTC 24
Finished Sep 01 06:37:05 AM UTC 24
Peak memory 222692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966509334 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3966509334
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_fifo_reset.1332973899
Short name T119
Test name
Test status
Simulation time 175021176834 ps
CPU time 146.56 seconds
Started Sep 01 06:26:59 AM UTC 24
Finished Sep 01 06:29:28 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332973899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1332973899
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_fifo_reset.3312184541
Short name T94
Test name
Test status
Simulation time 175622915537 ps
CPU time 49.71 seconds
Started Sep 01 06:26:03 AM UTC 24
Finished Sep 01 06:26:54 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312184541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3312184541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_perf.299739496
Short name T298
Test name
Test status
Simulation time 18525358511 ps
CPU time 298.28 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:30:21 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299739496 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.299739496
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.3921385661
Short name T145
Test name
Test status
Simulation time 83954600712 ps
CPU time 71.75 seconds
Started Sep 01 06:25:38 AM UTC 24
Finished Sep 01 06:26:51 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921385661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3921385661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_stress_all.1492231088
Short name T548
Test name
Test status
Simulation time 120903283013 ps
CPU time 519.8 seconds
Started Sep 01 06:25:54 AM UTC 24
Finished Sep 01 06:34:41 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492231088 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.1492231088
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.860584855
Short name T98
Test name
Test status
Simulation time 21964754784 ps
CPU time 7.77 seconds
Started Sep 01 06:30:47 AM UTC 24
Finished Sep 01 06:30:56 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860584855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.860584855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_intr.1056025594
Short name T92
Test name
Test status
Simulation time 53124332489 ps
CPU time 62.72 seconds
Started Sep 01 06:25:35 AM UTC 24
Finished Sep 01 06:26:40 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056025594 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1056025594
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.620742986
Short name T81
Test name
Test status
Simulation time 92961228 ps
CPU time 2.11 seconds
Started Sep 01 06:57:58 AM UTC 24
Finished Sep 01 06:58:01 AM UTC 24
Peak memory 202880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620742986 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.620742986
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.2074530611
Short name T268
Test name
Test status
Simulation time 202178741631 ps
CPU time 440.45 seconds
Started Sep 01 06:25:32 AM UTC 24
Finished Sep 01 06:32:58 AM UTC 24
Peak memory 212152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074530611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.2074530611
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_fifo_reset.876090100
Short name T30
Test name
Test status
Simulation time 109461882342 ps
CPU time 25.21 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:25:45 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876090100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.876090100
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_stress_all.3706861858
Short name T156
Test name
Test status
Simulation time 254202650426 ps
CPU time 464.69 seconds
Started Sep 01 06:28:37 AM UTC 24
Finished Sep 01 06:36:28 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706861858 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3706861858
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_alert_test.46211913
Short name T1
Test name
Test status
Simulation time 33769138 ps
CPU time 0.79 seconds
Started Sep 01 06:25:17 AM UTC 24
Finished Sep 01 06:25:18 AM UTC 24
Peak memory 204492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46211913 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.46211913
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_fifo_full.2527956476
Short name T274
Test name
Test status
Simulation time 57446290233 ps
CPU time 130.8 seconds
Started Sep 01 06:25:17 AM UTC 24
Finished Sep 01 06:27:30 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527956476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2527956476
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.2682141363
Short name T130
Test name
Test status
Simulation time 131812216842 ps
CPU time 292.94 seconds
Started Sep 01 06:28:57 AM UTC 24
Finished Sep 01 06:33:54 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682141363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2682141363
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.917190019
Short name T283
Test name
Test status
Simulation time 118335987836 ps
CPU time 130.46 seconds
Started Sep 01 06:25:21 AM UTC 24
Finished Sep 01 06:27:34 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917190019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.917190019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.604689754
Short name T137
Test name
Test status
Simulation time 11603253483 ps
CPU time 19.18 seconds
Started Sep 01 06:26:48 AM UTC 24
Finished Sep 01 06:27:08 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604689754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.604689754
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_fifo_full.1957459375
Short name T264
Test name
Test status
Simulation time 61765093926 ps
CPU time 94.1 seconds
Started Sep 01 06:25:43 AM UTC 24
Finished Sep 01 06:27:19 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957459375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1957459375
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.3625100470
Short name T161
Test name
Test status
Simulation time 101188816092 ps
CPU time 211.74 seconds
Started Sep 01 06:26:42 AM UTC 24
Finished Sep 01 06:30:17 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625100470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3625100470
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_stress_all.2044118709
Short name T115
Test name
Test status
Simulation time 487663572845 ps
CPU time 474.67 seconds
Started Sep 01 06:26:15 AM UTC 24
Finished Sep 01 06:34:15 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044118709 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2044118709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.991278050
Short name T66
Test name
Test status
Simulation time 24306626 ps
CPU time 0.99 seconds
Started Sep 01 06:57:42 AM UTC 24
Finished Sep 01 06:57:44 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991278050 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.991278050
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.3386327532
Short name T100
Test name
Test status
Simulation time 4758754262 ps
CPU time 61.61 seconds
Started Sep 01 06:29:29 AM UTC 24
Finished Sep 01 06:30:32 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3386327532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all
_with_rand_reset.3386327532
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_fifo_full.22346652
Short name T385
Test name
Test status
Simulation time 94584530504 ps
CPU time 112.14 seconds
Started Sep 01 06:37:12 AM UTC 24
Finished Sep 01 06:39:07 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22346652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.22346652
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_fifo_reset.279003359
Short name T177
Test name
Test status
Simulation time 46445504746 ps
CPU time 35.15 seconds
Started Sep 01 06:27:24 AM UTC 24
Finished Sep 01 06:28:01 AM UTC 24
Peak memory 208948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279003359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.279003359
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3036893322
Short name T76
Test name
Test status
Simulation time 140526496 ps
CPU time 1.43 seconds
Started Sep 01 06:57:39 AM UTC 24
Finished Sep 01 06:57:41 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036893322 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3036893322
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.3398867335
Short name T105
Test name
Test status
Simulation time 26698955362 ps
CPU time 100.87 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:27:01 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398867335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3398867335
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_fifo_reset.211500983
Short name T150
Test name
Test status
Simulation time 18084400515 ps
CPU time 25.1 seconds
Started Sep 01 06:30:40 AM UTC 24
Finished Sep 01 06:31:07 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211500983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.211500983
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.531514956
Short name T113
Test name
Test status
Simulation time 55230470632 ps
CPU time 88.14 seconds
Started Sep 01 06:26:25 AM UTC 24
Finished Sep 01 06:27:56 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531514956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.531514956
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_tx_rx.2650217765
Short name T269
Test name
Test status
Simulation time 102279911488 ps
CPU time 70.33 seconds
Started Sep 01 06:31:57 AM UTC 24
Finished Sep 01 06:33:09 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650217765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2650217765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_intr.1418832722
Short name T22
Test name
Test status
Simulation time 59754501362 ps
CPU time 38.04 seconds
Started Sep 01 06:26:21 AM UTC 24
Finished Sep 01 06:27:00 AM UTC 24
Peak memory 208480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418832722 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1418832722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.954790400
Short name T369
Test name
Test status
Simulation time 280021626926 ps
CPU time 46.11 seconds
Started Sep 01 06:30:38 AM UTC 24
Finished Sep 01 06:31:26 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954790400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.954790400
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_fifo_full.1419516226
Short name T142
Test name
Test status
Simulation time 260454639140 ps
CPU time 57.12 seconds
Started Sep 01 06:34:35 AM UTC 24
Finished Sep 01 06:35:34 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419516226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1419516226
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_fifo_full.2963896984
Short name T128
Test name
Test status
Simulation time 154080638661 ps
CPU time 73.87 seconds
Started Sep 01 06:31:03 AM UTC 24
Finished Sep 01 06:32:18 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963896984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.2963896984
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_stress_all.2748706765
Short name T172
Test name
Test status
Simulation time 491693502154 ps
CPU time 368.98 seconds
Started Sep 01 06:44:11 AM UTC 24
Finished Sep 01 06:50:25 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748706765 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2748706765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_stress_all.2706208178
Short name T259
Test name
Test status
Simulation time 180972588950 ps
CPU time 96.88 seconds
Started Sep 01 06:30:58 AM UTC 24
Finished Sep 01 06:32:37 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706208178 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2706208178
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/211.uart_fifo_reset.3481103870
Short name T167
Test name
Test status
Simulation time 99786066429 ps
CPU time 369.2 seconds
Started Sep 01 06:54:51 AM UTC 24
Finished Sep 01 07:01:05 AM UTC 24
Peak memory 208296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481103870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3481103870
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/211.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_fifo_reset.2413298988
Short name T158
Test name
Test status
Simulation time 62268468500 ps
CPU time 99.06 seconds
Started Sep 01 06:33:35 AM UTC 24
Finished Sep 01 06:35:17 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413298988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2413298988
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.3002418153
Short name T41
Test name
Test status
Simulation time 7486994403 ps
CPU time 31.48 seconds
Started Sep 01 06:27:51 AM UTC 24
Finished Sep 01 06:28:24 AM UTC 24
Peak memory 217792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3002418153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all
_with_rand_reset.3002418153
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/169.uart_fifo_reset.34609469
Short name T256
Test name
Test status
Simulation time 84359555037 ps
CPU time 250.83 seconds
Started Sep 01 06:53:27 AM UTC 24
Finished Sep 01 06:57:42 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34609469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.34609469
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/169.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.2764243051
Short name T140
Test name
Test status
Simulation time 18617514528 ps
CPU time 36.32 seconds
Started Sep 01 06:32:54 AM UTC 24
Finished Sep 01 06:33:31 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764243051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2764243051
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2476444665
Short name T1162
Test name
Test status
Simulation time 73810835095 ps
CPU time 143.06 seconds
Started Sep 01 06:56:50 AM UTC 24
Finished Sep 01 06:59:16 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476444665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2476444665
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/273.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_fifo_full.520575614
Short name T168
Test name
Test status
Simulation time 114200750996 ps
CPU time 44.44 seconds
Started Sep 01 06:36:42 AM UTC 24
Finished Sep 01 06:37:29 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520575614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.520575614
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_intr.1258424095
Short name T392
Test name
Test status
Simulation time 20833698068 ps
CPU time 46.87 seconds
Started Sep 01 06:27:35 AM UTC 24
Finished Sep 01 06:28:23 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258424095 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1258424095
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_fifo_reset.2503934086
Short name T179
Test name
Test status
Simulation time 39814012205 ps
CPU time 64.75 seconds
Started Sep 01 06:39:04 AM UTC 24
Finished Sep 01 06:40:10 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503934086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2503934086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_tx_rx.712832295
Short name T281
Test name
Test status
Simulation time 57929859238 ps
CPU time 88.51 seconds
Started Sep 01 06:25:17 AM UTC 24
Finished Sep 01 06:26:47 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712832295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.712832295
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_fifo_reset.2021321836
Short name T121
Test name
Test status
Simulation time 43238362491 ps
CPU time 54.99 seconds
Started Sep 01 06:28:01 AM UTC 24
Finished Sep 01 06:28:57 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021321836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2021321836
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.2592624760
Short name T406
Test name
Test status
Simulation time 2117407972 ps
CPU time 34.85 seconds
Started Sep 01 06:28:37 AM UTC 24
Finished Sep 01 06:29:13 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2592624760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all
_with_rand_reset.2592624760
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/120.uart_fifo_reset.3528923338
Short name T1032
Test name
Test status
Simulation time 23914668426 ps
CPU time 41.65 seconds
Started Sep 01 06:52:13 AM UTC 24
Finished Sep 01 06:52:56 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528923338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3528923338
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/120.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3376552767
Short name T214
Test name
Test status
Simulation time 178773894299 ps
CPU time 30.2 seconds
Started Sep 01 06:52:21 AM UTC 24
Finished Sep 01 06:52:53 AM UTC 24
Peak memory 208588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376552767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3376552767
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/125.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.342932886
Short name T307
Test name
Test status
Simulation time 61116919519 ps
CPU time 106.68 seconds
Started Sep 01 06:28:41 AM UTC 24
Finished Sep 01 06:30:29 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342932886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.342932886
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/152.uart_fifo_reset.3804654236
Short name T248
Test name
Test status
Simulation time 77794544777 ps
CPU time 90.3 seconds
Started Sep 01 06:52:59 AM UTC 24
Finished Sep 01 06:54:31 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804654236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3804654236
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/152.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2632951038
Short name T212
Test name
Test status
Simulation time 20485317480 ps
CPU time 23.54 seconds
Started Sep 01 06:54:43 AM UTC 24
Finished Sep 01 06:55:08 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632951038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2632951038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/203.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/215.uart_fifo_reset.1730642615
Short name T166
Test name
Test status
Simulation time 131871363481 ps
CPU time 99.14 seconds
Started Sep 01 06:55:01 AM UTC 24
Finished Sep 01 06:56:42 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730642615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1730642615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/215.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1803695723
Short name T238
Test name
Test status
Simulation time 217985389123 ps
CPU time 202.37 seconds
Started Sep 01 06:57:32 AM UTC 24
Finished Sep 01 07:00:58 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803695723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1803695723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/296.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/72.uart_fifo_reset.2910140337
Short name T229
Test name
Test status
Simulation time 189394447997 ps
CPU time 308.96 seconds
Started Sep 01 06:49:59 AM UTC 24
Finished Sep 01 06:55:12 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910140337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2910140337
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/72.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.2826881721
Short name T31
Test name
Test status
Simulation time 2516821507 ps
CPU time 48.43 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:26:09 AM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2826881721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_
with_rand_reset.2826881721
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_stress_all.1273563533
Short name T353
Test name
Test status
Simulation time 173904665722 ps
CPU time 251.69 seconds
Started Sep 01 06:27:51 AM UTC 24
Finished Sep 01 06:32:07 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273563533 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1273563533
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/105.uart_fifo_reset.612779491
Short name T226
Test name
Test status
Simulation time 96457131525 ps
CPU time 153.99 seconds
Started Sep 01 06:51:47 AM UTC 24
Finished Sep 01 06:54:23 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612779491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.612779491
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/105.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_tx_rx.4098672629
Short name T338
Test name
Test status
Simulation time 90732734842 ps
CPU time 265.19 seconds
Started Sep 01 06:27:57 AM UTC 24
Finished Sep 01 06:32:26 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098672629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4098672629
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/112.uart_fifo_reset.1435327033
Short name T163
Test name
Test status
Simulation time 102038349727 ps
CPU time 37.34 seconds
Started Sep 01 06:51:57 AM UTC 24
Finished Sep 01 06:52:36 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435327033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1435327033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/112.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/113.uart_fifo_reset.2910921650
Short name T209
Test name
Test status
Simulation time 44675626457 ps
CPU time 43.38 seconds
Started Sep 01 06:51:59 AM UTC 24
Finished Sep 01 06:52:44 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910921650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2910921650
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/113.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/115.uart_fifo_reset.3666973742
Short name T243
Test name
Test status
Simulation time 18221012752 ps
CPU time 25.59 seconds
Started Sep 01 06:52:04 AM UTC 24
Finished Sep 01 06:52:31 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666973742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3666973742
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/115.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_tx_rx.596759397
Short name T355
Test name
Test status
Simulation time 238999621317 ps
CPU time 218.76 seconds
Started Sep 01 06:28:17 AM UTC 24
Finished Sep 01 06:31:59 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596759397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.596759397
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/131.uart_fifo_reset.4008674814
Short name T216
Test name
Test status
Simulation time 43894522884 ps
CPU time 69.65 seconds
Started Sep 01 06:52:33 AM UTC 24
Finished Sep 01 06:53:44 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008674814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.4008674814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/131.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/134.uart_fifo_reset.3657795563
Short name T236
Test name
Test status
Simulation time 58082707556 ps
CPU time 23.66 seconds
Started Sep 01 06:52:36 AM UTC 24
Finished Sep 01 06:53:01 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657795563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3657795563
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/134.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_stress_all.3482461331
Short name T139
Test name
Test status
Simulation time 48282147030 ps
CPU time 133.83 seconds
Started Sep 01 06:29:29 AM UTC 24
Finished Sep 01 06:31:45 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482461331 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3482461331
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/161.uart_fifo_reset.2846500678
Short name T252
Test name
Test status
Simulation time 321728834550 ps
CPU time 572.68 seconds
Started Sep 01 06:53:12 AM UTC 24
Finished Sep 01 07:02:52 AM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846500678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2846500678
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/161.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/167.uart_fifo_reset.1722592297
Short name T237
Test name
Test status
Simulation time 74103246758 ps
CPU time 148 seconds
Started Sep 01 06:53:23 AM UTC 24
Finished Sep 01 06:55:54 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722592297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1722592297
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/167.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/171.uart_fifo_reset.3570986073
Short name T233
Test name
Test status
Simulation time 180513844087 ps
CPU time 189.27 seconds
Started Sep 01 06:53:31 AM UTC 24
Finished Sep 01 06:56:44 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570986073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3570986073
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/171.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/201.uart_fifo_reset.1883263240
Short name T165
Test name
Test status
Simulation time 72442928486 ps
CPU time 74.83 seconds
Started Sep 01 06:54:34 AM UTC 24
Finished Sep 01 06:55:51 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883263240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.1883263240
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/201.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2533121964
Short name T253
Test name
Test status
Simulation time 99706254191 ps
CPU time 101.48 seconds
Started Sep 01 06:54:49 AM UTC 24
Finished Sep 01 06:56:33 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533121964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2533121964
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/208.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/213.uart_fifo_reset.289001267
Short name T246
Test name
Test status
Simulation time 301907986774 ps
CPU time 76.95 seconds
Started Sep 01 06:54:52 AM UTC 24
Finished Sep 01 06:56:11 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289001267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.289001267
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/213.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/229.uart_fifo_reset.929264473
Short name T239
Test name
Test status
Simulation time 25089531175 ps
CPU time 49.12 seconds
Started Sep 01 06:55:19 AM UTC 24
Finished Sep 01 06:56:10 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929264473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.929264473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/229.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/238.uart_fifo_reset.460766009
Short name T204
Test name
Test status
Simulation time 15185403303 ps
CPU time 43.37 seconds
Started Sep 01 06:55:42 AM UTC 24
Finished Sep 01 06:56:27 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460766009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.460766009
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/238.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/239.uart_fifo_reset.488522887
Short name T224
Test name
Test status
Simulation time 32581461163 ps
CPU time 28.52 seconds
Started Sep 01 06:55:43 AM UTC 24
Finished Sep 01 06:56:13 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488522887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.488522887
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/239.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/282.uart_fifo_reset.4116028346
Short name T254
Test name
Test status
Simulation time 49269717594 ps
CPU time 111.44 seconds
Started Sep 01 06:57:02 AM UTC 24
Finished Sep 01 06:58:56 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116028346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.4116028346
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/282.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/285.uart_fifo_reset.2066190569
Short name T240
Test name
Test status
Simulation time 8905529187 ps
CPU time 15.49 seconds
Started Sep 01 06:57:16 AM UTC 24
Finished Sep 01 06:57:33 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066190569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2066190569
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/285.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_fifo_reset.3132926250
Short name T93
Test name
Test status
Simulation time 20902583918 ps
CPU time 47.39 seconds
Started Sep 01 06:26:43 AM UTC 24
Finished Sep 01 06:27:32 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132926250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3132926250
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.3714778759
Short name T1193
Test name
Test status
Simulation time 93882034 ps
CPU time 2.26 seconds
Started Sep 01 06:57:41 AM UTC 24
Finished Sep 01 06:57:44 AM UTC 24
Peak memory 202696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714778759 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3714778759
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.208878001
Short name T52
Test name
Test status
Simulation time 21602809 ps
CPU time 0.88 seconds
Started Sep 01 06:57:40 AM UTC 24
Finished Sep 01 06:57:42 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208878001 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.208878001
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2741067049
Short name T1194
Test name
Test status
Simulation time 36471997 ps
CPU time 0.98 seconds
Started Sep 01 06:57:42 AM UTC 24
Finished Sep 01 06:57:44 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2741067049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r
eset.2741067049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.92896893
Short name T1192
Test name
Test status
Simulation time 17985150 ps
CPU time 0.94 seconds
Started Sep 01 06:57:41 AM UTC 24
Finished Sep 01 06:57:43 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92896893 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.92896893
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2114527373
Short name T1191
Test name
Test status
Simulation time 12024118 ps
CPU time 0.81 seconds
Started Sep 01 06:57:39 AM UTC 24
Finished Sep 01 06:57:41 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114527373 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2114527373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2225954935
Short name T1190
Test name
Test status
Simulation time 53285576 ps
CPU time 3.11 seconds
Started Sep 01 06:57:36 AM UTC 24
Finished Sep 01 06:57:40 AM UTC 24
Peak memory 204848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225954935 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2225954935
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.183337785
Short name T55
Test name
Test status
Simulation time 19511100 ps
CPU time 0.97 seconds
Started Sep 01 06:57:47 AM UTC 24
Finished Sep 01 06:57:49 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183337785 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.183337785
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.2407583904
Short name T1198
Test name
Test status
Simulation time 793984259 ps
CPU time 3.43 seconds
Started Sep 01 06:57:47 AM UTC 24
Finished Sep 01 06:57:51 AM UTC 24
Peak memory 202696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407583904 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2407583904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.2601299744
Short name T54
Test name
Test status
Simulation time 13790366 ps
CPU time 0.89 seconds
Started Sep 01 06:57:46 AM UTC 24
Finished Sep 01 06:57:48 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601299744 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.2601299744
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.256717186
Short name T1200
Test name
Test status
Simulation time 16006724 ps
CPU time 1.09 seconds
Started Sep 01 06:57:49 AM UTC 24
Finished Sep 01 06:57:52 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=256717186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_re
set.256717186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.230704274
Short name T1196
Test name
Test status
Simulation time 42920475 ps
CPU time 0.8 seconds
Started Sep 01 06:57:46 AM UTC 24
Finished Sep 01 06:57:48 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230704274 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.230704274
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.923234219
Short name T1197
Test name
Test status
Simulation time 44961743 ps
CPU time 0.86 seconds
Started Sep 01 06:57:45 AM UTC 24
Finished Sep 01 06:57:48 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923234219 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.923234219
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.937119628
Short name T67
Test name
Test status
Simulation time 50756899 ps
CPU time 0.98 seconds
Started Sep 01 06:57:48 AM UTC 24
Finished Sep 01 06:57:50 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937119628 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.937119628
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2215500858
Short name T1195
Test name
Test status
Simulation time 49833394 ps
CPU time 1.64 seconds
Started Sep 01 06:57:43 AM UTC 24
Finished Sep 01 06:57:46 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215500858 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2215500858
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.2097960836
Short name T77
Test name
Test status
Simulation time 45837423 ps
CPU time 1.37 seconds
Started Sep 01 06:57:45 AM UTC 24
Finished Sep 01 06:57:48 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097960836 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2097960836
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4272883848
Short name T1244
Test name
Test status
Simulation time 24717771 ps
CPU time 1.53 seconds
Started Sep 01 06:58:10 AM UTC 24
Finished Sep 01 06:58:12 AM UTC 24
Peak memory 203680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4272883848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_
reset.4272883848
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.3000447003
Short name T64
Test name
Test status
Simulation time 62615116 ps
CPU time 0.86 seconds
Started Sep 01 06:58:10 AM UTC 24
Finished Sep 01 06:58:12 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000447003 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3000447003
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2808786407
Short name T1236
Test name
Test status
Simulation time 14426724 ps
CPU time 0.85 seconds
Started Sep 01 06:58:08 AM UTC 24
Finished Sep 01 06:58:10 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808786407 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2808786407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.4007141409
Short name T1241
Test name
Test status
Simulation time 52725666 ps
CPU time 1.05 seconds
Started Sep 01 06:58:10 AM UTC 24
Finished Sep 01 06:58:12 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007141409 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.4007141409
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1366873435
Short name T1238
Test name
Test status
Simulation time 68135120 ps
CPU time 1.48 seconds
Started Sep 01 06:58:08 AM UTC 24
Finished Sep 01 06:58:10 AM UTC 24
Peak memory 201012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366873435 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1366873435
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1217207012
Short name T83
Test name
Test status
Simulation time 77845585 ps
CPU time 1.42 seconds
Started Sep 01 06:58:08 AM UTC 24
Finished Sep 01 06:58:10 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217207012 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1217207012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1154638062
Short name T1248
Test name
Test status
Simulation time 171487524 ps
CPU time 1.06 seconds
Started Sep 01 06:58:13 AM UTC 24
Finished Sep 01 06:58:15 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1154638062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_
reset.1154638062
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.184030435
Short name T1245
Test name
Test status
Simulation time 15881532 ps
CPU time 0.93 seconds
Started Sep 01 06:58:13 AM UTC 24
Finished Sep 01 06:58:15 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184030435 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.184030435
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.1115615908
Short name T1240
Test name
Test status
Simulation time 18287118 ps
CPU time 0.83 seconds
Started Sep 01 06:58:10 AM UTC 24
Finished Sep 01 06:58:12 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115615908 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1115615908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.4209695400
Short name T1247
Test name
Test status
Simulation time 25684687 ps
CPU time 1.15 seconds
Started Sep 01 06:58:13 AM UTC 24
Finished Sep 01 06:58:15 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209695400 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.4209695400
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2971521039
Short name T1243
Test name
Test status
Simulation time 61035268 ps
CPU time 1.45 seconds
Started Sep 01 06:58:10 AM UTC 24
Finished Sep 01 06:58:12 AM UTC 24
Peak memory 201656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971521039 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2971521039
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1200773894
Short name T1242
Test name
Test status
Simulation time 139007731 ps
CPU time 1.37 seconds
Started Sep 01 06:58:10 AM UTC 24
Finished Sep 01 06:58:12 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200773894 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1200773894
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3850374656
Short name T1250
Test name
Test status
Simulation time 72097478 ps
CPU time 1.09 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:16 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3850374656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_
reset.3850374656
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.290043733
Short name T62
Test name
Test status
Simulation time 49685222 ps
CPU time 0.93 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:16 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290043733 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.290043733
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.242559025
Short name T1246
Test name
Test status
Simulation time 14420173 ps
CPU time 0.8 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:15 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242559025 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.242559025
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.1826696778
Short name T1249
Test name
Test status
Simulation time 24029976 ps
CPU time 1.1 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:16 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826696778 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.1826696778
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.2575848649
Short name T1254
Test name
Test status
Simulation time 477211328 ps
CPU time 3.49 seconds
Started Sep 01 06:58:13 AM UTC 24
Finished Sep 01 06:58:18 AM UTC 24
Peak memory 204608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575848649 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2575848649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.1274806953
Short name T102
Test name
Test status
Simulation time 97613382 ps
CPU time 1.97 seconds
Started Sep 01 06:58:13 AM UTC 24
Finished Sep 01 06:58:16 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274806953 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1274806953
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4293165327
Short name T1253
Test name
Test status
Simulation time 65973232 ps
CPU time 1.16 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:16 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4293165327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_
reset.4293165327
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.3822989465
Short name T63
Test name
Test status
Simulation time 18741816 ps
CPU time 0.8 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:16 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822989465 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3822989465
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1523905692
Short name T1251
Test name
Test status
Simulation time 16619459 ps
CPU time 0.88 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:16 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523905692 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1523905692
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.3074236178
Short name T1252
Test name
Test status
Simulation time 12454836 ps
CPU time 0.92 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:16 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074236178 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.3074236178
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3542746066
Short name T1255
Test name
Test status
Simulation time 252063047 ps
CPU time 3.34 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:18 AM UTC 24
Peak memory 204740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542746066 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3542746066
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.2773796481
Short name T101
Test name
Test status
Simulation time 52810745 ps
CPU time 1.39 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:16 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773796481 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.2773796481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1279343790
Short name T1262
Test name
Test status
Simulation time 108507898 ps
CPU time 1.19 seconds
Started Sep 01 06:58:17 AM UTC 24
Finished Sep 01 06:58:19 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1279343790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_
reset.1279343790
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3537868975
Short name T65
Test name
Test status
Simulation time 15008596 ps
CPU time 0.83 seconds
Started Sep 01 06:58:17 AM UTC 24
Finished Sep 01 06:58:19 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537868975 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3537868975
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.3542167340
Short name T1257
Test name
Test status
Simulation time 15335807 ps
CPU time 0.85 seconds
Started Sep 01 06:58:17 AM UTC 24
Finished Sep 01 06:58:19 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542167340 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3542167340
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.2675028566
Short name T1259
Test name
Test status
Simulation time 114004814 ps
CPU time 1.05 seconds
Started Sep 01 06:58:17 AM UTC 24
Finished Sep 01 06:58:19 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675028566 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.2675028566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.1404727363
Short name T1256
Test name
Test status
Simulation time 105842510 ps
CPU time 3.1 seconds
Started Sep 01 06:58:14 AM UTC 24
Finished Sep 01 06:58:18 AM UTC 24
Peak memory 204740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404727363 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1404727363
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.3162938627
Short name T1264
Test name
Test status
Simulation time 478410893 ps
CPU time 1.72 seconds
Started Sep 01 06:58:17 AM UTC 24
Finished Sep 01 06:58:20 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162938627 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3162938627
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2825735118
Short name T1263
Test name
Test status
Simulation time 18242558 ps
CPU time 1.03 seconds
Started Sep 01 06:58:18 AM UTC 24
Finished Sep 01 06:58:20 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2825735118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_
reset.2825735118
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.4210167851
Short name T1260
Test name
Test status
Simulation time 50995706 ps
CPU time 0.81 seconds
Started Sep 01 06:58:17 AM UTC 24
Finished Sep 01 06:58:19 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210167851 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4210167851
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3797572664
Short name T1258
Test name
Test status
Simulation time 49463396 ps
CPU time 0.85 seconds
Started Sep 01 06:58:17 AM UTC 24
Finished Sep 01 06:58:19 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797572664 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3797572664
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.482090392
Short name T1261
Test name
Test status
Simulation time 13844714 ps
CPU time 0.86 seconds
Started Sep 01 06:58:18 AM UTC 24
Finished Sep 01 06:58:19 AM UTC 24
Peak memory 203680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482090392 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.482090392
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.2527002688
Short name T1266
Test name
Test status
Simulation time 113964543 ps
CPU time 2.21 seconds
Started Sep 01 06:58:17 AM UTC 24
Finished Sep 01 06:58:20 AM UTC 24
Peak memory 202692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527002688 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2527002688
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.2098570250
Short name T1265
Test name
Test status
Simulation time 200212858 ps
CPU time 1.84 seconds
Started Sep 01 06:58:17 AM UTC 24
Finished Sep 01 06:58:20 AM UTC 24
Peak memory 201704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098570250 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2098570250
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.19736248
Short name T1271
Test name
Test status
Simulation time 78691983 ps
CPU time 1.08 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:24 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=19736248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.19736248
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.323689503
Short name T1267
Test name
Test status
Simulation time 115745268 ps
CPU time 0.7 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:24 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323689503 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.323689503
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.561460492
Short name T1268
Test name
Test status
Simulation time 14265949 ps
CPU time 0.81 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:24 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561460492 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.561460492
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1942147687
Short name T1269
Test name
Test status
Simulation time 43869658 ps
CPU time 0.94 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:24 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942147687 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.1942147687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.950560976
Short name T1285
Test name
Test status
Simulation time 344770145 ps
CPU time 3.63 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:27 AM UTC 24
Peak memory 204324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950560976 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.950560976
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.2886967053
Short name T1270
Test name
Test status
Simulation time 46931223 ps
CPU time 1.19 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:24 AM UTC 24
Peak memory 201248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886967053 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2886967053
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2268087878
Short name T1277
Test name
Test status
Simulation time 20517544 ps
CPU time 1.04 seconds
Started Sep 01 06:58:23 AM UTC 24
Finished Sep 01 06:58:25 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2268087878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_
reset.2268087878
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.739208830
Short name T1273
Test name
Test status
Simulation time 54848301 ps
CPU time 0.87 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:24 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739208830 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.739208830
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.3487519921
Short name T1272
Test name
Test status
Simulation time 52894768 ps
CPU time 0.86 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:24 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487519921 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3487519921
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.3434070958
Short name T1274
Test name
Test status
Simulation time 41115354 ps
CPU time 0.92 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:24 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434070958 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.3434070958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.302069343
Short name T1279
Test name
Test status
Simulation time 68144336 ps
CPU time 1.5 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:25 AM UTC 24
Peak memory 203612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302069343 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.302069343
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3835272398
Short name T1278
Test name
Test status
Simulation time 82013861 ps
CPU time 1.39 seconds
Started Sep 01 06:58:22 AM UTC 24
Finished Sep 01 06:58:25 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835272398 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3835272398
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.639980650
Short name T1283
Test name
Test status
Simulation time 233833129 ps
CPU time 1.88 seconds
Started Sep 01 06:58:23 AM UTC 24
Finished Sep 01 06:58:26 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=639980650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_r
eset.639980650
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2574640773
Short name T1275
Test name
Test status
Simulation time 22027207 ps
CPU time 0.82 seconds
Started Sep 01 06:58:23 AM UTC 24
Finished Sep 01 06:58:24 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574640773 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2574640773
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.4182530515
Short name T1276
Test name
Test status
Simulation time 29766705 ps
CPU time 0.81 seconds
Started Sep 01 06:58:23 AM UTC 24
Finished Sep 01 06:58:25 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182530515 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.4182530515
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.3173499121
Short name T1281
Test name
Test status
Simulation time 16777636 ps
CPU time 1.12 seconds
Started Sep 01 06:58:23 AM UTC 24
Finished Sep 01 06:58:25 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173499121 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.3173499121
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.315874872
Short name T1284
Test name
Test status
Simulation time 41958103 ps
CPU time 2.86 seconds
Started Sep 01 06:58:23 AM UTC 24
Finished Sep 01 06:58:26 AM UTC 24
Peak memory 202672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315874872 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.315874872
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.359844743
Short name T1280
Test name
Test status
Simulation time 136154591 ps
CPU time 1.23 seconds
Started Sep 01 06:58:23 AM UTC 24
Finished Sep 01 06:58:25 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359844743 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.359844743
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.181002257
Short name T1294
Test name
Test status
Simulation time 14411144 ps
CPU time 0.86 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=181002257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_r
eset.181002257
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.4023966797
Short name T1286
Test name
Test status
Simulation time 80399270 ps
CPU time 0.7 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:28 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023966797 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.4023966797
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1930580563
Short name T1288
Test name
Test status
Simulation time 25786985 ps
CPU time 0.78 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930580563 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1930580563
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2655071479
Short name T1289
Test name
Test status
Simulation time 12368181 ps
CPU time 0.84 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655071479 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.2655071479
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.1956078459
Short name T1282
Test name
Test status
Simulation time 120446799 ps
CPU time 1.43 seconds
Started Sep 01 06:58:23 AM UTC 24
Finished Sep 01 06:58:25 AM UTC 24
Peak memory 203628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956078459 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1956078459
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.1583699475
Short name T1303
Test name
Test status
Simulation time 108880721 ps
CPU time 1.64 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583699475 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1583699475
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.1302274151
Short name T1203
Test name
Test status
Simulation time 210620111 ps
CPU time 1.16 seconds
Started Sep 01 06:57:52 AM UTC 24
Finished Sep 01 06:57:54 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302274151 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1302274151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.124000327
Short name T1204
Test name
Test status
Simulation time 109232866 ps
CPU time 3.17 seconds
Started Sep 01 06:57:51 AM UTC 24
Finished Sep 01 06:57:55 AM UTC 24
Peak memory 202684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124000327 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.124000327
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.463189280
Short name T1201
Test name
Test status
Simulation time 16330157 ps
CPU time 0.88 seconds
Started Sep 01 06:57:49 AM UTC 24
Finished Sep 01 06:57:52 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463189280 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.463189280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3918052852
Short name T1206
Test name
Test status
Simulation time 118188029 ps
CPU time 1.25 seconds
Started Sep 01 06:57:53 AM UTC 24
Finished Sep 01 06:57:56 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3918052852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_r
eset.3918052852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3173957467
Short name T68
Test name
Test status
Simulation time 13679706 ps
CPU time 0.89 seconds
Started Sep 01 06:57:50 AM UTC 24
Finished Sep 01 06:57:53 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173957467 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3173957467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.834968192
Short name T1199
Test name
Test status
Simulation time 36578603 ps
CPU time 0.87 seconds
Started Sep 01 06:57:49 AM UTC 24
Finished Sep 01 06:57:52 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834968192 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.834968192
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3972979098
Short name T70
Test name
Test status
Simulation time 36919020 ps
CPU time 1.3 seconds
Started Sep 01 06:57:53 AM UTC 24
Finished Sep 01 06:57:56 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972979098 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.3972979098
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2934031020
Short name T1202
Test name
Test status
Simulation time 428872959 ps
CPU time 2.9 seconds
Started Sep 01 06:57:49 AM UTC 24
Finished Sep 01 06:57:54 AM UTC 24
Peak memory 202672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934031020 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2934031020
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2318781826
Short name T78
Test name
Test status
Simulation time 65252585 ps
CPU time 1.34 seconds
Started Sep 01 06:57:49 AM UTC 24
Finished Sep 01 06:57:52 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318781826 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2318781826
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.609920181
Short name T1287
Test name
Test status
Simulation time 44894476 ps
CPU time 0.6 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609920181 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.609920181
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.3222246515
Short name T1290
Test name
Test status
Simulation time 37537742 ps
CPU time 0.87 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222246515 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3222246515
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1089436167
Short name T1291
Test name
Test status
Simulation time 29142166 ps
CPU time 0.75 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089436167 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1089436167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1858084999
Short name T1295
Test name
Test status
Simulation time 15537004 ps
CPU time 0.85 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858084999 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1858084999
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2319784604
Short name T1293
Test name
Test status
Simulation time 23118158 ps
CPU time 0.73 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319784604 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2319784604
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2686401140
Short name T1292
Test name
Test status
Simulation time 23469458 ps
CPU time 0.73 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686401140 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2686401140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2573373650
Short name T1297
Test name
Test status
Simulation time 51767334 ps
CPU time 0.79 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573373650 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2573373650
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.2282456420
Short name T1296
Test name
Test status
Simulation time 37114801 ps
CPU time 0.76 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282456420 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2282456420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.4180268347
Short name T1298
Test name
Test status
Simulation time 32049687 ps
CPU time 0.76 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180268347 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4180268347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2665794891
Short name T1300
Test name
Test status
Simulation time 32027737 ps
CPU time 0.84 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665794891 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2665794891
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2030079883
Short name T57
Test name
Test status
Simulation time 13123081 ps
CPU time 1 seconds
Started Sep 01 06:57:55 AM UTC 24
Finished Sep 01 06:57:57 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030079883 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2030079883
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2114390187
Short name T1212
Test name
Test status
Simulation time 230991454 ps
CPU time 3.14 seconds
Started Sep 01 06:57:55 AM UTC 24
Finished Sep 01 06:57:59 AM UTC 24
Peak memory 202884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114390187 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2114390187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.612653167
Short name T56
Test name
Test status
Simulation time 13417120 ps
CPU time 0.88 seconds
Started Sep 01 06:57:53 AM UTC 24
Finished Sep 01 06:57:55 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612653167 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.612653167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.2190562547
Short name T1208
Test name
Test status
Simulation time 54201807 ps
CPU time 1.99 seconds
Started Sep 01 06:57:55 AM UTC 24
Finished Sep 01 06:57:58 AM UTC 24
Peak memory 203680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2190562547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r
eset.2190562547
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.4224094631
Short name T69
Test name
Test status
Simulation time 11634450 ps
CPU time 0.88 seconds
Started Sep 01 06:57:53 AM UTC 24
Finished Sep 01 06:57:55 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224094631 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.4224094631
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.2148519429
Short name T1205
Test name
Test status
Simulation time 14466513 ps
CPU time 0.85 seconds
Started Sep 01 06:57:53 AM UTC 24
Finished Sep 01 06:57:55 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148519429 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2148519429
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.1861554996
Short name T71
Test name
Test status
Simulation time 44421859 ps
CPU time 0.94 seconds
Started Sep 01 06:57:55 AM UTC 24
Finished Sep 01 06:57:57 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861554996 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.1861554996
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.2421183790
Short name T1207
Test name
Test status
Simulation time 164163381 ps
CPU time 2.43 seconds
Started Sep 01 06:57:53 AM UTC 24
Finished Sep 01 06:57:57 AM UTC 24
Peak memory 202692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421183790 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2421183790
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1006624708
Short name T80
Test name
Test status
Simulation time 380664789 ps
CPU time 1.5 seconds
Started Sep 01 06:57:53 AM UTC 24
Finished Sep 01 06:57:56 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006624708 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1006624708
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.108868169
Short name T1299
Test name
Test status
Simulation time 64201508 ps
CPU time 0.86 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108868169 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.108868169
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2610057222
Short name T1301
Test name
Test status
Simulation time 46957633 ps
CPU time 0.83 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610057222 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2610057222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.4286080791
Short name T1302
Test name
Test status
Simulation time 28078123 ps
CPU time 0.69 seconds
Started Sep 01 06:58:27 AM UTC 24
Finished Sep 01 06:58:29 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286080791 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4286080791
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.2844565076
Short name T1307
Test name
Test status
Simulation time 33722342 ps
CPU time 0.84 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844565076 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.2844565076
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3379110313
Short name T1304
Test name
Test status
Simulation time 46628721 ps
CPU time 0.62 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379110313 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3379110313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.358081572
Short name T1305
Test name
Test status
Simulation time 25138055 ps
CPU time 0.61 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358081572 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.358081572
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2245901431
Short name T1308
Test name
Test status
Simulation time 17731054 ps
CPU time 0.85 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245901431 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2245901431
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.2101346424
Short name T1306
Test name
Test status
Simulation time 59926956 ps
CPU time 0.62 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101346424 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2101346424
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.183079951
Short name T1310
Test name
Test status
Simulation time 108549637 ps
CPU time 0.84 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183079951 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.183079951
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.2683464999
Short name T1311
Test name
Test status
Simulation time 27748097 ps
CPU time 0.86 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683464999 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.2683464999
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2718140536
Short name T1211
Test name
Test status
Simulation time 15613036 ps
CPU time 1 seconds
Started Sep 01 06:57:57 AM UTC 24
Finished Sep 01 06:57:59 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718140536 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2718140536
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.381364005
Short name T1214
Test name
Test status
Simulation time 357659358 ps
CPU time 2.11 seconds
Started Sep 01 06:57:57 AM UTC 24
Finished Sep 01 06:58:00 AM UTC 24
Peak memory 202888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381364005 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.381364005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.1514918964
Short name T1209
Test name
Test status
Simulation time 14664594 ps
CPU time 0.89 seconds
Started Sep 01 06:57:56 AM UTC 24
Finished Sep 01 06:57:58 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514918964 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1514918964
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2645045038
Short name T1216
Test name
Test status
Simulation time 51126612 ps
CPU time 1.2 seconds
Started Sep 01 06:57:58 AM UTC 24
Finished Sep 01 06:58:00 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2645045038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r
eset.2645045038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.3612337195
Short name T59
Test name
Test status
Simulation time 102825481 ps
CPU time 0.93 seconds
Started Sep 01 06:57:57 AM UTC 24
Finished Sep 01 06:57:58 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612337195 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3612337195
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.814555021
Short name T1210
Test name
Test status
Simulation time 42193584 ps
CPU time 0.88 seconds
Started Sep 01 06:57:56 AM UTC 24
Finished Sep 01 06:57:58 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814555021 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.814555021
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.311683508
Short name T72
Test name
Test status
Simulation time 48991849 ps
CPU time 1.12 seconds
Started Sep 01 06:57:58 AM UTC 24
Finished Sep 01 06:58:00 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311683508 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.311683508
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.2246037009
Short name T1215
Test name
Test status
Simulation time 364328845 ps
CPU time 2.91 seconds
Started Sep 01 06:57:56 AM UTC 24
Finished Sep 01 06:58:00 AM UTC 24
Peak memory 202632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246037009 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2246037009
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.696375180
Short name T82
Test name
Test status
Simulation time 302337201 ps
CPU time 1.47 seconds
Started Sep 01 06:57:56 AM UTC 24
Finished Sep 01 06:57:59 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696375180 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.696375180
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1204134415
Short name T1309
Test name
Test status
Simulation time 20510173 ps
CPU time 0.7 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204134415 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1204134415
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.90041994
Short name T1312
Test name
Test status
Simulation time 56401747 ps
CPU time 0.85 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90041994 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.90041994
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1319484684
Short name T1313
Test name
Test status
Simulation time 12363308 ps
CPU time 0.82 seconds
Started Sep 01 06:58:32 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319484684 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1319484684
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.683994518
Short name T1315
Test name
Test status
Simulation time 42415355 ps
CPU time 0.84 seconds
Started Sep 01 06:58:33 AM UTC 24
Finished Sep 01 06:58:35 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683994518 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.683994518
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1707884908
Short name T1314
Test name
Test status
Simulation time 36069919 ps
CPU time 0.75 seconds
Started Sep 01 06:58:33 AM UTC 24
Finished Sep 01 06:58:34 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707884908 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1707884908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1485034482
Short name T1317
Test name
Test status
Simulation time 187932211 ps
CPU time 0.87 seconds
Started Sep 01 06:58:33 AM UTC 24
Finished Sep 01 06:58:35 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485034482 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1485034482
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.4008632972
Short name T1316
Test name
Test status
Simulation time 37194851 ps
CPU time 0.64 seconds
Started Sep 01 06:58:33 AM UTC 24
Finished Sep 01 06:58:35 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008632972 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.4008632972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.951342891
Short name T1319
Test name
Test status
Simulation time 20980921 ps
CPU time 0.83 seconds
Started Sep 01 06:58:33 AM UTC 24
Finished Sep 01 06:58:35 AM UTC 24
Peak memory 201624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951342891 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.951342891
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2562416218
Short name T1318
Test name
Test status
Simulation time 52571419 ps
CPU time 0.88 seconds
Started Sep 01 06:58:33 AM UTC 24
Finished Sep 01 06:58:35 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562416218 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2562416218
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3690460524
Short name T1320
Test name
Test status
Simulation time 51252964 ps
CPU time 0.83 seconds
Started Sep 01 06:58:33 AM UTC 24
Finished Sep 01 06:58:35 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690460524 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3690460524
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3208848440
Short name T1219
Test name
Test status
Simulation time 25231124 ps
CPU time 1.12 seconds
Started Sep 01 06:58:00 AM UTC 24
Finished Sep 01 06:58:02 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3208848440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r
eset.3208848440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.583610709
Short name T73
Test name
Test status
Simulation time 49155292 ps
CPU time 0.89 seconds
Started Sep 01 06:58:00 AM UTC 24
Finished Sep 01 06:58:02 AM UTC 24
Peak memory 201640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583610709 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.583610709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3880437877
Short name T1218
Test name
Test status
Simulation time 14198465 ps
CPU time 0.84 seconds
Started Sep 01 06:58:00 AM UTC 24
Finished Sep 01 06:58:01 AM UTC 24
Peak memory 201648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880437877 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3880437877
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1848774417
Short name T74
Test name
Test status
Simulation time 56657268 ps
CPU time 1.1 seconds
Started Sep 01 06:58:00 AM UTC 24
Finished Sep 01 06:58:02 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848774417 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.1848774417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.3235217570
Short name T1217
Test name
Test status
Simulation time 125738626 ps
CPU time 1.98 seconds
Started Sep 01 06:57:58 AM UTC 24
Finished Sep 01 06:58:01 AM UTC 24
Peak memory 203692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235217570 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3235217570
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.683168441
Short name T1224
Test name
Test status
Simulation time 35227062 ps
CPU time 0.99 seconds
Started Sep 01 06:58:01 AM UTC 24
Finished Sep 01 06:58:03 AM UTC 24
Peak memory 201572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=683168441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_re
set.683168441
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.1592767275
Short name T60
Test name
Test status
Simulation time 44496518 ps
CPU time 0.89 seconds
Started Sep 01 06:58:01 AM UTC 24
Finished Sep 01 06:58:03 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592767275 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1592767275
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.1369606847
Short name T1221
Test name
Test status
Simulation time 39148620 ps
CPU time 0.87 seconds
Started Sep 01 06:58:01 AM UTC 24
Finished Sep 01 06:58:03 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369606847 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1369606847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.3028917617
Short name T1222
Test name
Test status
Simulation time 42362688 ps
CPU time 0.97 seconds
Started Sep 01 06:58:01 AM UTC 24
Finished Sep 01 06:58:03 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028917617 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.3028917617
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.639188263
Short name T1220
Test name
Test status
Simulation time 148733157 ps
CPU time 1.63 seconds
Started Sep 01 06:58:00 AM UTC 24
Finished Sep 01 06:58:03 AM UTC 24
Peak memory 201684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639188263 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.639188263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.743028616
Short name T1223
Test name
Test status
Simulation time 465184687 ps
CPU time 2.5 seconds
Started Sep 01 06:58:00 AM UTC 24
Finished Sep 01 06:58:03 AM UTC 24
Peak memory 202752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743028616 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.743028616
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2248473211
Short name T1227
Test name
Test status
Simulation time 33599871 ps
CPU time 1.03 seconds
Started Sep 01 06:58:03 AM UTC 24
Finished Sep 01 06:58:06 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2248473211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r
eset.2248473211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1043044466
Short name T61
Test name
Test status
Simulation time 51293650 ps
CPU time 0.9 seconds
Started Sep 01 06:58:03 AM UTC 24
Finished Sep 01 06:58:05 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043044466 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1043044466
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.4208074756
Short name T1226
Test name
Test status
Simulation time 42839980 ps
CPU time 0.83 seconds
Started Sep 01 06:58:03 AM UTC 24
Finished Sep 01 06:58:05 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208074756 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.4208074756
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.1075870001
Short name T1228
Test name
Test status
Simulation time 19121528 ps
CPU time 1.13 seconds
Started Sep 01 06:58:03 AM UTC 24
Finished Sep 01 06:58:06 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075870001 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.1075870001
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.4281282578
Short name T1225
Test name
Test status
Simulation time 77712372 ps
CPU time 2.78 seconds
Started Sep 01 06:58:02 AM UTC 24
Finished Sep 01 06:58:05 AM UTC 24
Peak memory 202672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281282578 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.4281282578
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.2470616579
Short name T79
Test name
Test status
Simulation time 323838398 ps
CPU time 2.09 seconds
Started Sep 01 06:58:03 AM UTC 24
Finished Sep 01 06:58:07 AM UTC 24
Peak memory 202752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470616579 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2470616579
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3336395643
Short name T1234
Test name
Test status
Simulation time 75859268 ps
CPU time 1.13 seconds
Started Sep 01 06:58:05 AM UTC 24
Finished Sep 01 06:58:08 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3336395643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r
eset.3336395643
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.2496497254
Short name T1232
Test name
Test status
Simulation time 96541403 ps
CPU time 0.87 seconds
Started Sep 01 06:58:05 AM UTC 24
Finished Sep 01 06:58:07 AM UTC 24
Peak memory 201756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496497254 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.2496497254
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.4280157908
Short name T1231
Test name
Test status
Simulation time 29081515 ps
CPU time 0.84 seconds
Started Sep 01 06:58:05 AM UTC 24
Finished Sep 01 06:58:07 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280157908 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4280157908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.1589868019
Short name T1233
Test name
Test status
Simulation time 16318393 ps
CPU time 0.97 seconds
Started Sep 01 06:58:05 AM UTC 24
Finished Sep 01 06:58:08 AM UTC 24
Peak memory 201628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589868019 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.1589868019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.198801107
Short name T1230
Test name
Test status
Simulation time 276845009 ps
CPU time 2.07 seconds
Started Sep 01 06:58:04 AM UTC 24
Finished Sep 01 06:58:07 AM UTC 24
Peak memory 202684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198801107 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.198801107
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.2912270527
Short name T1229
Test name
Test status
Simulation time 93311423 ps
CPU time 1.41 seconds
Started Sep 01 06:58:04 AM UTC 24
Finished Sep 01 06:58:06 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912270527 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2912270527
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1985334166
Short name T1239
Test name
Test status
Simulation time 181099337 ps
CPU time 1.43 seconds
Started Sep 01 06:58:08 AM UTC 24
Finished Sep 01 06:58:10 AM UTC 24
Peak memory 201696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1985334166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r
eset.1985334166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.2283812238
Short name T58
Test name
Test status
Simulation time 39949919 ps
CPU time 0.91 seconds
Started Sep 01 06:58:07 AM UTC 24
Finished Sep 01 06:58:10 AM UTC 24
Peak memory 200948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283812238 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2283812238
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.3816106626
Short name T1213
Test name
Test status
Simulation time 35590516 ps
CPU time 0.81 seconds
Started Sep 01 06:58:07 AM UTC 24
Finished Sep 01 06:58:09 AM UTC 24
Peak memory 201688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816106626 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3816106626
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2585631722
Short name T1237
Test name
Test status
Simulation time 27636589 ps
CPU time 1.15 seconds
Started Sep 01 06:58:08 AM UTC 24
Finished Sep 01 06:58:10 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585631722 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.2585631722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.1896714851
Short name T1235
Test name
Test status
Simulation time 244045379 ps
CPU time 2.22 seconds
Started Sep 01 06:58:05 AM UTC 24
Finished Sep 01 06:58:09 AM UTC 24
Peak memory 202616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896714851 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1896714851
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3259299692
Short name T103
Test name
Test status
Simulation time 41382891 ps
CPU time 1.4 seconds
Started Sep 01 06:58:07 AM UTC 24
Finished Sep 01 06:58:10 AM UTC 24
Peak memory 201692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259299692 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3259299692
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_fifo_full.1097061770
Short name T75
Test name
Test status
Simulation time 43281903932 ps
CPU time 32.61 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:25:49 AM UTC 24
Peak memory 208544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097061770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1097061770
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.4281147682
Short name T12
Test name
Test status
Simulation time 167678683861 ps
CPU time 18.41 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:25:35 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281147682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4281147682
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_fifo_reset.1396838570
Short name T26
Test name
Test status
Simulation time 18028193107 ps
CPU time 25.98 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:25:43 AM UTC 24
Peak memory 208972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396838570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1396838570
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_intr.3014369979
Short name T18
Test name
Test status
Simulation time 20294855351 ps
CPU time 61.9 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:26:19 AM UTC 24
Peak memory 208544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014369979 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3014369979
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.33246128
Short name T656
Test name
Test status
Simulation time 76107469437 ps
CPU time 838.44 seconds
Started Sep 01 06:25:16 AM UTC 24
Finished Sep 01 06:39:25 AM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33246128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.33246128
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_loopback.2143252223
Short name T27
Test name
Test status
Simulation time 11558712860 ps
CPU time 21.22 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:25:38 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143252223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2143252223
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_noise_filter.1574039424
Short name T276
Test name
Test status
Simulation time 44913690234 ps
CPU time 59.16 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:26:16 AM UTC 24
Peak memory 208944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574039424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1574039424
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_perf.1461081146
Short name T332
Test name
Test status
Simulation time 8115049990 ps
CPU time 134.01 seconds
Started Sep 01 06:25:16 AM UTC 24
Finished Sep 01 06:27:33 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461081146 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1461081146
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2537172317
Short name T43
Test name
Test status
Simulation time 2427101591 ps
CPU time 19.86 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:25:36 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537172317 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2537172317
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_smoke.2961887381
Short name T374
Test name
Test status
Simulation time 11047383394 ps
CPU time 34.36 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:25:51 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961887381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2961887381
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.1021797700
Short name T3
Test name
Test status
Simulation time 529884470 ps
CPU time 2.42 seconds
Started Sep 01 06:25:15 AM UTC 24
Finished Sep 01 06:25:19 AM UTC 24
Peak memory 207608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021797700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1021797700
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_alert_test.1679048008
Short name T6
Test name
Test status
Simulation time 41152399 ps
CPU time 0.87 seconds
Started Sep 01 06:25:20 AM UTC 24
Finished Sep 01 06:25:21 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679048008 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1679048008
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_intr.2959987835
Short name T408
Test name
Test status
Simulation time 22211187047 ps
CPU time 40.34 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:26:00 AM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959987835 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2959987835
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.3354917255
Short name T509
Test name
Test status
Simulation time 114474663023 ps
CPU time 407.69 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:32:12 AM UTC 24
Peak memory 212208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354917255 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.3354917255
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_loopback.1593963262
Short name T10
Test name
Test status
Simulation time 5888509113 ps
CPU time 6.77 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:25:26 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593963262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1593963262
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_noise_filter.599320650
Short name T46
Test name
Test status
Simulation time 42243140312 ps
CPU time 43.16 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:26:03 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599320650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.599320650
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_rx_oversample.3421121591
Short name T25
Test name
Test status
Simulation time 6366150754 ps
CPU time 64.47 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:26:24 AM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421121591 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3421121591
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.1882906962
Short name T107
Test name
Test status
Simulation time 28992855929 ps
CPU time 48.31 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:26:08 AM UTC 24
Peak memory 208528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882906962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.1882906962
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.2061587044
Short name T311
Test name
Test status
Simulation time 76729162217 ps
CPU time 53.97 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:26:14 AM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061587044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2061587044
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_sec_cm.3325135379
Short name T7
Test name
Test status
Simulation time 127321953 ps
CPU time 1.09 seconds
Started Sep 01 06:25:19 AM UTC 24
Finished Sep 01 06:25:22 AM UTC 24
Peak memory 240196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325135379 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3325135379
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_smoke.879848630
Short name T5
Test name
Test status
Simulation time 491408377 ps
CPU time 2.03 seconds
Started Sep 01 06:25:17 AM UTC 24
Finished Sep 01 06:25:20 AM UTC 24
Peak memory 207540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879848630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.uart_smoke.879848630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.809019382
Short name T8
Test name
Test status
Simulation time 1300389434 ps
CPU time 3.34 seconds
Started Sep 01 06:25:18 AM UTC 24
Finished Sep 01 06:25:23 AM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809019382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.809019382
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_alert_test.484628162
Short name T465
Test name
Test status
Simulation time 78091575 ps
CPU time 0.82 seconds
Started Sep 01 06:27:53 AM UTC 24
Finished Sep 01 06:27:55 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484628162 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.484628162
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_fifo_full.448661049
Short name T562
Test name
Test status
Simulation time 195127253103 ps
CPU time 445.15 seconds
Started Sep 01 06:27:34 AM UTC 24
Finished Sep 01 06:35:05 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448661049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.448661049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.3818498677
Short name T320
Test name
Test status
Simulation time 76694566054 ps
CPU time 201.93 seconds
Started Sep 01 06:27:34 AM UTC 24
Finished Sep 01 06:31:00 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818498677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3818498677
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_fifo_reset.375308472
Short name T270
Test name
Test status
Simulation time 12811024442 ps
CPU time 24.17 seconds
Started Sep 01 06:27:35 AM UTC 24
Finished Sep 01 06:28:00 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375308472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.375308472
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.748532052
Short name T384
Test name
Test status
Simulation time 77937786375 ps
CPU time 386.54 seconds
Started Sep 01 06:27:49 AM UTC 24
Finished Sep 01 06:34:21 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748532052 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.748532052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_loopback.1721783881
Short name T463
Test name
Test status
Simulation time 3366946702 ps
CPU time 2.47 seconds
Started Sep 01 06:27:45 AM UTC 24
Finished Sep 01 06:27:49 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721783881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.1721783881
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_noise_filter.1461029741
Short name T303
Test name
Test status
Simulation time 35104425345 ps
CPU time 27.68 seconds
Started Sep 01 06:27:36 AM UTC 24
Finished Sep 01 06:28:05 AM UTC 24
Peak memory 207892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461029741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1461029741
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_perf.525508176
Short name T336
Test name
Test status
Simulation time 18449240968 ps
CPU time 338.5 seconds
Started Sep 01 06:27:45 AM UTC 24
Finished Sep 01 06:33:28 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525508176 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.525508176
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_rx_oversample.4090114263
Short name T472
Test name
Test status
Simulation time 7373641679 ps
CPU time 63.87 seconds
Started Sep 01 06:27:35 AM UTC 24
Finished Sep 01 06:28:40 AM UTC 24
Peak memory 207564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090114263 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4090114263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.1623748001
Short name T175
Test name
Test status
Simulation time 157686449576 ps
CPU time 93.73 seconds
Started Sep 01 06:27:38 AM UTC 24
Finished Sep 01 06:29:14 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623748001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1623748001
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.986591884
Short name T366
Test name
Test status
Simulation time 31681287517 ps
CPU time 12.56 seconds
Started Sep 01 06:27:37 AM UTC 24
Finished Sep 01 06:27:51 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986591884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.986591884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_smoke.646478731
Short name T351
Test name
Test status
Simulation time 473251065 ps
CPU time 2.1 seconds
Started Sep 01 06:27:33 AM UTC 24
Finished Sep 01 06:27:36 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646478731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.uart_smoke.646478731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.431214046
Short name T304
Test name
Test status
Simulation time 9868771219 ps
CPU time 16.66 seconds
Started Sep 01 06:27:43 AM UTC 24
Finished Sep 01 06:28:01 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431214046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.431214046
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/10.uart_tx_rx.1473357873
Short name T258
Test name
Test status
Simulation time 92607930548 ps
CPU time 95.32 seconds
Started Sep 01 06:27:34 AM UTC 24
Finished Sep 01 06:29:12 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473357873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1473357873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/10.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/100.uart_fifo_reset.1099336577
Short name T1043
Test name
Test status
Simulation time 41571121978 ps
CPU time 98.46 seconds
Started Sep 01 06:51:41 AM UTC 24
Finished Sep 01 06:53:22 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099336577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1099336577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/100.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/101.uart_fifo_reset.3450373038
Short name T1188
Test name
Test status
Simulation time 144009295039 ps
CPU time 1093.86 seconds
Started Sep 01 06:51:43 AM UTC 24
Finished Sep 01 07:10:10 AM UTC 24
Peak memory 212148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450373038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3450373038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/101.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/102.uart_fifo_reset.3747988953
Short name T1018
Test name
Test status
Simulation time 36760269046 ps
CPU time 39.49 seconds
Started Sep 01 06:51:43 AM UTC 24
Finished Sep 01 06:52:24 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747988953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3747988953
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/102.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/103.uart_fifo_reset.1600093992
Short name T221
Test name
Test status
Simulation time 132680217004 ps
CPU time 57.63 seconds
Started Sep 01 06:51:43 AM UTC 24
Finished Sep 01 06:52:43 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600093992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1600093992
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/103.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/104.uart_fifo_reset.1794335158
Short name T1044
Test name
Test status
Simulation time 39902759723 ps
CPU time 94.84 seconds
Started Sep 01 06:51:45 AM UTC 24
Finished Sep 01 06:53:22 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794335158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1794335158
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/104.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/106.uart_fifo_reset.2548897896
Short name T1050
Test name
Test status
Simulation time 170470307372 ps
CPU time 119.57 seconds
Started Sep 01 06:51:48 AM UTC 24
Finished Sep 01 06:53:50 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548897896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2548897896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/106.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/107.uart_fifo_reset.268209364
Short name T1146
Test name
Test status
Simulation time 195340728941 ps
CPU time 386.14 seconds
Started Sep 01 06:51:48 AM UTC 24
Finished Sep 01 06:58:19 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268209364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.268209364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/107.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/108.uart_fifo_reset.101332622
Short name T1030
Test name
Test status
Simulation time 73452144880 ps
CPU time 62.75 seconds
Started Sep 01 06:51:49 AM UTC 24
Finished Sep 01 06:52:54 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101332622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.101332622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/108.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/109.uart_fifo_reset.3836461196
Short name T255
Test name
Test status
Simulation time 28019714262 ps
CPU time 54.13 seconds
Started Sep 01 06:51:51 AM UTC 24
Finished Sep 01 06:52:47 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836461196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3836461196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/109.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_alert_test.3743705942
Short name T467
Test name
Test status
Simulation time 22608348 ps
CPU time 0.83 seconds
Started Sep 01 06:28:13 AM UTC 24
Finished Sep 01 06:28:15 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743705942 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3743705942
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_fifo_full.668490634
Short name T124
Test name
Test status
Simulation time 26722686704 ps
CPU time 27.92 seconds
Started Sep 01 06:27:57 AM UTC 24
Finished Sep 01 06:28:26 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668490634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.668490634
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.2341590475
Short name T95
Test name
Test status
Simulation time 36078468889 ps
CPU time 34.31 seconds
Started Sep 01 06:27:59 AM UTC 24
Finished Sep 01 06:28:35 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341590475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2341590475
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_intr.849552244
Short name T411
Test name
Test status
Simulation time 24583868415 ps
CPU time 33.06 seconds
Started Sep 01 06:28:02 AM UTC 24
Finished Sep 01 06:28:37 AM UTC 24
Peak memory 207140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849552244 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.849552244
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.829170626
Short name T393
Test name
Test status
Simulation time 66597571163 ps
CPU time 147.72 seconds
Started Sep 01 06:28:08 AM UTC 24
Finished Sep 01 06:30:38 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829170626 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.829170626
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_loopback.3814243838
Short name T469
Test name
Test status
Simulation time 8060470249 ps
CPU time 27.04 seconds
Started Sep 01 06:28:06 AM UTC 24
Finished Sep 01 06:28:35 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814243838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.3814243838
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_noise_filter.2369553519
Short name T326
Test name
Test status
Simulation time 26896872843 ps
CPU time 74.07 seconds
Started Sep 01 06:28:02 AM UTC 24
Finished Sep 01 06:29:18 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369553519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2369553519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_perf.1693545167
Short name T399
Test name
Test status
Simulation time 18516282432 ps
CPU time 308.86 seconds
Started Sep 01 06:28:08 AM UTC 24
Finished Sep 01 06:33:21 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693545167 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1693545167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_rx_oversample.3288156344
Short name T466
Test name
Test status
Simulation time 2114166433 ps
CPU time 4.74 seconds
Started Sep 01 06:28:01 AM UTC 24
Finished Sep 01 06:28:07 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288156344 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3288156344
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.880826138
Short name T328
Test name
Test status
Simulation time 76339654222 ps
CPU time 88.44 seconds
Started Sep 01 06:28:02 AM UTC 24
Finished Sep 01 06:29:33 AM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880826138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.880826138
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.1839569789
Short name T377
Test name
Test status
Simulation time 3163222275 ps
CPU time 12.49 seconds
Started Sep 01 06:28:02 AM UTC 24
Finished Sep 01 06:28:16 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839569789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1839569789
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_smoke.2061195786
Short name T343
Test name
Test status
Simulation time 500837185 ps
CPU time 2.38 seconds
Started Sep 01 06:27:55 AM UTC 24
Finished Sep 01 06:27:58 AM UTC 24
Peak memory 208108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061195786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2061195786
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_stress_all.2825989467
Short name T646
Test name
Test status
Simulation time 11688576604 ps
CPU time 638.5 seconds
Started Sep 01 06:28:09 AM UTC 24
Finished Sep 01 06:38:55 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825989467 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2825989467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.3515475128
Short name T341
Test name
Test status
Simulation time 3730483868 ps
CPU time 21.93 seconds
Started Sep 01 06:28:09 AM UTC 24
Finished Sep 01 06:28:32 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3515475128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all
_with_rand_reset.3515475128
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.2757225808
Short name T383
Test name
Test status
Simulation time 1070175963 ps
CPU time 1.58 seconds
Started Sep 01 06:28:05 AM UTC 24
Finished Sep 01 06:28:08 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757225808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.2757225808
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/110.uart_fifo_reset.2491654244
Short name T1022
Test name
Test status
Simulation time 44652945267 ps
CPU time 40.04 seconds
Started Sep 01 06:51:52 AM UTC 24
Finished Sep 01 06:52:34 AM UTC 24
Peak memory 208492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491654244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2491654244
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/110.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/111.uart_fifo_reset.1521364489
Short name T244
Test name
Test status
Simulation time 10568858931 ps
CPU time 35.62 seconds
Started Sep 01 06:51:55 AM UTC 24
Finished Sep 01 06:52:32 AM UTC 24
Peak memory 208288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521364489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1521364489
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/111.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/114.uart_fifo_reset.1014673785
Short name T1039
Test name
Test status
Simulation time 166105613256 ps
CPU time 64.13 seconds
Started Sep 01 06:52:03 AM UTC 24
Finished Sep 01 06:53:09 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014673785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1014673785
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/114.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/116.uart_fifo_reset.3349916162
Short name T189
Test name
Test status
Simulation time 61865735556 ps
CPU time 41.71 seconds
Started Sep 01 06:52:08 AM UTC 24
Finished Sep 01 06:52:51 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349916162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.3349916162
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/116.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/117.uart_fifo_reset.463957273
Short name T1113
Test name
Test status
Simulation time 246801564496 ps
CPU time 279.94 seconds
Started Sep 01 06:52:09 AM UTC 24
Finished Sep 01 06:56:53 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463957273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.463957273
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/117.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/118.uart_fifo_reset.2681640462
Short name T1031
Test name
Test status
Simulation time 39183883952 ps
CPU time 43.48 seconds
Started Sep 01 06:52:11 AM UTC 24
Finished Sep 01 06:52:56 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681640462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2681640462
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/118.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/119.uart_fifo_reset.1662544729
Short name T208
Test name
Test status
Simulation time 25910737681 ps
CPU time 64.08 seconds
Started Sep 01 06:52:11 AM UTC 24
Finished Sep 01 06:53:17 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662544729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1662544729
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/119.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_alert_test.2605736239
Short name T471
Test name
Test status
Simulation time 14153811 ps
CPU time 0.85 seconds
Started Sep 01 06:28:38 AM UTC 24
Finished Sep 01 06:28:40 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605736239 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.2605736239
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_fifo_full.2332112167
Short name T310
Test name
Test status
Simulation time 28061426724 ps
CPU time 34.65 seconds
Started Sep 01 06:28:17 AM UTC 24
Finished Sep 01 06:28:53 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332112167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2332112167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.1582573378
Short name T148
Test name
Test status
Simulation time 7815973928 ps
CPU time 17.74 seconds
Started Sep 01 06:28:20 AM UTC 24
Finished Sep 01 06:28:39 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582573378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.1582573378
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_fifo_reset.1287495081
Short name T373
Test name
Test status
Simulation time 100356143180 ps
CPU time 65.5 seconds
Started Sep 01 06:28:21 AM UTC 24
Finished Sep 01 06:29:28 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287495081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1287495081
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_intr.136303904
Short name T96
Test name
Test status
Simulation time 24334946593 ps
CPU time 13.2 seconds
Started Sep 01 06:28:23 AM UTC 24
Finished Sep 01 06:28:38 AM UTC 24
Peak memory 208744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136303904 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.136303904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.1248477505
Short name T533
Test name
Test status
Simulation time 76816083834 ps
CPU time 319.47 seconds
Started Sep 01 06:28:36 AM UTC 24
Finished Sep 01 06:34:00 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248477505 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1248477505
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_loopback.1284790373
Short name T474
Test name
Test status
Simulation time 5845838538 ps
CPU time 24.16 seconds
Started Sep 01 06:28:33 AM UTC 24
Finished Sep 01 06:28:58 AM UTC 24
Peak memory 207636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284790373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1284790373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_noise_filter.1812325131
Short name T294
Test name
Test status
Simulation time 194917670170 ps
CPU time 82.65 seconds
Started Sep 01 06:28:26 AM UTC 24
Finished Sep 01 06:29:50 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812325131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1812325131
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_perf.2715923414
Short name T669
Test name
Test status
Simulation time 13102507816 ps
CPU time 672.24 seconds
Started Sep 01 06:28:35 AM UTC 24
Finished Sep 01 06:39:55 AM UTC 24
Peak memory 212144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715923414 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.2715923414
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_rx_oversample.284546095
Short name T470
Test name
Test status
Simulation time 2543346416 ps
CPU time 16.52 seconds
Started Sep 01 06:28:22 AM UTC 24
Finished Sep 01 06:28:40 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284546095 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.284546095
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.938910605
Short name T645
Test name
Test status
Simulation time 113921805530 ps
CPU time 620.33 seconds
Started Sep 01 06:28:27 AM UTC 24
Finished Sep 01 06:38:55 AM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938910605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.938910605
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.66490951
Short name T362
Test name
Test status
Simulation time 4408398298 ps
CPU time 4.54 seconds
Started Sep 01 06:28:27 AM UTC 24
Finished Sep 01 06:28:32 AM UTC 24
Peak memory 207280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66490951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.66490951
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_smoke.4122421114
Short name T379
Test name
Test status
Simulation time 642040727 ps
CPU time 2.11 seconds
Started Sep 01 06:28:16 AM UTC 24
Finished Sep 01 06:28:19 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122421114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4122421114
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.50460220
Short name T398
Test name
Test status
Simulation time 1367168259 ps
CPU time 2.54 seconds
Started Sep 01 06:28:33 AM UTC 24
Finished Sep 01 06:28:36 AM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50460220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.50460220
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/121.uart_fifo_reset.300934852
Short name T1026
Test name
Test status
Simulation time 33851592597 ps
CPU time 36.66 seconds
Started Sep 01 06:52:13 AM UTC 24
Finished Sep 01 06:52:51 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300934852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.300934852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/121.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/122.uart_fifo_reset.2167533985
Short name T1040
Test name
Test status
Simulation time 41622740200 ps
CPU time 52.62 seconds
Started Sep 01 06:52:15 AM UTC 24
Finished Sep 01 06:53:09 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167533985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2167533985
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/122.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/123.uart_fifo_reset.3698048378
Short name T146
Test name
Test status
Simulation time 141767223183 ps
CPU time 77.21 seconds
Started Sep 01 06:52:19 AM UTC 24
Finished Sep 01 06:53:38 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698048378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3698048378
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/123.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/124.uart_fifo_reset.1380827099
Short name T213
Test name
Test status
Simulation time 103498014247 ps
CPU time 205.84 seconds
Started Sep 01 06:52:20 AM UTC 24
Finished Sep 01 06:55:49 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380827099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1380827099
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/124.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/126.uart_fifo_reset.2957142842
Short name T984
Test name
Test status
Simulation time 23941364005 ps
CPU time 57.92 seconds
Started Sep 01 06:52:25 AM UTC 24
Finished Sep 01 06:53:25 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957142842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2957142842
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/126.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/127.uart_fifo_reset.977703253
Short name T1028
Test name
Test status
Simulation time 134357698352 ps
CPU time 24.08 seconds
Started Sep 01 06:52:27 AM UTC 24
Finished Sep 01 06:52:52 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977703253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.977703253
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/127.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/128.uart_fifo_reset.2854179421
Short name T1038
Test name
Test status
Simulation time 37869378161 ps
CPU time 34.33 seconds
Started Sep 01 06:52:28 AM UTC 24
Finished Sep 01 06:53:03 AM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854179421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2854179421
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/128.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/129.uart_fifo_reset.2845633892
Short name T443
Test name
Test status
Simulation time 110415614399 ps
CPU time 64.09 seconds
Started Sep 01 06:52:32 AM UTC 24
Finished Sep 01 06:53:37 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845633892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2845633892
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/129.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_alert_test.108251767
Short name T475
Test name
Test status
Simulation time 13084447 ps
CPU time 0.84 seconds
Started Sep 01 06:29:12 AM UTC 24
Finished Sep 01 06:29:14 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108251767 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.108251767
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_fifo_full.2775250454
Short name T279
Test name
Test status
Simulation time 20747518107 ps
CPU time 37.13 seconds
Started Sep 01 06:28:41 AM UTC 24
Finished Sep 01 06:29:19 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775250454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2775250454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_fifo_reset.1740548635
Short name T117
Test name
Test status
Simulation time 30833056942 ps
CPU time 32.17 seconds
Started Sep 01 06:28:42 AM UTC 24
Finished Sep 01 06:29:15 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740548635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1740548635
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_intr.2364336938
Short name T277
Test name
Test status
Simulation time 11244669575 ps
CPU time 19.54 seconds
Started Sep 01 06:28:43 AM UTC 24
Finished Sep 01 06:29:04 AM UTC 24
Peak memory 208460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364336938 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2364336938
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.1695441446
Short name T983
Test name
Test status
Simulation time 115019092794 ps
CPU time 1320.71 seconds
Started Sep 01 06:29:04 AM UTC 24
Finished Sep 01 06:51:20 AM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695441446 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1695441446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_loopback.1506160351
Short name T476
Test name
Test status
Simulation time 6935604518 ps
CPU time 19.54 seconds
Started Sep 01 06:28:59 AM UTC 24
Finished Sep 01 06:29:20 AM UTC 24
Peak memory 207884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506160351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1506160351
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_noise_filter.2993067309
Short name T410
Test name
Test status
Simulation time 112924705568 ps
CPU time 150.06 seconds
Started Sep 01 06:28:53 AM UTC 24
Finished Sep 01 06:31:26 AM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993067309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2993067309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_perf.3834461213
Short name T370
Test name
Test status
Simulation time 7754076126 ps
CPU time 100.09 seconds
Started Sep 01 06:29:02 AM UTC 24
Finished Sep 01 06:30:45 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834461213 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3834461213
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_rx_oversample.98508315
Short name T473
Test name
Test status
Simulation time 4648941730 ps
CPU time 9.76 seconds
Started Sep 01 06:28:42 AM UTC 24
Finished Sep 01 06:28:53 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98508315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.98508315
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.3332443446
Short name T291
Test name
Test status
Simulation time 4717203006 ps
CPU time 11.1 seconds
Started Sep 01 06:28:54 AM UTC 24
Finished Sep 01 06:29:06 AM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332443446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3332443446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_smoke.3504240287
Short name T322
Test name
Test status
Simulation time 869033431 ps
CPU time 3.12 seconds
Started Sep 01 06:28:38 AM UTC 24
Finished Sep 01 06:28:42 AM UTC 24
Peak memory 208404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504240287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3504240287
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.4149990143
Short name T86
Test name
Test status
Simulation time 6828682039 ps
CPU time 46.87 seconds
Started Sep 01 06:29:05 AM UTC 24
Finished Sep 01 06:29:53 AM UTC 24
Peak memory 219860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4149990143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all
_with_rand_reset.4149990143
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.3027570464
Short name T327
Test name
Test status
Simulation time 7365938218 ps
CPU time 37.85 seconds
Started Sep 01 06:28:58 AM UTC 24
Finished Sep 01 06:29:37 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027570464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3027570464
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/13.uart_tx_rx.2942581480
Short name T339
Test name
Test status
Simulation time 102062282240 ps
CPU time 243.19 seconds
Started Sep 01 06:28:39 AM UTC 24
Finished Sep 01 06:32:46 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942581480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2942581480
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/13.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/130.uart_fifo_reset.3807190188
Short name T222
Test name
Test status
Simulation time 37397782263 ps
CPU time 31.79 seconds
Started Sep 01 06:52:33 AM UTC 24
Finished Sep 01 06:53:06 AM UTC 24
Peak memory 208584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807190188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3807190188
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/130.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/132.uart_fifo_reset.35324726
Short name T1034
Test name
Test status
Simulation time 11343975705 ps
CPU time 23.94 seconds
Started Sep 01 06:52:33 AM UTC 24
Finished Sep 01 06:52:58 AM UTC 24
Peak memory 207944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35324726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.35324726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/132.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/133.uart_fifo_reset.883625056
Short name T1027
Test name
Test status
Simulation time 4840824818 ps
CPU time 15.99 seconds
Started Sep 01 06:52:34 AM UTC 24
Finished Sep 01 06:52:51 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883625056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.883625056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/133.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/135.uart_fifo_reset.324656722
Short name T155
Test name
Test status
Simulation time 47420562747 ps
CPU time 34.43 seconds
Started Sep 01 06:52:37 AM UTC 24
Finished Sep 01 06:53:13 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324656722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.324656722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/135.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/136.uart_fifo_reset.3777899377
Short name T434
Test name
Test status
Simulation time 83275445987 ps
CPU time 77.46 seconds
Started Sep 01 06:52:37 AM UTC 24
Finished Sep 01 06:53:56 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777899377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3777899377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/136.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/137.uart_fifo_reset.3808973703
Short name T1036
Test name
Test status
Simulation time 7313647114 ps
CPU time 22.29 seconds
Started Sep 01 06:52:38 AM UTC 24
Finished Sep 01 06:53:02 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808973703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3808973703
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/137.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/138.uart_fifo_reset.1576904211
Short name T249
Test name
Test status
Simulation time 214698822650 ps
CPU time 235.45 seconds
Started Sep 01 06:52:43 AM UTC 24
Finished Sep 01 06:56:42 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576904211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1576904211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/138.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/139.uart_fifo_reset.1340644081
Short name T1041
Test name
Test status
Simulation time 29543591921 ps
CPU time 25.45 seconds
Started Sep 01 06:52:45 AM UTC 24
Finished Sep 01 06:53:11 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340644081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1340644081
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/139.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_alert_test.3522933538
Short name T478
Test name
Test status
Simulation time 26102815 ps
CPU time 0.86 seconds
Started Sep 01 06:29:30 AM UTC 24
Finished Sep 01 06:29:32 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522933538 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3522933538
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_fifo_full.1180011306
Short name T412
Test name
Test status
Simulation time 242956720477 ps
CPU time 68.61 seconds
Started Sep 01 06:29:14 AM UTC 24
Finished Sep 01 06:30:24 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180011306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1180011306
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1777271314
Short name T697
Test name
Test status
Simulation time 87304756730 ps
CPU time 697.37 seconds
Started Sep 01 06:29:14 AM UTC 24
Finished Sep 01 06:41:00 AM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777271314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1777271314
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_fifo_reset.4135826249
Short name T200
Test name
Test status
Simulation time 49285197320 ps
CPU time 20.49 seconds
Started Sep 01 06:29:14 AM UTC 24
Finished Sep 01 06:29:36 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135826249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.4135826249
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_intr.2933512370
Short name T395
Test name
Test status
Simulation time 36760110509 ps
CPU time 39.95 seconds
Started Sep 01 06:29:15 AM UTC 24
Finished Sep 01 06:29:57 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933512370 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2933512370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.3082970682
Short name T834
Test name
Test status
Simulation time 137268180539 ps
CPU time 923.59 seconds
Started Sep 01 06:29:29 AM UTC 24
Finished Sep 01 06:45:04 AM UTC 24
Peak memory 212228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082970682 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3082970682
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_loopback.2190502007
Short name T477
Test name
Test status
Simulation time 4238090068 ps
CPU time 7.86 seconds
Started Sep 01 06:29:21 AM UTC 24
Finished Sep 01 06:29:30 AM UTC 24
Peak memory 207604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190502007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2190502007
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_noise_filter.1176392894
Short name T397
Test name
Test status
Simulation time 49614851037 ps
CPU time 39 seconds
Started Sep 01 06:29:16 AM UTC 24
Finished Sep 01 06:29:57 AM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176392894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1176392894
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_perf.3192607394
Short name T488
Test name
Test status
Simulation time 12439835320 ps
CPU time 82.28 seconds
Started Sep 01 06:29:22 AM UTC 24
Finished Sep 01 06:30:46 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192607394 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3192607394
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_rx_oversample.1887459777
Short name T484
Test name
Test status
Simulation time 6757156734 ps
CPU time 51.8 seconds
Started Sep 01 06:29:15 AM UTC 24
Finished Sep 01 06:30:08 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887459777 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1887459777
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.86923870
Short name T403
Test name
Test status
Simulation time 22606999268 ps
CPU time 19.6 seconds
Started Sep 01 06:29:19 AM UTC 24
Finished Sep 01 06:29:39 AM UTC 24
Peak memory 208464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86923870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.86923870
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.4217484473
Short name T401
Test name
Test status
Simulation time 481580483 ps
CPU time 1.94 seconds
Started Sep 01 06:29:18 AM UTC 24
Finished Sep 01 06:29:21 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217484473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.4217484473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_smoke.2696687835
Short name T415
Test name
Test status
Simulation time 108039595 ps
CPU time 1.16 seconds
Started Sep 01 06:29:12 AM UTC 24
Finished Sep 01 06:29:14 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696687835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.2696687835
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.3995557006
Short name T367
Test name
Test status
Simulation time 9474871820 ps
CPU time 12.91 seconds
Started Sep 01 06:29:20 AM UTC 24
Finished Sep 01 06:29:34 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995557006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3995557006
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/14.uart_tx_rx.1732815461
Short name T301
Test name
Test status
Simulation time 30323676636 ps
CPU time 30.25 seconds
Started Sep 01 06:29:13 AM UTC 24
Finished Sep 01 06:29:44 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732815461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1732815461
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/14.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/140.uart_fifo_reset.631147814
Short name T1048
Test name
Test status
Simulation time 149757615076 ps
CPU time 50.89 seconds
Started Sep 01 06:52:48 AM UTC 24
Finished Sep 01 06:53:40 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631147814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.631147814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/140.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/141.uart_fifo_reset.2687970971
Short name T430
Test name
Test status
Simulation time 9840891392 ps
CPU time 23.92 seconds
Started Sep 01 06:52:51 AM UTC 24
Finished Sep 01 06:53:16 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687970971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2687970971
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/141.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/142.uart_fifo_reset.1581623587
Short name T1057
Test name
Test status
Simulation time 204278184242 ps
CPU time 74.54 seconds
Started Sep 01 06:52:52 AM UTC 24
Finished Sep 01 06:54:08 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581623587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1581623587
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/142.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/143.uart_fifo_reset.4041698184
Short name T1069
Test name
Test status
Simulation time 197667320946 ps
CPU time 115.38 seconds
Started Sep 01 06:52:52 AM UTC 24
Finished Sep 01 06:54:49 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041698184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.4041698184
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/143.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/144.uart_fifo_reset.286097570
Short name T1063
Test name
Test status
Simulation time 52994775538 ps
CPU time 107.8 seconds
Started Sep 01 06:52:52 AM UTC 24
Finished Sep 01 06:54:42 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286097570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.286097570
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/144.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/145.uart_fifo_reset.61279519
Short name T1176
Test name
Test status
Simulation time 226240590146 ps
CPU time 426.66 seconds
Started Sep 01 06:52:53 AM UTC 24
Finished Sep 01 07:00:05 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61279519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.61279519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/145.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/146.uart_fifo_reset.144287770
Short name T1185
Test name
Test status
Simulation time 221273053479 ps
CPU time 790.78 seconds
Started Sep 01 06:52:53 AM UTC 24
Finished Sep 01 07:06:14 AM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144287770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.144287770
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/146.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/147.uart_fifo_reset.1980469022
Short name T1062
Test name
Test status
Simulation time 54363534096 ps
CPU time 103.31 seconds
Started Sep 01 06:52:54 AM UTC 24
Finished Sep 01 06:54:40 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980469022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.1980469022
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/147.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/148.uart_fifo_reset.4187183862
Short name T193
Test name
Test status
Simulation time 12542487742 ps
CPU time 33.6 seconds
Started Sep 01 06:52:54 AM UTC 24
Finished Sep 01 06:53:29 AM UTC 24
Peak memory 208868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187183862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.4187183862
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/148.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/149.uart_fifo_reset.3749660290
Short name T1083
Test name
Test status
Simulation time 128797651822 ps
CPU time 139.26 seconds
Started Sep 01 06:52:56 AM UTC 24
Finished Sep 01 06:55:18 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749660290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3749660290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/149.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_alert_test.4234830066
Short name T482
Test name
Test status
Simulation time 81543482 ps
CPU time 0.81 seconds
Started Sep 01 06:29:59 AM UTC 24
Finished Sep 01 06:30:00 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234830066 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4234830066
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_fifo_full.278925732
Short name T407
Test name
Test status
Simulation time 109827904971 ps
CPU time 41.63 seconds
Started Sep 01 06:29:34 AM UTC 24
Finished Sep 01 06:30:18 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278925732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.278925732
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.3084924160
Short name T122
Test name
Test status
Simulation time 40512935436 ps
CPU time 40.87 seconds
Started Sep 01 06:29:36 AM UTC 24
Finished Sep 01 06:30:19 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084924160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3084924160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_fifo_reset.55537636
Short name T183
Test name
Test status
Simulation time 44299657431 ps
CPU time 86.24 seconds
Started Sep 01 06:29:38 AM UTC 24
Finished Sep 01 06:31:06 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55537636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.55537636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_intr.4036163526
Short name T368
Test name
Test status
Simulation time 29888377278 ps
CPU time 46.34 seconds
Started Sep 01 06:29:41 AM UTC 24
Finished Sep 01 06:30:29 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036163526 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.4036163526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.4006358199
Short name T658
Test name
Test status
Simulation time 109517746932 ps
CPU time 570.85 seconds
Started Sep 01 06:29:57 AM UTC 24
Finished Sep 01 06:39:36 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006358199 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.4006358199
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_loopback.2848040089
Short name T481
Test name
Test status
Simulation time 3695599258 ps
CPU time 4.58 seconds
Started Sep 01 06:29:54 AM UTC 24
Finished Sep 01 06:30:00 AM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848040089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2848040089
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_noise_filter.3430556842
Short name T363
Test name
Test status
Simulation time 3397129733 ps
CPU time 14.72 seconds
Started Sep 01 06:29:45 AM UTC 24
Finished Sep 01 06:30:01 AM UTC 24
Peak memory 207500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430556842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3430556842
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_perf.1106809408
Short name T546
Test name
Test status
Simulation time 16668288865 ps
CPU time 273.62 seconds
Started Sep 01 06:29:57 AM UTC 24
Finished Sep 01 06:34:35 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106809408 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1106809408
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_rx_oversample.3558678405
Short name T480
Test name
Test status
Simulation time 5005482425 ps
CPU time 16.19 seconds
Started Sep 01 06:29:39 AM UTC 24
Finished Sep 01 06:29:56 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558678405 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3558678405
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.4212648094
Short name T357
Test name
Test status
Simulation time 8638787886 ps
CPU time 32.04 seconds
Started Sep 01 06:29:51 AM UTC 24
Finished Sep 01 06:30:25 AM UTC 24
Peak memory 208508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212648094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4212648094
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.2345953301
Short name T479
Test name
Test status
Simulation time 4251629203 ps
CPU time 4.98 seconds
Started Sep 01 06:29:46 AM UTC 24
Finished Sep 01 06:29:52 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345953301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2345953301
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_smoke.1339313159
Short name T299
Test name
Test status
Simulation time 756168912 ps
CPU time 1.67 seconds
Started Sep 01 06:29:33 AM UTC 24
Finished Sep 01 06:29:36 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339313159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1339313159
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_stress_all.1563028026
Short name T704
Test name
Test status
Simulation time 329870664458 ps
CPU time 667.03 seconds
Started Sep 01 06:29:57 AM UTC 24
Finished Sep 01 06:41:12 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563028026 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1563028026
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.150522448
Short name T87
Test name
Test status
Simulation time 1402234840 ps
CPU time 12.59 seconds
Started Sep 01 06:29:57 AM UTC 24
Finished Sep 01 06:30:11 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=150522448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all_
with_rand_reset.150522448
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.70734404
Short name T375
Test name
Test status
Simulation time 1380021167 ps
CPU time 2.4 seconds
Started Sep 01 06:29:53 AM UTC 24
Finished Sep 01 06:29:57 AM UTC 24
Peak memory 207088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70734404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.70734404
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/15.uart_tx_rx.4287098165
Short name T337
Test name
Test status
Simulation time 5599545657 ps
CPU time 10.49 seconds
Started Sep 01 06:29:33 AM UTC 24
Finished Sep 01 06:29:45 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287098165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.4287098165
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/15.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/150.uart_fifo_reset.2099155800
Short name T227
Test name
Test status
Simulation time 45896463006 ps
CPU time 91.41 seconds
Started Sep 01 06:52:56 AM UTC 24
Finished Sep 01 06:54:30 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099155800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2099155800
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/150.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/151.uart_fifo_reset.2804761131
Short name T228
Test name
Test status
Simulation time 20146458163 ps
CPU time 41.81 seconds
Started Sep 01 06:52:58 AM UTC 24
Finished Sep 01 06:53:41 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804761131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2804761131
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/151.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/153.uart_fifo_reset.3145553468
Short name T1150
Test name
Test status
Simulation time 147221664813 ps
CPU time 325.79 seconds
Started Sep 01 06:53:02 AM UTC 24
Finished Sep 01 06:58:32 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145553468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.3145553468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/153.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/154.uart_fifo_reset.1238777889
Short name T1078
Test name
Test status
Simulation time 94095887423 ps
CPU time 122.98 seconds
Started Sep 01 06:53:03 AM UTC 24
Finished Sep 01 06:55:08 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238777889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1238777889
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/154.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/155.uart_fifo_reset.301570578
Short name T1051
Test name
Test status
Simulation time 128280711497 ps
CPU time 46.31 seconds
Started Sep 01 06:53:03 AM UTC 24
Finished Sep 01 06:53:51 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301570578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.301570578
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/155.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/156.uart_fifo_reset.1172039164
Short name T201
Test name
Test status
Simulation time 21625072236 ps
CPU time 61.66 seconds
Started Sep 01 06:53:03 AM UTC 24
Finished Sep 01 06:54:06 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172039164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1172039164
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/156.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/157.uart_fifo_reset.980300792
Short name T1045
Test name
Test status
Simulation time 8529193175 ps
CPU time 24.86 seconds
Started Sep 01 06:53:04 AM UTC 24
Finished Sep 01 06:53:30 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980300792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.980300792
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/157.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/158.uart_fifo_reset.3531350048
Short name T1053
Test name
Test status
Simulation time 14192401187 ps
CPU time 49.41 seconds
Started Sep 01 06:53:07 AM UTC 24
Finished Sep 01 06:53:58 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531350048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3531350048
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/158.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/159.uart_fifo_reset.858585254
Short name T245
Test name
Test status
Simulation time 17133753513 ps
CPU time 35.25 seconds
Started Sep 01 06:53:10 AM UTC 24
Finished Sep 01 06:53:47 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858585254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.858585254
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/159.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_alert_test.213912648
Short name T486
Test name
Test status
Simulation time 41619525 ps
CPU time 0.85 seconds
Started Sep 01 06:30:30 AM UTC 24
Finished Sep 01 06:30:32 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213912648 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.213912648
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_fifo_full.2770849377
Short name T129
Test name
Test status
Simulation time 115637793521 ps
CPU time 159.34 seconds
Started Sep 01 06:30:02 AM UTC 24
Finished Sep 01 06:32:44 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770849377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2770849377
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.624908003
Short name T312
Test name
Test status
Simulation time 145724295661 ps
CPU time 113.86 seconds
Started Sep 01 06:30:02 AM UTC 24
Finished Sep 01 06:31:58 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624908003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.624908003
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_fifo_reset.3577378092
Short name T206
Test name
Test status
Simulation time 143829801103 ps
CPU time 95.63 seconds
Started Sep 01 06:30:05 AM UTC 24
Finished Sep 01 06:31:43 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577378092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3577378092
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_intr.1242606911
Short name T516
Test name
Test status
Simulation time 222158607373 ps
CPU time 147.24 seconds
Started Sep 01 06:30:12 AM UTC 24
Finished Sep 01 06:32:42 AM UTC 24
Peak memory 208360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242606911 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1242606911
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.3424988049
Short name T720
Test name
Test status
Simulation time 240158920397 ps
CPU time 657.56 seconds
Started Sep 01 06:30:26 AM UTC 24
Finished Sep 01 06:41:31 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424988049 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.3424988049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_loopback.2650351392
Short name T485
Test name
Test status
Simulation time 6465851156 ps
CPU time 6.38 seconds
Started Sep 01 06:30:22 AM UTC 24
Finished Sep 01 06:30:29 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650351392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2650351392
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_noise_filter.1382119076
Short name T496
Test name
Test status
Simulation time 31511480226 ps
CPU time 48.6 seconds
Started Sep 01 06:30:18 AM UTC 24
Finished Sep 01 06:31:08 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382119076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.1382119076
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_perf.1765465121
Short name T502
Test name
Test status
Simulation time 7081751966 ps
CPU time 88.16 seconds
Started Sep 01 06:30:25 AM UTC 24
Finished Sep 01 06:31:55 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765465121 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1765465121
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_rx_oversample.2473602727
Short name T491
Test name
Test status
Simulation time 4654256859 ps
CPU time 50.03 seconds
Started Sep 01 06:30:09 AM UTC 24
Finished Sep 01 06:31:01 AM UTC 24
Peak memory 207480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473602727 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2473602727
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.3478149672
Short name T414
Test name
Test status
Simulation time 24328584594 ps
CPU time 27.75 seconds
Started Sep 01 06:30:19 AM UTC 24
Finished Sep 01 06:30:48 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478149672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3478149672
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.1286651809
Short name T487
Test name
Test status
Simulation time 40546450754 ps
CPU time 22.12 seconds
Started Sep 01 06:30:18 AM UTC 24
Finished Sep 01 06:30:42 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286651809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1286651809
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_smoke.3003709802
Short name T483
Test name
Test status
Simulation time 452025303 ps
CPU time 2.89 seconds
Started Sep 01 06:30:01 AM UTC 24
Finished Sep 01 06:30:05 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003709802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3003709802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_stress_all.1005824222
Short name T897
Test name
Test status
Simulation time 153394996126 ps
CPU time 1020.45 seconds
Started Sep 01 06:30:30 AM UTC 24
Finished Sep 01 06:47:42 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005824222 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1005824222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.3548894736
Short name T409
Test name
Test status
Simulation time 7575642827 ps
CPU time 54.62 seconds
Started Sep 01 06:30:30 AM UTC 24
Finished Sep 01 06:31:26 AM UTC 24
Peak memory 225268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3548894736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all
_with_rand_reset.3548894736
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.2709113779
Short name T389
Test name
Test status
Simulation time 6674145492 ps
CPU time 17.78 seconds
Started Sep 01 06:30:21 AM UTC 24
Finished Sep 01 06:30:39 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709113779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2709113779
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/16.uart_tx_rx.2267475275
Short name T360
Test name
Test status
Simulation time 23908881334 ps
CPU time 34.65 seconds
Started Sep 01 06:30:01 AM UTC 24
Finished Sep 01 06:30:37 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267475275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2267475275
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/16.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/160.uart_fifo_reset.758519679
Short name T1046
Test name
Test status
Simulation time 98755368784 ps
CPU time 21.18 seconds
Started Sep 01 06:53:10 AM UTC 24
Finished Sep 01 06:53:33 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758519679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.758519679
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/160.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2520852757
Short name T1143
Test name
Test status
Simulation time 170648864127 ps
CPU time 291.94 seconds
Started Sep 01 06:53:13 AM UTC 24
Finished Sep 01 06:58:09 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520852757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2520852757
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/162.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/163.uart_fifo_reset.538820438
Short name T241
Test name
Test status
Simulation time 107819334222 ps
CPU time 74.75 seconds
Started Sep 01 06:53:17 AM UTC 24
Finished Sep 01 06:54:33 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538820438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.538820438
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/163.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/164.uart_fifo_reset.2400409374
Short name T1054
Test name
Test status
Simulation time 22920749343 ps
CPU time 43.24 seconds
Started Sep 01 06:53:18 AM UTC 24
Finished Sep 01 06:54:02 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400409374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2400409374
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/164.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/165.uart_fifo_reset.231303630
Short name T225
Test name
Test status
Simulation time 85140611545 ps
CPU time 22.85 seconds
Started Sep 01 06:53:22 AM UTC 24
Finished Sep 01 06:53:46 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231303630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.231303630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/165.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/166.uart_fifo_reset.3274527234
Short name T1061
Test name
Test status
Simulation time 13362994130 ps
CPU time 64.47 seconds
Started Sep 01 06:53:23 AM UTC 24
Finished Sep 01 06:54:29 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274527234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3274527234
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/166.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/168.uart_fifo_reset.158475499
Short name T251
Test name
Test status
Simulation time 65430811350 ps
CPU time 64.05 seconds
Started Sep 01 06:53:26 AM UTC 24
Finished Sep 01 06:54:32 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158475499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.158475499
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/168.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_alert_test.782361097
Short name T493
Test name
Test status
Simulation time 40325086 ps
CPU time 0.68 seconds
Started Sep 01 06:31:01 AM UTC 24
Finished Sep 01 06:31:02 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782361097 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.782361097
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_fifo_full.3522302706
Short name T394
Test name
Test status
Simulation time 42276075578 ps
CPU time 31.62 seconds
Started Sep 01 06:30:37 AM UTC 24
Finished Sep 01 06:31:10 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522302706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3522302706
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_intr.2753892914
Short name T495
Test name
Test status
Simulation time 8659857022 ps
CPU time 20.73 seconds
Started Sep 01 06:30:46 AM UTC 24
Finished Sep 01 06:31:08 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753892914 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2753892914
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.1813476002
Short name T691
Test name
Test status
Simulation time 69236614736 ps
CPU time 579.09 seconds
Started Sep 01 06:30:56 AM UTC 24
Finished Sep 01 06:40:43 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813476002 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1813476002
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_loopback.1448644576
Short name T494
Test name
Test status
Simulation time 9324416467 ps
CPU time 15.37 seconds
Started Sep 01 06:30:50 AM UTC 24
Finished Sep 01 06:31:07 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448644576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1448644576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_noise_filter.2466680730
Short name T380
Test name
Test status
Simulation time 138520288238 ps
CPU time 84.81 seconds
Started Sep 01 06:30:46 AM UTC 24
Finished Sep 01 06:32:12 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466680730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2466680730
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_perf.1343830997
Short name T531
Test name
Test status
Simulation time 18867927300 ps
CPU time 179.54 seconds
Started Sep 01 06:30:51 AM UTC 24
Finished Sep 01 06:33:54 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343830997 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1343830997
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_rx_oversample.2894168370
Short name T492
Test name
Test status
Simulation time 6475313247 ps
CPU time 18.29 seconds
Started Sep 01 06:30:43 AM UTC 24
Finished Sep 01 06:31:02 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894168370 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2894168370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.3184269636
Short name T490
Test name
Test status
Simulation time 3816547120 ps
CPU time 1.62 seconds
Started Sep 01 06:30:47 AM UTC 24
Finished Sep 01 06:30:49 AM UTC 24
Peak memory 204500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184269636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3184269636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_smoke.1649328004
Short name T319
Test name
Test status
Simulation time 6043741976 ps
CPU time 15.5 seconds
Started Sep 01 06:30:33 AM UTC 24
Finished Sep 01 06:30:50 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649328004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1649328004
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.3352599878
Short name T309
Test name
Test status
Simulation time 3508771998 ps
CPU time 24.25 seconds
Started Sep 01 06:30:57 AM UTC 24
Finished Sep 01 06:31:23 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3352599878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all
_with_rand_reset.3352599878
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.500639591
Short name T391
Test name
Test status
Simulation time 8124567493 ps
CPU time 11.43 seconds
Started Sep 01 06:30:49 AM UTC 24
Finished Sep 01 06:31:02 AM UTC 24
Peak memory 208568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500639591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.500639591
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/17.uart_tx_rx.2290931121
Short name T489
Test name
Test status
Simulation time 14704262389 ps
CPU time 11.65 seconds
Started Sep 01 06:30:33 AM UTC 24
Finished Sep 01 06:30:46 AM UTC 24
Peak memory 208516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290931121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2290931121
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/17.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/170.uart_fifo_reset.2128241836
Short name T1056
Test name
Test status
Simulation time 61985003707 ps
CPU time 34.35 seconds
Started Sep 01 06:53:30 AM UTC 24
Finished Sep 01 06:54:06 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128241836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2128241836
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/170.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/172.uart_fifo_reset.305102938
Short name T191
Test name
Test status
Simulation time 106891441045 ps
CPU time 111.43 seconds
Started Sep 01 06:53:33 AM UTC 24
Finished Sep 01 06:55:27 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305102938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.305102938
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/172.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/173.uart_fifo_reset.3261414750
Short name T1067
Test name
Test status
Simulation time 30636925702 ps
CPU time 70.02 seconds
Started Sep 01 06:53:36 AM UTC 24
Finished Sep 01 06:54:47 AM UTC 24
Peak memory 207592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261414750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.3261414750
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/173.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/174.uart_fifo_reset.1176303303
Short name T169
Test name
Test status
Simulation time 244435809662 ps
CPU time 51.2 seconds
Started Sep 01 06:53:39 AM UTC 24
Finished Sep 01 06:54:31 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176303303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1176303303
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/174.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/175.uart_fifo_reset.601364922
Short name T1089
Test name
Test status
Simulation time 52083590439 ps
CPU time 120.77 seconds
Started Sep 01 06:53:39 AM UTC 24
Finished Sep 01 06:55:42 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601364922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.601364922
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/175.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/176.uart_fifo_reset.2860689589
Short name T1098
Test name
Test status
Simulation time 76557478993 ps
CPU time 149.68 seconds
Started Sep 01 06:53:41 AM UTC 24
Finished Sep 01 06:56:13 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860689589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2860689589
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/176.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/177.uart_fifo_reset.3820926415
Short name T1079
Test name
Test status
Simulation time 210650513895 ps
CPU time 86.25 seconds
Started Sep 01 06:53:42 AM UTC 24
Finished Sep 01 06:55:10 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820926415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3820926415
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/177.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/178.uart_fifo_reset.1285037828
Short name T1059
Test name
Test status
Simulation time 37241299643 ps
CPU time 33.9 seconds
Started Sep 01 06:53:45 AM UTC 24
Finished Sep 01 06:54:20 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285037828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1285037828
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/178.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/179.uart_fifo_reset.3953232841
Short name T1076
Test name
Test status
Simulation time 23807486836 ps
CPU time 74.24 seconds
Started Sep 01 06:53:47 AM UTC 24
Finished Sep 01 06:55:03 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953232841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3953232841
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/179.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_alert_test.1245784382
Short name T498
Test name
Test status
Simulation time 11210403 ps
CPU time 0.85 seconds
Started Sep 01 06:31:27 AM UTC 24
Finished Sep 01 06:31:29 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245784382 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.1245784382
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.3036117847
Short name T324
Test name
Test status
Simulation time 21647512786 ps
CPU time 17.64 seconds
Started Sep 01 06:31:03 AM UTC 24
Finished Sep 01 06:31:22 AM UTC 24
Peak memory 208568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036117847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3036117847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_fifo_reset.3915727942
Short name T171
Test name
Test status
Simulation time 28450189616 ps
CPU time 26.06 seconds
Started Sep 01 06:31:04 AM UTC 24
Finished Sep 01 06:31:32 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915727942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3915727942
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_intr.478725191
Short name T421
Test name
Test status
Simulation time 27582100616 ps
CPU time 73.15 seconds
Started Sep 01 06:31:07 AM UTC 24
Finished Sep 01 06:32:22 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478725191 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.478725191
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.3788508282
Short name T614
Test name
Test status
Simulation time 123362187976 ps
CPU time 347.65 seconds
Started Sep 01 06:31:24 AM UTC 24
Finished Sep 01 06:37:17 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788508282 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3788508282
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_loopback.2006353829
Short name T499
Test name
Test status
Simulation time 2598332683 ps
CPU time 11.07 seconds
Started Sep 01 06:31:18 AM UTC 24
Finished Sep 01 06:31:30 AM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006353829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2006353829
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_noise_filter.2749023557
Short name T447
Test name
Test status
Simulation time 15678499092 ps
CPU time 23.06 seconds
Started Sep 01 06:31:07 AM UTC 24
Finished Sep 01 06:31:32 AM UTC 24
Peak memory 208968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749023557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2749023557
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_rx_oversample.3514570638
Short name T497
Test name
Test status
Simulation time 4498823976 ps
CPU time 8.07 seconds
Started Sep 01 06:31:07 AM UTC 24
Finished Sep 01 06:31:16 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514570638 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3514570638
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.2460221994
Short name T265
Test name
Test status
Simulation time 22531536833 ps
CPU time 24.76 seconds
Started Sep 01 06:31:10 AM UTC 24
Finished Sep 01 06:31:36 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460221994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.2460221994
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.1403783157
Short name T308
Test name
Test status
Simulation time 45560617412 ps
CPU time 18.99 seconds
Started Sep 01 06:31:08 AM UTC 24
Finished Sep 01 06:31:29 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403783157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1403783157
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_smoke.2383938913
Short name T364
Test name
Test status
Simulation time 110924880 ps
CPU time 1 seconds
Started Sep 01 06:31:02 AM UTC 24
Finished Sep 01 06:31:04 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383938913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2383938913
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_stress_all.2563060594
Short name T432
Test name
Test status
Simulation time 137816114596 ps
CPU time 722.65 seconds
Started Sep 01 06:31:26 AM UTC 24
Finished Sep 01 06:43:37 AM UTC 24
Peak memory 221364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563060594 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2563060594
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.3920923831
Short name T88
Test name
Test status
Simulation time 7419574512 ps
CPU time 21.71 seconds
Started Sep 01 06:31:26 AM UTC 24
Finished Sep 01 06:31:49 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3920923831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all
_with_rand_reset.3920923831
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.155465016
Short name T381
Test name
Test status
Simulation time 12773667563 ps
CPU time 54.2 seconds
Started Sep 01 06:31:11 AM UTC 24
Finished Sep 01 06:32:06 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155465016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.155465016
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/18.uart_tx_rx.756288985
Short name T404
Test name
Test status
Simulation time 7657127092 ps
CPU time 25.47 seconds
Started Sep 01 06:31:03 AM UTC 24
Finished Sep 01 06:31:30 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756288985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.756288985
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/18.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2689766895
Short name T1138
Test name
Test status
Simulation time 93689073907 ps
CPU time 240.56 seconds
Started Sep 01 06:53:48 AM UTC 24
Finished Sep 01 06:57:52 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689766895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2689766895
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/180.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/181.uart_fifo_reset.1911131391
Short name T1100
Test name
Test status
Simulation time 87669310541 ps
CPU time 152.96 seconds
Started Sep 01 06:53:48 AM UTC 24
Finished Sep 01 06:56:23 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911131391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1911131391
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/181.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/182.uart_fifo_reset.3814286355
Short name T1103
Test name
Test status
Simulation time 155893338582 ps
CPU time 153.57 seconds
Started Sep 01 06:53:50 AM UTC 24
Finished Sep 01 06:56:26 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814286355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3814286355
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/182.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/183.uart_fifo_reset.140624165
Short name T1055
Test name
Test status
Simulation time 4802825989 ps
CPU time 13.25 seconds
Started Sep 01 06:53:51 AM UTC 24
Finished Sep 01 06:54:06 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140624165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.140624165
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/183.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/184.uart_fifo_reset.3115085566
Short name T1071
Test name
Test status
Simulation time 83939502413 ps
CPU time 53.15 seconds
Started Sep 01 06:53:56 AM UTC 24
Finished Sep 01 06:54:51 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115085566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3115085566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/184.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/185.uart_fifo_reset.637565126
Short name T1086
Test name
Test status
Simulation time 42007159469 ps
CPU time 96.2 seconds
Started Sep 01 06:53:58 AM UTC 24
Finished Sep 01 06:55:36 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637565126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.637565126
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/185.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/186.uart_fifo_reset.5700140
Short name T1060
Test name
Test status
Simulation time 20374234701 ps
CPU time 22.5 seconds
Started Sep 01 06:54:00 AM UTC 24
Finished Sep 01 06:54:23 AM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5700140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.5700140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/186.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2234845905
Short name T1097
Test name
Test status
Simulation time 286513150768 ps
CPU time 124.32 seconds
Started Sep 01 06:54:03 AM UTC 24
Finished Sep 01 06:56:09 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234845905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2234845905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/187.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/188.uart_fifo_reset.2367580207
Short name T1109
Test name
Test status
Simulation time 137473989392 ps
CPU time 159.54 seconds
Started Sep 01 06:54:07 AM UTC 24
Finished Sep 01 06:56:49 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367580207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2367580207
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/188.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/189.uart_fifo_reset.4060263379
Short name T1068
Test name
Test status
Simulation time 169005846114 ps
CPU time 40.68 seconds
Started Sep 01 06:54:07 AM UTC 24
Finished Sep 01 06:54:49 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060263379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4060263379
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/189.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_alert_test.1703317639
Short name T503
Test name
Test status
Simulation time 14012672 ps
CPU time 0.85 seconds
Started Sep 01 06:31:54 AM UTC 24
Finished Sep 01 06:31:56 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703317639 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1703317639
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_fifo_full.1585801421
Short name T396
Test name
Test status
Simulation time 45659299395 ps
CPU time 50.1 seconds
Started Sep 01 06:31:30 AM UTC 24
Finished Sep 01 06:32:22 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585801421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1585801421
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.34039287
Short name T275
Test name
Test status
Simulation time 74700166989 ps
CPU time 136.41 seconds
Started Sep 01 06:31:31 AM UTC 24
Finished Sep 01 06:33:49 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34039287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.34039287
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_fifo_reset.1189806371
Short name T186
Test name
Test status
Simulation time 113867678922 ps
CPU time 166.43 seconds
Started Sep 01 06:31:31 AM UTC 24
Finished Sep 01 06:34:19 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189806371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1189806371
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_intr.1790121949
Short name T507
Test name
Test status
Simulation time 34808284635 ps
CPU time 29.39 seconds
Started Sep 01 06:31:33 AM UTC 24
Finished Sep 01 06:32:03 AM UTC 24
Peak memory 207636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790121949 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1790121949
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.2183810012
Short name T581
Test name
Test status
Simulation time 120657715160 ps
CPU time 252.49 seconds
Started Sep 01 06:31:48 AM UTC 24
Finished Sep 01 06:36:05 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183810012 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2183810012
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_loopback.2890325710
Short name T501
Test name
Test status
Simulation time 6386423967 ps
CPU time 7.27 seconds
Started Sep 01 06:31:44 AM UTC 24
Finished Sep 01 06:31:53 AM UTC 24
Peak memory 208416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890325710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2890325710
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_noise_filter.2863913812
Short name T302
Test name
Test status
Simulation time 293782315677 ps
CPU time 94.16 seconds
Started Sep 01 06:31:33 AM UTC 24
Finished Sep 01 06:33:09 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863913812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2863913812
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_perf.1921053980
Short name T961
Test name
Test status
Simulation time 15892120637 ps
CPU time 1103.66 seconds
Started Sep 01 06:31:46 AM UTC 24
Finished Sep 01 06:50:23 AM UTC 24
Peak memory 212208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921053980 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1921053980
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_rx_oversample.117374608
Short name T514
Test name
Test status
Simulation time 5486312241 ps
CPU time 59.26 seconds
Started Sep 01 06:31:32 AM UTC 24
Finished Sep 01 06:32:33 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117374608 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.117374608
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.1808075397
Short name T134
Test name
Test status
Simulation time 10375433894 ps
CPU time 20.27 seconds
Started Sep 01 06:31:36 AM UTC 24
Finished Sep 01 06:31:58 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808075397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1808075397
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.1913114747
Short name T346
Test name
Test status
Simulation time 3829607132 ps
CPU time 4.32 seconds
Started Sep 01 06:31:36 AM UTC 24
Finished Sep 01 06:31:41 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913114747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1913114747
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_smoke.1515344098
Short name T500
Test name
Test status
Simulation time 1020892597 ps
CPU time 2.31 seconds
Started Sep 01 06:31:27 AM UTC 24
Finished Sep 01 06:31:31 AM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515344098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1515344098
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_stress_all.804550063
Short name T1178
Test name
Test status
Simulation time 122813139882 ps
CPU time 1711.52 seconds
Started Sep 01 06:31:53 AM UTC 24
Finished Sep 01 07:00:43 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804550063 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.804550063
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.456351448
Short name T89
Test name
Test status
Simulation time 2883404351 ps
CPU time 36.22 seconds
Started Sep 01 06:31:49 AM UTC 24
Finished Sep 01 06:32:27 AM UTC 24
Peak memory 217648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=456351448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all_
with_rand_reset.456351448
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.2089398794
Short name T400
Test name
Test status
Simulation time 1301160109 ps
CPU time 7.57 seconds
Started Sep 01 06:31:42 AM UTC 24
Finished Sep 01 06:31:51 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089398794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2089398794
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/19.uart_tx_rx.1865674825
Short name T506
Test name
Test status
Simulation time 10310137721 ps
CPU time 30.94 seconds
Started Sep 01 06:31:29 AM UTC 24
Finished Sep 01 06:32:02 AM UTC 24
Peak memory 207700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865674825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1865674825
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/19.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/190.uart_fifo_reset.2508993306
Short name T1058
Test name
Test status
Simulation time 2663414791 ps
CPU time 9.76 seconds
Started Sep 01 06:54:07 AM UTC 24
Finished Sep 01 06:54:18 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508993306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2508993306
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/190.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/191.uart_fifo_reset.2631484569
Short name T1066
Test name
Test status
Simulation time 15761549564 ps
CPU time 35.96 seconds
Started Sep 01 06:54:09 AM UTC 24
Finished Sep 01 06:54:46 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631484569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2631484569
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/191.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/192.uart_fifo_reset.2094171047
Short name T198
Test name
Test status
Simulation time 162826439820 ps
CPU time 110.84 seconds
Started Sep 01 06:54:18 AM UTC 24
Finished Sep 01 06:56:11 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094171047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2094171047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/192.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/193.uart_fifo_reset.1632444945
Short name T1077
Test name
Test status
Simulation time 13172394550 ps
CPU time 42.53 seconds
Started Sep 01 06:54:21 AM UTC 24
Finished Sep 01 06:55:05 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632444945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1632444945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/193.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3725841450
Short name T1151
Test name
Test status
Simulation time 104522643254 ps
CPU time 246.98 seconds
Started Sep 01 06:54:24 AM UTC 24
Finished Sep 01 06:58:35 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725841450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3725841450
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/194.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/195.uart_fifo_reset.2186947784
Short name T1081
Test name
Test status
Simulation time 56727096632 ps
CPU time 46.94 seconds
Started Sep 01 06:54:24 AM UTC 24
Finished Sep 01 06:55:13 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186947784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2186947784
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/195.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/196.uart_fifo_reset.4111651000
Short name T1074
Test name
Test status
Simulation time 18380216030 ps
CPU time 29.74 seconds
Started Sep 01 06:54:31 AM UTC 24
Finished Sep 01 06:55:02 AM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111651000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4111651000
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/196.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3445835370
Short name T1073
Test name
Test status
Simulation time 33129132365 ps
CPU time 28.77 seconds
Started Sep 01 06:54:31 AM UTC 24
Finished Sep 01 06:55:01 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445835370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3445835370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/197.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/198.uart_fifo_reset.4141709627
Short name T1084
Test name
Test status
Simulation time 35883513771 ps
CPU time 58.04 seconds
Started Sep 01 06:54:32 AM UTC 24
Finished Sep 01 06:55:31 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141709627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4141709627
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/198.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/199.uart_fifo_reset.2779315271
Short name T215
Test name
Test status
Simulation time 23363443939 ps
CPU time 16.28 seconds
Started Sep 01 06:54:32 AM UTC 24
Finished Sep 01 06:54:49 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779315271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.2779315271
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/199.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_alert_test.1782737683
Short name T34
Test name
Test status
Simulation time 40633138 ps
CPU time 0.83 seconds
Started Sep 01 06:25:29 AM UTC 24
Finished Sep 01 06:25:31 AM UTC 24
Peak memory 204444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782737683 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1782737683
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_fifo_full.2262715623
Short name T114
Test name
Test status
Simulation time 97762971950 ps
CPU time 48.67 seconds
Started Sep 01 06:25:21 AM UTC 24
Finished Sep 01 06:26:11 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262715623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2262715623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_fifo_reset.3445402307
Short name T285
Test name
Test status
Simulation time 19191344707 ps
CPU time 61.26 seconds
Started Sep 01 06:25:21 AM UTC 24
Finished Sep 01 06:26:24 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445402307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3445402307
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_intr.4220945574
Short name T24
Test name
Test status
Simulation time 22956126319 ps
CPU time 13.48 seconds
Started Sep 01 06:25:22 AM UTC 24
Finished Sep 01 06:25:37 AM UTC 24
Peak memory 207208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220945574 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.4220945574
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_loopback.2597084173
Short name T17
Test name
Test status
Simulation time 3430375984 ps
CPU time 8.08 seconds
Started Sep 01 06:25:24 AM UTC 24
Finished Sep 01 06:25:34 AM UTC 24
Peak memory 207652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597084173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2597084173
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_noise_filter.769302989
Short name T261
Test name
Test status
Simulation time 32700414020 ps
CPU time 93.91 seconds
Started Sep 01 06:25:22 AM UTC 24
Finished Sep 01 06:26:58 AM UTC 24
Peak memory 208344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769302989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.769302989
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_perf.2156870558
Short name T898
Test name
Test status
Simulation time 17714198758 ps
CPU time 1328.42 seconds
Started Sep 01 06:25:27 AM UTC 24
Finished Sep 01 06:47:51 AM UTC 24
Peak memory 212300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156870558 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.2156870558
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_rx_oversample.2569504066
Short name T15
Test name
Test status
Simulation time 3077668511 ps
CPU time 6.32 seconds
Started Sep 01 06:25:21 AM UTC 24
Finished Sep 01 06:25:28 AM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569504066 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2569504066
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.2642548635
Short name T289
Test name
Test status
Simulation time 232415778477 ps
CPU time 161.15 seconds
Started Sep 01 06:25:22 AM UTC 24
Finished Sep 01 06:28:06 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642548635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2642548635
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.2921079209
Short name T14
Test name
Test status
Simulation time 4931688546 ps
CPU time 3.45 seconds
Started Sep 01 06:25:22 AM UTC 24
Finished Sep 01 06:25:27 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921079209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2921079209
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_sec_cm.903848138
Short name T35
Test name
Test status
Simulation time 60263912 ps
CPU time 1.3 seconds
Started Sep 01 06:25:29 AM UTC 24
Finished Sep 01 06:25:32 AM UTC 24
Peak memory 240196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903848138 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.903848138
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_smoke.638874269
Short name T9
Test name
Test status
Simulation time 503444158 ps
CPU time 5.48 seconds
Started Sep 01 06:25:20 AM UTC 24
Finished Sep 01 06:25:26 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638874269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.uart_smoke.638874269
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.227828731
Short name T13
Test name
Test status
Simulation time 2179310838 ps
CPU time 12.85 seconds
Started Sep 01 06:25:28 AM UTC 24
Finished Sep 01 06:25:42 AM UTC 24
Peak memory 209044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=227828731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_w
ith_rand_reset.227828731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/2.uart_tx_rx.2453789443
Short name T104
Test name
Test status
Simulation time 43075719658 ps
CPU time 48.08 seconds
Started Sep 01 06:25:20 AM UTC 24
Finished Sep 01 06:26:09 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453789443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2453789443
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/2.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_alert_test.2260253940
Short name T511
Test name
Test status
Simulation time 145641553 ps
CPU time 0.82 seconds
Started Sep 01 06:32:21 AM UTC 24
Finished Sep 01 06:32:23 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260253940 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2260253940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_fifo_full.3366552202
Short name T520
Test name
Test status
Simulation time 66842016419 ps
CPU time 50.7 seconds
Started Sep 01 06:31:58 AM UTC 24
Finished Sep 01 06:32:50 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366552202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3366552202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.2382029152
Short name T164
Test name
Test status
Simulation time 113736307327 ps
CPU time 353.49 seconds
Started Sep 01 06:31:58 AM UTC 24
Finished Sep 01 06:37:56 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382029152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2382029152
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_fifo_reset.3566157351
Short name T125
Test name
Test status
Simulation time 116968950172 ps
CPU time 25.63 seconds
Started Sep 01 06:31:59 AM UTC 24
Finished Sep 01 06:32:26 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566157351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3566157351
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_intr.713584590
Short name T632
Test name
Test status
Simulation time 257856014398 ps
CPU time 367.52 seconds
Started Sep 01 06:32:00 AM UTC 24
Finished Sep 01 06:38:13 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713584590 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.713584590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.643555169
Short name T590
Test name
Test status
Simulation time 79421591675 ps
CPU time 256.88 seconds
Started Sep 01 06:32:13 AM UTC 24
Finished Sep 01 06:36:33 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643555169 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.643555169
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_loopback.3065680111
Short name T513
Test name
Test status
Simulation time 4714268946 ps
CPU time 15.3 seconds
Started Sep 01 06:32:12 AM UTC 24
Finished Sep 01 06:32:28 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065680111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3065680111
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_noise_filter.3701590177
Short name T376
Test name
Test status
Simulation time 106409213250 ps
CPU time 90.15 seconds
Started Sep 01 06:32:02 AM UTC 24
Finished Sep 01 06:33:35 AM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701590177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3701590177
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_perf.598869216
Short name T671
Test name
Test status
Simulation time 24816097517 ps
CPU time 464.39 seconds
Started Sep 01 06:32:13 AM UTC 24
Finished Sep 01 06:40:03 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598869216 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.598869216
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_rx_oversample.1672624451
Short name T522
Test name
Test status
Simulation time 4839613201 ps
CPU time 51.84 seconds
Started Sep 01 06:31:59 AM UTC 24
Finished Sep 01 06:32:53 AM UTC 24
Peak memory 208396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672624451 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1672624451
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.1870675371
Short name T517
Test name
Test status
Simulation time 36485822139 ps
CPU time 36.88 seconds
Started Sep 01 06:32:07 AM UTC 24
Finished Sep 01 06:32:46 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870675371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1870675371
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.2089388257
Short name T510
Test name
Test status
Simulation time 3947920678 ps
CPU time 14.58 seconds
Started Sep 01 06:32:04 AM UTC 24
Finished Sep 01 06:32:20 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089388257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2089388257
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_smoke.2028963943
Short name T505
Test name
Test status
Simulation time 156803385 ps
CPU time 1.17 seconds
Started Sep 01 06:31:56 AM UTC 24
Finished Sep 01 06:31:58 AM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028963943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2028963943
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_stress_all.1188698704
Short name T135
Test name
Test status
Simulation time 61865316017 ps
CPU time 80.62 seconds
Started Sep 01 06:32:20 AM UTC 24
Finished Sep 01 06:33:42 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188698704 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1188698704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.2909395020
Short name T515
Test name
Test status
Simulation time 3272562873 ps
CPU time 17.02 seconds
Started Sep 01 06:32:19 AM UTC 24
Finished Sep 01 06:32:37 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2909395020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all
_with_rand_reset.2909395020
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.2173174437
Short name T508
Test name
Test status
Simulation time 764463391 ps
CPU time 2.63 seconds
Started Sep 01 06:32:08 AM UTC 24
Finished Sep 01 06:32:11 AM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173174437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2173174437
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/200.uart_fifo_reset.4248888298
Short name T1137
Test name
Test status
Simulation time 97876464417 ps
CPU time 191.72 seconds
Started Sep 01 06:54:33 AM UTC 24
Finished Sep 01 06:57:47 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248888298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4248888298
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/200.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/202.uart_fifo_reset.2347432607
Short name T1095
Test name
Test status
Simulation time 27400371984 ps
CPU time 80.99 seconds
Started Sep 01 06:54:40 AM UTC 24
Finished Sep 01 06:56:03 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347432607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2347432607
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/202.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/204.uart_fifo_reset.3706653360
Short name T1088
Test name
Test status
Simulation time 84188130423 ps
CPU time 54.39 seconds
Started Sep 01 06:54:44 AM UTC 24
Finished Sep 01 06:55:40 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706653360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3706653360
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/204.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/205.uart_fifo_reset.2950685579
Short name T1092
Test name
Test status
Simulation time 53796790007 ps
CPU time 63.04 seconds
Started Sep 01 06:54:45 AM UTC 24
Finished Sep 01 06:55:50 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950685579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2950685579
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/205.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2600309964
Short name T190
Test name
Test status
Simulation time 53546123605 ps
CPU time 20.89 seconds
Started Sep 01 06:54:46 AM UTC 24
Finished Sep 01 06:55:08 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600309964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2600309964
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/206.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2406777363
Short name T1072
Test name
Test status
Simulation time 8317485098 ps
CPU time 11.21 seconds
Started Sep 01 06:54:47 AM UTC 24
Finished Sep 01 06:55:00 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406777363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2406777363
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/207.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/209.uart_fifo_reset.1736471627
Short name T242
Test name
Test status
Simulation time 99099000918 ps
CPU time 352.59 seconds
Started Sep 01 06:54:50 AM UTC 24
Finished Sep 01 07:00:47 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736471627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1736471627
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/209.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_alert_test.4244179618
Short name T521
Test name
Test status
Simulation time 11998949 ps
CPU time 0.85 seconds
Started Sep 01 06:32:49 AM UTC 24
Finished Sep 01 06:32:51 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244179618 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.4244179618
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_fifo_full.1854536963
Short name T524
Test name
Test status
Simulation time 72228089813 ps
CPU time 49.47 seconds
Started Sep 01 06:32:23 AM UTC 24
Finished Sep 01 06:33:14 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854536963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.1854536963
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.1526461541
Short name T534
Test name
Test status
Simulation time 94578924736 ps
CPU time 92.82 seconds
Started Sep 01 06:32:26 AM UTC 24
Finished Sep 01 06:34:01 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526461541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1526461541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_fifo_reset.1436536056
Short name T413
Test name
Test status
Simulation time 82182281100 ps
CPU time 61.66 seconds
Started Sep 01 06:32:26 AM UTC 24
Finished Sep 01 06:33:30 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436536056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.1436536056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_intr.2360259107
Short name T544
Test name
Test status
Simulation time 63953078405 ps
CPU time 120.94 seconds
Started Sep 01 06:32:29 AM UTC 24
Finished Sep 01 06:34:32 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360259107 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2360259107
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.3938738348
Short name T647
Test name
Test status
Simulation time 79985365896 ps
CPU time 365.59 seconds
Started Sep 01 06:32:46 AM UTC 24
Finished Sep 01 06:38:57 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938738348 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.3938738348
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_loopback.1694363180
Short name T519
Test name
Test status
Simulation time 2510717104 ps
CPU time 4.63 seconds
Started Sep 01 06:32:43 AM UTC 24
Finished Sep 01 06:32:49 AM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694363180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1694363180
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_noise_filter.1284034104
Short name T347
Test name
Test status
Simulation time 161984348196 ps
CPU time 53.68 seconds
Started Sep 01 06:32:29 AM UTC 24
Finished Sep 01 06:33:24 AM UTC 24
Peak memory 207760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284034104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1284034104
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_perf.1980059776
Short name T769
Test name
Test status
Simulation time 10038173319 ps
CPU time 602.6 seconds
Started Sep 01 06:32:45 AM UTC 24
Finished Sep 01 06:42:55 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980059776 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1980059776
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_rx_oversample.3449346884
Short name T523
Test name
Test status
Simulation time 3886571205 ps
CPU time 31.35 seconds
Started Sep 01 06:32:27 AM UTC 24
Finished Sep 01 06:33:00 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449346884 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3449346884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.1587513714
Short name T439
Test name
Test status
Simulation time 112561351657 ps
CPU time 244.42 seconds
Started Sep 01 06:32:38 AM UTC 24
Finished Sep 01 06:36:46 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587513714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1587513714
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.2087246206
Short name T518
Test name
Test status
Simulation time 3557568073 ps
CPU time 11.9 seconds
Started Sep 01 06:32:34 AM UTC 24
Finished Sep 01 06:32:47 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087246206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2087246206
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_smoke.1015953299
Short name T512
Test name
Test status
Simulation time 745982958 ps
CPU time 1.69 seconds
Started Sep 01 06:32:23 AM UTC 24
Finished Sep 01 06:32:26 AM UTC 24
Peak memory 206568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015953299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1015953299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_stress_all.2855492711
Short name T132
Test name
Test status
Simulation time 28574412031 ps
CPU time 113.75 seconds
Started Sep 01 06:32:47 AM UTC 24
Finished Sep 01 06:34:43 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855492711 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2855492711
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.4216113710
Short name T416
Test name
Test status
Simulation time 15369998748 ps
CPU time 78.38 seconds
Started Sep 01 06:32:47 AM UTC 24
Finished Sep 01 06:34:08 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4216113710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all
_with_rand_reset.4216113710
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.520686681
Short name T350
Test name
Test status
Simulation time 6250960358 ps
CPU time 13.62 seconds
Started Sep 01 06:32:38 AM UTC 24
Finished Sep 01 06:32:53 AM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520686681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.520686681
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/21.uart_tx_rx.187103590
Short name T436
Test name
Test status
Simulation time 44335337029 ps
CPU time 129.19 seconds
Started Sep 01 06:32:23 AM UTC 24
Finished Sep 01 06:34:35 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187103590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.187103590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/21.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/210.uart_fifo_reset.115449019
Short name T1082
Test name
Test status
Simulation time 24711900798 ps
CPU time 25.01 seconds
Started Sep 01 06:54:50 AM UTC 24
Finished Sep 01 06:55:16 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115449019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.115449019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/210.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/212.uart_fifo_reset.1066241210
Short name T195
Test name
Test status
Simulation time 9005266764 ps
CPU time 27.3 seconds
Started Sep 01 06:54:51 AM UTC 24
Finished Sep 01 06:55:20 AM UTC 24
Peak memory 208452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066241210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1066241210
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/212.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2082456068
Short name T1167
Test name
Test status
Simulation time 124844530008 ps
CPU time 283.47 seconds
Started Sep 01 06:54:59 AM UTC 24
Finished Sep 01 06:59:46 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082456068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2082456068
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/214.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/216.uart_fifo_reset.2833291252
Short name T1166
Test name
Test status
Simulation time 111142368520 ps
CPU time 268.14 seconds
Started Sep 01 06:55:01 AM UTC 24
Finished Sep 01 06:59:33 AM UTC 24
Peak memory 208908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833291252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2833291252
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/216.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/217.uart_fifo_reset.59886296
Short name T1121
Test name
Test status
Simulation time 112164193952 ps
CPU time 131.57 seconds
Started Sep 01 06:55:02 AM UTC 24
Finished Sep 01 06:57:16 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59886296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.59886296
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/217.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1349547746
Short name T1111
Test name
Test status
Simulation time 34927453861 ps
CPU time 105.33 seconds
Started Sep 01 06:55:03 AM UTC 24
Finished Sep 01 06:56:51 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349547746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1349547746
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/218.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2118975454
Short name T1094
Test name
Test status
Simulation time 202086337352 ps
CPU time 55.06 seconds
Started Sep 01 06:55:04 AM UTC 24
Finished Sep 01 06:56:01 AM UTC 24
Peak memory 208668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118975454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2118975454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/219.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_alert_test.1564013600
Short name T527
Test name
Test status
Simulation time 13249395 ps
CPU time 0.87 seconds
Started Sep 01 06:33:30 AM UTC 24
Finished Sep 01 06:33:32 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564013600 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1564013600
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_fifo_full.4196197276
Short name T529
Test name
Test status
Simulation time 12475342798 ps
CPU time 42.64 seconds
Started Sep 01 06:32:54 AM UTC 24
Finished Sep 01 06:33:38 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196197276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4196197276
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_fifo_reset.450811622
Short name T141
Test name
Test status
Simulation time 43834199185 ps
CPU time 22.89 seconds
Started Sep 01 06:32:54 AM UTC 24
Finished Sep 01 06:33:18 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450811622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.450811622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_intr.3046084625
Short name T537
Test name
Test status
Simulation time 18214956774 ps
CPU time 62.38 seconds
Started Sep 01 06:33:01 AM UTC 24
Finished Sep 01 06:34:05 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046084625 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3046084625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.3748223020
Short name T577
Test name
Test status
Simulation time 64422394686 ps
CPU time 156.36 seconds
Started Sep 01 06:33:23 AM UTC 24
Finished Sep 01 06:36:02 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748223020 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3748223020
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_loopback.4252867990
Short name T525
Test name
Test status
Simulation time 26115490 ps
CPU time 0.89 seconds
Started Sep 01 06:33:20 AM UTC 24
Finished Sep 01 06:33:21 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252867990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.4252867990
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_noise_filter.2817428431
Short name T402
Test name
Test status
Simulation time 229579392547 ps
CPU time 130.55 seconds
Started Sep 01 06:33:09 AM UTC 24
Finished Sep 01 06:35:22 AM UTC 24
Peak memory 217500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817428431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2817428431
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_perf.2749289550
Short name T570
Test name
Test status
Simulation time 5368056736 ps
CPU time 126.44 seconds
Started Sep 01 06:33:22 AM UTC 24
Finished Sep 01 06:35:31 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749289550 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2749289550
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_rx_oversample.2369621335
Short name T526
Test name
Test status
Simulation time 5359357214 ps
CPU time 28.74 seconds
Started Sep 01 06:32:59 AM UTC 24
Finished Sep 01 06:33:29 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369621335 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2369621335
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.265701427
Short name T372
Test name
Test status
Simulation time 235105018508 ps
CPU time 241.61 seconds
Started Sep 01 06:33:15 AM UTC 24
Finished Sep 01 06:37:21 AM UTC 24
Peak memory 208588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265701427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.265701427
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.18969998
Short name T382
Test name
Test status
Simulation time 47302171994 ps
CPU time 31.74 seconds
Started Sep 01 06:33:09 AM UTC 24
Finished Sep 01 06:33:42 AM UTC 24
Peak memory 205104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18969998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.18969998
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_smoke.2384262736
Short name T342
Test name
Test status
Simulation time 5852820500 ps
CPU time 26.19 seconds
Started Sep 01 06:32:52 AM UTC 24
Finished Sep 01 06:33:19 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384262736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2384262736
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_stress_all.167488022
Short name T173
Test name
Test status
Simulation time 75426016486 ps
CPU time 125.52 seconds
Started Sep 01 06:33:29 AM UTC 24
Finished Sep 01 06:35:37 AM UTC 24
Peak memory 208496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167488022 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.167488022
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.3166567482
Short name T90
Test name
Test status
Simulation time 3160577036 ps
CPU time 25.08 seconds
Started Sep 01 06:33:25 AM UTC 24
Finished Sep 01 06:33:51 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3166567482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all
_with_rand_reset.3166567482
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.593485813
Short name T260
Test name
Test status
Simulation time 6221030253 ps
CPU time 36.23 seconds
Started Sep 01 06:33:18 AM UTC 24
Finished Sep 01 06:33:56 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593485813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.593485813
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/22.uart_tx_rx.877455564
Short name T321
Test name
Test status
Simulation time 383258605379 ps
CPU time 91.22 seconds
Started Sep 01 06:32:53 AM UTC 24
Finished Sep 01 06:34:26 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877455564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.877455564
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/22.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/220.uart_fifo_reset.2992979916
Short name T170
Test name
Test status
Simulation time 9558615249 ps
CPU time 34.7 seconds
Started Sep 01 06:55:06 AM UTC 24
Finished Sep 01 06:55:43 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992979916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2992979916
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/220.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/221.uart_fifo_reset.1539506306
Short name T1116
Test name
Test status
Simulation time 97547888077 ps
CPU time 108.43 seconds
Started Sep 01 06:55:09 AM UTC 24
Finished Sep 01 06:56:59 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539506306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1539506306
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/221.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/222.uart_fifo_reset.4287781217
Short name T1118
Test name
Test status
Simulation time 162020099911 ps
CPU time 110.41 seconds
Started Sep 01 06:55:09 AM UTC 24
Finished Sep 01 06:57:01 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287781217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.4287781217
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/222.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/223.uart_fifo_reset.3626544254
Short name T1165
Test name
Test status
Simulation time 117110256068 ps
CPU time 259.42 seconds
Started Sep 01 06:55:10 AM UTC 24
Finished Sep 01 06:59:33 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626544254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3626544254
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/223.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2929809919
Short name T1091
Test name
Test status
Simulation time 282085369611 ps
CPU time 31.51 seconds
Started Sep 01 06:55:11 AM UTC 24
Finished Sep 01 06:55:44 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929809919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2929809919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/224.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/225.uart_fifo_reset.968977749
Short name T1110
Test name
Test status
Simulation time 95284579807 ps
CPU time 96.92 seconds
Started Sep 01 06:55:12 AM UTC 24
Finished Sep 01 06:56:51 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968977749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.968977749
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/225.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/226.uart_fifo_reset.723226711
Short name T232
Test name
Test status
Simulation time 6592617025 ps
CPU time 23.13 seconds
Started Sep 01 06:55:13 AM UTC 24
Finished Sep 01 06:55:37 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723226711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.723226711
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/226.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/227.uart_fifo_reset.888528949
Short name T1093
Test name
Test status
Simulation time 17860279369 ps
CPU time 41.6 seconds
Started Sep 01 06:55:14 AM UTC 24
Finished Sep 01 06:55:57 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888528949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.888528949
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/227.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/228.uart_fifo_reset.3965493494
Short name T1085
Test name
Test status
Simulation time 14565831156 ps
CPU time 15.7 seconds
Started Sep 01 06:55:17 AM UTC 24
Finished Sep 01 06:55:34 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965493494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3965493494
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/228.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_alert_test.2177419503
Short name T536
Test name
Test status
Simulation time 13588939 ps
CPU time 0.85 seconds
Started Sep 01 06:34:02 AM UTC 24
Finished Sep 01 06:34:04 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177419503 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2177419503
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_fifo_full.3207620542
Short name T538
Test name
Test status
Simulation time 19420122231 ps
CPU time 31.7 seconds
Started Sep 01 06:33:33 AM UTC 24
Finished Sep 01 06:34:06 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207620542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3207620542
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.3163587519
Short name T136
Test name
Test status
Simulation time 46581754407 ps
CPU time 81.19 seconds
Started Sep 01 06:33:35 AM UTC 24
Finished Sep 01 06:34:59 AM UTC 24
Peak memory 208816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163587519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3163587519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_intr.478654592
Short name T552
Test name
Test status
Simulation time 31799686390 ps
CPU time 62.61 seconds
Started Sep 01 06:33:44 AM UTC 24
Finished Sep 01 06:34:48 AM UTC 24
Peak memory 208908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478654592 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.478654592
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.3062621955
Short name T575
Test name
Test status
Simulation time 121375455299 ps
CPU time 116.28 seconds
Started Sep 01 06:33:57 AM UTC 24
Finished Sep 01 06:35:56 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062621955 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3062621955
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_loopback.1637760140
Short name T540
Test name
Test status
Simulation time 10536090044 ps
CPU time 12.64 seconds
Started Sep 01 06:33:55 AM UTC 24
Finished Sep 01 06:34:09 AM UTC 24
Peak memory 208556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637760140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1637760140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_noise_filter.1394419484
Short name T428
Test name
Test status
Simulation time 71199641792 ps
CPU time 32.27 seconds
Started Sep 01 06:33:44 AM UTC 24
Finished Sep 01 06:34:17 AM UTC 24
Peak memory 208048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394419484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1394419484
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_perf.3332251118
Short name T664
Test name
Test status
Simulation time 8572977643 ps
CPU time 346.03 seconds
Started Sep 01 06:33:55 AM UTC 24
Finished Sep 01 06:39:46 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332251118 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3332251118
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_rx_oversample.2902099220
Short name T549
Test name
Test status
Simulation time 5158324089 ps
CPU time 61.11 seconds
Started Sep 01 06:33:38 AM UTC 24
Finished Sep 01 06:34:41 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902099220 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2902099220
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.2190935477
Short name T123
Test name
Test status
Simulation time 26305555343 ps
CPU time 46.48 seconds
Started Sep 01 06:33:52 AM UTC 24
Finished Sep 01 06:34:40 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190935477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2190935477
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.1450855495
Short name T530
Test name
Test status
Simulation time 5794088384 ps
CPU time 2.26 seconds
Started Sep 01 06:33:50 AM UTC 24
Finished Sep 01 06:33:53 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450855495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1450855495
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_smoke.2233238454
Short name T528
Test name
Test status
Simulation time 569169883 ps
CPU time 1.78 seconds
Started Sep 01 06:33:31 AM UTC 24
Finished Sep 01 06:33:34 AM UTC 24
Peak memory 206436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233238454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.2233238454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_stress_all.2405843983
Short name T126
Test name
Test status
Simulation time 174930295295 ps
CPU time 92.55 seconds
Started Sep 01 06:34:00 AM UTC 24
Finished Sep 01 06:35:35 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405843983 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2405843983
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.3689073583
Short name T550
Test name
Test status
Simulation time 3876576400 ps
CPU time 43.2 seconds
Started Sep 01 06:33:59 AM UTC 24
Finished Sep 01 06:34:44 AM UTC 24
Peak memory 224628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3689073583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all
_with_rand_reset.3689073583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.1615892110
Short name T532
Test name
Test status
Simulation time 2192139989 ps
CPU time 3.21 seconds
Started Sep 01 06:33:54 AM UTC 24
Finished Sep 01 06:33:58 AM UTC 24
Peak memory 207704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615892110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1615892110
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/23.uart_tx_rx.3974709428
Short name T535
Test name
Test status
Simulation time 37216279642 ps
CPU time 30.56 seconds
Started Sep 01 06:33:32 AM UTC 24
Finished Sep 01 06:34:04 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974709428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3974709428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/23.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/230.uart_fifo_reset.1677528322
Short name T1163
Test name
Test status
Simulation time 143497926445 ps
CPU time 237.05 seconds
Started Sep 01 06:55:20 AM UTC 24
Finished Sep 01 06:59:20 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677528322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1677528322
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/230.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/231.uart_fifo_reset.3458979096
Short name T1112
Test name
Test status
Simulation time 26480765315 ps
CPU time 81.82 seconds
Started Sep 01 06:55:27 AM UTC 24
Finished Sep 01 06:56:51 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458979096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.3458979096
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/231.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/232.uart_fifo_reset.936705202
Short name T1156
Test name
Test status
Simulation time 96000749625 ps
CPU time 191.83 seconds
Started Sep 01 06:55:33 AM UTC 24
Finished Sep 01 06:58:47 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936705202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.936705202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/232.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2096097134
Short name T1104
Test name
Test status
Simulation time 39163107101 ps
CPU time 52.12 seconds
Started Sep 01 06:55:35 AM UTC 24
Finished Sep 01 06:56:28 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096097134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2096097134
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/233.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/234.uart_fifo_reset.3642853554
Short name T1106
Test name
Test status
Simulation time 146644726033 ps
CPU time 58.29 seconds
Started Sep 01 06:55:37 AM UTC 24
Finished Sep 01 06:56:36 AM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642853554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3642853554
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/234.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3706843222
Short name T217
Test name
Test status
Simulation time 29930080237 ps
CPU time 48.85 seconds
Started Sep 01 06:55:37 AM UTC 24
Finished Sep 01 06:56:27 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706843222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3706843222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/235.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/236.uart_fifo_reset.3393052789
Short name T1108
Test name
Test status
Simulation time 28550484609 ps
CPU time 65.54 seconds
Started Sep 01 06:55:38 AM UTC 24
Finished Sep 01 06:56:45 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393052789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3393052789
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/236.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/237.uart_fifo_reset.4195580908
Short name T1115
Test name
Test status
Simulation time 106589727989 ps
CPU time 72.13 seconds
Started Sep 01 06:55:41 AM UTC 24
Finished Sep 01 06:56:55 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195580908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.4195580908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/237.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_alert_test.1976469336
Short name T543
Test name
Test status
Simulation time 45122243 ps
CPU time 0.86 seconds
Started Sep 01 06:34:29 AM UTC 24
Finished Sep 01 06:34:31 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976469336 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1976469336
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_fifo_full.3316033524
Short name T558
Test name
Test status
Simulation time 58659226984 ps
CPU time 49.95 seconds
Started Sep 01 06:34:06 AM UTC 24
Finished Sep 01 06:34:57 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316033524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3316033524
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3319869621
Short name T127
Test name
Test status
Simulation time 215244671403 ps
CPU time 47.46 seconds
Started Sep 01 06:34:07 AM UTC 24
Finished Sep 01 06:34:56 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319869621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3319869621
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_fifo_reset.3838986466
Short name T234
Test name
Test status
Simulation time 26791891487 ps
CPU time 76.84 seconds
Started Sep 01 06:34:09 AM UTC 24
Finished Sep 01 06:35:28 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838986466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3838986466
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_intr.2033098573
Short name T504
Test name
Test status
Simulation time 6653931377 ps
CPU time 13.32 seconds
Started Sep 01 06:34:10 AM UTC 24
Finished Sep 01 06:34:25 AM UTC 24
Peak memory 208540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033098573 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2033098573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.4163605102
Short name T809
Test name
Test status
Simulation time 196732780996 ps
CPU time 574.79 seconds
Started Sep 01 06:34:27 AM UTC 24
Finished Sep 01 06:44:09 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163605102 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4163605102
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_loopback.3918401555
Short name T545
Test name
Test status
Simulation time 5921149457 ps
CPU time 10.89 seconds
Started Sep 01 06:34:22 AM UTC 24
Finished Sep 01 06:34:35 AM UTC 24
Peak memory 208536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918401555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3918401555
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_noise_filter.1406701520
Short name T579
Test name
Test status
Simulation time 77235517856 ps
CPU time 109.07 seconds
Started Sep 01 06:34:13 AM UTC 24
Finished Sep 01 06:36:04 AM UTC 24
Peak memory 217636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406701520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1406701520
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_perf.3481513521
Short name T608
Test name
Test status
Simulation time 14844625754 ps
CPU time 162.99 seconds
Started Sep 01 06:34:26 AM UTC 24
Finished Sep 01 06:37:12 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481513521 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3481513521
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_rx_oversample.3656267261
Short name T557
Test name
Test status
Simulation time 5590914679 ps
CPU time 45.99 seconds
Started Sep 01 06:34:09 AM UTC 24
Finished Sep 01 06:34:56 AM UTC 24
Peak memory 208124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656267261 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3656267261
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.3898293132
Short name T378
Test name
Test status
Simulation time 199951522642 ps
CPU time 236.9 seconds
Started Sep 01 06:34:18 AM UTC 24
Finished Sep 01 06:38:18 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898293132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3898293132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.511750841
Short name T542
Test name
Test status
Simulation time 2448570027 ps
CPU time 10.26 seconds
Started Sep 01 06:34:16 AM UTC 24
Finished Sep 01 06:34:28 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511750841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.511750841
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_smoke.2490986954
Short name T539
Test name
Test status
Simulation time 770691123 ps
CPU time 2.15 seconds
Started Sep 01 06:34:05 AM UTC 24
Finished Sep 01 06:34:08 AM UTC 24
Peak memory 207680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490986954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2490986954
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_stress_all.2762669860
Short name T1183
Test name
Test status
Simulation time 481995045237 ps
CPU time 1847.17 seconds
Started Sep 01 06:34:29 AM UTC 24
Finished Sep 01 07:05:36 AM UTC 24
Peak memory 221172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762669860 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2762669860
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.3255062994
Short name T418
Test name
Test status
Simulation time 3536421009 ps
CPU time 41.85 seconds
Started Sep 01 06:34:27 AM UTC 24
Finished Sep 01 06:35:10 AM UTC 24
Peak memory 224000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3255062994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all
_with_rand_reset.3255062994
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.380338402
Short name T541
Test name
Test status
Simulation time 960328497 ps
CPU time 4.66 seconds
Started Sep 01 06:34:20 AM UTC 24
Finished Sep 01 06:34:26 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380338402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.380338402
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/24.uart_tx_rx.3124053583
Short name T564
Test name
Test status
Simulation time 56166816932 ps
CPU time 67.51 seconds
Started Sep 01 06:34:06 AM UTC 24
Finished Sep 01 06:35:15 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124053583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3124053583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/24.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/240.uart_fifo_reset.1900989412
Short name T1096
Test name
Test status
Simulation time 28950200064 ps
CPU time 22.19 seconds
Started Sep 01 06:55:44 AM UTC 24
Finished Sep 01 06:56:08 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900989412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1900989412
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/240.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/241.uart_fifo_reset.4125329486
Short name T1129
Test name
Test status
Simulation time 56083996162 ps
CPU time 102.88 seconds
Started Sep 01 06:55:44 AM UTC 24
Finished Sep 01 06:57:29 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125329486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.4125329486
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/241.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/242.uart_fifo_reset.4198873928
Short name T1099
Test name
Test status
Simulation time 39887563227 ps
CPU time 24.8 seconds
Started Sep 01 06:55:49 AM UTC 24
Finished Sep 01 06:56:15 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198873928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4198873928
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/242.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/243.uart_fifo_reset.2756389590
Short name T1139
Test name
Test status
Simulation time 123099297650 ps
CPU time 119.57 seconds
Started Sep 01 06:55:51 AM UTC 24
Finished Sep 01 06:57:52 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756389590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2756389590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/243.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/244.uart_fifo_reset.1092150189
Short name T1171
Test name
Test status
Simulation time 94691528292 ps
CPU time 238.3 seconds
Started Sep 01 06:55:52 AM UTC 24
Finished Sep 01 06:59:53 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092150189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1092150189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/244.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3025272124
Short name T1181
Test name
Test status
Simulation time 106628344979 ps
CPU time 352.97 seconds
Started Sep 01 06:55:55 AM UTC 24
Finished Sep 01 07:01:52 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025272124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3025272124
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/245.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/246.uart_fifo_reset.856698786
Short name T1102
Test name
Test status
Simulation time 30098522469 ps
CPU time 26.62 seconds
Started Sep 01 06:55:58 AM UTC 24
Finished Sep 01 06:56:26 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856698786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.856698786
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/246.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/247.uart_fifo_reset.32631238
Short name T1107
Test name
Test status
Simulation time 248730881286 ps
CPU time 34.11 seconds
Started Sep 01 06:56:02 AM UTC 24
Finished Sep 01 06:56:37 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32631238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.32631238
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/247.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/248.uart_fifo_reset.638435174
Short name T250
Test name
Test status
Simulation time 47890650831 ps
CPU time 31.43 seconds
Started Sep 01 06:56:04 AM UTC 24
Finished Sep 01 06:56:37 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638435174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.638435174
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/248.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/249.uart_fifo_reset.2866705538
Short name T444
Test name
Test status
Simulation time 180753510817 ps
CPU time 151.43 seconds
Started Sep 01 06:56:08 AM UTC 24
Finished Sep 01 06:58:42 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866705538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2866705538
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/249.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_alert_test.246431330
Short name T559
Test name
Test status
Simulation time 14810084 ps
CPU time 0.72 seconds
Started Sep 01 06:34:56 AM UTC 24
Finished Sep 01 06:34:58 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246431330 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.246431330
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.987301480
Short name T623
Test name
Test status
Simulation time 104607484603 ps
CPU time 181.46 seconds
Started Sep 01 06:34:36 AM UTC 24
Finished Sep 01 06:37:40 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987301480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.987301480
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_fifo_reset.1718424290
Short name T181
Test name
Test status
Simulation time 138786080820 ps
CPU time 219.65 seconds
Started Sep 01 06:34:36 AM UTC 24
Finished Sep 01 06:38:19 AM UTC 24
Peak memory 208924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718424290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1718424290
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_intr.4004351021
Short name T573
Test name
Test status
Simulation time 51955643726 ps
CPU time 68.6 seconds
Started Sep 01 06:34:40 AM UTC 24
Finished Sep 01 06:35:51 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004351021 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.4004351021
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.2266574280
Short name T752
Test name
Test status
Simulation time 131068368569 ps
CPU time 445.27 seconds
Started Sep 01 06:34:49 AM UTC 24
Finished Sep 01 06:42:20 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266574280 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2266574280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_loopback.2357318032
Short name T561
Test name
Test status
Simulation time 7535313745 ps
CPU time 15.1 seconds
Started Sep 01 06:34:46 AM UTC 24
Finished Sep 01 06:35:02 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357318032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2357318032
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_noise_filter.1261174392
Short name T553
Test name
Test status
Simulation time 1533364020 ps
CPU time 5.93 seconds
Started Sep 01 06:34:42 AM UTC 24
Finished Sep 01 06:34:49 AM UTC 24
Peak memory 205108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261174392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1261174392
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_perf.479056225
Short name T556
Test name
Test status
Simulation time 2289774380 ps
CPU time 5.85 seconds
Started Sep 01 06:34:49 AM UTC 24
Finished Sep 01 06:34:56 AM UTC 24
Peak memory 208572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479056225 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.479056225
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_rx_oversample.991499710
Short name T551
Test name
Test status
Simulation time 3563136100 ps
CPU time 6.58 seconds
Started Sep 01 06:34:37 AM UTC 24
Finished Sep 01 06:34:45 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991499710 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.991499710
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.1898850807
Short name T571
Test name
Test status
Simulation time 26737764954 ps
CPU time 57.3 seconds
Started Sep 01 06:34:45 AM UTC 24
Finished Sep 01 06:35:44 AM UTC 24
Peak memory 208108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898850807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1898850807
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.3047180887
Short name T555
Test name
Test status
Simulation time 3992756220 ps
CPU time 7.88 seconds
Started Sep 01 06:34:42 AM UTC 24
Finished Sep 01 06:34:50 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047180887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3047180887
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_smoke.2562936517
Short name T547
Test name
Test status
Simulation time 504303448 ps
CPU time 3.25 seconds
Started Sep 01 06:34:32 AM UTC 24
Finished Sep 01 06:34:36 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562936517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2562936517
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_stress_all.3871492176
Short name T563
Test name
Test status
Simulation time 87194167393 ps
CPU time 18.98 seconds
Started Sep 01 06:34:51 AM UTC 24
Finished Sep 01 06:35:11 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871492176 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3871492176
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.2500704315
Short name T390
Test name
Test status
Simulation time 7442490666 ps
CPU time 24.15 seconds
Started Sep 01 06:34:51 AM UTC 24
Finished Sep 01 06:35:16 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2500704315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all
_with_rand_reset.2500704315
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.175843646
Short name T554
Test name
Test status
Simulation time 716470020 ps
CPU time 4.13 seconds
Started Sep 01 06:34:45 AM UTC 24
Finished Sep 01 06:34:50 AM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175843646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.175843646
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/25.uart_tx_rx.1843278933
Short name T572
Test name
Test status
Simulation time 135287804003 ps
CPU time 76.91 seconds
Started Sep 01 06:34:32 AM UTC 24
Finished Sep 01 06:35:51 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843278933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1843278933
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/25.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/250.uart_fifo_reset.371150903
Short name T205
Test name
Test status
Simulation time 50192305827 ps
CPU time 43.13 seconds
Started Sep 01 06:56:10 AM UTC 24
Finished Sep 01 06:56:55 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371150903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.371150903
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/250.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/251.uart_fifo_reset.3632917568
Short name T1149
Test name
Test status
Simulation time 41448754053 ps
CPU time 135.64 seconds
Started Sep 01 06:56:10 AM UTC 24
Finished Sep 01 06:58:28 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632917568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3632917568
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/251.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/252.uart_fifo_reset.1455649274
Short name T1135
Test name
Test status
Simulation time 129895182896 ps
CPU time 85.46 seconds
Started Sep 01 06:56:11 AM UTC 24
Finished Sep 01 06:57:39 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455649274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1455649274
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/252.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/253.uart_fifo_reset.4059294689
Short name T1127
Test name
Test status
Simulation time 21528888604 ps
CPU time 72.27 seconds
Started Sep 01 06:56:12 AM UTC 24
Finished Sep 01 06:57:27 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059294689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4059294689
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/253.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/254.uart_fifo_reset.2827173625
Short name T1117
Test name
Test status
Simulation time 41948992070 ps
CPU time 45.79 seconds
Started Sep 01 06:56:14 AM UTC 24
Finished Sep 01 06:57:01 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827173625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2827173625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/254.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/255.uart_fifo_reset.2630313197
Short name T1123
Test name
Test status
Simulation time 45354887057 ps
CPU time 64.73 seconds
Started Sep 01 06:56:14 AM UTC 24
Finished Sep 01 06:57:20 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630313197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2630313197
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/255.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/256.uart_fifo_reset.1074904508
Short name T1172
Test name
Test status
Simulation time 177132722601 ps
CPU time 215.84 seconds
Started Sep 01 06:56:17 AM UTC 24
Finished Sep 01 06:59:56 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074904508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.1074904508
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/256.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/257.uart_fifo_reset.1230533866
Short name T1161
Test name
Test status
Simulation time 59785932664 ps
CPU time 159.83 seconds
Started Sep 01 06:56:25 AM UTC 24
Finished Sep 01 06:59:07 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230533866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1230533866
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/257.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/258.uart_fifo_reset.366225690
Short name T1128
Test name
Test status
Simulation time 124330086717 ps
CPU time 60 seconds
Started Sep 01 06:56:26 AM UTC 24
Finished Sep 01 06:57:28 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366225690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.366225690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/258.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/259.uart_fifo_reset.3886906447
Short name T1126
Test name
Test status
Simulation time 63504152523 ps
CPU time 53.33 seconds
Started Sep 01 06:56:27 AM UTC 24
Finished Sep 01 06:57:22 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886906447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3886906447
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/259.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_alert_test.1363097979
Short name T567
Test name
Test status
Simulation time 17003754 ps
CPU time 0.86 seconds
Started Sep 01 06:35:23 AM UTC 24
Finished Sep 01 06:35:25 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363097979 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1363097979
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_fifo_full.2568493709
Short name T133
Test name
Test status
Simulation time 25906937700 ps
CPU time 87.59 seconds
Started Sep 01 06:34:58 AM UTC 24
Finished Sep 01 06:36:27 AM UTC 24
Peak memory 208812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568493709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2568493709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.2727905423
Short name T619
Test name
Test status
Simulation time 41958408179 ps
CPU time 148.76 seconds
Started Sep 01 06:34:59 AM UTC 24
Finished Sep 01 06:37:30 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727905423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2727905423
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_fifo_reset.863139649
Short name T348
Test name
Test status
Simulation time 174396819461 ps
CPU time 228.1 seconds
Started Sep 01 06:35:00 AM UTC 24
Finished Sep 01 06:38:51 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863139649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.863139649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_intr.3442612940
Short name T569
Test name
Test status
Simulation time 25482717126 ps
CPU time 25.13 seconds
Started Sep 01 06:35:03 AM UTC 24
Finished Sep 01 06:35:29 AM UTC 24
Peak memory 208468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442612940 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3442612940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.2939364421
Short name T1141
Test name
Test status
Simulation time 138011981506 ps
CPU time 1342.41 seconds
Started Sep 01 06:35:17 AM UTC 24
Finished Sep 01 06:57:55 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939364421 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2939364421
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_loopback.92542864
Short name T568
Test name
Test status
Simulation time 2657598517 ps
CPU time 11.18 seconds
Started Sep 01 06:35:15 AM UTC 24
Finished Sep 01 06:35:28 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92542864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.uart_loopback.92542864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_noise_filter.2660085717
Short name T587
Test name
Test status
Simulation time 20023674432 ps
CPU time 78.81 seconds
Started Sep 01 06:35:06 AM UTC 24
Finished Sep 01 06:36:27 AM UTC 24
Peak memory 208968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660085717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2660085717
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_perf.4244725607
Short name T791
Test name
Test status
Simulation time 26696628445 ps
CPU time 495.59 seconds
Started Sep 01 06:35:16 AM UTC 24
Finished Sep 01 06:43:39 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244725607 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4244725607
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_rx_oversample.100487256
Short name T566
Test name
Test status
Simulation time 4777047921 ps
CPU time 15.84 seconds
Started Sep 01 06:35:00 AM UTC 24
Finished Sep 01 06:35:17 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100487256 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.100487256
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.545942538
Short name T582
Test name
Test status
Simulation time 27107386628 ps
CPU time 53.71 seconds
Started Sep 01 06:35:11 AM UTC 24
Finished Sep 01 06:36:06 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545942538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.545942538
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.2307771292
Short name T589
Test name
Test status
Simulation time 37895683503 ps
CPU time 83.93 seconds
Started Sep 01 06:35:07 AM UTC 24
Finished Sep 01 06:36:33 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307771292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2307771292
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_smoke.1346398849
Short name T560
Test name
Test status
Simulation time 320618371 ps
CPU time 1.88 seconds
Started Sep 01 06:34:56 AM UTC 24
Finished Sep 01 06:34:59 AM UTC 24
Peak memory 206436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346398849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1346398849
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_stress_all.403163988
Short name T1189
Test name
Test status
Simulation time 147346779633 ps
CPU time 2175.77 seconds
Started Sep 01 06:35:18 AM UTC 24
Finished Sep 01 07:11:58 AM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403163988 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.403163988
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.3625849092
Short name T576
Test name
Test status
Simulation time 26012091219 ps
CPU time 38.72 seconds
Started Sep 01 06:35:18 AM UTC 24
Finished Sep 01 06:35:58 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3625849092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all
_with_rand_reset.3625849092
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.4135871573
Short name T565
Test name
Test status
Simulation time 2106649266 ps
CPU time 2.64 seconds
Started Sep 01 06:35:12 AM UTC 24
Finished Sep 01 06:35:16 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135871573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.4135871573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/26.uart_tx_rx.4153917260
Short name T613
Test name
Test status
Simulation time 50600999616 ps
CPU time 136.09 seconds
Started Sep 01 06:34:57 AM UTC 24
Finished Sep 01 06:37:16 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153917260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.4153917260
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/26.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/260.uart_fifo_reset.345374675
Short name T1114
Test name
Test status
Simulation time 16458494609 ps
CPU time 25.97 seconds
Started Sep 01 06:56:27 AM UTC 24
Finished Sep 01 06:56:54 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345374675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.345374675
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/260.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/261.uart_fifo_reset.486127903
Short name T1145
Test name
Test status
Simulation time 162457598075 ps
CPU time 100.75 seconds
Started Sep 01 06:56:28 AM UTC 24
Finished Sep 01 06:58:11 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486127903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.486127903
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/261.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/262.uart_fifo_reset.3241343900
Short name T1157
Test name
Test status
Simulation time 158580215409 ps
CPU time 138.62 seconds
Started Sep 01 06:56:28 AM UTC 24
Finished Sep 01 06:58:49 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241343900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3241343900
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/262.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/263.uart_fifo_reset.572829809
Short name T1168
Test name
Test status
Simulation time 175683939061 ps
CPU time 195.64 seconds
Started Sep 01 06:56:29 AM UTC 24
Finished Sep 01 06:59:48 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572829809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.572829809
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/263.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/264.uart_fifo_reset.3889213255
Short name T1132
Test name
Test status
Simulation time 17039688847 ps
CPU time 59.49 seconds
Started Sep 01 06:56:32 AM UTC 24
Finished Sep 01 06:57:34 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889213255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3889213255
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/264.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/265.uart_fifo_reset.1229170527
Short name T1175
Test name
Test status
Simulation time 123441026006 ps
CPU time 204.65 seconds
Started Sep 01 06:56:33 AM UTC 24
Finished Sep 01 07:00:01 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229170527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1229170527
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/265.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/266.uart_fifo_reset.2776760892
Short name T1122
Test name
Test status
Simulation time 69879492787 ps
CPU time 39.83 seconds
Started Sep 01 06:56:38 AM UTC 24
Finished Sep 01 06:57:19 AM UTC 24
Peak memory 208548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776760892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2776760892
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/266.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1382258405
Short name T1140
Test name
Test status
Simulation time 21920028530 ps
CPU time 73.12 seconds
Started Sep 01 06:56:38 AM UTC 24
Finished Sep 01 06:57:53 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382258405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1382258405
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/267.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/268.uart_fifo_reset.855497456
Short name T1124
Test name
Test status
Simulation time 105916738296 ps
CPU time 40.31 seconds
Started Sep 01 06:56:39 AM UTC 24
Finished Sep 01 06:57:20 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855497456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.855497456
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/268.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/269.uart_fifo_reset.3295841634
Short name T1125
Test name
Test status
Simulation time 35115722421 ps
CPU time 37.48 seconds
Started Sep 01 06:56:43 AM UTC 24
Finished Sep 01 06:57:22 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295841634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3295841634
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/269.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_alert_test.3599741350
Short name T583
Test name
Test status
Simulation time 21518823 ps
CPU time 0.8 seconds
Started Sep 01 06:36:05 AM UTC 24
Finished Sep 01 06:36:07 AM UTC 24
Peak memory 204164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599741350 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3599741350
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_fifo_full.3141363793
Short name T144
Test name
Test status
Simulation time 114168472231 ps
CPU time 227.61 seconds
Started Sep 01 06:35:29 AM UTC 24
Finished Sep 01 06:39:20 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141363793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3141363793
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.2882670291
Short name T600
Test name
Test status
Simulation time 21839320082 ps
CPU time 74.53 seconds
Started Sep 01 06:35:30 AM UTC 24
Finished Sep 01 06:36:46 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882670291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.2882670291
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_fifo_reset.3655571944
Short name T149
Test name
Test status
Simulation time 104262714882 ps
CPU time 66.88 seconds
Started Sep 01 06:35:31 AM UTC 24
Finished Sep 01 06:36:40 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655571944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3655571944
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_intr.2037145037
Short name T847
Test name
Test status
Simulation time 305951385284 ps
CPU time 590.76 seconds
Started Sep 01 06:35:35 AM UTC 24
Finished Sep 01 06:45:33 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037145037 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2037145037
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2486760777
Short name T679
Test name
Test status
Simulation time 84958747280 ps
CPU time 258.26 seconds
Started Sep 01 06:35:59 AM UTC 24
Finished Sep 01 06:40:21 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486760777 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2486760777
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_loopback.2165508988
Short name T586
Test name
Test status
Simulation time 8838871523 ps
CPU time 26 seconds
Started Sep 01 06:35:56 AM UTC 24
Finished Sep 01 06:36:23 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165508988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2165508988
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_noise_filter.2056231620
Short name T445
Test name
Test status
Simulation time 96706005280 ps
CPU time 89.18 seconds
Started Sep 01 06:35:37 AM UTC 24
Finished Sep 01 06:37:09 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056231620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2056231620
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_perf.1015753565
Short name T792
Test name
Test status
Simulation time 29882139917 ps
CPU time 455.67 seconds
Started Sep 01 06:35:57 AM UTC 24
Finished Sep 01 06:43:39 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015753565 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1015753565
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_rx_oversample.371769437
Short name T595
Test name
Test status
Simulation time 6692010476 ps
CPU time 64.6 seconds
Started Sep 01 06:35:34 AM UTC 24
Finished Sep 01 06:36:41 AM UTC 24
Peak memory 207480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371769437 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.371769437
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.4162319873
Short name T585
Test name
Test status
Simulation time 50577861573 ps
CPU time 25.98 seconds
Started Sep 01 06:35:52 AM UTC 24
Finished Sep 01 06:36:19 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162319873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.4162319873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.2509045440
Short name T580
Test name
Test status
Simulation time 4762674383 ps
CPU time 18.84 seconds
Started Sep 01 06:35:44 AM UTC 24
Finished Sep 01 06:36:05 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509045440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2509045440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_smoke.702412999
Short name T578
Test name
Test status
Simulation time 6050096276 ps
CPU time 36.6 seconds
Started Sep 01 06:35:26 AM UTC 24
Finished Sep 01 06:36:04 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702412999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.uart_smoke.702412999
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_stress_all.1091057065
Short name T425
Test name
Test status
Simulation time 49888831347 ps
CPU time 85.87 seconds
Started Sep 01 06:36:05 AM UTC 24
Finished Sep 01 06:37:33 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091057065 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1091057065
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.3175279196
Short name T591
Test name
Test status
Simulation time 2266293870 ps
CPU time 29.67 seconds
Started Sep 01 06:36:03 AM UTC 24
Finished Sep 01 06:36:34 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3175279196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all
_with_rand_reset.3175279196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.863030872
Short name T574
Test name
Test status
Simulation time 1637651037 ps
CPU time 2.89 seconds
Started Sep 01 06:35:52 AM UTC 24
Finished Sep 01 06:35:55 AM UTC 24
Peak memory 207560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863030872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.863030872
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/27.uart_tx_rx.775043549
Short name T429
Test name
Test status
Simulation time 89737982629 ps
CPU time 200.99 seconds
Started Sep 01 06:35:29 AM UTC 24
Finished Sep 01 06:38:54 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775043549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.775043549
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/27.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/270.uart_fifo_reset.604296797
Short name T1120
Test name
Test status
Simulation time 31319157366 ps
CPU time 31.27 seconds
Started Sep 01 06:56:43 AM UTC 24
Finished Sep 01 06:57:15 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604296797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.604296797
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/270.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/271.uart_fifo_reset.2392838097
Short name T1148
Test name
Test status
Simulation time 86316527406 ps
CPU time 99.61 seconds
Started Sep 01 06:56:44 AM UTC 24
Finished Sep 01 06:58:26 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392838097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2392838097
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/271.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/272.uart_fifo_reset.2124146448
Short name T1169
Test name
Test status
Simulation time 96755033766 ps
CPU time 179.08 seconds
Started Sep 01 06:56:46 AM UTC 24
Finished Sep 01 06:59:48 AM UTC 24
Peak memory 208872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124146448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2124146448
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/272.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/274.uart_fifo_reset.729967166
Short name T1173
Test name
Test status
Simulation time 76687371874 ps
CPU time 181.99 seconds
Started Sep 01 06:56:51 AM UTC 24
Finished Sep 01 06:59:56 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729967166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.729967166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/274.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2752552874
Short name T1119
Test name
Test status
Simulation time 19289321918 ps
CPU time 20.16 seconds
Started Sep 01 06:56:52 AM UTC 24
Finished Sep 01 06:57:14 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752552874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2752552874
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/275.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/276.uart_fifo_reset.3008022915
Short name T210
Test name
Test status
Simulation time 27347882624 ps
CPU time 43.8 seconds
Started Sep 01 06:56:52 AM UTC 24
Finished Sep 01 06:57:38 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008022915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3008022915
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/276.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/277.uart_fifo_reset.2485805891
Short name T1131
Test name
Test status
Simulation time 72541097833 ps
CPU time 38.37 seconds
Started Sep 01 06:56:54 AM UTC 24
Finished Sep 01 06:57:33 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485805891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2485805891
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/277.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/278.uart_fifo_reset.3956638742
Short name T147
Test name
Test status
Simulation time 29958778078 ps
CPU time 34.73 seconds
Started Sep 01 06:56:55 AM UTC 24
Finished Sep 01 06:57:31 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956638742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3956638742
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/278.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2392998469
Short name T1130
Test name
Test status
Simulation time 14479182906 ps
CPU time 34.15 seconds
Started Sep 01 06:56:56 AM UTC 24
Finished Sep 01 06:57:31 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392998469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2392998469
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/279.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_alert_test.159087697
Short name T596
Test name
Test status
Simulation time 17387085 ps
CPU time 0.82 seconds
Started Sep 01 06:36:41 AM UTC 24
Finished Sep 01 06:36:43 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159087697 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.159087697
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_fifo_full.1419621761
Short name T588
Test name
Test status
Simulation time 24740128694 ps
CPU time 21.87 seconds
Started Sep 01 06:36:07 AM UTC 24
Finished Sep 01 06:36:31 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419621761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1419621761
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.1951551280
Short name T174
Test name
Test status
Simulation time 75205895132 ps
CPU time 89.98 seconds
Started Sep 01 06:36:07 AM UTC 24
Finished Sep 01 06:37:39 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951551280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.1951551280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_fifo_reset.811961612
Short name T422
Test name
Test status
Simulation time 45372194606 ps
CPU time 42.34 seconds
Started Sep 01 06:36:17 AM UTC 24
Finished Sep 01 06:37:00 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811961612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.811961612
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_intr.45809327
Short name T625
Test name
Test status
Simulation time 58276393877 ps
CPU time 79.41 seconds
Started Sep 01 06:36:20 AM UTC 24
Finished Sep 01 06:37:41 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45809327 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.45809327
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.2565781013
Short name T682
Test name
Test status
Simulation time 108145134972 ps
CPU time 225.42 seconds
Started Sep 01 06:36:34 AM UTC 24
Finished Sep 01 06:40:23 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565781013 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2565781013
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_loopback.1628019314
Short name T598
Test name
Test status
Simulation time 3025622840 ps
CPU time 12.94 seconds
Started Sep 01 06:36:31 AM UTC 24
Finished Sep 01 06:36:45 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628019314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1628019314
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_noise_filter.304630028
Short name T618
Test name
Test status
Simulation time 86230458308 ps
CPU time 59.07 seconds
Started Sep 01 06:36:24 AM UTC 24
Finished Sep 01 06:37:24 AM UTC 24
Peak memory 217608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304630028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.304630028
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_perf.1242884802
Short name T709
Test name
Test status
Simulation time 11354460500 ps
CPU time 284.98 seconds
Started Sep 01 06:36:33 AM UTC 24
Finished Sep 01 06:41:22 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242884802 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1242884802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_rx_oversample.3947384630
Short name T599
Test name
Test status
Simulation time 7748818530 ps
CPU time 25.35 seconds
Started Sep 01 06:36:20 AM UTC 24
Finished Sep 01 06:36:46 AM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947384630 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.3947384630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.3086462421
Short name T601
Test name
Test status
Simulation time 7930857813 ps
CPU time 18.94 seconds
Started Sep 01 06:36:28 AM UTC 24
Finished Sep 01 06:36:48 AM UTC 24
Peak memory 207472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086462421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3086462421
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.2026761074
Short name T592
Test name
Test status
Simulation time 3037220396 ps
CPU time 6.19 seconds
Started Sep 01 06:36:28 AM UTC 24
Finished Sep 01 06:36:35 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026761074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2026761074
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_smoke.751347587
Short name T593
Test name
Test status
Simulation time 5374255024 ps
CPU time 33.34 seconds
Started Sep 01 06:36:05 AM UTC 24
Finished Sep 01 06:36:40 AM UTC 24
Peak memory 208288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751347587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.uart_smoke.751347587
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_stress_all.3789197129
Short name T754
Test name
Test status
Simulation time 534414132252 ps
CPU time 343.41 seconds
Started Sep 01 06:36:35 AM UTC 24
Finished Sep 01 06:42:24 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789197129 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3789197129
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.4043868665
Short name T628
Test name
Test status
Simulation time 6249086529 ps
CPU time 85.07 seconds
Started Sep 01 06:36:34 AM UTC 24
Finished Sep 01 06:38:01 AM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4043868665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all
_with_rand_reset.4043868665
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.2732878723
Short name T603
Test name
Test status
Simulation time 6269841405 ps
CPU time 18.45 seconds
Started Sep 01 06:36:29 AM UTC 24
Finished Sep 01 06:36:49 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732878723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2732878723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/28.uart_tx_rx.4212001387
Short name T424
Test name
Test status
Simulation time 5401572433 ps
CPU time 10.93 seconds
Started Sep 01 06:36:06 AM UTC 24
Finished Sep 01 06:36:18 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212001387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.4212001387
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/28.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/280.uart_fifo_reset.442334360
Short name T1134
Test name
Test status
Simulation time 190604766826 ps
CPU time 40.96 seconds
Started Sep 01 06:56:56 AM UTC 24
Finished Sep 01 06:57:38 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442334360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.442334360
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/280.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/281.uart_fifo_reset.1412746300
Short name T1153
Test name
Test status
Simulation time 159831211064 ps
CPU time 97.96 seconds
Started Sep 01 06:57:00 AM UTC 24
Finished Sep 01 06:58:40 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412746300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1412746300
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/281.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/283.uart_fifo_reset.1295807289
Short name T1144
Test name
Test status
Simulation time 31608254657 ps
CPU time 66.98 seconds
Started Sep 01 06:57:02 AM UTC 24
Finished Sep 01 06:58:11 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295807289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1295807289
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/283.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2491291738
Short name T1160
Test name
Test status
Simulation time 44577001789 ps
CPU time 107.39 seconds
Started Sep 01 06:57:14 AM UTC 24
Finished Sep 01 06:59:04 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491291738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2491291738
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/284.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3038562329
Short name T230
Test name
Test status
Simulation time 13191596744 ps
CPU time 33.55 seconds
Started Sep 01 06:57:17 AM UTC 24
Finished Sep 01 06:57:52 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038562329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3038562329
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/286.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3699114128
Short name T1154
Test name
Test status
Simulation time 117522436311 ps
CPU time 81.33 seconds
Started Sep 01 06:57:19 AM UTC 24
Finished Sep 01 06:58:43 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699114128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3699114128
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/287.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/288.uart_fifo_reset.4119826987
Short name T1155
Test name
Test status
Simulation time 87736550696 ps
CPU time 83.73 seconds
Started Sep 01 06:57:21 AM UTC 24
Finished Sep 01 06:58:46 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119826987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.4119826987
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/288.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/289.uart_fifo_reset.3659345245
Short name T1133
Test name
Test status
Simulation time 11844972120 ps
CPU time 12.44 seconds
Started Sep 01 06:57:22 AM UTC 24
Finished Sep 01 06:57:35 AM UTC 24
Peak memory 208284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659345245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3659345245
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/289.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_alert_test.2057103850
Short name T607
Test name
Test status
Simulation time 214619278 ps
CPU time 0.84 seconds
Started Sep 01 06:37:08 AM UTC 24
Finished Sep 01 06:37:10 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057103850 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2057103850
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.3782478905
Short name T907
Test name
Test status
Simulation time 201959406516 ps
CPU time 686.57 seconds
Started Sep 01 06:36:44 AM UTC 24
Finished Sep 01 06:48:19 AM UTC 24
Peak memory 212152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782478905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3782478905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_fifo_reset.2115378210
Short name T188
Test name
Test status
Simulation time 111724261301 ps
CPU time 218.17 seconds
Started Sep 01 06:36:45 AM UTC 24
Finished Sep 01 06:40:26 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115378210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2115378210
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_intr.3665514512
Short name T606
Test name
Test status
Simulation time 21931823977 ps
CPU time 19.98 seconds
Started Sep 01 06:36:46 AM UTC 24
Finished Sep 01 06:37:08 AM UTC 24
Peak memory 207888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665514512 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3665514512
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.272941468
Short name T675
Test name
Test status
Simulation time 194457094695 ps
CPU time 185.52 seconds
Started Sep 01 06:37:06 AM UTC 24
Finished Sep 01 06:40:14 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272941468 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.272941468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_loopback.2581749319
Short name T615
Test name
Test status
Simulation time 6817793609 ps
CPU time 26.95 seconds
Started Sep 01 06:36:55 AM UTC 24
Finished Sep 01 06:37:23 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581749319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2581749319
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_noise_filter.2690432175
Short name T622
Test name
Test status
Simulation time 56738340335 ps
CPU time 46.65 seconds
Started Sep 01 06:36:47 AM UTC 24
Finished Sep 01 06:37:35 AM UTC 24
Peak memory 209028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690432175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2690432175
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_perf.2316443388
Short name T1070
Test name
Test status
Simulation time 16193255216 ps
CPU time 1057.33 seconds
Started Sep 01 06:37:01 AM UTC 24
Finished Sep 01 06:54:50 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316443388 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2316443388
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_rx_oversample.1169629590
Short name T605
Test name
Test status
Simulation time 5830788021 ps
CPU time 17.09 seconds
Started Sep 01 06:36:46 AM UTC 24
Finished Sep 01 06:37:05 AM UTC 24
Peak memory 207380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169629590 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1169629590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.399594423
Short name T610
Test name
Test status
Simulation time 56848010260 ps
CPU time 21.5 seconds
Started Sep 01 06:36:49 AM UTC 24
Finished Sep 01 06:37:12 AM UTC 24
Peak memory 208416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399594423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.399594423
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.3233063274
Short name T602
Test name
Test status
Simulation time 4138370718 ps
CPU time 16.87 seconds
Started Sep 01 06:36:47 AM UTC 24
Finished Sep 01 06:37:05 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233063274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3233063274
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_smoke.2714510119
Short name T597
Test name
Test status
Simulation time 523104260 ps
CPU time 1.94 seconds
Started Sep 01 06:36:41 AM UTC 24
Finished Sep 01 06:36:44 AM UTC 24
Peak memory 207872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714510119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.2714510119
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_stress_all.2519808781
Short name T764
Test name
Test status
Simulation time 297144760237 ps
CPU time 339.86 seconds
Started Sep 01 06:37:06 AM UTC 24
Finished Sep 01 06:42:50 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519808781 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2519808781
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.79920536
Short name T626
Test name
Test status
Simulation time 6438835951 ps
CPU time 37.34 seconds
Started Sep 01 06:37:06 AM UTC 24
Finished Sep 01 06:37:45 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=79920536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all_w
ith_rand_reset.79920536
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.1860001373
Short name T604
Test name
Test status
Simulation time 1847182375 ps
CPU time 2.82 seconds
Started Sep 01 06:36:49 AM UTC 24
Finished Sep 01 06:36:53 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860001373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1860001373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/29.uart_tx_rx.840714331
Short name T611
Test name
Test status
Simulation time 68858000076 ps
CPU time 30.78 seconds
Started Sep 01 06:36:41 AM UTC 24
Finished Sep 01 06:37:13 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840714331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.840714331
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/29.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/290.uart_fifo_reset.3311232965
Short name T218
Test name
Test status
Simulation time 59010166439 ps
CPU time 52.93 seconds
Started Sep 01 06:57:23 AM UTC 24
Finished Sep 01 06:58:17 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311232965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3311232965
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/290.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/291.uart_fifo_reset.2156040592
Short name T1136
Test name
Test status
Simulation time 36538267398 ps
CPU time 21.83 seconds
Started Sep 01 06:57:23 AM UTC 24
Finished Sep 01 06:57:46 AM UTC 24
Peak memory 208864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156040592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2156040592
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/291.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/292.uart_fifo_reset.1516347541
Short name T1147
Test name
Test status
Simulation time 130521013534 ps
CPU time 52.91 seconds
Started Sep 01 06:57:28 AM UTC 24
Finished Sep 01 06:58:23 AM UTC 24
Peak memory 208464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516347541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1516347541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/292.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/293.uart_fifo_reset.4272633408
Short name T1164
Test name
Test status
Simulation time 54924973719 ps
CPU time 110.88 seconds
Started Sep 01 06:57:28 AM UTC 24
Finished Sep 01 06:59:21 AM UTC 24
Peak memory 208596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272633408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4272633408
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/293.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/294.uart_fifo_reset.3140709219
Short name T211
Test name
Test status
Simulation time 76442516047 ps
CPU time 18.48 seconds
Started Sep 01 06:57:30 AM UTC 24
Finished Sep 01 06:57:50 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140709219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3140709219
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/294.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3887187349
Short name T199
Test name
Test status
Simulation time 75956354915 ps
CPU time 40.05 seconds
Started Sep 01 06:57:31 AM UTC 24
Finished Sep 01 06:58:13 AM UTC 24
Peak memory 208680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887187349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3887187349
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/295.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/297.uart_fifo_reset.750425717
Short name T1142
Test name
Test status
Simulation time 24802049342 ps
CPU time 31.12 seconds
Started Sep 01 06:57:33 AM UTC 24
Finished Sep 01 06:58:06 AM UTC 24
Peak memory 208476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750425717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.750425717
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/297.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1785663005
Short name T1152
Test name
Test status
Simulation time 61517751534 ps
CPU time 63.1 seconds
Started Sep 01 06:57:34 AM UTC 24
Finished Sep 01 06:58:39 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785663005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1785663005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/298.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/299.uart_fifo_reset.781030195
Short name T1182
Test name
Test status
Simulation time 112637892824 ps
CPU time 453.48 seconds
Started Sep 01 06:57:34 AM UTC 24
Finished Sep 01 07:05:14 AM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781030195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.781030195
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/299.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_alert_test.3678427919
Short name T448
Test name
Test status
Simulation time 86774402 ps
CPU time 0.84 seconds
Started Sep 01 06:25:42 AM UTC 24
Finished Sep 01 06:25:44 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678427919 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3678427919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_fifo_full.2929835228
Short name T106
Test name
Test status
Simulation time 131166887857 ps
CPU time 69.7 seconds
Started Sep 01 06:25:31 AM UTC 24
Finished Sep 01 06:26:43 AM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929835228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2929835228
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_fifo_reset.3235221612
Short name T49
Test name
Test status
Simulation time 98997625930 ps
CPU time 107.35 seconds
Started Sep 01 06:25:32 AM UTC 24
Finished Sep 01 06:27:22 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235221612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3235221612
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.3221581609
Short name T300
Test name
Test status
Simulation time 73630473778 ps
CPU time 145.88 seconds
Started Sep 01 06:25:40 AM UTC 24
Finished Sep 01 06:28:08 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221581609 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3221581609
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_loopback.4186214669
Short name T450
Test name
Test status
Simulation time 6507536432 ps
CPU time 16.28 seconds
Started Sep 01 06:25:39 AM UTC 24
Finished Sep 01 06:25:56 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186214669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.4186214669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_noise_filter.2189374769
Short name T262
Test name
Test status
Simulation time 155589137497 ps
CPU time 108.38 seconds
Started Sep 01 06:25:36 AM UTC 24
Finished Sep 01 06:27:27 AM UTC 24
Peak memory 208576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189374769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2189374769
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_perf.1980424419
Short name T711
Test name
Test status
Simulation time 14046598621 ps
CPU time 933.13 seconds
Started Sep 01 06:25:39 AM UTC 24
Finished Sep 01 06:41:23 AM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980424419 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.1980424419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_rx_oversample.3264839705
Short name T28
Test name
Test status
Simulation time 1783795445 ps
CPU time 6.46 seconds
Started Sep 01 06:25:34 AM UTC 24
Finished Sep 01 06:25:42 AM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264839705 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3264839705
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.261222402
Short name T295
Test name
Test status
Simulation time 44361097733 ps
CPU time 51.43 seconds
Started Sep 01 06:25:37 AM UTC 24
Finished Sep 01 06:26:30 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261222402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.261222402
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_sec_cm.78878261
Short name T84
Test name
Test status
Simulation time 151593062 ps
CPU time 1.16 seconds
Started Sep 01 06:25:41 AM UTC 24
Finished Sep 01 06:25:43 AM UTC 24
Peak memory 237460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78878261 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.78878261
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_smoke.2579671731
Short name T42
Test name
Test status
Simulation time 899688759 ps
CPU time 4.31 seconds
Started Sep 01 06:25:30 AM UTC 24
Finished Sep 01 06:25:36 AM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579671731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2579671731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.2202907096
Short name T21
Test name
Test status
Simulation time 3750468290 ps
CPU time 33.92 seconds
Started Sep 01 06:25:40 AM UTC 24
Finished Sep 01 06:26:15 AM UTC 24
Peak memory 223956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2202907096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_
with_rand_reset.2202907096
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.1787889317
Short name T44
Test name
Test status
Simulation time 1882948590 ps
CPU time 3.35 seconds
Started Sep 01 06:25:38 AM UTC 24
Finished Sep 01 06:25:42 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787889317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1787889317
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/3.uart_tx_rx.3471736658
Short name T33
Test name
Test status
Simulation time 57895940653 ps
CPU time 32.44 seconds
Started Sep 01 06:25:30 AM UTC 24
Finished Sep 01 06:26:04 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471736658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3471736658
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/3.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_alert_test.3102956619
Short name T621
Test name
Test status
Simulation time 29592153 ps
CPU time 0.83 seconds
Started Sep 01 06:37:31 AM UTC 24
Finished Sep 01 06:37:33 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102956619 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3102956619
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.3414093452
Short name T639
Test name
Test status
Simulation time 102828845087 ps
CPU time 73.21 seconds
Started Sep 01 06:37:13 AM UTC 24
Finished Sep 01 06:38:28 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414093452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3414093452
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_fifo_reset.1605463941
Short name T617
Test name
Test status
Simulation time 25406393087 ps
CPU time 9.24 seconds
Started Sep 01 06:37:13 AM UTC 24
Finished Sep 01 06:37:24 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605463941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1605463941
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_intr.976258512
Short name T635
Test name
Test status
Simulation time 37151813431 ps
CPU time 56.51 seconds
Started Sep 01 06:37:17 AM UTC 24
Finished Sep 01 06:38:15 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976258512 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.976258512
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.3100107108
Short name T725
Test name
Test status
Simulation time 35100644636 ps
CPU time 246.78 seconds
Started Sep 01 06:37:25 AM UTC 24
Finished Sep 01 06:41:36 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100107108 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3100107108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_loopback.4261047530
Short name T629
Test name
Test status
Simulation time 8316192289 ps
CPU time 37.54 seconds
Started Sep 01 06:37:25 AM UTC 24
Finished Sep 01 06:38:04 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261047530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.4261047530
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_noise_filter.4238448026
Short name T630
Test name
Test status
Simulation time 129995986376 ps
CPU time 46.94 seconds
Started Sep 01 06:37:17 AM UTC 24
Finished Sep 01 06:38:05 AM UTC 24
Peak memory 208128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238448026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.4238448026
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_perf.4281459950
Short name T1025
Test name
Test status
Simulation time 12626638522 ps
CPU time 900.77 seconds
Started Sep 01 06:37:25 AM UTC 24
Finished Sep 01 06:52:37 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281459950 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.4281459950
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_rx_oversample.3225623649
Short name T641
Test name
Test status
Simulation time 6463104668 ps
CPU time 75.18 seconds
Started Sep 01 06:37:15 AM UTC 24
Finished Sep 01 06:38:32 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225623649 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3225623649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.76743022
Short name T702
Test name
Test status
Simulation time 132235897446 ps
CPU time 226.16 seconds
Started Sep 01 06:37:22 AM UTC 24
Finished Sep 01 06:41:11 AM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76743022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.76743022
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.1089756017
Short name T616
Test name
Test status
Simulation time 4595292048 ps
CPU time 4.87 seconds
Started Sep 01 06:37:18 AM UTC 24
Finished Sep 01 06:37:24 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089756017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1089756017
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_smoke.3710807022
Short name T609
Test name
Test status
Simulation time 503283274 ps
CPU time 2.02 seconds
Started Sep 01 06:37:09 AM UTC 24
Finished Sep 01 06:37:12 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710807022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3710807022
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_stress_all.3540438971
Short name T770
Test name
Test status
Simulation time 313298661691 ps
CPU time 320.11 seconds
Started Sep 01 06:37:31 AM UTC 24
Finished Sep 01 06:42:56 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540438971 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3540438971
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.3422059276
Short name T653
Test name
Test status
Simulation time 8225107093 ps
CPU time 102.59 seconds
Started Sep 01 06:37:29 AM UTC 24
Finished Sep 01 06:39:14 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3422059276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all
_with_rand_reset.3422059276
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.2317907407
Short name T620
Test name
Test status
Simulation time 765999467 ps
CPU time 5.03 seconds
Started Sep 01 06:37:24 AM UTC 24
Finished Sep 01 06:37:30 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317907407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2317907407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/30.uart_tx_rx.2799633844
Short name T624
Test name
Test status
Simulation time 113559217234 ps
CPU time 28.34 seconds
Started Sep 01 06:37:11 AM UTC 24
Finished Sep 01 06:37:41 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799633844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2799633844
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/30.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_alert_test.400214652
Short name T636
Test name
Test status
Simulation time 30163294 ps
CPU time 0.8 seconds
Started Sep 01 06:38:16 AM UTC 24
Finished Sep 01 06:38:18 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400214652 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.400214652
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_fifo_full.3380956394
Short name T659
Test name
Test status
Simulation time 138458188751 ps
CPU time 118.97 seconds
Started Sep 01 06:37:37 AM UTC 24
Finished Sep 01 06:39:38 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380956394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3380956394
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.3203649500
Short name T138
Test name
Test status
Simulation time 137061733280 ps
CPU time 241.63 seconds
Started Sep 01 06:37:40 AM UTC 24
Finished Sep 01 06:41:45 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203649500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3203649500
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_fifo_reset.1321196507
Short name T666
Test name
Test status
Simulation time 270246455327 ps
CPU time 126.4 seconds
Started Sep 01 06:37:41 AM UTC 24
Finished Sep 01 06:39:50 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321196507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1321196507
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_intr.3731087089
Short name T699
Test name
Test status
Simulation time 257806094793 ps
CPU time 195.26 seconds
Started Sep 01 06:37:42 AM UTC 24
Finished Sep 01 06:41:00 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731087089 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3731087089
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.3697466457
Short name T724
Test name
Test status
Simulation time 359723952317 ps
CPU time 199.82 seconds
Started Sep 01 06:38:12 AM UTC 24
Finished Sep 01 06:41:35 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697466457 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3697466457
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_loopback.827339365
Short name T634
Test name
Test status
Simulation time 6113726699 ps
CPU time 7.88 seconds
Started Sep 01 06:38:05 AM UTC 24
Finished Sep 01 06:38:15 AM UTC 24
Peak memory 208928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827339365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.uart_loopback.827339365
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_noise_filter.3544558620
Short name T729
Test name
Test status
Simulation time 140075445884 ps
CPU time 228.98 seconds
Started Sep 01 06:37:45 AM UTC 24
Finished Sep 01 06:41:37 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544558620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3544558620
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_perf.1942438398
Short name T781
Test name
Test status
Simulation time 30473190560 ps
CPU time 307.97 seconds
Started Sep 01 06:38:06 AM UTC 24
Finished Sep 01 06:43:18 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942438398 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1942438398
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_rx_oversample.1374482327
Short name T637
Test name
Test status
Simulation time 4847439647 ps
CPU time 34.41 seconds
Started Sep 01 06:37:42 AM UTC 24
Finished Sep 01 06:38:18 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374482327 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1374482327
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.329488523
Short name T151
Test name
Test status
Simulation time 16754090595 ps
CPU time 62.16 seconds
Started Sep 01 06:37:59 AM UTC 24
Finished Sep 01 06:39:03 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329488523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.329488523
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.2431819400
Short name T640
Test name
Test status
Simulation time 44751629026 ps
CPU time 30.87 seconds
Started Sep 01 06:37:57 AM UTC 24
Finished Sep 01 06:38:30 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431819400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2431819400
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_smoke.4077504646
Short name T631
Test name
Test status
Simulation time 5994629174 ps
CPU time 35.46 seconds
Started Sep 01 06:37:33 AM UTC 24
Finished Sep 01 06:38:10 AM UTC 24
Peak memory 208400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077504646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4077504646
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_stress_all.4065607754
Short name T684
Test name
Test status
Simulation time 144050687525 ps
CPU time 127.94 seconds
Started Sep 01 06:38:14 AM UTC 24
Finished Sep 01 06:40:24 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065607754 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.4065607754
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.3431407644
Short name T688
Test name
Test status
Simulation time 8851614259 ps
CPU time 142.07 seconds
Started Sep 01 06:38:14 AM UTC 24
Finished Sep 01 06:40:39 AM UTC 24
Peak memory 225388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3431407644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all
_with_rand_reset.3431407644
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.903845255
Short name T633
Test name
Test status
Simulation time 11105928550 ps
CPU time 9.8 seconds
Started Sep 01 06:38:02 AM UTC 24
Finished Sep 01 06:38:13 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903845255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.903845255
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/31.uart_tx_rx.3429002497
Short name T627
Test name
Test status
Simulation time 11421493800 ps
CPU time 22.48 seconds
Started Sep 01 06:37:35 AM UTC 24
Finished Sep 01 06:37:58 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429002497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3429002497
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/31.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_alert_test.2281348613
Short name T650
Test name
Test status
Simulation time 27365548 ps
CPU time 0.83 seconds
Started Sep 01 06:38:57 AM UTC 24
Finished Sep 01 06:38:59 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281348613 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2281348613
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_fifo_full.3065655422
Short name T648
Test name
Test status
Simulation time 35257356518 ps
CPU time 37.64 seconds
Started Sep 01 06:38:18 AM UTC 24
Finished Sep 01 06:38:57 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065655422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3065655422
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.3482403641
Short name T660
Test name
Test status
Simulation time 20254294788 ps
CPU time 79.14 seconds
Started Sep 01 06:38:19 AM UTC 24
Finished Sep 01 06:39:40 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482403641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.3482403641
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_fifo_reset.4089320797
Short name T652
Test name
Test status
Simulation time 34495708757 ps
CPU time 41.47 seconds
Started Sep 01 06:38:20 AM UTC 24
Finished Sep 01 06:39:03 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089320797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.4089320797
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_intr.2745145080
Short name T683
Test name
Test status
Simulation time 55422193617 ps
CPU time 112 seconds
Started Sep 01 06:38:29 AM UTC 24
Finished Sep 01 06:40:24 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745145080 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2745145080
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.3563700335
Short name T767
Test name
Test status
Simulation time 93754530773 ps
CPU time 236.85 seconds
Started Sep 01 06:38:54 AM UTC 24
Finished Sep 01 06:42:54 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563700335 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3563700335
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_loopback.1961320111
Short name T649
Test name
Test status
Simulation time 7156972495 ps
CPU time 5.37 seconds
Started Sep 01 06:38:52 AM UTC 24
Finished Sep 01 06:38:58 AM UTC 24
Peak memory 208236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961320111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1961320111
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_noise_filter.4066136569
Short name T654
Test name
Test status
Simulation time 135875498557 ps
CPU time 44.71 seconds
Started Sep 01 06:38:31 AM UTC 24
Finished Sep 01 06:39:17 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066136569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.4066136569
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_perf.1499886703
Short name T784
Test name
Test status
Simulation time 8197256207 ps
CPU time 264.59 seconds
Started Sep 01 06:38:54 AM UTC 24
Finished Sep 01 06:43:23 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499886703 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1499886703
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_rx_oversample.936941414
Short name T643
Test name
Test status
Simulation time 6648072432 ps
CPU time 24.37 seconds
Started Sep 01 06:38:22 AM UTC 24
Finished Sep 01 06:38:48 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936941414 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.936941414
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.58196738
Short name T657
Test name
Test status
Simulation time 25413817983 ps
CPU time 51.91 seconds
Started Sep 01 06:38:37 AM UTC 24
Finished Sep 01 06:39:30 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58196738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.58196738
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.1256546866
Short name T642
Test name
Test status
Simulation time 4395928286 ps
CPU time 2.67 seconds
Started Sep 01 06:38:33 AM UTC 24
Finished Sep 01 06:38:36 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256546866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1256546866
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_smoke.2733486930
Short name T638
Test name
Test status
Simulation time 843707399 ps
CPU time 4.93 seconds
Started Sep 01 06:38:16 AM UTC 24
Finished Sep 01 06:38:22 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733486930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2733486930
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_stress_all.2592290819
Short name T160
Test name
Test status
Simulation time 230226468511 ps
CPU time 776.89 seconds
Started Sep 01 06:38:56 AM UTC 24
Finished Sep 01 06:52:03 AM UTC 24
Peak memory 222652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592290819 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2592290819
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.3671974744
Short name T665
Test name
Test status
Simulation time 6164737125 ps
CPU time 51.88 seconds
Started Sep 01 06:38:55 AM UTC 24
Finished Sep 01 06:39:49 AM UTC 24
Peak memory 217580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3671974744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all
_with_rand_reset.3671974744
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.3617039592
Short name T644
Test name
Test status
Simulation time 1682200608 ps
CPU time 3.69 seconds
Started Sep 01 06:38:49 AM UTC 24
Finished Sep 01 06:38:54 AM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617039592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3617039592
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/32.uart_tx_rx.4161527609
Short name T426
Test name
Test status
Simulation time 55252323591 ps
CPU time 56.86 seconds
Started Sep 01 06:38:18 AM UTC 24
Finished Sep 01 06:39:17 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161527609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.4161527609
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/32.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_alert_test.3340664301
Short name T662
Test name
Test status
Simulation time 14198494 ps
CPU time 0.86 seconds
Started Sep 01 06:39:41 AM UTC 24
Finished Sep 01 06:39:43 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340664301 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.3340664301
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_fifo_full.3250880202
Short name T673
Test name
Test status
Simulation time 127950328405 ps
CPU time 72.23 seconds
Started Sep 01 06:39:00 AM UTC 24
Finished Sep 01 06:40:13 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250880202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3250880202
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.3413155101
Short name T739
Test name
Test status
Simulation time 121779218085 ps
CPU time 175.47 seconds
Started Sep 01 06:39:04 AM UTC 24
Finished Sep 01 06:42:02 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413155101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3413155101
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_intr.3903074122
Short name T728
Test name
Test status
Simulation time 59378657724 ps
CPU time 147.76 seconds
Started Sep 01 06:39:07 AM UTC 24
Finished Sep 01 06:41:37 AM UTC 24
Peak memory 207904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903074122 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3903074122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.2176663662
Short name T1080
Test name
Test status
Simulation time 95509472216 ps
CPU time 927.77 seconds
Started Sep 01 06:39:32 AM UTC 24
Finished Sep 01 06:55:11 AM UTC 24
Peak memory 212144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176663662 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2176663662
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_loopback.2394989830
Short name T661
Test name
Test status
Simulation time 4833885952 ps
CPU time 17.24 seconds
Started Sep 01 06:39:23 AM UTC 24
Finished Sep 01 06:39:42 AM UTC 24
Peak memory 207276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394989830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2394989830
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_noise_filter.2446387873
Short name T435
Test name
Test status
Simulation time 8251937627 ps
CPU time 30.68 seconds
Started Sep 01 06:39:15 AM UTC 24
Finished Sep 01 06:39:47 AM UTC 24
Peak memory 205240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446387873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2446387873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_perf.3148242367
Short name T807
Test name
Test status
Simulation time 23678133231 ps
CPU time 276.38 seconds
Started Sep 01 06:39:26 AM UTC 24
Finished Sep 01 06:44:07 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148242367 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3148242367
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_rx_oversample.2893747014
Short name T672
Test name
Test status
Simulation time 6508601119 ps
CPU time 67.15 seconds
Started Sep 01 06:39:04 AM UTC 24
Finished Sep 01 06:40:13 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893747014 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2893747014
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.338431937
Short name T153
Test name
Test status
Simulation time 39293833040 ps
CPU time 78.84 seconds
Started Sep 01 06:39:17 AM UTC 24
Finished Sep 01 06:40:38 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338431937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.338431937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.4042391497
Short name T655
Test name
Test status
Simulation time 1983567315 ps
CPU time 3.81 seconds
Started Sep 01 06:39:17 AM UTC 24
Finished Sep 01 06:39:22 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042391497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.4042391497
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_smoke.1849915608
Short name T651
Test name
Test status
Simulation time 431371123 ps
CPU time 3.36 seconds
Started Sep 01 06:38:58 AM UTC 24
Finished Sep 01 06:39:03 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849915608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1849915608
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_stress_all.945790873
Short name T723
Test name
Test status
Simulation time 218940561832 ps
CPU time 113.55 seconds
Started Sep 01 06:39:39 AM UTC 24
Finished Sep 01 06:41:35 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945790873 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.945790873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.4071278069
Short name T670
Test name
Test status
Simulation time 10467420747 ps
CPU time 23.02 seconds
Started Sep 01 06:39:37 AM UTC 24
Finished Sep 01 06:40:01 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4071278069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all
_with_rand_reset.4071278069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.119590742
Short name T681
Test name
Test status
Simulation time 12672871480 ps
CPU time 58.79 seconds
Started Sep 01 06:39:21 AM UTC 24
Finished Sep 01 06:40:22 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119590742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.119590742
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/33.uart_tx_rx.1078473353
Short name T719
Test name
Test status
Simulation time 46935928912 ps
CPU time 148.4 seconds
Started Sep 01 06:39:00 AM UTC 24
Finished Sep 01 06:41:30 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078473353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1078473353
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/33.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_alert_test.551223313
Short name T676
Test name
Test status
Simulation time 21133160 ps
CPU time 0.87 seconds
Started Sep 01 06:40:15 AM UTC 24
Finished Sep 01 06:40:17 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551223313 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.551223313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_fifo_full.2282273937
Short name T701
Test name
Test status
Simulation time 147230510760 ps
CPU time 79.92 seconds
Started Sep 01 06:39:46 AM UTC 24
Finished Sep 01 06:41:08 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282273937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2282273937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.1454434205
Short name T386
Test name
Test status
Simulation time 129514037080 ps
CPU time 185.7 seconds
Started Sep 01 06:39:47 AM UTC 24
Finished Sep 01 06:42:56 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454434205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1454434205
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_fifo_reset.92648931
Short name T718
Test name
Test status
Simulation time 51181047727 ps
CPU time 99.8 seconds
Started Sep 01 06:39:48 AM UTC 24
Finished Sep 01 06:41:30 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92648931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.92648931
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_intr.3493335040
Short name T695
Test name
Test status
Simulation time 29545451602 ps
CPU time 59.49 seconds
Started Sep 01 06:39:50 AM UTC 24
Finished Sep 01 06:40:52 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493335040 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.3493335040
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.3697745654
Short name T765
Test name
Test status
Simulation time 48040268328 ps
CPU time 156.76 seconds
Started Sep 01 06:40:13 AM UTC 24
Finished Sep 01 06:42:53 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697745654 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3697745654
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_loopback.2068935682
Short name T687
Test name
Test status
Simulation time 11495184364 ps
CPU time 33.26 seconds
Started Sep 01 06:40:04 AM UTC 24
Finished Sep 01 06:40:39 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068935682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2068935682
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_noise_filter.2645906144
Short name T698
Test name
Test status
Simulation time 17533082354 ps
CPU time 67.54 seconds
Started Sep 01 06:39:51 AM UTC 24
Finished Sep 01 06:41:00 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645906144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2645906144
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_perf.300120905
Short name T437
Test name
Test status
Simulation time 32927339194 ps
CPU time 189.11 seconds
Started Sep 01 06:40:11 AM UTC 24
Finished Sep 01 06:43:23 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300120905 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.300120905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_rx_oversample.774648140
Short name T668
Test name
Test status
Simulation time 3149420162 ps
CPU time 2.72 seconds
Started Sep 01 06:39:49 AM UTC 24
Finished Sep 01 06:39:53 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774648140 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.774648140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.3972925110
Short name T713
Test name
Test status
Simulation time 20083618511 ps
CPU time 85.47 seconds
Started Sep 01 06:39:57 AM UTC 24
Finished Sep 01 06:41:24 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972925110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.3972925110
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1514202848
Short name T674
Test name
Test status
Simulation time 4725978978 ps
CPU time 19.16 seconds
Started Sep 01 06:39:54 AM UTC 24
Finished Sep 01 06:40:14 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514202848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1514202848
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_smoke.3176576261
Short name T663
Test name
Test status
Simulation time 567715044 ps
CPU time 1.8 seconds
Started Sep 01 06:39:43 AM UTC 24
Finished Sep 01 06:39:46 AM UTC 24
Peak memory 206396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176576261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3176576261
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_stress_all.2368373183
Short name T805
Test name
Test status
Simulation time 95897162372 ps
CPU time 221.66 seconds
Started Sep 01 06:40:15 AM UTC 24
Finished Sep 01 06:44:00 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368373183 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.2368373183
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.3289635818
Short name T714
Test name
Test status
Simulation time 16512834413 ps
CPU time 68.87 seconds
Started Sep 01 06:40:14 AM UTC 24
Finished Sep 01 06:41:25 AM UTC 24
Peak memory 217812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3289635818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all
_with_rand_reset.3289635818
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.3418965628
Short name T678
Test name
Test status
Simulation time 8356776808 ps
CPU time 16.52 seconds
Started Sep 01 06:40:02 AM UTC 24
Finished Sep 01 06:40:20 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418965628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3418965628
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/34.uart_tx_rx.2578114453
Short name T677
Test name
Test status
Simulation time 63229442489 ps
CPU time 32.94 seconds
Started Sep 01 06:39:44 AM UTC 24
Finished Sep 01 06:40:18 AM UTC 24
Peak memory 208620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578114453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2578114453
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/34.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_alert_test.1254417519
Short name T692
Test name
Test status
Simulation time 27311394 ps
CPU time 0.82 seconds
Started Sep 01 06:40:42 AM UTC 24
Finished Sep 01 06:40:44 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254417519 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1254417519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_fifo_full.2848913468
Short name T741
Test name
Test status
Simulation time 46863785938 ps
CPU time 99.82 seconds
Started Sep 01 06:40:21 AM UTC 24
Finished Sep 01 06:42:02 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848913468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2848913468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.1380735840
Short name T1052
Test name
Test status
Simulation time 310560683294 ps
CPU time 804.74 seconds
Started Sep 01 06:40:22 AM UTC 24
Finished Sep 01 06:53:56 AM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380735840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1380735840
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_fifo_reset.107159343
Short name T850
Test name
Test status
Simulation time 123651147197 ps
CPU time 314.99 seconds
Started Sep 01 06:40:23 AM UTC 24
Finished Sep 01 06:45:42 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107159343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.107159343
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_intr.3242624316
Short name T734
Test name
Test status
Simulation time 22144412138 ps
CPU time 75.93 seconds
Started Sep 01 06:40:24 AM UTC 24
Finished Sep 01 06:41:42 AM UTC 24
Peak memory 208236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242624316 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3242624316
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.3376770441
Short name T964
Test name
Test status
Simulation time 143869555020 ps
CPU time 585.35 seconds
Started Sep 01 06:40:40 AM UTC 24
Finished Sep 01 06:50:32 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376770441 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3376770441
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_loopback.819863900
Short name T694
Test name
Test status
Simulation time 4682419606 ps
CPU time 18.65 seconds
Started Sep 01 06:40:29 AM UTC 24
Finished Sep 01 06:40:49 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819863900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_loopback.819863900
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_noise_filter.296463661
Short name T721
Test name
Test status
Simulation time 29361509208 ps
CPU time 65.49 seconds
Started Sep 01 06:40:25 AM UTC 24
Finished Sep 01 06:41:32 AM UTC 24
Peak memory 207496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296463661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.296463661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_perf.3467247414
Short name T788
Test name
Test status
Simulation time 19365192248 ps
CPU time 166.05 seconds
Started Sep 01 06:40:39 AM UTC 24
Finished Sep 01 06:43:28 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467247414 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3467247414
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_rx_oversample.2876701516
Short name T689
Test name
Test status
Simulation time 6038763497 ps
CPU time 15.13 seconds
Started Sep 01 06:40:23 AM UTC 24
Finished Sep 01 06:40:39 AM UTC 24
Peak memory 207980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876701516 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.2876701516
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.1466984483
Short name T696
Test name
Test status
Simulation time 30471320497 ps
CPU time 23.17 seconds
Started Sep 01 06:40:27 AM UTC 24
Finished Sep 01 06:40:52 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466984483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1466984483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.3175095901
Short name T685
Test name
Test status
Simulation time 403844773 ps
CPU time 1.8 seconds
Started Sep 01 06:40:25 AM UTC 24
Finished Sep 01 06:40:28 AM UTC 24
Peak memory 204436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175095901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.3175095901
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_smoke.2263136785
Short name T680
Test name
Test status
Simulation time 454392549 ps
CPU time 2.44 seconds
Started Sep 01 06:40:18 AM UTC 24
Finished Sep 01 06:40:22 AM UTC 24
Peak memory 208548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263136785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.2263136785
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_stress_all.2986086439
Short name T1087
Test name
Test status
Simulation time 292463089491 ps
CPU time 884.43 seconds
Started Sep 01 06:40:41 AM UTC 24
Finished Sep 01 06:55:36 AM UTC 24
Peak memory 212140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986086439 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2986086439
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.1901627623
Short name T703
Test name
Test status
Simulation time 2034534100 ps
CPU time 30.49 seconds
Started Sep 01 06:40:40 AM UTC 24
Finished Sep 01 06:41:12 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1901627623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all
_with_rand_reset.1901627623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.3039085603
Short name T690
Test name
Test status
Simulation time 6932568202 ps
CPU time 10.51 seconds
Started Sep 01 06:40:29 AM UTC 24
Finished Sep 01 06:40:41 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039085603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3039085603
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/35.uart_tx_rx.1464580979
Short name T686
Test name
Test status
Simulation time 8020781763 ps
CPU time 7.93 seconds
Started Sep 01 06:40:20 AM UTC 24
Finished Sep 01 06:40:29 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464580979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1464580979
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/35.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_alert_test.166385615
Short name T712
Test name
Test status
Simulation time 15747960 ps
CPU time 0.85 seconds
Started Sep 01 06:41:22 AM UTC 24
Finished Sep 01 06:41:23 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166385615 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.166385615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_fifo_full.2345616327
Short name T707
Test name
Test status
Simulation time 13480366557 ps
CPU time 31.25 seconds
Started Sep 01 06:40:47 AM UTC 24
Finished Sep 01 06:41:20 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345616327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2345616327
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.2513682038
Short name T154
Test name
Test status
Simulation time 99837993200 ps
CPU time 50.74 seconds
Started Sep 01 06:40:50 AM UTC 24
Finished Sep 01 06:41:43 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513682038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2513682038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_fifo_reset.3081516969
Short name T710
Test name
Test status
Simulation time 16897869329 ps
CPU time 28.9 seconds
Started Sep 01 06:40:52 AM UTC 24
Finished Sep 01 06:41:23 AM UTC 24
Peak memory 208548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081516969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3081516969
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_intr.6151126
Short name T727
Test name
Test status
Simulation time 53309393528 ps
CPU time 34.61 seconds
Started Sep 01 06:41:01 AM UTC 24
Finished Sep 01 06:41:37 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6151126 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.6151126
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.3247573259
Short name T975
Test name
Test status
Simulation time 236245813510 ps
CPU time 579.28 seconds
Started Sep 01 06:41:13 AM UTC 24
Finished Sep 01 06:50:59 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247573259 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3247573259
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_loopback.926184640
Short name T708
Test name
Test status
Simulation time 6595743814 ps
CPU time 8.17 seconds
Started Sep 01 06:41:12 AM UTC 24
Finished Sep 01 06:41:21 AM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926184640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.uart_loopback.926184640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_noise_filter.1965791570
Short name T716
Test name
Test status
Simulation time 16198194895 ps
CPU time 23.23 seconds
Started Sep 01 06:41:01 AM UTC 24
Finished Sep 01 06:41:25 AM UTC 24
Peak memory 203192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965791570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.1965791570
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_perf.3229233495
Short name T846
Test name
Test status
Simulation time 8488563655 ps
CPU time 254.33 seconds
Started Sep 01 06:41:12 AM UTC 24
Finished Sep 01 06:45:30 AM UTC 24
Peak memory 208516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229233495 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3229233495
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_rx_oversample.2678002962
Short name T715
Test name
Test status
Simulation time 5761282869 ps
CPU time 31.17 seconds
Started Sep 01 06:40:52 AM UTC 24
Finished Sep 01 06:41:25 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678002962 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2678002962
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.2710085558
Short name T748
Test name
Test status
Simulation time 24477502270 ps
CPU time 63.95 seconds
Started Sep 01 06:41:08 AM UTC 24
Finished Sep 01 06:42:13 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710085558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.2710085558
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.3033620764
Short name T700
Test name
Test status
Simulation time 1924893892 ps
CPU time 3.95 seconds
Started Sep 01 06:41:02 AM UTC 24
Finished Sep 01 06:41:07 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033620764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.3033620764
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_smoke.3662640193
Short name T693
Test name
Test status
Simulation time 305054316 ps
CPU time 1.56 seconds
Started Sep 01 06:40:44 AM UTC 24
Finished Sep 01 06:40:47 AM UTC 24
Peak memory 206508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662640193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3662640193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_stress_all.409700045
Short name T839
Test name
Test status
Simulation time 82413961683 ps
CPU time 234.11 seconds
Started Sep 01 06:41:18 AM UTC 24
Finished Sep 01 06:45:16 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409700045 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.409700045
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.2349950381
Short name T733
Test name
Test status
Simulation time 1756929340 ps
CPU time 22.99 seconds
Started Sep 01 06:41:17 AM UTC 24
Finished Sep 01 06:41:42 AM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2349950381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all
_with_rand_reset.2349950381
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.952082685
Short name T705
Test name
Test status
Simulation time 1054100274 ps
CPU time 6.34 seconds
Started Sep 01 06:41:09 AM UTC 24
Finished Sep 01 06:41:16 AM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952082685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.952082685
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/36.uart_tx_rx.2611168868
Short name T706
Test name
Test status
Simulation time 9317636942 ps
CPU time 30.87 seconds
Started Sep 01 06:40:45 AM UTC 24
Finished Sep 01 06:41:18 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611168868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2611168868
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/36.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_alert_test.1620768602
Short name T730
Test name
Test status
Simulation time 13643893 ps
CPU time 0.86 seconds
Started Sep 01 06:41:36 AM UTC 24
Finished Sep 01 06:41:38 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620768602 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1620768602
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_fifo_full.1943222784
Short name T759
Test name
Test status
Simulation time 117402498212 ps
CPU time 67.57 seconds
Started Sep 01 06:41:24 AM UTC 24
Finished Sep 01 06:42:33 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943222784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1943222784
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.3461477526
Short name T740
Test name
Test status
Simulation time 22669247180 ps
CPU time 36.84 seconds
Started Sep 01 06:41:24 AM UTC 24
Finished Sep 01 06:42:02 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461477526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3461477526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_fifo_reset.3459058590
Short name T749
Test name
Test status
Simulation time 70100236164 ps
CPU time 50.63 seconds
Started Sep 01 06:41:24 AM UTC 24
Finished Sep 01 06:42:16 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459058590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3459058590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_intr.2611275885
Short name T763
Test name
Test status
Simulation time 41238247319 ps
CPU time 81.14 seconds
Started Sep 01 06:41:26 AM UTC 24
Finished Sep 01 06:42:49 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611275885 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2611275885
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.1834468977
Short name T853
Test name
Test status
Simulation time 63687940402 ps
CPU time 248.03 seconds
Started Sep 01 06:41:34 AM UTC 24
Finished Sep 01 06:45:45 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834468977 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.1834468977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_loopback.256466977
Short name T732
Test name
Test status
Simulation time 8900624324 ps
CPU time 8.52 seconds
Started Sep 01 06:41:31 AM UTC 24
Finished Sep 01 06:41:41 AM UTC 24
Peak memory 208604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256466977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.uart_loopback.256466977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_noise_filter.2024762266
Short name T745
Test name
Test status
Simulation time 25699115113 ps
CPU time 39.12 seconds
Started Sep 01 06:41:26 AM UTC 24
Finished Sep 01 06:42:07 AM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024762266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2024762266
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_perf.957325166
Short name T768
Test name
Test status
Simulation time 5211044320 ps
CPU time 80.78 seconds
Started Sep 01 06:41:33 AM UTC 24
Finished Sep 01 06:42:55 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957325166 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.957325166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_rx_oversample.1175693624
Short name T722
Test name
Test status
Simulation time 2664746321 ps
CPU time 7.16 seconds
Started Sep 01 06:41:25 AM UTC 24
Finished Sep 01 06:41:33 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175693624 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1175693624
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.340243662
Short name T440
Test name
Test status
Simulation time 66320043397 ps
CPU time 56.66 seconds
Started Sep 01 06:41:26 AM UTC 24
Finished Sep 01 06:42:25 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340243662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.340243662
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.3667931436
Short name T738
Test name
Test status
Simulation time 75966773240 ps
CPU time 33.75 seconds
Started Sep 01 06:41:26 AM UTC 24
Finished Sep 01 06:42:01 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667931436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3667931436
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_smoke.1250053795
Short name T717
Test name
Test status
Simulation time 740017704 ps
CPU time 2.22 seconds
Started Sep 01 06:41:23 AM UTC 24
Finished Sep 01 06:41:26 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250053795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1250053795
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_stress_all.1511830801
Short name T387
Test name
Test status
Simulation time 239701478003 ps
CPU time 145.22 seconds
Started Sep 01 06:41:36 AM UTC 24
Finished Sep 01 06:44:04 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511830801 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1511830801
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.164936898
Short name T755
Test name
Test status
Simulation time 2843888912 ps
CPU time 50.8 seconds
Started Sep 01 06:41:34 AM UTC 24
Finished Sep 01 06:42:26 AM UTC 24
Peak memory 217604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=164936898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all_
with_rand_reset.164936898
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.7859015
Short name T726
Test name
Test status
Simulation time 1233283908 ps
CPU time 3.07 seconds
Started Sep 01 06:41:31 AM UTC 24
Finished Sep 01 06:41:36 AM UTC 24
Peak memory 208584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7859015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.7859015
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/37.uart_tx_rx.2642364935
Short name T831
Test name
Test status
Simulation time 93994586821 ps
CPU time 209.21 seconds
Started Sep 01 06:41:24 AM UTC 24
Finished Sep 01 06:44:56 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642364935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2642364935
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/37.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_alert_test.4097491923
Short name T742
Test name
Test status
Simulation time 38242314 ps
CPU time 0.83 seconds
Started Sep 01 06:42:02 AM UTC 24
Finished Sep 01 06:42:04 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097491923 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4097491923
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_fifo_full.163615730
Short name T751
Test name
Test status
Simulation time 26365136693 ps
CPU time 40.1 seconds
Started Sep 01 06:41:38 AM UTC 24
Finished Sep 01 06:42:20 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163615730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.163615730
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.79146042
Short name T886
Test name
Test status
Simulation time 255838036939 ps
CPU time 334.12 seconds
Started Sep 01 06:41:38 AM UTC 24
Finished Sep 01 06:47:17 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79146042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.79146042
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_fifo_reset.3927685621
Short name T176
Test name
Test status
Simulation time 173310020283 ps
CPU time 67.47 seconds
Started Sep 01 06:41:38 AM UTC 24
Finished Sep 01 06:42:47 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927685621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3927685621
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_intr.914359953
Short name T760
Test name
Test status
Simulation time 17393313441 ps
CPU time 51.84 seconds
Started Sep 01 06:41:41 AM UTC 24
Finished Sep 01 06:42:35 AM UTC 24
Peak memory 207228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914359953 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.914359953
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.4054541774
Short name T958
Test name
Test status
Simulation time 245566227170 ps
CPU time 504.45 seconds
Started Sep 01 06:41:48 AM UTC 24
Finished Sep 01 06:50:19 AM UTC 24
Peak memory 208676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054541774 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.4054541774
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_loopback.1023147299
Short name T746
Test name
Test status
Simulation time 5193369122 ps
CPU time 21.3 seconds
Started Sep 01 06:41:46 AM UTC 24
Finished Sep 01 06:42:08 AM UTC 24
Peak memory 208672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023147299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1023147299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_noise_filter.1024239627
Short name T431
Test name
Test status
Simulation time 2080984208 ps
CPU time 4.12 seconds
Started Sep 01 06:41:41 AM UTC 24
Finished Sep 01 06:41:47 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024239627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1024239627
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_perf.4097711724
Short name T775
Test name
Test status
Simulation time 3489795990 ps
CPU time 79.07 seconds
Started Sep 01 06:41:47 AM UTC 24
Finished Sep 01 06:43:08 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097711724 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.4097711724
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1792058313
Short name T736
Test name
Test status
Simulation time 4949570375 ps
CPU time 7.29 seconds
Started Sep 01 06:41:38 AM UTC 24
Finished Sep 01 06:41:47 AM UTC 24
Peak memory 207480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792058313 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1792058313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.3908746194
Short name T779
Test name
Test status
Simulation time 69421600366 ps
CPU time 90.57 seconds
Started Sep 01 06:41:43 AM UTC 24
Finished Sep 01 06:43:15 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908746194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3908746194
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.1179885828
Short name T737
Test name
Test status
Simulation time 4762219794 ps
CPU time 3.19 seconds
Started Sep 01 06:41:43 AM UTC 24
Finished Sep 01 06:41:47 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179885828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1179885828
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_smoke.4261185031
Short name T731
Test name
Test status
Simulation time 467119721 ps
CPU time 2.63 seconds
Started Sep 01 06:41:37 AM UTC 24
Finished Sep 01 06:41:41 AM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261185031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.4261185031
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_stress_all.1802179158
Short name T257
Test name
Test status
Simulation time 321933980534 ps
CPU time 558.11 seconds
Started Sep 01 06:41:48 AM UTC 24
Finished Sep 01 06:51:13 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802179158 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1802179158
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.2507479651
Short name T743
Test name
Test status
Simulation time 2128773472 ps
CPU time 15.25 seconds
Started Sep 01 06:41:48 AM UTC 24
Finished Sep 01 06:42:04 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2507479651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all
_with_rand_reset.2507479651
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.1406226712
Short name T735
Test name
Test status
Simulation time 614760064 ps
CPU time 1.47 seconds
Started Sep 01 06:41:44 AM UTC 24
Finished Sep 01 06:41:46 AM UTC 24
Peak memory 206488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406226712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1406226712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/38.uart_tx_rx.3358943084
Short name T747
Test name
Test status
Simulation time 62204704649 ps
CPU time 34.74 seconds
Started Sep 01 06:41:37 AM UTC 24
Finished Sep 01 06:42:13 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358943084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3358943084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/38.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_alert_test.2443601908
Short name T756
Test name
Test status
Simulation time 78072172 ps
CPU time 0.85 seconds
Started Sep 01 06:42:26 AM UTC 24
Finished Sep 01 06:42:28 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443601908 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2443601908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_fifo_full.1914140882
Short name T790
Test name
Test status
Simulation time 35936392464 ps
CPU time 87.04 seconds
Started Sep 01 06:42:03 AM UTC 24
Finished Sep 01 06:43:32 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914140882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1914140882
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.4103820737
Short name T842
Test name
Test status
Simulation time 90831867519 ps
CPU time 196.26 seconds
Started Sep 01 06:42:05 AM UTC 24
Finished Sep 01 06:45:24 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103820737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4103820737
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_fifo_reset.1996685893
Short name T202
Test name
Test status
Simulation time 45650195662 ps
CPU time 50.79 seconds
Started Sep 01 06:42:06 AM UTC 24
Finished Sep 01 06:42:58 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996685893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1996685893
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_intr.3039812429
Short name T802
Test name
Test status
Simulation time 44119072029 ps
CPU time 103.38 seconds
Started Sep 01 06:42:08 AM UTC 24
Finished Sep 01 06:43:54 AM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039812429 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.3039812429
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.1991133564
Short name T900
Test name
Test status
Simulation time 125077577613 ps
CPU time 326.87 seconds
Started Sep 01 06:42:21 AM UTC 24
Finished Sep 01 06:47:53 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991133564 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1991133564
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_loopback.39893832
Short name T761
Test name
Test status
Simulation time 5519292368 ps
CPU time 22.08 seconds
Started Sep 01 06:42:18 AM UTC 24
Finished Sep 01 06:42:42 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39893832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.uart_loopback.39893832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_noise_filter.820744824
Short name T785
Test name
Test status
Simulation time 187013842574 ps
CPU time 74.98 seconds
Started Sep 01 06:42:09 AM UTC 24
Finished Sep 01 06:43:26 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820744824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.820744824
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_perf.3065854262
Short name T932
Test name
Test status
Simulation time 13516573281 ps
CPU time 418.7 seconds
Started Sep 01 06:42:20 AM UTC 24
Finished Sep 01 06:49:25 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065854262 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3065854262
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_rx_oversample.3987047806
Short name T757
Test name
Test status
Simulation time 7270455508 ps
CPU time 21.89 seconds
Started Sep 01 06:42:07 AM UTC 24
Finished Sep 01 06:42:30 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987047806 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3987047806
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.3358797230
Short name T131
Test name
Test status
Simulation time 140312763728 ps
CPU time 108.71 seconds
Started Sep 01 06:42:14 AM UTC 24
Finished Sep 01 06:44:05 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358797230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3358797230
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.3099291833
Short name T750
Test name
Test status
Simulation time 1307713205 ps
CPU time 2.25 seconds
Started Sep 01 06:42:14 AM UTC 24
Finished Sep 01 06:42:17 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099291833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3099291833
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_smoke.3962219640
Short name T744
Test name
Test status
Simulation time 715081493 ps
CPU time 2.02 seconds
Started Sep 01 06:42:03 AM UTC 24
Finished Sep 01 06:42:06 AM UTC 24
Peak memory 206440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962219640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3962219640
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_stress_all.1755969315
Short name T982
Test name
Test status
Simulation time 317353811821 ps
CPU time 529.42 seconds
Started Sep 01 06:42:25 AM UTC 24
Finished Sep 01 06:51:20 AM UTC 24
Peak memory 225060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755969315 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1755969315
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.3511411526
Short name T762
Test name
Test status
Simulation time 3140622270 ps
CPU time 23.39 seconds
Started Sep 01 06:42:24 AM UTC 24
Finished Sep 01 06:42:48 AM UTC 24
Peak memory 209044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3511411526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all
_with_rand_reset.3511411526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.4273654516
Short name T753
Test name
Test status
Simulation time 2362123902 ps
CPU time 4.2 seconds
Started Sep 01 06:42:17 AM UTC 24
Finished Sep 01 06:42:23 AM UTC 24
Peak memory 208004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273654516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.4273654516
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/39.uart_tx_rx.954968211
Short name T806
Test name
Test status
Simulation time 67009774104 ps
CPU time 119.18 seconds
Started Sep 01 06:42:03 AM UTC 24
Finished Sep 01 06:44:05 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954968211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.954968211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/39.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_alert_test.3971684936
Short name T451
Test name
Test status
Simulation time 25142105 ps
CPU time 0.83 seconds
Started Sep 01 06:25:57 AM UTC 24
Finished Sep 01 06:25:59 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971684936 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3971684936
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.2906825235
Short name T143
Test name
Test status
Simulation time 97927731579 ps
CPU time 118.22 seconds
Started Sep 01 06:25:43 AM UTC 24
Finished Sep 01 06:27:44 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906825235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2906825235
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_fifo_reset.2401106674
Short name T91
Test name
Test status
Simulation time 22556068440 ps
CPU time 31.41 seconds
Started Sep 01 06:25:43 AM UTC 24
Finished Sep 01 06:26:16 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401106674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2401106674
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_intr.3056043566
Short name T349
Test name
Test status
Simulation time 385928493057 ps
CPU time 210.39 seconds
Started Sep 01 06:25:45 AM UTC 24
Finished Sep 01 06:29:18 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056043566 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3056043566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.2687144139
Short name T612
Test name
Test status
Simulation time 99482075904 ps
CPU time 675.42 seconds
Started Sep 01 06:25:52 AM UTC 24
Finished Sep 01 06:37:16 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687144139 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.2687144139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_loopback.3334022446
Short name T449
Test name
Test status
Simulation time 80876786 ps
CPU time 0.93 seconds
Started Sep 01 06:25:50 AM UTC 24
Finished Sep 01 06:25:52 AM UTC 24
Peak memory 204440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334022446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3334022446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_noise_filter.2361000408
Short name T267
Test name
Test status
Simulation time 43917544128 ps
CPU time 97.58 seconds
Started Sep 01 06:25:46 AM UTC 24
Finished Sep 01 06:27:25 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361000408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2361000408
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_perf.3414707625
Short name T297
Test name
Test status
Simulation time 14912054516 ps
CPU time 243.61 seconds
Started Sep 01 06:25:51 AM UTC 24
Finished Sep 01 06:29:58 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414707625 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3414707625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_rx_oversample.3762745031
Short name T47
Test name
Test status
Simulation time 6161339988 ps
CPU time 38.6 seconds
Started Sep 01 06:25:44 AM UTC 24
Finished Sep 01 06:26:25 AM UTC 24
Peak memory 207048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762745031 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3762745031
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.1618031311
Short name T19
Test name
Test status
Simulation time 117601374797 ps
CPU time 41.12 seconds
Started Sep 01 06:25:48 AM UTC 24
Finished Sep 01 06:26:30 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618031311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1618031311
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.265987942
Short name T292
Test name
Test status
Simulation time 1759269570 ps
CPU time 2.3 seconds
Started Sep 01 06:25:47 AM UTC 24
Finished Sep 01 06:25:50 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265987942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.265987942
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_sec_cm.3096617924
Short name T85
Test name
Test status
Simulation time 59271530 ps
CPU time 1.13 seconds
Started Sep 01 06:25:55 AM UTC 24
Finished Sep 01 06:25:57 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096617924 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3096617924
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_smoke.1610144594
Short name T45
Test name
Test status
Simulation time 266406736 ps
CPU time 2.35 seconds
Started Sep 01 06:25:42 AM UTC 24
Finished Sep 01 06:25:45 AM UTC 24
Peak memory 207548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610144594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1610144594
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.2139029088
Short name T37
Test name
Test status
Simulation time 2971121968 ps
CPU time 46.64 seconds
Started Sep 01 06:25:53 AM UTC 24
Finished Sep 01 06:26:41 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2139029088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_
with_rand_reset.2139029088
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.416003347
Short name T359
Test name
Test status
Simulation time 763398349 ps
CPU time 5.33 seconds
Started Sep 01 06:25:48 AM UTC 24
Finished Sep 01 06:25:54 AM UTC 24
Peak memory 207600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416003347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.416003347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/4.uart_tx_rx.2520150892
Short name T48
Test name
Test status
Simulation time 19566805165 ps
CPU time 56.95 seconds
Started Sep 01 06:25:43 AM UTC 24
Finished Sep 01 06:26:42 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520150892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2520150892
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/4.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_alert_test.2429262340
Short name T772
Test name
Test status
Simulation time 14840920 ps
CPU time 0.85 seconds
Started Sep 01 06:42:57 AM UTC 24
Finished Sep 01 06:42:59 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429262340 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2429262340
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_fifo_full.1631693708
Short name T783
Test name
Test status
Simulation time 453434282758 ps
CPU time 48.41 seconds
Started Sep 01 06:42:31 AM UTC 24
Finished Sep 01 06:43:21 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631693708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1631693708
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.282713409
Short name T776
Test name
Test status
Simulation time 13888946925 ps
CPU time 36.4 seconds
Started Sep 01 06:42:31 AM UTC 24
Finished Sep 01 06:43:09 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282713409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.282713409
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_fifo_reset.3300104370
Short name T441
Test name
Test status
Simulation time 75997906460 ps
CPU time 76.42 seconds
Started Sep 01 06:42:34 AM UTC 24
Finished Sep 01 06:43:52 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300104370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3300104370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_intr.2546582280
Short name T811
Test name
Test status
Simulation time 24320334262 ps
CPU time 87.42 seconds
Started Sep 01 06:42:42 AM UTC 24
Finished Sep 01 06:44:12 AM UTC 24
Peak memory 208152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546582280 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.2546582280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.2406684635
Short name T1179
Test name
Test status
Simulation time 114147399166 ps
CPU time 1087.05 seconds
Started Sep 01 06:42:55 AM UTC 24
Finished Sep 01 07:01:15 AM UTC 24
Peak memory 212228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406684635 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.2406684635
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_loopback.2766700984
Short name T774
Test name
Test status
Simulation time 6105510850 ps
CPU time 8.91 seconds
Started Sep 01 06:42:54 AM UTC 24
Finished Sep 01 06:43:04 AM UTC 24
Peak memory 208656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766700984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2766700984
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_noise_filter.1034317417
Short name T823
Test name
Test status
Simulation time 381856077735 ps
CPU time 109.67 seconds
Started Sep 01 06:42:48 AM UTC 24
Finished Sep 01 06:44:40 AM UTC 24
Peak memory 217624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034317417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1034317417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_perf.2106067765
Short name T1014
Test name
Test status
Simulation time 31018695302 ps
CPU time 552.79 seconds
Started Sep 01 06:42:55 AM UTC 24
Finished Sep 01 06:52:15 AM UTC 24
Peak memory 208712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106067765 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2106067765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_rx_oversample.2564388926
Short name T777
Test name
Test status
Simulation time 3663025272 ps
CPU time 33.61 seconds
Started Sep 01 06:42:35 AM UTC 24
Finished Sep 01 06:43:10 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564388926 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2564388926
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.2366542033
Short name T895
Test name
Test status
Simulation time 121521068881 ps
CPU time 285.06 seconds
Started Sep 01 06:42:50 AM UTC 24
Finished Sep 01 06:47:39 AM UTC 24
Peak memory 208664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366542033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2366542033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.3306164967
Short name T766
Test name
Test status
Simulation time 747395890 ps
CPU time 3.74 seconds
Started Sep 01 06:42:50 AM UTC 24
Finished Sep 01 06:42:54 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306164967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3306164967
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_smoke.1380498310
Short name T758
Test name
Test status
Simulation time 863653366 ps
CPU time 2.77 seconds
Started Sep 01 06:42:27 AM UTC 24
Finished Sep 01 06:42:31 AM UTC 24
Peak memory 207900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380498310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1380498310
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_stress_all.1320411432
Short name T824
Test name
Test status
Simulation time 321650668001 ps
CPU time 105.59 seconds
Started Sep 01 06:42:56 AM UTC 24
Finished Sep 01 06:44:44 AM UTC 24
Peak memory 219832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320411432 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1320411432
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.2811276228
Short name T787
Test name
Test status
Simulation time 4773220825 ps
CPU time 30.13 seconds
Started Sep 01 06:42:56 AM UTC 24
Finished Sep 01 06:43:28 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2811276228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all
_with_rand_reset.2811276228
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.3636674501
Short name T789
Test name
Test status
Simulation time 6783989139 ps
CPU time 38.08 seconds
Started Sep 01 06:42:51 AM UTC 24
Finished Sep 01 06:43:30 AM UTC 24
Peak memory 208536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636674501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3636674501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/40.uart_tx_rx.3380655222
Short name T771
Test name
Test status
Simulation time 32577404677 ps
CPU time 27.08 seconds
Started Sep 01 06:42:28 AM UTC 24
Finished Sep 01 06:42:56 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380655222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3380655222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/40.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_alert_test.1443226785
Short name T786
Test name
Test status
Simulation time 82305750 ps
CPU time 0.84 seconds
Started Sep 01 06:43:25 AM UTC 24
Finished Sep 01 06:43:27 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443226785 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1443226785
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_fifo_full.3456537120
Short name T801
Test name
Test status
Simulation time 33644968791 ps
CPU time 50.58 seconds
Started Sep 01 06:42:59 AM UTC 24
Finished Sep 01 06:43:52 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456537120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3456537120
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.3171969879
Short name T808
Test name
Test status
Simulation time 170731648712 ps
CPU time 66.68 seconds
Started Sep 01 06:43:00 AM UTC 24
Finished Sep 01 06:44:08 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171969879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3171969879
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_fifo_reset.2574956350
Short name T438
Test name
Test status
Simulation time 76167155436 ps
CPU time 66.75 seconds
Started Sep 01 06:43:01 AM UTC 24
Finished Sep 01 06:44:09 AM UTC 24
Peak memory 208504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574956350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2574956350
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_intr.1413389107
Short name T778
Test name
Test status
Simulation time 4106352245 ps
CPU time 5.07 seconds
Started Sep 01 06:43:09 AM UTC 24
Finished Sep 01 06:43:15 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413389107 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1413389107
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.4287790752
Short name T826
Test name
Test status
Simulation time 149419206407 ps
CPU time 83.48 seconds
Started Sep 01 06:43:21 AM UTC 24
Finished Sep 01 06:44:47 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287790752 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4287790752
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_loopback.567275069
Short name T793
Test name
Test status
Simulation time 7749312069 ps
CPU time 20.77 seconds
Started Sep 01 06:43:17 AM UTC 24
Finished Sep 01 06:43:39 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567275069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.uart_loopback.567275069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_noise_filter.2813532294
Short name T892
Test name
Test status
Simulation time 219908737465 ps
CPU time 261.08 seconds
Started Sep 01 06:43:10 AM UTC 24
Finished Sep 01 06:47:35 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813532294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2813532294
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_perf.1913221598
Short name T840
Test name
Test status
Simulation time 7773939771 ps
CPU time 116.89 seconds
Started Sep 01 06:43:18 AM UTC 24
Finished Sep 01 06:45:17 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913221598 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1913221598
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_rx_oversample.1993847593
Short name T780
Test name
Test status
Simulation time 3672646313 ps
CPU time 10.84 seconds
Started Sep 01 06:43:05 AM UTC 24
Finished Sep 01 06:43:17 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993847593 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1993847593
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.3948995159
Short name T157
Test name
Test status
Simulation time 283618397307 ps
CPU time 73.07 seconds
Started Sep 01 06:43:16 AM UTC 24
Finished Sep 01 06:44:31 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948995159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3948995159
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.3114807996
Short name T816
Test name
Test status
Simulation time 42812416160 ps
CPU time 75.07 seconds
Started Sep 01 06:43:11 AM UTC 24
Finished Sep 01 06:44:28 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114807996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3114807996
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_smoke.2349520169
Short name T773
Test name
Test status
Simulation time 965256674 ps
CPU time 1.77 seconds
Started Sep 01 06:42:57 AM UTC 24
Finished Sep 01 06:43:00 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349520169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2349520169
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_stress_all.3576552904
Short name T942
Test name
Test status
Simulation time 207524589833 ps
CPU time 376.92 seconds
Started Sep 01 06:43:24 AM UTC 24
Finished Sep 01 06:49:45 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576552904 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3576552904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.3020183852
Short name T798
Test name
Test status
Simulation time 3194222205 ps
CPU time 23.16 seconds
Started Sep 01 06:43:21 AM UTC 24
Finished Sep 01 06:43:46 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3020183852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all
_with_rand_reset.3020183852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.83313720
Short name T782
Test name
Test status
Simulation time 1814556240 ps
CPU time 3.23 seconds
Started Sep 01 06:43:16 AM UTC 24
Finished Sep 01 06:43:20 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83313720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.83313720
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/41.uart_tx_rx.65341378
Short name T427
Test name
Test status
Simulation time 19503754776 ps
CPU time 33.73 seconds
Started Sep 01 06:42:57 AM UTC 24
Finished Sep 01 06:43:32 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65341378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.65341378
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/41.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_alert_test.1469534697
Short name T800
Test name
Test status
Simulation time 27499922 ps
CPU time 0.82 seconds
Started Sep 01 06:43:48 AM UTC 24
Finished Sep 01 06:43:50 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469534697 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1469534697
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_fifo_full.1100262582
Short name T814
Test name
Test status
Simulation time 44697294438 ps
CPU time 47.01 seconds
Started Sep 01 06:43:29 AM UTC 24
Finished Sep 01 06:44:18 AM UTC 24
Peak memory 207896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100262582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1100262582
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.1512866542
Short name T880
Test name
Test status
Simulation time 151432075501 ps
CPU time 197.34 seconds
Started Sep 01 06:43:29 AM UTC 24
Finished Sep 01 06:46:50 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512866542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1512866542
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_fifo_reset.308343191
Short name T235
Test name
Test status
Simulation time 24209669793 ps
CPU time 13.79 seconds
Started Sep 01 06:43:31 AM UTC 24
Finished Sep 01 06:43:47 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308343191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.308343191
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_intr.3481887847
Short name T804
Test name
Test status
Simulation time 22033311040 ps
CPU time 20.97 seconds
Started Sep 01 06:43:33 AM UTC 24
Finished Sep 01 06:43:56 AM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481887847 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3481887847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.1372429928
Short name T929
Test name
Test status
Simulation time 141958769907 ps
CPU time 327.19 seconds
Started Sep 01 06:43:44 AM UTC 24
Finished Sep 01 06:49:16 AM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372429928 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1372429928
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_loopback.171762036
Short name T797
Test name
Test status
Simulation time 122259809 ps
CPU time 1.64 seconds
Started Sep 01 06:43:43 AM UTC 24
Finished Sep 01 06:43:46 AM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171762036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.uart_loopback.171762036
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_noise_filter.1942561167
Short name T819
Test name
Test status
Simulation time 89107950576 ps
CPU time 52.98 seconds
Started Sep 01 06:43:38 AM UTC 24
Finished Sep 01 06:44:33 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942561167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1942561167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_perf.3679022937
Short name T1158
Test name
Test status
Simulation time 14306529578 ps
CPU time 896.9 seconds
Started Sep 01 06:43:44 AM UTC 24
Finished Sep 01 06:58:52 AM UTC 24
Peak memory 212200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679022937 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3679022937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_rx_oversample.968948747
Short name T796
Test name
Test status
Simulation time 1377120829 ps
CPU time 8.66 seconds
Started Sep 01 06:43:33 AM UTC 24
Finished Sep 01 06:43:43 AM UTC 24
Peak memory 207420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968948747 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.968948747
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.151227051
Short name T818
Test name
Test status
Simulation time 37075101081 ps
CPU time 50.49 seconds
Started Sep 01 06:43:39 AM UTC 24
Finished Sep 01 06:44:31 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151227051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.151227051
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.4241989831
Short name T795
Test name
Test status
Simulation time 4555238423 ps
CPU time 2.31 seconds
Started Sep 01 06:43:39 AM UTC 24
Finished Sep 01 06:43:43 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241989831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.4241989831
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_smoke.1888683853
Short name T794
Test name
Test status
Simulation time 6101498582 ps
CPU time 13.46 seconds
Started Sep 01 06:43:27 AM UTC 24
Finished Sep 01 06:43:41 AM UTC 24
Peak memory 208160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888683853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1888683853
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_stress_all.2668805318
Short name T924
Test name
Test status
Simulation time 322678941358 ps
CPU time 321.17 seconds
Started Sep 01 06:43:47 AM UTC 24
Finished Sep 01 06:49:13 AM UTC 24
Peak memory 225344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668805318 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2668805318
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.1280539334
Short name T417
Test name
Test status
Simulation time 8781679545 ps
CPU time 67.62 seconds
Started Sep 01 06:43:46 AM UTC 24
Finished Sep 01 06:44:56 AM UTC 24
Peak memory 217844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1280539334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all
_with_rand_reset.1280539334
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.50568816
Short name T799
Test name
Test status
Simulation time 903877477 ps
CPU time 5.41 seconds
Started Sep 01 06:43:41 AM UTC 24
Finished Sep 01 06:43:47 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50568816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.50568816
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/42.uart_tx_rx.1598120268
Short name T858
Test name
Test status
Simulation time 59759138829 ps
CPU time 142.44 seconds
Started Sep 01 06:43:28 AM UTC 24
Finished Sep 01 06:45:53 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598120268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1598120268
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/42.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_alert_test.1827587076
Short name T813
Test name
Test status
Simulation time 26131711 ps
CPU time 0.84 seconds
Started Sep 01 06:44:13 AM UTC 24
Finished Sep 01 06:44:14 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827587076 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1827587076
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_fifo_full.3384410633
Short name T856
Test name
Test status
Simulation time 75230272126 ps
CPU time 113.3 seconds
Started Sep 01 06:43:52 AM UTC 24
Finished Sep 01 06:45:48 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384410633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3384410633
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.3878894583
Short name T861
Test name
Test status
Simulation time 136650779720 ps
CPU time 120.57 seconds
Started Sep 01 06:43:53 AM UTC 24
Finished Sep 01 06:45:56 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878894583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3878894583
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_fifo_reset.2653802563
Short name T194
Test name
Test status
Simulation time 238446427579 ps
CPU time 655.98 seconds
Started Sep 01 06:43:55 AM UTC 24
Finished Sep 01 06:54:58 AM UTC 24
Peak memory 212152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653802563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.2653802563
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_intr.992947651
Short name T1019
Test name
Test status
Simulation time 111860882909 ps
CPU time 503.41 seconds
Started Sep 01 06:43:57 AM UTC 24
Finished Sep 01 06:52:27 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992947651 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.992947651
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.2044767171
Short name T921
Test name
Test status
Simulation time 187291977859 ps
CPU time 293.88 seconds
Started Sep 01 06:44:09 AM UTC 24
Finished Sep 01 06:49:08 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044767171 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.2044767171
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_loopback.1555667691
Short name T817
Test name
Test status
Simulation time 5601568910 ps
CPU time 19.96 seconds
Started Sep 01 06:44:08 AM UTC 24
Finished Sep 01 06:44:29 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555667691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1555667691
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_noise_filter.3783082481
Short name T836
Test name
Test status
Simulation time 78589457864 ps
CPU time 63.54 seconds
Started Sep 01 06:44:01 AM UTC 24
Finished Sep 01 06:45:06 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783082481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3783082481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_perf.219169371
Short name T913
Test name
Test status
Simulation time 14426608667 ps
CPU time 262.39 seconds
Started Sep 01 06:44:08 AM UTC 24
Finished Sep 01 06:48:35 AM UTC 24
Peak memory 208576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219169371 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.219169371
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_rx_oversample.801702027
Short name T821
Test name
Test status
Simulation time 6316468085 ps
CPU time 38.26 seconds
Started Sep 01 06:43:57 AM UTC 24
Finished Sep 01 06:44:36 AM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801702027 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.801702027
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.2053678847
Short name T820
Test name
Test status
Simulation time 52440760438 ps
CPU time 27.34 seconds
Started Sep 01 06:44:06 AM UTC 24
Finished Sep 01 06:44:34 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053678847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2053678847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.180403262
Short name T812
Test name
Test status
Simulation time 1867693892 ps
CPU time 7.07 seconds
Started Sep 01 06:44:05 AM UTC 24
Finished Sep 01 06:44:13 AM UTC 24
Peak memory 204956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180403262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.180403262
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_smoke.1789258772
Short name T803
Test name
Test status
Simulation time 840873033 ps
CPU time 6.09 seconds
Started Sep 01 06:43:48 AM UTC 24
Finished Sep 01 06:43:55 AM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789258772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1789258772
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.3026765263
Short name T848
Test name
Test status
Simulation time 19672665967 ps
CPU time 86.8 seconds
Started Sep 01 06:44:09 AM UTC 24
Finished Sep 01 06:45:38 AM UTC 24
Peak memory 225332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3026765263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all
_with_rand_reset.3026765263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.3197184713
Short name T810
Test name
Test status
Simulation time 3880740857 ps
CPU time 3.76 seconds
Started Sep 01 06:44:06 AM UTC 24
Finished Sep 01 06:44:11 AM UTC 24
Peak memory 208132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197184713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3197184713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/43.uart_tx_rx.584023019
Short name T830
Test name
Test status
Simulation time 29762415614 ps
CPU time 62.34 seconds
Started Sep 01 06:43:51 AM UTC 24
Finished Sep 01 06:44:55 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584023019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.584023019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/43.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_alert_test.1305305632
Short name T827
Test name
Test status
Simulation time 12933356 ps
CPU time 0.83 seconds
Started Sep 01 06:44:48 AM UTC 24
Finished Sep 01 06:44:50 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305305632 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.1305305632
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_fifo_full.3188962607
Short name T918
Test name
Test status
Simulation time 147690956097 ps
CPU time 273.19 seconds
Started Sep 01 06:44:19 AM UTC 24
Finished Sep 01 06:48:55 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188962607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3188962607
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2075059768
Short name T152
Test name
Test status
Simulation time 110380129805 ps
CPU time 182.24 seconds
Started Sep 01 06:44:19 AM UTC 24
Finished Sep 01 06:47:24 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075059768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2075059768
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_fifo_reset.4270587507
Short name T851
Test name
Test status
Simulation time 111812996650 ps
CPU time 71.97 seconds
Started Sep 01 06:44:29 AM UTC 24
Finished Sep 01 06:45:43 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270587507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4270587507
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_intr.3677977495
Short name T835
Test name
Test status
Simulation time 19936728365 ps
CPU time 31.1 seconds
Started Sep 01 06:44:32 AM UTC 24
Finished Sep 01 06:45:05 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677977495 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3677977495
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.94350770
Short name T1003
Test name
Test status
Simulation time 56477210278 ps
CPU time 425.13 seconds
Started Sep 01 06:44:41 AM UTC 24
Finished Sep 01 06:51:51 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94350770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.94350770
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_loopback.2520048287
Short name T825
Test name
Test status
Simulation time 5877725075 ps
CPU time 7.74 seconds
Started Sep 01 06:44:37 AM UTC 24
Finished Sep 01 06:44:45 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520048287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.2520048287
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_noise_filter.2785506891
Short name T844
Test name
Test status
Simulation time 109525461288 ps
CPU time 52.69 seconds
Started Sep 01 06:44:32 AM UTC 24
Finished Sep 01 06:45:26 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785506891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2785506891
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_perf.2794643424
Short name T917
Test name
Test status
Simulation time 17955156188 ps
CPU time 237.46 seconds
Started Sep 01 06:44:41 AM UTC 24
Finished Sep 01 06:48:42 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794643424 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2794643424
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_rx_oversample.3174348533
Short name T832
Test name
Test status
Simulation time 2984045620 ps
CPU time 24.78 seconds
Started Sep 01 06:44:30 AM UTC 24
Finished Sep 01 06:44:56 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174348533 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3174348533
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.510891750
Short name T838
Test name
Test status
Simulation time 45279788220 ps
CPU time 38.09 seconds
Started Sep 01 06:44:35 AM UTC 24
Finished Sep 01 06:45:14 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510891750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.510891750
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.3286320731
Short name T828
Test name
Test status
Simulation time 34547744686 ps
CPU time 17.52 seconds
Started Sep 01 06:44:33 AM UTC 24
Finished Sep 01 06:44:52 AM UTC 24
Peak memory 205032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286320731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3286320731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_smoke.3934101835
Short name T815
Test name
Test status
Simulation time 479061138 ps
CPU time 3.58 seconds
Started Sep 01 06:44:14 AM UTC 24
Finished Sep 01 06:44:18 AM UTC 24
Peak memory 208424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934101835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3934101835
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_stress_all.1673993904
Short name T863
Test name
Test status
Simulation time 76591903587 ps
CPU time 69.16 seconds
Started Sep 01 06:44:46 AM UTC 24
Finished Sep 01 06:45:57 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673993904 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1673993904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.2530018224
Short name T833
Test name
Test status
Simulation time 810259655 ps
CPU time 13.4 seconds
Started Sep 01 06:44:44 AM UTC 24
Finished Sep 01 06:44:59 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2530018224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all
_with_rand_reset.2530018224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.2043750126
Short name T822
Test name
Test status
Simulation time 2142325708 ps
CPU time 3.13 seconds
Started Sep 01 06:44:36 AM UTC 24
Finished Sep 01 06:44:40 AM UTC 24
Peak memory 207604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043750126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2043750126
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/44.uart_tx_rx.1734180720
Short name T857
Test name
Test status
Simulation time 142924169466 ps
CPU time 93.5 seconds
Started Sep 01 06:44:15 AM UTC 24
Finished Sep 01 06:45:50 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734180720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1734180720
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/44.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_alert_test.1706330102
Short name T845
Test name
Test status
Simulation time 19227046 ps
CPU time 0.83 seconds
Started Sep 01 06:45:25 AM UTC 24
Finished Sep 01 06:45:27 AM UTC 24
Peak memory 202392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706330102 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1706330102
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_fifo_full.1791586222
Short name T837
Test name
Test status
Simulation time 154608914202 ps
CPU time 16.44 seconds
Started Sep 01 06:44:54 AM UTC 24
Finished Sep 01 06:45:12 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791586222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1791586222
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.2596129834
Short name T876
Test name
Test status
Simulation time 169710649568 ps
CPU time 107.54 seconds
Started Sep 01 06:44:56 AM UTC 24
Finished Sep 01 06:46:45 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596129834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2596129834
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_fifo_reset.4258042585
Short name T874
Test name
Test status
Simulation time 54953273826 ps
CPU time 101.65 seconds
Started Sep 01 06:44:57 AM UTC 24
Finished Sep 01 06:46:41 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258042585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4258042585
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_intr.3124892430
Short name T865
Test name
Test status
Simulation time 42409221279 ps
CPU time 62.07 seconds
Started Sep 01 06:44:57 AM UTC 24
Finished Sep 01 06:46:01 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124892430 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3124892430
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.424096204
Short name T996
Test name
Test status
Simulation time 61754759986 ps
CPU time 380.31 seconds
Started Sep 01 06:45:17 AM UTC 24
Finished Sep 01 06:51:42 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424096204 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.424096204
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_loopback.1959161431
Short name T854
Test name
Test status
Simulation time 10452153481 ps
CPU time 31.62 seconds
Started Sep 01 06:45:13 AM UTC 24
Finished Sep 01 06:45:46 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959161431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1959161431
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_noise_filter.1455188563
Short name T1021
Test name
Test status
Simulation time 129248372436 ps
CPU time 446.15 seconds
Started Sep 01 06:45:00 AM UTC 24
Finished Sep 01 06:52:32 AM UTC 24
Peak memory 208212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455188563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1455188563
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_perf.3494269485
Short name T1180
Test name
Test status
Simulation time 15273874935 ps
CPU time 962.81 seconds
Started Sep 01 06:45:14 AM UTC 24
Finished Sep 01 07:01:29 AM UTC 24
Peak memory 212348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494269485 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3494269485
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_rx_oversample.3620231139
Short name T859
Test name
Test status
Simulation time 6330914197 ps
CPU time 55.65 seconds
Started Sep 01 06:44:57 AM UTC 24
Finished Sep 01 06:45:54 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620231139 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3620231139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.869279337
Short name T930
Test name
Test status
Simulation time 72797653061 ps
CPU time 248.08 seconds
Started Sep 01 06:45:05 AM UTC 24
Finished Sep 01 06:49:17 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869279337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.869279337
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.3963816587
Short name T841
Test name
Test status
Simulation time 4053818559 ps
CPU time 13.59 seconds
Started Sep 01 06:45:04 AM UTC 24
Finished Sep 01 06:45:19 AM UTC 24
Peak memory 205096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963816587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3963816587
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_smoke.704141483
Short name T829
Test name
Test status
Simulation time 123398376 ps
CPU time 1.17 seconds
Started Sep 01 06:44:51 AM UTC 24
Finished Sep 01 06:44:53 AM UTC 24
Peak memory 206492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704141483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 45.uart_smoke.704141483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_stress_all.2050171847
Short name T1187
Test name
Test status
Simulation time 174571022602 ps
CPU time 1412.82 seconds
Started Sep 01 06:45:20 AM UTC 24
Finished Sep 01 07:09:09 AM UTC 24
Peak memory 222592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050171847 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2050171847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.1959582552
Short name T852
Test name
Test status
Simulation time 12743455123 ps
CPU time 24.22 seconds
Started Sep 01 06:45:19 AM UTC 24
Finished Sep 01 06:45:44 AM UTC 24
Peak memory 217904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1959582552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all
_with_rand_reset.1959582552
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.4256102547
Short name T843
Test name
Test status
Simulation time 6697065443 ps
CPU time 18.29 seconds
Started Sep 01 06:45:06 AM UTC 24
Finished Sep 01 06:45:26 AM UTC 24
Peak memory 208392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256102547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.4256102547
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/45.uart_tx_rx.2591571250
Short name T947
Test name
Test status
Simulation time 97374843132 ps
CPU time 297.2 seconds
Started Sep 01 06:44:52 AM UTC 24
Finished Sep 01 06:49:54 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591571250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2591571250
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/45.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_alert_test.3883483231
Short name T862
Test name
Test status
Simulation time 63069662 ps
CPU time 0.81 seconds
Started Sep 01 06:45:55 AM UTC 24
Finished Sep 01 06:45:57 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883483231 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3883483231
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_fifo_full.1126730956
Short name T855
Test name
Test status
Simulation time 30040017980 ps
CPU time 19.17 seconds
Started Sep 01 06:45:27 AM UTC 24
Finished Sep 01 06:45:47 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126730956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1126730956
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.9186462
Short name T864
Test name
Test status
Simulation time 159334887193 ps
CPU time 25.3 seconds
Started Sep 01 06:45:31 AM UTC 24
Finished Sep 01 06:45:58 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9186462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.9186462
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_fifo_reset.1887322325
Short name T203
Test name
Test status
Simulation time 85552679965 ps
CPU time 148 seconds
Started Sep 01 06:45:33 AM UTC 24
Finished Sep 01 06:48:04 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887322325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1887322325
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_intr.4290783580
Short name T866
Test name
Test status
Simulation time 20719641390 ps
CPU time 19.36 seconds
Started Sep 01 06:45:40 AM UTC 24
Finished Sep 01 06:46:01 AM UTC 24
Peak memory 207072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290783580 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4290783580
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.1158662329
Short name T957
Test name
Test status
Simulation time 102589235116 ps
CPU time 266.14 seconds
Started Sep 01 06:45:49 AM UTC 24
Finished Sep 01 06:50:19 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158662329 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1158662329
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_loopback.716390511
Short name T860
Test name
Test status
Simulation time 4618888249 ps
CPU time 7.86 seconds
Started Sep 01 06:45:47 AM UTC 24
Finished Sep 01 06:45:56 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716390511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.uart_loopback.716390511
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_noise_filter.1906898472
Short name T423
Test name
Test status
Simulation time 47321983901 ps
CPU time 171.39 seconds
Started Sep 01 06:45:44 AM UTC 24
Finished Sep 01 06:48:38 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906898472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.1906898472
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_perf.3043185291
Short name T1184
Test name
Test status
Simulation time 22115342179 ps
CPU time 1176.72 seconds
Started Sep 01 06:45:48 AM UTC 24
Finished Sep 01 07:05:38 AM UTC 24
Peak memory 212280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043185291 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3043185291
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_rx_oversample.4188886200
Short name T868
Test name
Test status
Simulation time 3068368667 ps
CPU time 31.88 seconds
Started Sep 01 06:45:39 AM UTC 24
Finished Sep 01 06:46:13 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188886200 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4188886200
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.3377666798
Short name T877
Test name
Test status
Simulation time 123996415046 ps
CPU time 61.14 seconds
Started Sep 01 06:45:45 AM UTC 24
Finished Sep 01 06:46:47 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377666798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.3377666798
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.2803819518
Short name T869
Test name
Test status
Simulation time 42755753863 ps
CPU time 35.51 seconds
Started Sep 01 06:45:44 AM UTC 24
Finished Sep 01 06:46:20 AM UTC 24
Peak memory 207208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803819518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2803819518
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_smoke.691954161
Short name T849
Test name
Test status
Simulation time 5366619332 ps
CPU time 11.12 seconds
Started Sep 01 06:45:27 AM UTC 24
Finished Sep 01 06:45:39 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691954161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.uart_smoke.691954161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_stress_all.702576868
Short name T1186
Test name
Test status
Simulation time 27795784562 ps
CPU time 1338.29 seconds
Started Sep 01 06:45:53 AM UTC 24
Finished Sep 01 07:08:27 AM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702576868 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.702576868
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.2772636167
Short name T899
Test name
Test status
Simulation time 3838044741 ps
CPU time 119.12 seconds
Started Sep 01 06:45:51 AM UTC 24
Finished Sep 01 06:47:53 AM UTC 24
Peak memory 217616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2772636167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all
_with_rand_reset.2772636167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.1038219351
Short name T867
Test name
Test status
Simulation time 6627618519 ps
CPU time 25.31 seconds
Started Sep 01 06:45:46 AM UTC 24
Finished Sep 01 06:46:12 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038219351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1038219351
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/46.uart_tx_rx.2891059530
Short name T893
Test name
Test status
Simulation time 35873570841 ps
CPU time 126.06 seconds
Started Sep 01 06:45:27 AM UTC 24
Finished Sep 01 06:47:36 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891059530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2891059530
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/46.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_alert_test.342433438
Short name T879
Test name
Test status
Simulation time 17240209 ps
CPU time 0.89 seconds
Started Sep 01 06:46:46 AM UTC 24
Finished Sep 01 06:46:48 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342433438 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.342433438
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_fifo_full.3606572238
Short name T884
Test name
Test status
Simulation time 31377210396 ps
CPU time 73.46 seconds
Started Sep 01 06:45:58 AM UTC 24
Finished Sep 01 06:47:13 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606572238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3606572238
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.3952367158
Short name T911
Test name
Test status
Simulation time 169598206241 ps
CPU time 153.63 seconds
Started Sep 01 06:45:58 AM UTC 24
Finished Sep 01 06:48:34 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952367158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3952367158
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_fifo_reset.2972857981
Short name T871
Test name
Test status
Simulation time 36908500493 ps
CPU time 29.26 seconds
Started Sep 01 06:45:59 AM UTC 24
Finished Sep 01 06:46:30 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972857981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2972857981
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_intr.2425950268
Short name T973
Test name
Test status
Simulation time 147930235513 ps
CPU time 291.12 seconds
Started Sep 01 06:46:02 AM UTC 24
Finished Sep 01 06:50:57 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425950268 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2425950268
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.985475551
Short name T1170
Test name
Test status
Simulation time 111488256880 ps
CPU time 785.74 seconds
Started Sep 01 06:46:35 AM UTC 24
Finished Sep 01 06:59:50 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985475551 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.985475551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_loopback.3579992653
Short name T878
Test name
Test status
Simulation time 3985614351 ps
CPU time 15.82 seconds
Started Sep 01 06:46:30 AM UTC 24
Finished Sep 01 06:46:48 AM UTC 24
Peak memory 208216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579992653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3579992653
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_noise_filter.4111235891
Short name T881
Test name
Test status
Simulation time 20126502758 ps
CPU time 35.79 seconds
Started Sep 01 06:46:13 AM UTC 24
Finished Sep 01 06:46:50 AM UTC 24
Peak memory 207356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111235891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.4111235891
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_perf.1803628122
Short name T1177
Test name
Test status
Simulation time 23982767530 ps
CPU time 808.22 seconds
Started Sep 01 06:46:32 AM UTC 24
Finished Sep 01 07:00:10 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803628122 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1803628122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_rx_oversample.4111222903
Short name T872
Test name
Test status
Simulation time 2970659808 ps
CPU time 27.47 seconds
Started Sep 01 06:46:02 AM UTC 24
Finished Sep 01 06:46:31 AM UTC 24
Peak memory 207212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111222903 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.4111222903
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.1719837750
Short name T1009
Test name
Test status
Simulation time 265099319576 ps
CPU time 342.17 seconds
Started Sep 01 06:46:21 AM UTC 24
Finished Sep 01 06:52:08 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719837750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1719837750
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.4145077822
Short name T870
Test name
Test status
Simulation time 4098498619 ps
CPU time 12.26 seconds
Started Sep 01 06:46:13 AM UTC 24
Finished Sep 01 06:46:27 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145077822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.4145077822
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_smoke.3621581251
Short name T875
Test name
Test status
Simulation time 6280929834 ps
CPU time 46.5 seconds
Started Sep 01 06:45:56 AM UTC 24
Finished Sep 01 06:46:45 AM UTC 24
Peak memory 207832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621581251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3621581251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_stress_all.2724345168
Short name T901
Test name
Test status
Simulation time 74502366388 ps
CPU time 74.07 seconds
Started Sep 01 06:46:46 AM UTC 24
Finished Sep 01 06:48:02 AM UTC 24
Peak memory 208684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724345168 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2724345168
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.385667047
Short name T887
Test name
Test status
Simulation time 1745934233 ps
CPU time 36.55 seconds
Started Sep 01 06:46:42 AM UTC 24
Finished Sep 01 06:47:20 AM UTC 24
Peak memory 209028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=385667047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all_
with_rand_reset.385667047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.537818086
Short name T873
Test name
Test status
Simulation time 913242598 ps
CPU time 5.17 seconds
Started Sep 01 06:46:27 AM UTC 24
Finished Sep 01 06:46:34 AM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537818086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.537818086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/47.uart_tx_rx.3125143451
Short name T936
Test name
Test status
Simulation time 70694770664 ps
CPU time 207.29 seconds
Started Sep 01 06:45:58 AM UTC 24
Finished Sep 01 06:49:28 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125143451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3125143451
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/47.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_alert_test.1420335835
Short name T894
Test name
Test status
Simulation time 24662741 ps
CPU time 0.87 seconds
Started Sep 01 06:47:35 AM UTC 24
Finished Sep 01 06:47:38 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420335835 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1420335835
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_fifo_full.3753591497
Short name T915
Test name
Test status
Simulation time 29558337150 ps
CPU time 104.76 seconds
Started Sep 01 06:46:49 AM UTC 24
Finished Sep 01 06:48:36 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753591497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3753591497
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.2599989160
Short name T905
Test name
Test status
Simulation time 46516729944 ps
CPU time 78.06 seconds
Started Sep 01 06:46:50 AM UTC 24
Finished Sep 01 06:48:10 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599989160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2599989160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_fifo_reset.2915174988
Short name T920
Test name
Test status
Simulation time 73220468824 ps
CPU time 123.76 seconds
Started Sep 01 06:46:51 AM UTC 24
Finished Sep 01 06:48:57 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915174988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2915174988
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_intr.335025789
Short name T890
Test name
Test status
Simulation time 16166051689 ps
CPU time 28.52 seconds
Started Sep 01 06:47:02 AM UTC 24
Finished Sep 01 06:47:31 AM UTC 24
Peak memory 205220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335025789 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.335025789
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.2316251378
Short name T1174
Test name
Test status
Simulation time 90430221084 ps
CPU time 740.14 seconds
Started Sep 01 06:47:28 AM UTC 24
Finished Sep 01 06:59:58 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316251378 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2316251378
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_loopback.2192739313
Short name T891
Test name
Test status
Simulation time 5081571169 ps
CPU time 7.51 seconds
Started Sep 01 06:47:23 AM UTC 24
Finished Sep 01 06:47:32 AM UTC 24
Peak memory 208908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192739313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2192739313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_noise_filter.325210501
Short name T927
Test name
Test status
Simulation time 181986152037 ps
CPU time 119.74 seconds
Started Sep 01 06:47:14 AM UTC 24
Finished Sep 01 06:49:16 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325210501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.325210501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_perf.1643946704
Short name T919
Test name
Test status
Simulation time 2196813694 ps
CPU time 87.75 seconds
Started Sep 01 06:47:25 AM UTC 24
Finished Sep 01 06:48:55 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643946704 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1643946704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_rx_oversample.4161023541
Short name T883
Test name
Test status
Simulation time 3573064300 ps
CPU time 7.82 seconds
Started Sep 01 06:46:51 AM UTC 24
Finished Sep 01 06:47:00 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161023541 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.4161023541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.443277231
Short name T912
Test name
Test status
Simulation time 47940880454 ps
CPU time 74.71 seconds
Started Sep 01 06:47:18 AM UTC 24
Finished Sep 01 06:48:34 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443277231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.443277231
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.1091564893
Short name T888
Test name
Test status
Simulation time 1948977213 ps
CPU time 3.76 seconds
Started Sep 01 06:47:17 AM UTC 24
Finished Sep 01 06:47:22 AM UTC 24
Peak memory 205224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091564893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1091564893
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_smoke.2348644224
Short name T882
Test name
Test status
Simulation time 468617656 ps
CPU time 1.68 seconds
Started Sep 01 06:46:48 AM UTC 24
Finished Sep 01 06:46:51 AM UTC 24
Peak memory 206904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348644224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2348644224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_stress_all.4023582959
Short name T950
Test name
Test status
Simulation time 123783914868 ps
CPU time 143.54 seconds
Started Sep 01 06:47:32 AM UTC 24
Finished Sep 01 06:49:58 AM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023582959 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.4023582959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.1694322977
Short name T903
Test name
Test status
Simulation time 6814765180 ps
CPU time 34.73 seconds
Started Sep 01 06:47:32 AM UTC 24
Finished Sep 01 06:48:08 AM UTC 24
Peak memory 217856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1694322977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all
_with_rand_reset.1694322977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.416095757
Short name T889
Test name
Test status
Simulation time 3856346487 ps
CPU time 4.86 seconds
Started Sep 01 06:47:21 AM UTC 24
Finished Sep 01 06:47:28 AM UTC 24
Peak memory 207672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416095757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.416095757
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/48.uart_tx_rx.2938700235
Short name T885
Test name
Test status
Simulation time 25154261692 ps
CPU time 26.63 seconds
Started Sep 01 06:46:48 AM UTC 24
Finished Sep 01 06:47:16 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938700235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2938700235
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/48.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_alert_test.3121807841
Short name T909
Test name
Test status
Simulation time 57940716 ps
CPU time 0.82 seconds
Started Sep 01 06:48:24 AM UTC 24
Finished Sep 01 06:48:26 AM UTC 24
Peak memory 204376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121807841 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3121807841
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_fifo_full.4074716240
Short name T1035
Test name
Test status
Simulation time 381130336968 ps
CPU time 317.4 seconds
Started Sep 01 06:47:40 AM UTC 24
Finished Sep 01 06:53:02 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074716240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4074716240
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.1422174691
Short name T904
Test name
Test status
Simulation time 11463433331 ps
CPU time 26.36 seconds
Started Sep 01 06:47:42 AM UTC 24
Finished Sep 01 06:48:10 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422174691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1422174691
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_fifo_reset.959185815
Short name T934
Test name
Test status
Simulation time 125736620621 ps
CPU time 100.01 seconds
Started Sep 01 06:47:43 AM UTC 24
Finished Sep 01 06:49:25 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959185815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.959185815
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_intr.1162721181
Short name T908
Test name
Test status
Simulation time 38732951269 ps
CPU time 29.05 seconds
Started Sep 01 06:47:53 AM UTC 24
Finished Sep 01 06:48:23 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162721181 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1162721181
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.2083067779
Short name T1006
Test name
Test status
Simulation time 53551254515 ps
CPU time 224 seconds
Started Sep 01 06:48:11 AM UTC 24
Finished Sep 01 06:51:58 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083067779 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2083067779
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_loopback.2199419084
Short name T916
Test name
Test status
Simulation time 8100505995 ps
CPU time 27.47 seconds
Started Sep 01 06:48:10 AM UTC 24
Finished Sep 01 06:48:38 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199419084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2199419084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_noise_filter.3150671188
Short name T926
Test name
Test status
Simulation time 48294137053 ps
CPU time 79.45 seconds
Started Sep 01 06:47:54 AM UTC 24
Finished Sep 01 06:49:15 AM UTC 24
Peak memory 217416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150671188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3150671188
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_perf.1628467352
Short name T963
Test name
Test status
Simulation time 17777734553 ps
CPU time 136.56 seconds
Started Sep 01 06:48:11 AM UTC 24
Finished Sep 01 06:50:30 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628467352 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1628467352
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_rx_oversample.356694101
Short name T914
Test name
Test status
Simulation time 7307278917 ps
CPU time 41.28 seconds
Started Sep 01 06:47:52 AM UTC 24
Finished Sep 01 06:48:35 AM UTC 24
Peak memory 208808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356694101 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.356694101
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.3935681880
Short name T1047
Test name
Test status
Simulation time 80073717263 ps
CPU time 325.71 seconds
Started Sep 01 06:48:04 AM UTC 24
Finished Sep 01 06:53:34 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935681880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3935681880
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.1148099773
Short name T902
Test name
Test status
Simulation time 3452452621 ps
CPU time 3.87 seconds
Started Sep 01 06:48:02 AM UTC 24
Finished Sep 01 06:48:07 AM UTC 24
Peak memory 207144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148099773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1148099773
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_smoke.650177263
Short name T896
Test name
Test status
Simulation time 862918846 ps
CPU time 3.24 seconds
Started Sep 01 06:47:37 AM UTC 24
Finished Sep 01 06:47:41 AM UTC 24
Peak memory 207100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650177263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.uart_smoke.650177263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_stress_all.2003302392
Short name T1159
Test name
Test status
Simulation time 332006652746 ps
CPU time 635.55 seconds
Started Sep 01 06:48:20 AM UTC 24
Finished Sep 01 06:59:03 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003302392 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2003302392
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.1756692084
Short name T931
Test name
Test status
Simulation time 6567905832 ps
CPU time 62.71 seconds
Started Sep 01 06:48:15 AM UTC 24
Finished Sep 01 06:49:19 AM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1756692084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all
_with_rand_reset.1756692084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.975474839
Short name T906
Test name
Test status
Simulation time 1394414015 ps
CPU time 4.1 seconds
Started Sep 01 06:48:08 AM UTC 24
Finished Sep 01 06:48:14 AM UTC 24
Peak memory 207552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975474839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.975474839
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/49.uart_tx_rx.3733959251
Short name T939
Test name
Test status
Simulation time 53321500443 ps
CPU time 119.11 seconds
Started Sep 01 06:47:39 AM UTC 24
Finished Sep 01 06:49:40 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733959251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3733959251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/49.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_alert_test.154902691
Short name T452
Test name
Test status
Simulation time 22858740 ps
CPU time 0.8 seconds
Started Sep 01 06:26:15 AM UTC 24
Finished Sep 01 06:26:16 AM UTC 24
Peak memory 202388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154902691 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.154902691
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.879385976
Short name T20
Test name
Test status
Simulation time 75443690679 ps
CPU time 35.68 seconds
Started Sep 01 06:26:01 AM UTC 24
Finished Sep 01 06:26:38 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879385976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.879385976
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_intr.2182164444
Short name T97
Test name
Test status
Simulation time 44823015964 ps
CPU time 36.19 seconds
Started Sep 01 06:26:04 AM UTC 24
Finished Sep 01 06:26:41 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182164444 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2182164444
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.907399437
Short name T594
Test name
Test status
Simulation time 104886742626 ps
CPU time 620.75 seconds
Started Sep 01 06:26:11 AM UTC 24
Finished Sep 01 06:36:40 AM UTC 24
Peak memory 212296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907399437 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.907399437
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_loopback.2185484068
Short name T453
Test name
Test status
Simulation time 2888380017 ps
CPU time 5.4 seconds
Started Sep 01 06:26:10 AM UTC 24
Finished Sep 01 06:26:17 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185484068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2185484068
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_noise_filter.3960174630
Short name T282
Test name
Test status
Simulation time 31827214162 ps
CPU time 77.7 seconds
Started Sep 01 06:26:05 AM UTC 24
Finished Sep 01 06:27:25 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960174630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3960174630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_perf.3271990828
Short name T667
Test name
Test status
Simulation time 15234616921 ps
CPU time 808.54 seconds
Started Sep 01 06:26:10 AM UTC 24
Finished Sep 01 06:39:50 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271990828 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3271990828
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_rx_oversample.3358306673
Short name T456
Test name
Test status
Simulation time 7181516284 ps
CPU time 45.11 seconds
Started Sep 01 06:26:04 AM UTC 24
Finished Sep 01 06:26:50 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358306673 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3358306673
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.2903655713
Short name T263
Test name
Test status
Simulation time 99417445425 ps
CPU time 91.43 seconds
Started Sep 01 06:26:09 AM UTC 24
Finished Sep 01 06:27:42 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903655713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2903655713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.1655906701
Short name T371
Test name
Test status
Simulation time 5292779724 ps
CPU time 6.7 seconds
Started Sep 01 06:26:05 AM UTC 24
Finished Sep 01 06:26:13 AM UTC 24
Peak memory 205036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655906701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1655906701
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_smoke.2232919765
Short name T333
Test name
Test status
Simulation time 452075911 ps
CPU time 3.15 seconds
Started Sep 01 06:25:58 AM UTC 24
Finished Sep 01 06:26:03 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232919765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2232919765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.2147769198
Short name T36
Test name
Test status
Simulation time 1296519022 ps
CPU time 19.18 seconds
Started Sep 01 06:26:14 AM UTC 24
Finished Sep 01 06:26:34 AM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2147769198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_
with_rand_reset.2147769198
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.1343145506
Short name T280
Test name
Test status
Simulation time 1174479118 ps
CPU time 4.55 seconds
Started Sep 01 06:26:09 AM UTC 24
Finished Sep 01 06:26:15 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343145506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1343145506
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/5.uart_tx_rx.66718400
Short name T50
Test name
Test status
Simulation time 149275486645 ps
CPU time 84.69 seconds
Started Sep 01 06:26:00 AM UTC 24
Finished Sep 01 06:27:26 AM UTC 24
Peak memory 208688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66718400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.66718400
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/5.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/50.uart_fifo_reset.1486499529
Short name T1105
Test name
Test status
Simulation time 190550565749 ps
CPU time 478.56 seconds
Started Sep 01 06:48:27 AM UTC 24
Finished Sep 01 06:56:32 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486499529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1486499529
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/50.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.662244496
Short name T922
Test name
Test status
Simulation time 8124381257 ps
CPU time 32.6 seconds
Started Sep 01 06:48:34 AM UTC 24
Finished Sep 01 06:49:08 AM UTC 24
Peak memory 217680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=662244496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all_
with_rand_reset.662244496
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/51.uart_fifo_reset.82018120
Short name T928
Test name
Test status
Simulation time 117315129603 ps
CPU time 38.88 seconds
Started Sep 01 06:48:35 AM UTC 24
Finished Sep 01 06:49:16 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82018120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.82018120
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/51.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.2323719438
Short name T923
Test name
Test status
Simulation time 3660704234 ps
CPU time 35.24 seconds
Started Sep 01 06:48:35 AM UTC 24
Finished Sep 01 06:49:12 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2323719438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all
_with_rand_reset.2323719438
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/52.uart_fifo_reset.3002183560
Short name T970
Test name
Test status
Simulation time 126940176014 ps
CPU time 134.64 seconds
Started Sep 01 06:48:35 AM UTC 24
Finished Sep 01 06:50:52 AM UTC 24
Peak memory 208820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002183560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3002183560
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/52.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.591712603
Short name T933
Test name
Test status
Simulation time 6590132316 ps
CPU time 47.79 seconds
Started Sep 01 06:48:36 AM UTC 24
Finished Sep 01 06:49:25 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=591712603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all_
with_rand_reset.591712603
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/53.uart_fifo_reset.2080866582
Short name T220
Test name
Test status
Simulation time 92199728168 ps
CPU time 177.42 seconds
Started Sep 01 06:48:37 AM UTC 24
Finished Sep 01 06:51:37 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080866582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2080866582
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/53.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.459112478
Short name T943
Test name
Test status
Simulation time 4443259869 ps
CPU time 66.94 seconds
Started Sep 01 06:48:39 AM UTC 24
Finished Sep 01 06:49:48 AM UTC 24
Peak memory 217660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=459112478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all_
with_rand_reset.459112478
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/54.uart_fifo_reset.1875214787
Short name T178
Test name
Test status
Simulation time 17455796548 ps
CPU time 22.49 seconds
Started Sep 01 06:48:39 AM UTC 24
Finished Sep 01 06:49:03 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875214787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1875214787
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/54.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.2245332062
Short name T952
Test name
Test status
Simulation time 9289049149 ps
CPU time 78.79 seconds
Started Sep 01 06:48:43 AM UTC 24
Finished Sep 01 06:50:04 AM UTC 24
Peak memory 217576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2245332062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all
_with_rand_reset.2245332062
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/55.uart_fifo_reset.3268994300
Short name T962
Test name
Test status
Simulation time 32336076177 ps
CPU time 89.38 seconds
Started Sep 01 06:48:56 AM UTC 24
Finished Sep 01 06:50:27 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268994300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.3268994300
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/55.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.1638036354
Short name T925
Test name
Test status
Simulation time 1687432955 ps
CPU time 17.42 seconds
Started Sep 01 06:48:56 AM UTC 24
Finished Sep 01 06:49:15 AM UTC 24
Peak memory 223892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1638036354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all
_with_rand_reset.1638036354
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/56.uart_fifo_reset.3428105277
Short name T185
Test name
Test status
Simulation time 190548335965 ps
CPU time 29.56 seconds
Started Sep 01 06:48:58 AM UTC 24
Finished Sep 01 06:49:29 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428105277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3428105277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/56.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.695261056
Short name T940
Test name
Test status
Simulation time 3488825751 ps
CPU time 37.69 seconds
Started Sep 01 06:49:03 AM UTC 24
Finished Sep 01 06:49:42 AM UTC 24
Peak memory 225132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=695261056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all_
with_rand_reset.695261056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/57.uart_fifo_reset.48560059
Short name T935
Test name
Test status
Simulation time 19860858550 ps
CPU time 18.3 seconds
Started Sep 01 06:49:08 AM UTC 24
Finished Sep 01 06:49:28 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48560059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.48560059
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/57.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.1073021458
Short name T938
Test name
Test status
Simulation time 2967809098 ps
CPU time 28.46 seconds
Started Sep 01 06:49:09 AM UTC 24
Finished Sep 01 06:49:39 AM UTC 24
Peak memory 217776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1073021458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all
_with_rand_reset.1073021458
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/58.uart_fifo_reset.974139258
Short name T941
Test name
Test status
Simulation time 54453123832 ps
CPU time 27.82 seconds
Started Sep 01 06:49:13 AM UTC 24
Finished Sep 01 06:49:43 AM UTC 24
Peak memory 208736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974139258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.974139258
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/58.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.242615863
Short name T956
Test name
Test status
Simulation time 4392074893 ps
CPU time 63.69 seconds
Started Sep 01 06:49:14 AM UTC 24
Finished Sep 01 06:50:19 AM UTC 24
Peak memory 217812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=242615863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all_
with_rand_reset.242615863
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/59.uart_fifo_reset.1868957491
Short name T937
Test name
Test status
Simulation time 38112535540 ps
CPU time 17.18 seconds
Started Sep 01 06:49:16 AM UTC 24
Finished Sep 01 06:49:34 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868957491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1868957491
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/59.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.990614639
Short name T946
Test name
Test status
Simulation time 9664668532 ps
CPU time 34.7 seconds
Started Sep 01 06:49:17 AM UTC 24
Finished Sep 01 06:49:53 AM UTC 24
Peak memory 217596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=990614639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all_
with_rand_reset.990614639
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_alert_test.1815153210
Short name T454
Test name
Test status
Simulation time 37334875 ps
CPU time 0.87 seconds
Started Sep 01 06:26:38 AM UTC 24
Finished Sep 01 06:26:40 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815153210 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1815153210
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_fifo_full.2944936511
Short name T51
Test name
Test status
Simulation time 29779416229 ps
CPU time 68.03 seconds
Started Sep 01 06:26:19 AM UTC 24
Finished Sep 01 06:27:28 AM UTC 24
Peak memory 208632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944936511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2944936511
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.3998670848
Short name T109
Test name
Test status
Simulation time 54808101045 ps
CPU time 99.89 seconds
Started Sep 01 06:26:19 AM UTC 24
Finished Sep 01 06:28:01 AM UTC 24
Peak memory 208984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998670848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3998670848
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_fifo_reset.265882483
Short name T110
Test name
Test status
Simulation time 74323169216 ps
CPU time 100.63 seconds
Started Sep 01 06:26:19 AM UTC 24
Finished Sep 01 06:28:02 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265882483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.265882483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.791038844
Short name T266
Test name
Test status
Simulation time 143355952051 ps
CPU time 156.5 seconds
Started Sep 01 06:26:32 AM UTC 24
Finished Sep 01 06:29:11 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791038844 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.791038844
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_loopback.643313388
Short name T420
Test name
Test status
Simulation time 2099627345 ps
CPU time 4.36 seconds
Started Sep 01 06:26:31 AM UTC 24
Finished Sep 01 06:26:37 AM UTC 24
Peak memory 207084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643313388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.uart_loopback.643313388
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_noise_filter.2402420211
Short name T305
Test name
Test status
Simulation time 202978397150 ps
CPU time 156.2 seconds
Started Sep 01 06:26:23 AM UTC 24
Finished Sep 01 06:29:02 AM UTC 24
Peak memory 208280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402420211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2402420211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_perf.540078471
Short name T584
Test name
Test status
Simulation time 18777306284 ps
CPU time 577.65 seconds
Started Sep 01 06:26:32 AM UTC 24
Finished Sep 01 06:36:16 AM UTC 24
Peak memory 208636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540078471 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.540078471
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_rx_oversample.2982863173
Short name T455
Test name
Test status
Simulation time 2549821644 ps
CPU time 27.62 seconds
Started Sep 01 06:26:19 AM UTC 24
Finished Sep 01 06:26:48 AM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982863173 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2982863173
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.3520072074
Short name T317
Test name
Test status
Simulation time 4830180386 ps
CPU time 4.81 seconds
Started Sep 01 06:26:25 AM UTC 24
Finished Sep 01 06:26:31 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520072074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3520072074
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_smoke.2022774541
Short name T293
Test name
Test status
Simulation time 531457461 ps
CPU time 3.44 seconds
Started Sep 01 06:26:18 AM UTC 24
Finished Sep 01 06:26:22 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022774541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2022774541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_stress_all.3193378786
Short name T288
Test name
Test status
Simulation time 256158895809 ps
CPU time 450.2 seconds
Started Sep 01 06:26:36 AM UTC 24
Finished Sep 01 06:34:12 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193378786 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3193378786
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.3220463113
Short name T340
Test name
Test status
Simulation time 3402051668 ps
CPU time 3.25 seconds
Started Sep 01 06:26:25 AM UTC 24
Finished Sep 01 06:26:30 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220463113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3220463113
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/6.uart_tx_rx.2961059111
Short name T365
Test name
Test status
Simulation time 20792640256 ps
CPU time 50.67 seconds
Started Sep 01 06:26:18 AM UTC 24
Finished Sep 01 06:27:10 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961059111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.2961059111
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/6.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/60.uart_fifo_reset.1138197776
Short name T949
Test name
Test status
Simulation time 100897227186 ps
CPU time 39.53 seconds
Started Sep 01 06:49:17 AM UTC 24
Finished Sep 01 06:49:58 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138197776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1138197776
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/60.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.3490836611
Short name T951
Test name
Test status
Simulation time 12441365522 ps
CPU time 43.05 seconds
Started Sep 01 06:49:17 AM UTC 24
Finished Sep 01 06:50:01 AM UTC 24
Peak memory 217916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3490836611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all
_with_rand_reset.3490836611
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/61.uart_fifo_reset.884951434
Short name T247
Test name
Test status
Simulation time 20562687600 ps
CPU time 33.07 seconds
Started Sep 01 06:49:17 AM UTC 24
Finished Sep 01 06:49:51 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884951434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.884951434
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/61.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.4117371938
Short name T948
Test name
Test status
Simulation time 12287302492 ps
CPU time 36.28 seconds
Started Sep 01 06:49:18 AM UTC 24
Finished Sep 01 06:49:56 AM UTC 24
Peak memory 221972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4117371938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all
_with_rand_reset.4117371938
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/62.uart_fifo_reset.989894948
Short name T1017
Test name
Test status
Simulation time 58682903067 ps
CPU time 177.47 seconds
Started Sep 01 06:49:20 AM UTC 24
Finished Sep 01 06:52:20 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989894948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.989894948
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/62.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.2479637489
Short name T944
Test name
Test status
Simulation time 5524463938 ps
CPU time 23.83 seconds
Started Sep 01 06:49:25 AM UTC 24
Finished Sep 01 06:49:50 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2479637489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all
_with_rand_reset.2479637489
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/63.uart_fifo_reset.97609159
Short name T989
Test name
Test status
Simulation time 39573694396 ps
CPU time 118.36 seconds
Started Sep 01 06:49:26 AM UTC 24
Finished Sep 01 06:51:27 AM UTC 24
Peak memory 208960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97609159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.97609159
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/63.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.2256643130
Short name T945
Test name
Test status
Simulation time 1602566305 ps
CPU time 23.74 seconds
Started Sep 01 06:49:26 AM UTC 24
Finished Sep 01 06:49:51 AM UTC 24
Peak memory 223792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2256643130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all
_with_rand_reset.2256643130
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/64.uart_fifo_reset.3528602193
Short name T219
Test name
Test status
Simulation time 22184182946 ps
CPU time 62.92 seconds
Started Sep 01 06:49:29 AM UTC 24
Finished Sep 01 06:50:33 AM UTC 24
Peak memory 208708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528602193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3528602193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/64.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.1098875414
Short name T966
Test name
Test status
Simulation time 16356963956 ps
CPU time 66.93 seconds
Started Sep 01 06:49:30 AM UTC 24
Finished Sep 01 06:50:38 AM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1098875414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all
_with_rand_reset.1098875414
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/65.uart_fifo_reset.2577559397
Short name T159
Test name
Test status
Simulation time 36615863102 ps
CPU time 26.04 seconds
Started Sep 01 06:49:31 AM UTC 24
Finished Sep 01 06:49:58 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577559397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2577559397
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/65.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.3856275308
Short name T959
Test name
Test status
Simulation time 5438569390 ps
CPU time 44.41 seconds
Started Sep 01 06:49:35 AM UTC 24
Finished Sep 01 06:50:21 AM UTC 24
Peak memory 219724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3856275308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all
_with_rand_reset.3856275308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/66.uart_fifo_reset.1263002755
Short name T223
Test name
Test status
Simulation time 58959625896 ps
CPU time 46.94 seconds
Started Sep 01 06:49:40 AM UTC 24
Finished Sep 01 06:50:28 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263002755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1263002755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/66.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.3449937589
Short name T954
Test name
Test status
Simulation time 2304597601 ps
CPU time 26.37 seconds
Started Sep 01 06:49:41 AM UTC 24
Finished Sep 01 06:50:09 AM UTC 24
Peak memory 219724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3449937589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all
_with_rand_reset.3449937589
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/67.uart_fifo_reset.10704903
Short name T1029
Test name
Test status
Simulation time 110348749085 ps
CPU time 186.13 seconds
Started Sep 01 06:49:43 AM UTC 24
Finished Sep 01 06:52:52 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10704903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.10704903
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/67.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.2947035671
Short name T965
Test name
Test status
Simulation time 8683361069 ps
CPU time 50.32 seconds
Started Sep 01 06:49:43 AM UTC 24
Finished Sep 01 06:50:35 AM UTC 24
Peak memory 217584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2947035671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all
_with_rand_reset.2947035671
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/68.uart_fifo_reset.1302973105
Short name T978
Test name
Test status
Simulation time 60162420950 ps
CPU time 76.85 seconds
Started Sep 01 06:49:46 AM UTC 24
Finished Sep 01 06:51:05 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302973105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1302973105
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/68.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.4284049950
Short name T953
Test name
Test status
Simulation time 1854451244 ps
CPU time 14.96 seconds
Started Sep 01 06:49:48 AM UTC 24
Finished Sep 01 06:50:04 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4284049950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all
_with_rand_reset.4284049950
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/69.uart_fifo_reset.2060725545
Short name T1065
Test name
Test status
Simulation time 85508118300 ps
CPU time 288.73 seconds
Started Sep 01 06:49:51 AM UTC 24
Finished Sep 01 06:54:44 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060725545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2060725545
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/69.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.3256090654
Short name T955
Test name
Test status
Simulation time 1304939595 ps
CPU time 23.57 seconds
Started Sep 01 06:49:53 AM UTC 24
Finished Sep 01 06:50:17 AM UTC 24
Peak memory 209024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3256090654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all
_with_rand_reset.3256090654
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_alert_test.1277666674
Short name T457
Test name
Test status
Simulation time 29595613 ps
CPU time 0.82 seconds
Started Sep 01 06:26:53 AM UTC 24
Finished Sep 01 06:26:55 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277666674 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1277666674
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_fifo_full.1759493968
Short name T118
Test name
Test status
Simulation time 46715655495 ps
CPU time 35.35 seconds
Started Sep 01 06:26:42 AM UTC 24
Finished Sep 01 06:27:19 AM UTC 24
Peak memory 208568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759493968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1759493968
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_intr.3156407465
Short name T290
Test name
Test status
Simulation time 34513428100 ps
CPU time 90.98 seconds
Started Sep 01 06:26:43 AM UTC 24
Finished Sep 01 06:28:16 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156407465 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3156407465
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_loopback.1529432652
Short name T419
Test name
Test status
Simulation time 5456095434 ps
CPU time 23.83 seconds
Started Sep 01 06:26:49 AM UTC 24
Finished Sep 01 06:27:14 AM UTC 24
Peak memory 208228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529432652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1529432652
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_noise_filter.2669134880
Short name T314
Test name
Test status
Simulation time 14865700857 ps
CPU time 28.15 seconds
Started Sep 01 06:26:44 AM UTC 24
Finished Sep 01 06:27:13 AM UTC 24
Peak memory 207644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669134880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2669134880
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_perf.3513192185
Short name T344
Test name
Test status
Simulation time 6071905429 ps
CPU time 324.7 seconds
Started Sep 01 06:26:50 AM UTC 24
Finished Sep 01 06:32:19 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513192185 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3513192185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_rx_oversample.1113939140
Short name T458
Test name
Test status
Simulation time 2952177917 ps
CPU time 24.71 seconds
Started Sep 01 06:26:43 AM UTC 24
Finished Sep 01 06:27:09 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113939140 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1113939140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.2852258252
Short name T334
Test name
Test status
Simulation time 596724373 ps
CPU time 3.45 seconds
Started Sep 01 06:26:46 AM UTC 24
Finished Sep 01 06:26:50 AM UTC 24
Peak memory 205164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852258252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2852258252
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_smoke.3530002647
Short name T306
Test name
Test status
Simulation time 453016644 ps
CPU time 3.66 seconds
Started Sep 01 06:26:40 AM UTC 24
Finished Sep 01 06:26:45 AM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530002647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3530002647
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_stress_all.751085050
Short name T960
Test name
Test status
Simulation time 136518692759 ps
CPU time 1393.91 seconds
Started Sep 01 06:26:52 AM UTC 24
Finished Sep 01 06:50:22 AM UTC 24
Peak memory 212212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751085050 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.751085050
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.12485657
Short name T40
Test name
Test status
Simulation time 9251279734 ps
CPU time 40.8 seconds
Started Sep 01 06:26:51 AM UTC 24
Finished Sep 01 06:27:33 AM UTC 24
Peak memory 217812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=12485657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_wi
th_rand_reset.12485657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.355131792
Short name T315
Test name
Test status
Simulation time 1084279728 ps
CPU time 3.46 seconds
Started Sep 01 06:26:49 AM UTC 24
Finished Sep 01 06:26:53 AM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355131792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.355131792
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/7.uart_tx_rx.3385799956
Short name T108
Test name
Test status
Simulation time 40710302586 ps
CPU time 24.33 seconds
Started Sep 01 06:26:40 AM UTC 24
Finished Sep 01 06:27:06 AM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385799956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3385799956
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/7.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/70.uart_fifo_reset.3291449706
Short name T192
Test name
Test status
Simulation time 113638011296 ps
CPU time 73.19 seconds
Started Sep 01 06:49:53 AM UTC 24
Finished Sep 01 06:51:08 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291449706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3291449706
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/70.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.391323562
Short name T1008
Test name
Test status
Simulation time 12709315636 ps
CPU time 130.23 seconds
Started Sep 01 06:49:54 AM UTC 24
Finished Sep 01 06:52:06 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=391323562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all_
with_rand_reset.391323562
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/71.uart_fifo_reset.1773316791
Short name T442
Test name
Test status
Simulation time 61100673548 ps
CPU time 25.87 seconds
Started Sep 01 06:49:55 AM UTC 24
Finished Sep 01 06:50:22 AM UTC 24
Peak memory 208700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773316791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1773316791
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/71.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.1114971369
Short name T967
Test name
Test status
Simulation time 2599170832 ps
CPU time 52.33 seconds
Started Sep 01 06:49:57 AM UTC 24
Finished Sep 01 06:50:51 AM UTC 24
Peak memory 225252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1114971369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all
_with_rand_reset.1114971369
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.3480841468
Short name T981
Test name
Test status
Simulation time 5664331046 ps
CPU time 73.92 seconds
Started Sep 01 06:49:59 AM UTC 24
Finished Sep 01 06:51:15 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3480841468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all
_with_rand_reset.3480841468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/73.uart_fifo_reset.2944633901
Short name T187
Test name
Test status
Simulation time 24285004402 ps
CPU time 29.3 seconds
Started Sep 01 06:49:59 AM UTC 24
Finished Sep 01 06:50:30 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944633901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2944633901
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/73.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.1206808892
Short name T979
Test name
Test status
Simulation time 7054292001 ps
CPU time 61.4 seconds
Started Sep 01 06:50:02 AM UTC 24
Finished Sep 01 06:51:05 AM UTC 24
Peak memory 221772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1206808892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all
_with_rand_reset.1206808892
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/74.uart_fifo_reset.772507282
Short name T976
Test name
Test status
Simulation time 199534321537 ps
CPU time 55.78 seconds
Started Sep 01 06:50:05 AM UTC 24
Finished Sep 01 06:51:03 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772507282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.772507282
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/74.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.1732672600
Short name T992
Test name
Test status
Simulation time 15125997753 ps
CPU time 85.83 seconds
Started Sep 01 06:50:05 AM UTC 24
Finished Sep 01 06:51:34 AM UTC 24
Peak memory 219780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1732672600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all
_with_rand_reset.1732672600
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/75.uart_fifo_reset.2950253737
Short name T196
Test name
Test status
Simulation time 94133455981 ps
CPU time 91.38 seconds
Started Sep 01 06:50:09 AM UTC 24
Finished Sep 01 06:51:43 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950253737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2950253737
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/75.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2442434272
Short name T972
Test name
Test status
Simulation time 7978857048 ps
CPU time 34.77 seconds
Started Sep 01 06:50:19 AM UTC 24
Finished Sep 01 06:50:55 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2442434272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all
_with_rand_reset.2442434272
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/76.uart_fifo_reset.1490571669
Short name T207
Test name
Test status
Simulation time 56539212151 ps
CPU time 64.13 seconds
Started Sep 01 06:50:20 AM UTC 24
Finished Sep 01 06:51:26 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490571669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1490571669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/76.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.129731422
Short name T990
Test name
Test status
Simulation time 8498519829 ps
CPU time 68 seconds
Started Sep 01 06:50:20 AM UTC 24
Finished Sep 01 06:51:30 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=129731422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all_
with_rand_reset.129731422
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/77.uart_fifo_reset.2484391463
Short name T969
Test name
Test status
Simulation time 19350605210 ps
CPU time 30.96 seconds
Started Sep 01 06:50:20 AM UTC 24
Finished Sep 01 06:50:52 AM UTC 24
Peak memory 208628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484391463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.2484391463
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/77.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.695331975
Short name T974
Test name
Test status
Simulation time 2814974889 ps
CPU time 34.21 seconds
Started Sep 01 06:50:22 AM UTC 24
Finished Sep 01 06:50:58 AM UTC 24
Peak memory 217816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=695331975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all_
with_rand_reset.695331975
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/78.uart_fifo_reset.2226275882
Short name T231
Test name
Test status
Simulation time 43944646331 ps
CPU time 45.46 seconds
Started Sep 01 06:50:23 AM UTC 24
Finished Sep 01 06:51:10 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226275882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.2226275882
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/78.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.98188154
Short name T980
Test name
Test status
Simulation time 5605611960 ps
CPU time 47.78 seconds
Started Sep 01 06:50:23 AM UTC 24
Finished Sep 01 06:51:13 AM UTC 24
Peak memory 217808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=98188154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all_w
ith_rand_reset.98188154
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/79.uart_fifo_reset.2551642940
Short name T1064
Test name
Test status
Simulation time 129502415733 ps
CPU time 255.34 seconds
Started Sep 01 06:50:24 AM UTC 24
Finished Sep 01 06:54:43 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551642940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2551642940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/79.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.1976698485
Short name T968
Test name
Test status
Simulation time 6755996619 ps
CPU time 24.43 seconds
Started Sep 01 06:50:26 AM UTC 24
Finished Sep 01 06:50:52 AM UTC 24
Peak memory 225416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1976698485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all
_with_rand_reset.1976698485
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_alert_test.1264546121
Short name T459
Test name
Test status
Simulation time 71630837 ps
CPU time 0.85 seconds
Started Sep 01 06:27:20 AM UTC 24
Finished Sep 01 06:27:21 AM UTC 24
Peak memory 204380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264546121 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1264546121
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1640239127
Short name T112
Test name
Test status
Simulation time 25022394946 ps
CPU time 34.3 seconds
Started Sep 01 06:26:58 AM UTC 24
Finished Sep 01 06:27:33 AM UTC 24
Peak memory 208652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640239127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1640239127
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_intr.1901006853
Short name T323
Test name
Test status
Simulation time 59667642496 ps
CPU time 174.99 seconds
Started Sep 01 06:27:02 AM UTC 24
Finished Sep 01 06:30:00 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901006853 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1901006853
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.331266349
Short name T329
Test name
Test status
Simulation time 72574728228 ps
CPU time 427.15 seconds
Started Sep 01 06:27:14 AM UTC 24
Finished Sep 01 06:34:28 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331266349 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.331266349
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_loopback.1415000550
Short name T460
Test name
Test status
Simulation time 12733423856 ps
CPU time 11.77 seconds
Started Sep 01 06:27:10 AM UTC 24
Finished Sep 01 06:27:23 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415000550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1415000550
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_noise_filter.1329992342
Short name T296
Test name
Test status
Simulation time 178419258572 ps
CPU time 128.76 seconds
Started Sep 01 06:27:02 AM UTC 24
Finished Sep 01 06:29:13 AM UTC 24
Peak memory 208032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329992342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1329992342
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_perf.3196457433
Short name T358
Test name
Test status
Simulation time 10123174868 ps
CPU time 208.09 seconds
Started Sep 01 06:27:13 AM UTC 24
Finished Sep 01 06:30:45 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196457433 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3196457433
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_rx_oversample.3407097535
Short name T462
Test name
Test status
Simulation time 7053710773 ps
CPU time 34.38 seconds
Started Sep 01 06:27:01 AM UTC 24
Finished Sep 01 06:27:36 AM UTC 24
Peak memory 207980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407097535 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.3407097535
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.2917848951
Short name T116
Test name
Test status
Simulation time 33311822642 ps
CPU time 56.47 seconds
Started Sep 01 06:27:09 AM UTC 24
Finished Sep 01 06:28:07 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917848951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2917848951
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.932927047
Short name T388
Test name
Test status
Simulation time 42868154168 ps
CPU time 21.45 seconds
Started Sep 01 06:27:06 AM UTC 24
Finished Sep 01 06:27:29 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932927047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.932927047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_smoke.4129202327
Short name T316
Test name
Test status
Simulation time 127926284 ps
CPU time 1.58 seconds
Started Sep 01 06:26:54 AM UTC 24
Finished Sep 01 06:26:57 AM UTC 24
Peak memory 206776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129202327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4129202327
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.1207533311
Short name T39
Test name
Test status
Simulation time 1314281310 ps
CPU time 13.32 seconds
Started Sep 01 06:27:14 AM UTC 24
Finished Sep 01 06:27:29 AM UTC 24
Peak memory 208900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1207533311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_
with_rand_reset.1207533311
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.3581606718
Short name T335
Test name
Test status
Simulation time 6635223363 ps
CPU time 12.62 seconds
Started Sep 01 06:27:10 AM UTC 24
Finished Sep 01 06:27:24 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581606718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3581606718
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/8.uart_tx_rx.1911883722
Short name T278
Test name
Test status
Simulation time 26653831986 ps
CPU time 65.61 seconds
Started Sep 01 06:26:54 AM UTC 24
Finished Sep 01 06:28:02 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911883722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1911883722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/8.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/80.uart_fifo_reset.210502475
Short name T994
Test name
Test status
Simulation time 237177658359 ps
CPU time 64.51 seconds
Started Sep 01 06:50:28 AM UTC 24
Finished Sep 01 06:51:35 AM UTC 24
Peak memory 208604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210502475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.210502475
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/80.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.4146671149
Short name T987
Test name
Test status
Simulation time 4981820993 ps
CPU time 52.02 seconds
Started Sep 01 06:50:29 AM UTC 24
Finished Sep 01 06:51:23 AM UTC 24
Peak memory 217868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4146671149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all
_with_rand_reset.4146671149
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/81.uart_fifo_reset.2655891124
Short name T182
Test name
Test status
Simulation time 20258175103 ps
CPU time 67.67 seconds
Started Sep 01 06:50:31 AM UTC 24
Finished Sep 01 06:51:40 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655891124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.2655891124
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/81.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.3127007180
Short name T971
Test name
Test status
Simulation time 1321744983 ps
CPU time 21.97 seconds
Started Sep 01 06:50:31 AM UTC 24
Finished Sep 01 06:50:54 AM UTC 24
Peak memory 217876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3127007180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all
_with_rand_reset.3127007180
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/82.uart_fifo_reset.824400837
Short name T162
Test name
Test status
Simulation time 71725121064 ps
CPU time 249.52 seconds
Started Sep 01 06:50:33 AM UTC 24
Finished Sep 01 06:54:46 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824400837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.824400837
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/82.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.1488801554
Short name T991
Test name
Test status
Simulation time 6093995278 ps
CPU time 55.48 seconds
Started Sep 01 06:50:34 AM UTC 24
Finished Sep 01 06:51:31 AM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1488801554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all
_with_rand_reset.1488801554
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1001770373
Short name T977
Test name
Test status
Simulation time 39725055023 ps
CPU time 26.51 seconds
Started Sep 01 06:50:36 AM UTC 24
Finished Sep 01 06:51:04 AM UTC 24
Peak memory 208572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001770373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1001770373
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/83.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.1073462268
Short name T985
Test name
Test status
Simulation time 2816749265 ps
CPU time 40.93 seconds
Started Sep 01 06:50:39 AM UTC 24
Finished Sep 01 06:51:21 AM UTC 24
Peak memory 217676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1073462268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all
_with_rand_reset.1073462268
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/84.uart_fifo_reset.2568152498
Short name T1004
Test name
Test status
Simulation time 134142594748 ps
CPU time 60.18 seconds
Started Sep 01 06:50:52 AM UTC 24
Finished Sep 01 06:51:54 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568152498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2568152498
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/84.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.1922870623
Short name T986
Test name
Test status
Simulation time 2558097539 ps
CPU time 27.57 seconds
Started Sep 01 06:50:53 AM UTC 24
Finished Sep 01 06:51:22 AM UTC 24
Peak memory 219776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1922870623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all
_with_rand_reset.1922870623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/85.uart_fifo_reset.1824257017
Short name T995
Test name
Test status
Simulation time 24629207883 ps
CPU time 47.05 seconds
Started Sep 01 06:50:53 AM UTC 24
Finished Sep 01 06:51:42 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824257017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1824257017
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/85.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.3523296444
Short name T1001
Test name
Test status
Simulation time 5815697320 ps
CPU time 53.51 seconds
Started Sep 01 06:50:53 AM UTC 24
Finished Sep 01 06:51:48 AM UTC 24
Peak memory 217976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3523296444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all
_with_rand_reset.3523296444
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3743459814
Short name T1007
Test name
Test status
Simulation time 26610595495 ps
CPU time 67.62 seconds
Started Sep 01 06:50:55 AM UTC 24
Finished Sep 01 06:52:04 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743459814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3743459814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/86.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.794017912
Short name T1012
Test name
Test status
Simulation time 19035663589 ps
CPU time 74.34 seconds
Started Sep 01 06:50:56 AM UTC 24
Finished Sep 01 06:52:12 AM UTC 24
Peak memory 222080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=794017912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all_
with_rand_reset.794017912
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/87.uart_fifo_reset.914996661
Short name T1101
Test name
Test status
Simulation time 152373099974 ps
CPU time 323.68 seconds
Started Sep 01 06:50:58 AM UTC 24
Finished Sep 01 06:56:25 AM UTC 24
Peak memory 208788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914996661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.914996661
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/87.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.779610580
Short name T1011
Test name
Test status
Simulation time 34259232268 ps
CPU time 69.2 seconds
Started Sep 01 06:50:59 AM UTC 24
Finished Sep 01 06:52:10 AM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=779610580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all_
with_rand_reset.779610580
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/88.uart_fifo_reset.317821297
Short name T997
Test name
Test status
Simulation time 22808419382 ps
CPU time 43.33 seconds
Started Sep 01 06:51:00 AM UTC 24
Finished Sep 01 06:51:45 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317821297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.317821297
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/88.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.323377264
Short name T988
Test name
Test status
Simulation time 6604927754 ps
CPU time 21.43 seconds
Started Sep 01 06:51:04 AM UTC 24
Finished Sep 01 06:51:27 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=323377264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all_
with_rand_reset.323377264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/89.uart_fifo_reset.1848376811
Short name T993
Test name
Test status
Simulation time 8201969301 ps
CPU time 27.72 seconds
Started Sep 01 06:51:05 AM UTC 24
Finished Sep 01 06:51:34 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848376811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1848376811
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/89.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.455053184
Short name T1005
Test name
Test status
Simulation time 22985525257 ps
CPU time 48.7 seconds
Started Sep 01 06:51:06 AM UTC 24
Finished Sep 01 06:51:56 AM UTC 24
Peak memory 217632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=455053184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all_
with_rand_reset.455053184
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_alert_test.2044647760
Short name T461
Test name
Test status
Simulation time 21126737 ps
CPU time 0.85 seconds
Started Sep 01 06:27:31 AM UTC 24
Finished Sep 01 06:27:33 AM UTC 24
Peak memory 204444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044647760 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2044647760
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_fifo_full.848584370
Short name T405
Test name
Test status
Simulation time 217880450029 ps
CPU time 457.52 seconds
Started Sep 01 06:27:23 AM UTC 24
Finished Sep 01 06:35:06 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848584370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.848584370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.2888559425
Short name T361
Test name
Test status
Simulation time 74425048169 ps
CPU time 173.47 seconds
Started Sep 01 06:27:23 AM UTC 24
Finished Sep 01 06:30:19 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888559425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2888559425
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_intr.3829852105
Short name T284
Test name
Test status
Simulation time 58533413043 ps
CPU time 27.67 seconds
Started Sep 01 06:27:25 AM UTC 24
Finished Sep 01 06:27:54 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829852105 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3829852105
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.2603173916
Short name T325
Test name
Test status
Simulation time 108550091599 ps
CPU time 253.78 seconds
Started Sep 01 06:27:30 AM UTC 24
Finished Sep 01 06:31:48 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603173916 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2603173916
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_loopback.1684267601
Short name T464
Test name
Test status
Simulation time 7817988311 ps
CPU time 24.29 seconds
Started Sep 01 06:27:28 AM UTC 24
Finished Sep 01 06:27:53 AM UTC 24
Peak memory 208640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684267601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1684267601
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_noise_filter.3125345804
Short name T313
Test name
Test status
Simulation time 49360258921 ps
CPU time 24.3 seconds
Started Sep 01 06:27:25 AM UTC 24
Finished Sep 01 06:27:51 AM UTC 24
Peak memory 207468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125345804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3125345804
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_perf.2121251256
Short name T354
Test name
Test status
Simulation time 20981380454 ps
CPU time 263.58 seconds
Started Sep 01 06:27:30 AM UTC 24
Finished Sep 01 06:31:57 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121251256 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2121251256
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_rx_oversample.828338205
Short name T468
Test name
Test status
Simulation time 7658830211 ps
CPU time 54.15 seconds
Started Sep 01 06:27:24 AM UTC 24
Finished Sep 01 06:28:20 AM UTC 24
Peak memory 207704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828338205 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.828338205
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.4051120079
Short name T271
Test name
Test status
Simulation time 60738279761 ps
CPU time 57.67 seconds
Started Sep 01 06:27:26 AM UTC 24
Finished Sep 01 06:28:26 AM UTC 24
Peak memory 208660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051120079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.4051120079
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.1017753902
Short name T330
Test name
Test status
Simulation time 4611351969 ps
CPU time 7.66 seconds
Started Sep 01 06:27:25 AM UTC 24
Finished Sep 01 06:27:34 AM UTC 24
Peak memory 205100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017753902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1017753902
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_smoke.3867122622
Short name T331
Test name
Test status
Simulation time 494051937 ps
CPU time 3 seconds
Started Sep 01 06:27:21 AM UTC 24
Finished Sep 01 06:27:25 AM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867122622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3867122622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_stress_all.4113153557
Short name T910
Test name
Test status
Simulation time 333217485603 ps
CPU time 1247.78 seconds
Started Sep 01 06:27:31 AM UTC 24
Finished Sep 01 06:48:33 AM UTC 24
Peak memory 212308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113153557 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4113153557
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3769993736
Short name T99
Test name
Test status
Simulation time 2779360781 ps
CPU time 90.13 seconds
Started Sep 01 06:27:30 AM UTC 24
Finished Sep 01 06:29:02 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3769993736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_
with_rand_reset.3769993736
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.3519201265
Short name T352
Test name
Test status
Simulation time 3256206053 ps
CPU time 3.16 seconds
Started Sep 01 06:27:27 AM UTC 24
Finished Sep 01 06:27:31 AM UTC 24
Peak memory 208092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519201265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3519201265
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/9.uart_tx_rx.19056139
Short name T345
Test name
Test status
Simulation time 99861211084 ps
CPU time 211.67 seconds
Started Sep 01 06:27:22 AM UTC 24
Finished Sep 01 06:30:57 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19056139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.19056139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/9.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/90.uart_fifo_reset.568624099
Short name T446
Test name
Test status
Simulation time 139864156292 ps
CPU time 101.84 seconds
Started Sep 01 06:51:06 AM UTC 24
Finished Sep 01 06:52:50 AM UTC 24
Peak memory 208512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568624099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.568624099
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/90.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.212428194
Short name T1002
Test name
Test status
Simulation time 2127185693 ps
CPU time 40.38 seconds
Started Sep 01 06:51:08 AM UTC 24
Finished Sep 01 06:51:50 AM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=212428194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all_
with_rand_reset.212428194
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/91.uart_fifo_reset.3488126036
Short name T184
Test name
Test status
Simulation time 141468187491 ps
CPU time 72.69 seconds
Started Sep 01 06:51:11 AM UTC 24
Finished Sep 01 06:52:26 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488126036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3488126036
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/91.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.414940709
Short name T1000
Test name
Test status
Simulation time 7639143560 ps
CPU time 31.82 seconds
Started Sep 01 06:51:14 AM UTC 24
Finished Sep 01 06:51:47 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=414940709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all_
with_rand_reset.414940709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/92.uart_fifo_reset.1533747762
Short name T999
Test name
Test status
Simulation time 77704421429 ps
CPU time 31.49 seconds
Started Sep 01 06:51:14 AM UTC 24
Finished Sep 01 06:51:46 AM UTC 24
Peak memory 208772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533747762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1533747762
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/92.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.2857332727
Short name T998
Test name
Test status
Simulation time 6360611237 ps
CPU time 28.23 seconds
Started Sep 01 06:51:16 AM UTC 24
Finished Sep 01 06:51:45 AM UTC 24
Peak memory 225500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2857332727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all
_with_rand_reset.2857332727
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/93.uart_fifo_reset.1680212616
Short name T433
Test name
Test status
Simulation time 266604222794 ps
CPU time 123.09 seconds
Started Sep 01 06:51:21 AM UTC 24
Finished Sep 01 06:53:26 AM UTC 24
Peak memory 208420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680212616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1680212616
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/93.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.2656212845
Short name T1015
Test name
Test status
Simulation time 40194584146 ps
CPU time 56.33 seconds
Started Sep 01 06:51:21 AM UTC 24
Finished Sep 01 06:52:19 AM UTC 24
Peak memory 217588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2656212845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all
_with_rand_reset.2656212845
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/94.uart_fifo_reset.2807979164
Short name T1075
Test name
Test status
Simulation time 217774242661 ps
CPU time 216.97 seconds
Started Sep 01 06:51:22 AM UTC 24
Finished Sep 01 06:55:02 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807979164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2807979164
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/94.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.2581480563
Short name T1010
Test name
Test status
Simulation time 3217423807 ps
CPU time 44.94 seconds
Started Sep 01 06:51:23 AM UTC 24
Finished Sep 01 06:52:10 AM UTC 24
Peak memory 217780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2581480563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all
_with_rand_reset.2581480563
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/95.uart_fifo_reset.2084329733
Short name T1042
Test name
Test status
Simulation time 98378386399 ps
CPU time 114.36 seconds
Started Sep 01 06:51:24 AM UTC 24
Finished Sep 01 06:53:21 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084329733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2084329733
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/95.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.725457541
Short name T1016
Test name
Test status
Simulation time 2982658122 ps
CPU time 51.1 seconds
Started Sep 01 06:51:26 AM UTC 24
Finished Sep 01 06:52:19 AM UTC 24
Peak memory 217592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=725457541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all_
with_rand_reset.725457541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/96.uart_fifo_reset.454763298
Short name T1024
Test name
Test status
Simulation time 121478482336 ps
CPU time 67.35 seconds
Started Sep 01 06:51:27 AM UTC 24
Finished Sep 01 06:52:37 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454763298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.454763298
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/96.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.2509997564
Short name T1023
Test name
Test status
Simulation time 15659084112 ps
CPU time 65.62 seconds
Started Sep 01 06:51:28 AM UTC 24
Finished Sep 01 06:52:35 AM UTC 24
Peak memory 221812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2509997564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all
_with_rand_reset.2509997564
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/97.uart_fifo_reset.3855799987
Short name T1090
Test name
Test status
Simulation time 147798513524 ps
CPU time 249.27 seconds
Started Sep 01 06:51:31 AM UTC 24
Finished Sep 01 06:55:43 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855799987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3855799987
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/97.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2283334123
Short name T1049
Test name
Test status
Simulation time 7177366129 ps
CPU time 132.39 seconds
Started Sep 01 06:51:32 AM UTC 24
Finished Sep 01 06:53:47 AM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2283334123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all
_with_rand_reset.2283334123
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/98.uart_fifo_reset.619397810
Short name T1013
Test name
Test status
Simulation time 17107153908 ps
CPU time 35.45 seconds
Started Sep 01 06:51:35 AM UTC 24
Finished Sep 01 06:52:12 AM UTC 24
Peak memory 208764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619397810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.619397810
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/98.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.4273314953
Short name T1037
Test name
Test status
Simulation time 7210657583 ps
CPU time 85.57 seconds
Started Sep 01 06:51:35 AM UTC 24
Finished Sep 01 06:53:02 AM UTC 24
Peak memory 219836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4273314953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all
_with_rand_reset.4273314953
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/99.uart_fifo_reset.3974405875
Short name T1020
Test name
Test status
Simulation time 55639813609 ps
CPU time 53.69 seconds
Started Sep 01 06:51:36 AM UTC 24
Finished Sep 01 06:52:32 AM UTC 24
Peak memory 208692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974405875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3974405875
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/99.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.4040142513
Short name T1033
Test name
Test status
Simulation time 4104743718 ps
CPU time 76.99 seconds
Started Sep 01 06:51:38 AM UTC 24
Finished Sep 01 06:52:57 AM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4040142513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all
_with_rand_reset.4040142513
Directory /workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest
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