| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/198.uart_fifo_reset.3326566610 |
|
|
Sep 09 07:05:28 AM UTC 24 |
Sep 09 07:05:43 AM UTC 24 |
30434055253 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/132.uart_fifo_reset.1885312696 |
|
|
Sep 09 07:04:10 AM UTC 24 |
Sep 09 07:05:44 AM UTC 24 |
54886096371 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_stress_all.176285781 |
|
|
Sep 09 06:51:42 AM UTC 24 |
Sep 09 07:05:46 AM UTC 24 |
364854706323 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/184.uart_fifo_reset.2698246691 |
|
|
Sep 09 07:05:10 AM UTC 24 |
Sep 09 07:05:47 AM UTC 24 |
42156728351 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/190.uart_fifo_reset.1718543095 |
|
|
Sep 09 07:05:14 AM UTC 24 |
Sep 09 07:05:48 AM UTC 24 |
16858969480 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.4103702150 |
|
|
Sep 09 06:45:53 AM UTC 24 |
Sep 09 07:05:48 AM UTC 24 |
123703261925 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/173.uart_fifo_reset.1679577849 |
|
|
Sep 09 07:05:00 AM UTC 24 |
Sep 09 07:05:48 AM UTC 24 |
16238216561 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_perf.2386753499 |
|
|
Sep 09 06:56:15 AM UTC 24 |
Sep 09 07:05:49 AM UTC 24 |
10173030378 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/165.uart_fifo_reset.785331649 |
|
|
Sep 09 07:04:53 AM UTC 24 |
Sep 09 07:05:50 AM UTC 24 |
128109160870 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/126.uart_fifo_reset.1200699914 |
|
|
Sep 09 07:04:00 AM UTC 24 |
Sep 09 07:05:52 AM UTC 24 |
139752513445 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3493433435 |
|
|
Sep 09 07:05:19 AM UTC 24 |
Sep 09 07:05:52 AM UTC 24 |
44106842022 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3485751376 |
|
|
Sep 09 07:05:33 AM UTC 24 |
Sep 09 07:05:55 AM UTC 24 |
37020574776 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/215.uart_fifo_reset.1977548617 |
|
|
Sep 09 07:05:49 AM UTC 24 |
Sep 09 07:05:55 AM UTC 24 |
9156407858 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/211.uart_fifo_reset.365759935 |
|
|
Sep 09 07:05:46 AM UTC 24 |
Sep 09 07:06:00 AM UTC 24 |
28997677223 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/134.uart_fifo_reset.3824590645 |
|
|
Sep 09 07:04:16 AM UTC 24 |
Sep 09 07:06:00 AM UTC 24 |
115931934626 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/189.uart_fifo_reset.899950065 |
|
|
Sep 09 07:05:13 AM UTC 24 |
Sep 09 07:06:00 AM UTC 24 |
56481580690 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/205.uart_fifo_reset.3391519189 |
|
|
Sep 09 07:05:37 AM UTC 24 |
Sep 09 07:06:01 AM UTC 24 |
51624752389 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/178.uart_fifo_reset.1073829270 |
|
|
Sep 09 07:05:04 AM UTC 24 |
Sep 09 07:06:04 AM UTC 24 |
62384017459 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/108.uart_fifo_reset.3886020050 |
|
|
Sep 09 07:03:36 AM UTC 24 |
Sep 09 07:06:05 AM UTC 24 |
102994535199 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/144.uart_fifo_reset.2396620055 |
|
|
Sep 09 07:04:31 AM UTC 24 |
Sep 09 07:06:07 AM UTC 24 |
152382023654 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/181.uart_fifo_reset.2194170459 |
|
|
Sep 09 07:05:08 AM UTC 24 |
Sep 09 07:06:07 AM UTC 24 |
20645947570 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/176.uart_fifo_reset.4261882007 |
|
|
Sep 09 07:05:01 AM UTC 24 |
Sep 09 07:06:11 AM UTC 24 |
33883361512 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2225205135 |
|
|
Sep 09 07:05:43 AM UTC 24 |
Sep 09 07:06:15 AM UTC 24 |
13010738567 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/164.uart_fifo_reset.599403584 |
|
|
Sep 09 07:04:53 AM UTC 24 |
Sep 09 07:06:17 AM UTC 24 |
186446008973 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/148.uart_fifo_reset.404631294 |
|
|
Sep 09 07:04:37 AM UTC 24 |
Sep 09 07:06:18 AM UTC 24 |
59615464726 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/212.uart_fifo_reset.193048681 |
|
|
Sep 09 07:05:48 AM UTC 24 |
Sep 09 07:06:20 AM UTC 24 |
313769661030 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/218.uart_fifo_reset.431755160 |
|
|
Sep 09 07:05:54 AM UTC 24 |
Sep 09 07:06:21 AM UTC 24 |
95913575126 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/191.uart_fifo_reset.3793868542 |
|
|
Sep 09 07:05:14 AM UTC 24 |
Sep 09 07:06:22 AM UTC 24 |
32434540034 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3251130030 |
|
|
Sep 09 07:05:19 AM UTC 24 |
Sep 09 07:06:25 AM UTC 24 |
33786900232 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/103.uart_fifo_reset.732595481 |
|
|
Sep 09 07:03:26 AM UTC 24 |
Sep 09 07:06:28 AM UTC 24 |
76661544268 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3396442485 |
|
|
Sep 09 07:05:45 AM UTC 24 |
Sep 09 07:06:31 AM UTC 24 |
34841298403 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_perf.395947512 |
|
|
Sep 09 06:57:55 AM UTC 24 |
Sep 09 07:06:31 AM UTC 24 |
18428003200 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/150.uart_fifo_reset.1615457787 |
|
|
Sep 09 07:04:40 AM UTC 24 |
Sep 09 07:06:36 AM UTC 24 |
36939759921 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2699845991 |
|
|
Sep 09 07:05:34 AM UTC 24 |
Sep 09 07:06:41 AM UTC 24 |
39311446388 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/137.uart_fifo_reset.3781480726 |
|
|
Sep 09 07:04:19 AM UTC 24 |
Sep 09 07:06:43 AM UTC 24 |
67232046409 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2593363105 |
|
|
Sep 09 07:06:01 AM UTC 24 |
Sep 09 07:06:44 AM UTC 24 |
78909295770 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1675768646 |
|
|
Sep 09 07:05:09 AM UTC 24 |
Sep 09 07:06:47 AM UTC 24 |
93921550061 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2275915887 |
|
|
Sep 09 07:05:44 AM UTC 24 |
Sep 09 07:06:47 AM UTC 24 |
43111824833 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/228.uart_fifo_reset.1319482969 |
|
|
Sep 09 07:06:07 AM UTC 24 |
Sep 09 07:06:50 AM UTC 24 |
81455470740 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/222.uart_fifo_reset.415598953 |
|
|
Sep 09 07:06:01 AM UTC 24 |
Sep 09 07:06:52 AM UTC 24 |
18560184895 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3849999295 |
|
|
Sep 09 07:05:27 AM UTC 24 |
Sep 09 07:06:52 AM UTC 24 |
161418827514 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2111504557 |
|
|
Sep 09 07:04:50 AM UTC 24 |
Sep 09 07:06:53 AM UTC 24 |
213154568788 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_perf.3391674528 |
|
|
Sep 09 06:58:26 AM UTC 24 |
Sep 09 07:06:53 AM UTC 24 |
9399489086 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/232.uart_fifo_reset.1524399218 |
|
|
Sep 09 07:06:18 AM UTC 24 |
Sep 09 07:06:55 AM UTC 24 |
20303256093 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/240.uart_fifo_reset.2769670908 |
|
|
Sep 09 07:06:32 AM UTC 24 |
Sep 09 07:06:58 AM UTC 24 |
20989779184 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/169.uart_fifo_reset.853529667 |
|
|
Sep 09 07:04:57 AM UTC 24 |
Sep 09 07:06:58 AM UTC 24 |
162576734038 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2363922344 |
|
|
Sep 09 07:06:02 AM UTC 24 |
Sep 09 07:07:00 AM UTC 24 |
136016379115 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/200.uart_fifo_reset.2755344427 |
|
|
Sep 09 07:05:33 AM UTC 24 |
Sep 09 07:07:00 AM UTC 24 |
144820641923 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/152.uart_fifo_reset.3285863808 |
|
|
Sep 09 07:04:42 AM UTC 24 |
Sep 09 07:07:01 AM UTC 24 |
85194002668 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/236.uart_fifo_reset.1199983796 |
|
|
Sep 09 07:06:23 AM UTC 24 |
Sep 09 07:07:02 AM UTC 24 |
53487772947 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/244.uart_fifo_reset.421627686 |
|
|
Sep 09 07:06:45 AM UTC 24 |
Sep 09 07:07:03 AM UTC 24 |
29833065354 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/206.uart_fifo_reset.345049601 |
|
|
Sep 09 07:05:37 AM UTC 24 |
Sep 09 07:07:04 AM UTC 24 |
161781502780 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/227.uart_fifo_reset.375273891 |
|
|
Sep 09 07:06:06 AM UTC 24 |
Sep 09 07:07:08 AM UTC 24 |
87646112384 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3110342920 |
|
|
Sep 09 07:05:33 AM UTC 24 |
Sep 09 07:07:09 AM UTC 24 |
43453033141 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/131.uart_fifo_reset.2298974530 |
|
|
Sep 09 07:04:08 AM UTC 24 |
Sep 09 07:07:10 AM UTC 24 |
66612234763 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/102.uart_fifo_reset.3724010588 |
|
|
Sep 09 07:03:23 AM UTC 24 |
Sep 09 07:07:11 AM UTC 24 |
113445419704 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/246.uart_fifo_reset.2406562258 |
|
|
Sep 09 07:06:48 AM UTC 24 |
Sep 09 07:07:13 AM UTC 24 |
21499079531 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/234.uart_fifo_reset.4006149504 |
|
|
Sep 09 07:06:21 AM UTC 24 |
Sep 09 07:07:13 AM UTC 24 |
23472827969 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/248.uart_fifo_reset.950065966 |
|
|
Sep 09 07:06:53 AM UTC 24 |
Sep 09 07:07:17 AM UTC 24 |
21484281541 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/252.uart_fifo_reset.646599067 |
|
|
Sep 09 07:06:56 AM UTC 24 |
Sep 09 07:07:17 AM UTC 24 |
9433603227 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2023810434 |
|
|
Sep 09 07:06:05 AM UTC 24 |
Sep 09 07:07:18 AM UTC 24 |
212478899086 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/238.uart_fifo_reset.1983891770 |
|
|
Sep 09 07:06:29 AM UTC 24 |
Sep 09 07:07:22 AM UTC 24 |
29470210959 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/237.uart_fifo_reset.4189687328 |
|
|
Sep 09 07:06:26 AM UTC 24 |
Sep 09 07:07:22 AM UTC 24 |
73087876157 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1540977288 |
|
|
Sep 09 07:05:49 AM UTC 24 |
Sep 09 07:07:22 AM UTC 24 |
95393206408 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/216.uart_fifo_reset.761282569 |
|
|
Sep 09 07:05:50 AM UTC 24 |
Sep 09 07:07:27 AM UTC 24 |
76467203171 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3137545745 |
|
|
Sep 09 07:05:50 AM UTC 24 |
Sep 09 07:07:29 AM UTC 24 |
39796044418 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/107.uart_fifo_reset.958046339 |
|
|
Sep 09 07:03:31 AM UTC 24 |
Sep 09 07:07:32 AM UTC 24 |
127147329072 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/261.uart_fifo_reset.3667415526 |
|
|
Sep 09 07:07:09 AM UTC 24 |
Sep 09 07:07:33 AM UTC 24 |
11979513477 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/259.uart_fifo_reset.2347733828 |
|
|
Sep 09 07:07:04 AM UTC 24 |
Sep 09 07:07:35 AM UTC 24 |
14991770146 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1621695194 |
|
|
Sep 09 07:05:29 AM UTC 24 |
Sep 09 07:07:38 AM UTC 24 |
36080597634 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/160.uart_fifo_reset.1458291850 |
|
|
Sep 09 07:04:49 AM UTC 24 |
Sep 09 07:07:38 AM UTC 24 |
113602570316 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/255.uart_fifo_reset.2172424411 |
|
|
Sep 09 07:07:00 AM UTC 24 |
Sep 09 07:07:39 AM UTC 24 |
62885041963 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/266.uart_fifo_reset.683683477 |
|
|
Sep 09 07:07:13 AM UTC 24 |
Sep 09 07:07:42 AM UTC 24 |
15217305569 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3577871097 |
|
|
Sep 09 07:06:19 AM UTC 24 |
Sep 09 07:07:42 AM UTC 24 |
30098039534 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/141.uart_fifo_reset.2970442602 |
|
|
Sep 09 07:04:28 AM UTC 24 |
Sep 09 07:07:44 AM UTC 24 |
133286265228 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/95.uart_fifo_reset.74782280 |
|
|
Sep 09 07:03:04 AM UTC 24 |
Sep 09 07:07:45 AM UTC 24 |
159636714203 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_stress_all.492711642 |
|
|
Sep 09 06:59:46 AM UTC 24 |
Sep 09 07:07:47 AM UTC 24 |
143813033294 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3444550757 |
|
|
Sep 09 07:07:05 AM UTC 24 |
Sep 09 07:07:49 AM UTC 24 |
14763863972 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/171.uart_fifo_reset.1622770274 |
|
|
Sep 09 07:04:59 AM UTC 24 |
Sep 09 07:07:49 AM UTC 24 |
163696665739 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3847913841 |
|
|
Sep 09 07:07:13 AM UTC 24 |
Sep 09 07:07:53 AM UTC 24 |
24926905208 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/121.uart_fifo_reset.297937567 |
|
|
Sep 09 07:03:57 AM UTC 24 |
Sep 09 07:07:54 AM UTC 24 |
170027717117 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3972191783 |
|
|
Sep 09 07:06:48 AM UTC 24 |
Sep 09 07:07:55 AM UTC 24 |
81480530380 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/281.uart_fifo_reset.745756104 |
|
|
Sep 09 07:07:42 AM UTC 24 |
Sep 09 07:07:56 AM UTC 24 |
31390148588 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/263.uart_fifo_reset.1153435695 |
|
|
Sep 09 07:07:11 AM UTC 24 |
Sep 09 07:07:56 AM UTC 24 |
24772446432 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3987952158 |
|
|
Sep 09 07:07:44 AM UTC 24 |
Sep 09 07:07:59 AM UTC 24 |
48088469433 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/279.uart_fifo_reset.1168511655 |
|
|
Sep 09 07:07:39 AM UTC 24 |
Sep 09 07:08:02 AM UTC 24 |
11132350151 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/195.uart_fifo_reset.2088738641 |
|
|
Sep 09 07:05:22 AM UTC 24 |
Sep 09 07:08:02 AM UTC 24 |
108661912088 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/253.uart_fifo_reset.4096904230 |
|
|
Sep 09 07:06:59 AM UTC 24 |
Sep 09 07:08:04 AM UTC 24 |
27897183225 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/254.uart_fifo_reset.3243386666 |
|
|
Sep 09 07:06:59 AM UTC 24 |
Sep 09 07:08:04 AM UTC 24 |
219856295387 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2568072635 |
|
|
Sep 09 07:07:28 AM UTC 24 |
Sep 09 07:08:05 AM UTC 24 |
19544808720 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3992775989 |
|
|
Sep 09 07:07:57 AM UTC 24 |
Sep 09 07:08:20 AM UTC 24 |
33330162230 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/264.uart_fifo_reset.292912688 |
|
|
Sep 09 07:07:12 AM UTC 24 |
Sep 09 07:08:21 AM UTC 24 |
26535508479 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/241.uart_fifo_reset.2785538677 |
|
|
Sep 09 07:06:37 AM UTC 24 |
Sep 09 07:08:21 AM UTC 24 |
119836753983 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3139405865 |
|
|
Sep 09 07:07:36 AM UTC 24 |
Sep 09 07:08:23 AM UTC 24 |
28226252969 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2285626398 |
|
|
Sep 09 07:07:30 AM UTC 24 |
Sep 09 07:08:23 AM UTC 24 |
50947796051 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_stress_all.1604453657 |
|
|
Sep 09 06:54:47 AM UTC 24 |
Sep 09 07:08:28 AM UTC 24 |
365137528374 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/293.uart_fifo_reset.4044679883 |
|
|
Sep 09 07:08:00 AM UTC 24 |
Sep 09 07:08:28 AM UTC 24 |
38750926338 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/291.uart_fifo_reset.2183387360 |
|
|
Sep 09 07:07:57 AM UTC 24 |
Sep 09 07:08:28 AM UTC 24 |
12453813258 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/276.uart_fifo_reset.191453441 |
|
|
Sep 09 07:07:34 AM UTC 24 |
Sep 09 07:08:28 AM UTC 24 |
46848489585 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/288.uart_fifo_reset.1505306653 |
|
|
Sep 09 07:07:54 AM UTC 24 |
Sep 09 07:08:29 AM UTC 24 |
42397334355 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/280.uart_fifo_reset.1420550984 |
|
|
Sep 09 07:07:39 AM UTC 24 |
Sep 09 07:08:30 AM UTC 24 |
106022516899 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/278.uart_fifo_reset.413387833 |
|
|
Sep 09 07:07:38 AM UTC 24 |
Sep 09 07:08:31 AM UTC 24 |
96247184317 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2009478826 |
|
|
Sep 09 07:07:55 AM UTC 24 |
Sep 09 07:08:31 AM UTC 24 |
44545642940 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/298.uart_fifo_reset.3635675705 |
|
|
Sep 09 07:08:07 AM UTC 24 |
Sep 09 07:08:34 AM UTC 24 |
17940320274 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1149283659 |
|
|
Sep 09 07:07:23 AM UTC 24 |
Sep 09 07:08:35 AM UTC 24 |
64880888157 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/251.uart_fifo_reset.259096520 |
|
|
Sep 09 07:06:54 AM UTC 24 |
Sep 09 07:08:38 AM UTC 24 |
178079425235 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/213.uart_fifo_reset.3020590829 |
|
|
Sep 09 07:05:48 AM UTC 24 |
Sep 09 07:08:40 AM UTC 24 |
65010937953 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/185.uart_fifo_reset.2396211787 |
|
|
Sep 09 07:05:10 AM UTC 24 |
Sep 09 07:08:41 AM UTC 24 |
100090766038 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3583474494 |
|
|
Sep 09 07:07:48 AM UTC 24 |
Sep 09 07:08:42 AM UTC 24 |
149492714431 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/220.uart_fifo_reset.3733497364 |
|
|
Sep 09 07:05:56 AM UTC 24 |
Sep 09 07:08:44 AM UTC 24 |
362185232653 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/294.uart_fifo_reset.998549447 |
|
|
Sep 09 07:08:02 AM UTC 24 |
Sep 09 07:08:47 AM UTC 24 |
60363426104 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/231.uart_fifo_reset.241348080 |
|
|
Sep 09 07:06:16 AM UTC 24 |
Sep 09 07:08:55 AM UTC 24 |
89543826490 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/196.uart_fifo_reset.450449209 |
|
|
Sep 09 07:05:24 AM UTC 24 |
Sep 09 07:08:57 AM UTC 24 |
192174212101 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/242.uart_fifo_reset.2920554924 |
|
|
Sep 09 07:06:41 AM UTC 24 |
Sep 09 07:08:59 AM UTC 24 |
132707848573 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3866250465 |
|
|
Sep 09 07:06:22 AM UTC 24 |
Sep 09 07:09:00 AM UTC 24 |
101787289734 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/299.uart_fifo_reset.2745031525 |
|
|
Sep 09 07:08:21 AM UTC 24 |
Sep 09 07:09:00 AM UTC 24 |
41332292310 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/268.uart_fifo_reset.1830145400 |
|
|
Sep 09 07:07:18 AM UTC 24 |
Sep 09 07:09:00 AM UTC 24 |
37746489059 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/230.uart_fifo_reset.1409251320 |
|
|
Sep 09 07:06:12 AM UTC 24 |
Sep 09 07:09:04 AM UTC 24 |
183270177083 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/224.uart_fifo_reset.52522041 |
|
|
Sep 09 07:06:01 AM UTC 24 |
Sep 09 07:09:06 AM UTC 24 |
119256114495 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/270.uart_fifo_reset.2313695311 |
|
|
Sep 09 07:07:23 AM UTC 24 |
Sep 09 07:09:07 AM UTC 24 |
104094667775 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/188.uart_fifo_reset.1460760634 |
|
|
Sep 09 07:05:13 AM UTC 24 |
Sep 09 07:09:08 AM UTC 24 |
353479326467 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3011256575 |
|
|
Sep 09 07:07:50 AM UTC 24 |
Sep 09 07:09:09 AM UTC 24 |
47890830662 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1187337773 |
|
|
Sep 09 07:06:44 AM UTC 24 |
Sep 09 07:09:10 AM UTC 24 |
64732936653 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/204.uart_fifo_reset.1024504508 |
|
|
Sep 09 07:05:34 AM UTC 24 |
Sep 09 07:09:11 AM UTC 24 |
107262686076 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/229.uart_fifo_reset.47938023 |
|
|
Sep 09 07:06:08 AM UTC 24 |
Sep 09 07:09:14 AM UTC 24 |
76007057532 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3821614907 |
|
|
Sep 09 07:08:04 AM UTC 24 |
Sep 09 07:09:22 AM UTC 24 |
169211503358 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/249.uart_fifo_reset.1179249343 |
|
|
Sep 09 07:06:53 AM UTC 24 |
Sep 09 07:09:22 AM UTC 24 |
91846612989 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/247.uart_fifo_reset.983527142 |
|
|
Sep 09 07:06:51 AM UTC 24 |
Sep 09 07:09:24 AM UTC 24 |
144118986160 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/289.uart_fifo_reset.3803368917 |
|
|
Sep 09 07:07:55 AM UTC 24 |
Sep 09 07:09:25 AM UTC 24 |
48395816081 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_stress_all.3052644500 |
|
|
Sep 09 06:53:35 AM UTC 24 |
Sep 09 07:09:26 AM UTC 24 |
229875343964 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_stress_all.3940847257 |
|
|
Sep 09 06:57:36 AM UTC 24 |
Sep 09 07:09:27 AM UTC 24 |
223591573037 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1485299858 |
|
|
Sep 09 07:06:54 AM UTC 24 |
Sep 09 07:09:32 AM UTC 24 |
77181282381 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/272.uart_fifo_reset.2474983259 |
|
|
Sep 09 07:07:24 AM UTC 24 |
Sep 09 07:09:32 AM UTC 24 |
144242346098 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/257.uart_fifo_reset.3381398901 |
|
|
Sep 09 07:07:01 AM UTC 24 |
Sep 09 07:09:34 AM UTC 24 |
275375894899 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/275.uart_fifo_reset.1504641811 |
|
|
Sep 09 07:07:33 AM UTC 24 |
Sep 09 07:09:37 AM UTC 24 |
68843689825 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/269.uart_fifo_reset.1935522522 |
|
|
Sep 09 07:07:19 AM UTC 24 |
Sep 09 07:09:48 AM UTC 24 |
130086779771 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_stress_all.3921108158 |
|
|
Sep 09 06:59:19 AM UTC 24 |
Sep 09 07:10:02 AM UTC 24 |
276276952305 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.3473594709 |
|
|
Sep 09 06:58:53 AM UTC 24 |
Sep 09 07:10:08 AM UTC 24 |
118803153041 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/284.uart_fifo_reset.388872082 |
|
|
Sep 09 07:07:47 AM UTC 24 |
Sep 09 07:10:17 AM UTC 24 |
251198597612 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2042055486 |
|
|
Sep 09 07:07:43 AM UTC 24 |
Sep 09 07:10:24 AM UTC 24 |
82607276160 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/221.uart_fifo_reset.148269042 |
|
|
Sep 09 07:05:56 AM UTC 24 |
Sep 09 07:10:44 AM UTC 24 |
93900892879 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/157.uart_fifo_reset.4195335734 |
|
|
Sep 09 07:04:47 AM UTC 24 |
Sep 09 07:10:50 AM UTC 24 |
190309063822 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2491434205 |
|
|
Sep 09 07:07:10 AM UTC 24 |
Sep 09 07:10:56 AM UTC 24 |
125826174636 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/286.uart_fifo_reset.1869223418 |
|
|
Sep 09 07:07:50 AM UTC 24 |
Sep 09 07:11:04 AM UTC 24 |
97027271888 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/239.uart_fifo_reset.440300513 |
|
|
Sep 09 07:06:32 AM UTC 24 |
Sep 09 07:11:33 AM UTC 24 |
145831487097 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/258.uart_fifo_reset.3334061354 |
|
|
Sep 09 07:07:03 AM UTC 24 |
Sep 09 07:11:34 AM UTC 24 |
102473420715 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2040883292 |
|
|
Sep 09 07:08:03 AM UTC 24 |
Sep 09 07:13:16 AM UTC 24 |
181207328316 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/297.uart_fifo_reset.467523442 |
|
|
Sep 09 07:08:05 AM UTC 24 |
Sep 09 07:13:21 AM UTC 24 |
117040137689 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2352645034 |
|
|
Sep 09 07:05:54 AM UTC 24 |
Sep 09 07:13:59 AM UTC 24 |
104716385018 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1461608615 |
|
|
Sep 09 07:07:17 AM UTC 24 |
Sep 09 07:15:44 AM UTC 24 |
204092921295 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/256.uart_fifo_reset.3650944858 |
|
|
Sep 09 07:07:01 AM UTC 24 |
Sep 09 07:17:07 AM UTC 24 |
229030947019 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_perf.2136432839 |
|
|
Sep 09 06:52:04 AM UTC 24 |
Sep 09 07:19:51 AM UTC 24 |
29356640972 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2139001638 |
|
|
Sep 09 07:05:38 AM UTC 24 |
Sep 09 07:20:27 AM UTC 24 |
157380496867 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_stress_all.2686063775 |
|
|
Sep 09 06:55:15 AM UTC 24 |
Sep 09 07:28:59 AM UTC 24 |
191116889920 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2127258498 |
|
|
Sep 09 07:08:22 AM UTC 24 |
Sep 09 07:08:25 AM UTC 24 |
99379964 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2943955159 |
|
|
Sep 09 07:08:23 AM UTC 24 |
Sep 09 07:08:25 AM UTC 24 |
43676145 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.2749718969 |
|
|
Sep 09 07:08:24 AM UTC 24 |
Sep 09 07:08:26 AM UTC 24 |
28656889 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.3004956540 |
|
|
Sep 09 07:08:22 AM UTC 24 |
Sep 09 07:08:26 AM UTC 24 |
197957966 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1432394736 |
|
|
Sep 09 07:08:26 AM UTC 24 |
Sep 09 07:08:28 AM UTC 24 |
13805036 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.1915016437 |
|
|
Sep 09 07:08:27 AM UTC 24 |
Sep 09 07:08:29 AM UTC 24 |
141678248 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.93154521 |
|
|
Sep 09 07:08:27 AM UTC 24 |
Sep 09 07:08:30 AM UTC 24 |
33544888 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2259608804 |
|
|
Sep 09 07:08:28 AM UTC 24 |
Sep 09 07:08:31 AM UTC 24 |
20295051 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.3029168079 |
|
|
Sep 09 07:08:26 AM UTC 24 |
Sep 09 07:08:31 AM UTC 24 |
3139112230 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.3107075640 |
|
|
Sep 09 07:08:29 AM UTC 24 |
Sep 09 07:08:31 AM UTC 24 |
70745560 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3911796059 |
|
|
Sep 09 07:08:29 AM UTC 24 |
Sep 09 07:08:31 AM UTC 24 |
52323360 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.55940754 |
|
|
Sep 09 07:08:30 AM UTC 24 |
Sep 09 07:08:31 AM UTC 24 |
15129193 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.2575919340 |
|
|
Sep 09 07:08:30 AM UTC 24 |
Sep 09 07:08:32 AM UTC 24 |
34674292 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3409182017 |
|
|
Sep 09 07:08:30 AM UTC 24 |
Sep 09 07:08:32 AM UTC 24 |
28588524 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3955158847 |
|
|
Sep 09 07:08:30 AM UTC 24 |
Sep 09 07:08:33 AM UTC 24 |
131266329 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.2761691727 |
|
|
Sep 09 07:08:31 AM UTC 24 |
Sep 09 07:08:33 AM UTC 24 |
23210299 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.4034081630 |
|
|
Sep 09 07:08:31 AM UTC 24 |
Sep 09 07:08:33 AM UTC 24 |
49740788 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.108051688 |
|
|
Sep 09 07:08:32 AM UTC 24 |
Sep 09 07:08:35 AM UTC 24 |
85047309 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1011746060 |
|
|
Sep 09 07:08:32 AM UTC 24 |
Sep 09 07:08:35 AM UTC 24 |
332303217 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3904860960 |
|
|
Sep 09 07:08:33 AM UTC 24 |
Sep 09 07:08:35 AM UTC 24 |
67108082 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2771138202 |
|
|
Sep 09 07:08:33 AM UTC 24 |
Sep 09 07:08:35 AM UTC 24 |
82393790 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.1022354414 |
|
|
Sep 09 07:08:33 AM UTC 24 |
Sep 09 07:08:35 AM UTC 24 |
71235324 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.1144925616 |
|
|
Sep 09 07:08:33 AM UTC 24 |
Sep 09 07:08:35 AM UTC 24 |
17683526 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2826916330 |
|
|
Sep 09 07:08:32 AM UTC 24 |
Sep 09 07:08:35 AM UTC 24 |
163756593 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.1562145635 |
|
|
Sep 09 07:08:32 AM UTC 24 |
Sep 09 07:08:36 AM UTC 24 |
97413280 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.2560851614 |
|
|
Sep 09 07:08:33 AM UTC 24 |
Sep 09 07:08:36 AM UTC 24 |
70786468 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3645272967 |
|
|
Sep 09 07:08:34 AM UTC 24 |
Sep 09 07:08:36 AM UTC 24 |
41398632 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.621004006 |
|
|
Sep 09 07:08:34 AM UTC 24 |
Sep 09 07:08:37 AM UTC 24 |
157860066 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1714339415 |
|
|
Sep 09 07:08:34 AM UTC 24 |
Sep 09 07:08:37 AM UTC 24 |
145124732 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3622157343 |
|
|
Sep 09 07:08:35 AM UTC 24 |
Sep 09 07:08:37 AM UTC 24 |
22923866 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2557709016 |
|
|
Sep 09 07:08:35 AM UTC 24 |
Sep 09 07:08:37 AM UTC 24 |
35549673 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.1021065490 |
|
|
Sep 09 07:08:35 AM UTC 24 |
Sep 09 07:08:38 AM UTC 24 |
16239904 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1256223318 |
|
|
Sep 09 07:08:36 AM UTC 24 |
Sep 09 07:08:38 AM UTC 24 |
92419462 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3736324105 |
|
|
Sep 09 07:08:36 AM UTC 24 |
Sep 09 07:08:38 AM UTC 24 |
36250460 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1175661922 |
|
|
Sep 09 07:08:36 AM UTC 24 |
Sep 09 07:08:38 AM UTC 24 |
68270157 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2989487266 |
|
|
Sep 09 07:08:35 AM UTC 24 |
Sep 09 07:08:38 AM UTC 24 |
59351657 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2349612931 |
|
|
Sep 09 07:08:37 AM UTC 24 |
Sep 09 07:08:39 AM UTC 24 |
15125425 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3687725812 |
|
|
Sep 09 07:08:37 AM UTC 24 |
Sep 09 07:08:39 AM UTC 24 |
17382530 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.2841291581 |
|
|
Sep 09 07:08:37 AM UTC 24 |
Sep 09 07:08:39 AM UTC 24 |
11802263 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3283556584 |
|
|
Sep 09 07:08:37 AM UTC 24 |
Sep 09 07:08:40 AM UTC 24 |
72460007 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.1406754643 |
|
|
Sep 09 07:08:37 AM UTC 24 |
Sep 09 07:08:40 AM UTC 24 |
424029256 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2866812716 |
|
|
Sep 09 07:08:39 AM UTC 24 |
Sep 09 07:08:41 AM UTC 24 |
15653207 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2399705426 |
|
|
Sep 09 07:08:39 AM UTC 24 |
Sep 09 07:08:41 AM UTC 24 |
22658885 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.689419821 |
|
|
Sep 09 07:08:39 AM UTC 24 |
Sep 09 07:08:41 AM UTC 24 |
180305388 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.583615205 |
|
|
Sep 09 07:08:39 AM UTC 24 |
Sep 09 07:08:41 AM UTC 24 |
36910536 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.457251020 |
|
|
Sep 09 07:08:39 AM UTC 24 |
Sep 09 07:08:41 AM UTC 24 |
152324633 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1895905360 |
|
|
Sep 09 07:08:39 AM UTC 24 |
Sep 09 07:08:42 AM UTC 24 |
93580084 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2249961015 |
|
|
Sep 09 07:08:40 AM UTC 24 |
Sep 09 07:08:42 AM UTC 24 |
46996819 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.3189388392 |
|
|
Sep 09 07:08:40 AM UTC 24 |
Sep 09 07:08:42 AM UTC 24 |
36574599 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3394358908 |
|
|
Sep 09 07:08:40 AM UTC 24 |
Sep 09 07:08:42 AM UTC 24 |
91609769 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.582026457 |
|
|
Sep 09 07:08:41 AM UTC 24 |
Sep 09 07:08:42 AM UTC 24 |
44300434 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2455404782 |
|
|
Sep 09 07:08:41 AM UTC 24 |
Sep 09 07:08:42 AM UTC 24 |
13771288 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2458750975 |
|
|
Sep 09 07:08:39 AM UTC 24 |
Sep 09 07:08:43 AM UTC 24 |
1427870019 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.4191135489 |
|
|
Sep 09 07:08:41 AM UTC 24 |
Sep 09 07:08:43 AM UTC 24 |
74158437 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3986425556 |
|
|
Sep 09 07:08:41 AM UTC 24 |
Sep 09 07:08:44 AM UTC 24 |
41651795 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.1687205502 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:44 AM UTC 24 |
184533421 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4271006027 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:45 AM UTC 24 |
97770712 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.3183969193 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:45 AM UTC 24 |
20483392 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2393160399 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:45 AM UTC 24 |
42086789 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.840859731 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:45 AM UTC 24 |
65834383 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.4102406910 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:45 AM UTC 24 |
12181234 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2331159890 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:45 AM UTC 24 |
80256633 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1494917019 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:45 AM UTC 24 |
275083540 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3938765943 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:45 AM UTC 24 |
64149581 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.740320292 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:46 AM UTC 24 |
81479503 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.2894403090 |
|
|
Sep 09 07:08:43 AM UTC 24 |
Sep 09 07:08:46 AM UTC 24 |
77582894 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.4281987255 |
|
|
Sep 09 07:08:45 AM UTC 24 |
Sep 09 07:08:47 AM UTC 24 |
35411906 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3886170250 |
|
|
Sep 09 07:08:45 AM UTC 24 |
Sep 09 07:08:47 AM UTC 24 |
105526918 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.1326459726 |
|
|
Sep 09 07:08:45 AM UTC 24 |
Sep 09 07:08:47 AM UTC 24 |
172062232 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.767616768 |
|
|
Sep 09 07:08:45 AM UTC 24 |
Sep 09 07:08:47 AM UTC 24 |
14052459 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.4090113722 |
|
|
Sep 09 07:08:45 AM UTC 24 |
Sep 09 07:08:47 AM UTC 24 |
15839808 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.234785834 |
|
|
Sep 09 07:08:45 AM UTC 24 |
Sep 09 07:08:47 AM UTC 24 |
24887785 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1755616990 |
|
|
Sep 09 07:08:45 AM UTC 24 |
Sep 09 07:08:47 AM UTC 24 |
22431281 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.199292295 |
|
|
Sep 09 07:08:45 AM UTC 24 |
Sep 09 07:08:48 AM UTC 24 |
420424297 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.3880066544 |
|
|
Sep 09 07:08:45 AM UTC 24 |
Sep 09 07:08:48 AM UTC 24 |
59158834 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2016955577 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
152326681 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1974541932 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
16309658 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1528668996 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
22826599 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1664256498 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
197545306 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.1834042292 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
73296435 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.2922903756 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
37557526 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.2043581768 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
15795465 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3593327975 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
146376459 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2849556892 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
54712436 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3582126610 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:49 AM UTC 24 |
26026198 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1080673179 |
|
|
Sep 09 07:08:47 AM UTC 24 |
Sep 09 07:08:50 AM UTC 24 |
109829541 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.4005514734 |
|
|
Sep 09 07:08:49 AM UTC 24 |
Sep 09 07:08:51 AM UTC 24 |
14482888 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.4115240246 |
|
|
Sep 09 07:08:49 AM UTC 24 |
Sep 09 07:08:51 AM UTC 24 |
122795551 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.3781332771 |
|
|
Sep 09 07:08:49 AM UTC 24 |
Sep 09 07:08:51 AM UTC 24 |
33123673 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.894512705 |
|
|
Sep 09 07:08:49 AM UTC 24 |
Sep 09 07:08:51 AM UTC 24 |
51472900 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4138064255 |
|
|
Sep 09 07:08:49 AM UTC 24 |
Sep 09 07:08:51 AM UTC 24 |
32693718 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3454532882 |
|
|
Sep 09 07:08:49 AM UTC 24 |
Sep 09 07:08:51 AM UTC 24 |
178353207 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1828945184 |
|
|
Sep 09 07:08:49 AM UTC 24 |
Sep 09 07:08:52 AM UTC 24 |
125354540 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.861140867 |
|
|
Sep 09 07:08:49 AM UTC 24 |
Sep 09 07:08:52 AM UTC 24 |
89896844 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3499998260 |
|
|
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