Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.10	97.65	100.00		98.38	100.00	99.44

Total test records in report: 1319

T1256	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2082979322	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:54 AM UTC 24	54193530 ps
T1257	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.1524082151	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:54 AM UTC 24	29645213 ps
T1258	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.2224077507	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:54 AM UTC 24	14153662 ps
T1259	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2157008192	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:55 AM UTC 24	17194574 ps
T1260	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3011273523	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:55 AM UTC 24	25075823 ps
T1261	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1498721045	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:55 AM UTC 24	80464987 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3147667713	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:55 AM UTC 24	56703380 ps
T1262	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.83034010	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:55 AM UTC 24	38042973 ps
T1263	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.2978602899	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:55 AM UTC 24	161610194 ps
T1264	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1557301614	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:55 AM UTC 24	26708201 ps
T1265	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.3583778461	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:55 AM UTC 24	40408153 ps
T1266	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.904116337	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:55 AM UTC 24	31062059 ps
T1267	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.901446683	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:56 AM UTC 24	378569761 ps
T1268	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.435688041	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:56 AM UTC 24	460623206 ps
T1269	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3092218132	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:56 AM UTC 24	345908811 ps
T1270	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.1062279067	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:56 AM UTC 24	38803548 ps
T1271	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.918475462	Sep 09 07:08:53 AM UTC 24	Sep 09 07:08:57 AM UTC 24	125767649 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.4099224647	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	16669467 ps
T1272	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.874037611	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	26833295 ps
T1273	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.2931642969	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	25049652 ps
T1274	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.33298176	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	64732944 ps
T1275	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.3142565131	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	23643228 ps
T1276	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3243802755	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	12624683 ps
T1277	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1932908309	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	38167198 ps
T1278	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2862517080	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	17142469 ps
T1279	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2476113189	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	84635198 ps
T1280	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.434993108	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:58 AM UTC 24	146027791 ps
T272	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1561848334	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:59 AM UTC 24	325837285 ps
T1281	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.4213400811	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:59 AM UTC 24	89596454 ps
T1282	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.4237136868	Sep 09 07:08:56 AM UTC 24	Sep 09 07:08:59 AM UTC 24	71342847 ps
T1283	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2212945736	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	21517557 ps
T1284	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.3539090532	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	85348651 ps
T1285	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2348668785	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	61212829 ps
T1286	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.830364106	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	125388418 ps
T1287	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1017583453	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	44085244 ps
T1288	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.504134160	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	20614217 ps
T1289	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1683901508	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	37561105 ps
T1290	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3618977915	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	30149088 ps
T66	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.3793157600	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	40080131 ps
T1291	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2830696942	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	12894954 ps
T1292	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1574609620	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	45471525 ps
T1293	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.3021344075	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	15113021 ps
T1294	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.665616614	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	12694291 ps
T1295	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2788259007	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	11710022 ps
T1296	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.3028956686	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	17370360 ps
T1297	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.94470921	Sep 09 07:09:01 AM UTC 24	Sep 09 07:09:02 AM UTC 24	44886074 ps
T1298	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.4152748338	Sep 09 07:09:01 AM UTC 24	Sep 09 07:09:02 AM UTC 24	15647155 ps
T1299	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.750858428	Sep 09 07:09:01 AM UTC 24	Sep 09 07:09:02 AM UTC 24	33340758 ps
T273	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.1020093983	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:02 AM UTC 24	576580003 ps
T1300	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.3459428313	Sep 09 07:09:01 AM UTC 24	Sep 09 07:09:02 AM UTC 24	16537440 ps
T1301	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2987552932	Sep 09 07:09:00 AM UTC 24	Sep 09 07:09:03 AM UTC 24	257056298 ps
T1302	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.740681263	Sep 09 07:09:05 AM UTC 24	Sep 09 07:09:07 AM UTC 24	14035486 ps
T1303	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3979434662	Sep 09 07:09:05 AM UTC 24	Sep 09 07:09:07 AM UTC 24	13379540 ps
T1304	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.758225888	Sep 09 07:09:05 AM UTC 24	Sep 09 07:09:07 AM UTC 24	33890506 ps
T1305	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.1628955073	Sep 09 07:09:05 AM UTC 24	Sep 09 07:09:07 AM UTC 24	12374845 ps
T1306	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.1085298097	Sep 09 07:09:05 AM UTC 24	Sep 09 07:09:07 AM UTC 24	67294805 ps
T1307	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3357269681	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:07 AM UTC 24	99428708 ps
T1308	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.1033536714	Sep 09 07:09:05 AM UTC 24	Sep 09 07:09:07 AM UTC 24	11514516 ps
T1309	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.859284791	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:07 AM UTC 24	15533383 ps
T1310	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1801782273	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:07 AM UTC 24	27510064 ps
T1311	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.2227006805	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:07 AM UTC 24	43568386 ps
T1312	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.489826335	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:07 AM UTC 24	15134116 ps
T1313	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.3436840599	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:07 AM UTC 24	41256442 ps
T1314	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.617505784	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:07 AM UTC 24	35714118 ps
T1315	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1531664559	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:07 AM UTC 24	38927353 ps
T1316	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1798086839	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:07 AM UTC 24	49130835 ps
T1317	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.518227496	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:08 AM UTC 24	43887920 ps
T1318	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.1608928928	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:08 AM UTC 24	12597145 ps
T1319	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3225008988	Sep 09 07:09:06 AM UTC 24	Sep 09 07:09:08 AM UTC 24	50609607 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_fifo_full.4046797648
Short name	T5
Test name
Test status
Simulation time	54469519418 ps
CPU time	28 seconds
Started	Sep 09 06:28:24 AM UTC 24
Finished	Sep 09 06:28:53 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046797648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.4046797648
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_stress_all.2046582427
Short name	T144
Test name
Test status
Simulation time	342957706213 ps
CPU time	378.77 seconds
Started	Sep 09 06:31:41 AM UTC 24
Finished	Sep 09 06:38:05 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046582427 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2046582427
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.1501168067
Short name	T12
Test name
Test status
Simulation time	2426768136 ps
CPU time	27.5 seconds
Started	Sep 09 06:29:01 AM UTC 24
Finished	Sep 09 06:29:30 AM UTC 24
Peak memory	217532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1501168067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_ with_rand_reset.1501168067
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_stress_all.1324034371
Short name	T122
Test name
Test status
Simulation time	79677226367 ps
CPU time	118.25 seconds
Started	Sep 09 06:29:03 AM UTC 24
Finished	Sep 09 06:31:03 AM UTC 24
Peak memory	208840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324034371 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1324034371
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_stress_all.1085394641
Short name	T125
Test name
Test status
Simulation time	237423092530 ps
CPU time	559.76 seconds
Started	Sep 09 06:29:36 AM UTC 24
Finished	Sep 09 06:39:02 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085394641 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1085394641
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_stress_all.498698617
Short name	T285
Test name
Test status
Simulation time	603265450259 ps
CPU time	213.18 seconds
Started	Sep 09 06:31:00 AM UTC 24
Finished	Sep 09 06:34:36 AM UTC 24
Peak memory	217528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498698617 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.498698617
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_intr.1963974184
Short name	T106
Test name
Test status
Simulation time	84451749247 ps
CPU time	37.18 seconds
Started	Sep 09 06:37:11 AM UTC 24
Finished	Sep 09 06:37:49 AM UTC 24
Peak memory	208628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963974184 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1963974184
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_stress_all.3246905498
Short name	T280
Test name
Test status
Simulation time	161344964274 ps
CPU time	148.9 seconds
Started	Sep 09 06:34:56 AM UTC 24
Finished	Sep 09 06:37:27 AM UTC 24
Peak memory	219776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246905498 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3246905498
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.677491793
Short name	T343
Test name
Test status
Simulation time	80153686097 ps
CPU time	613.62 seconds
Started	Sep 09 06:30:01 AM UTC 24
Finished	Sep 09 06:40:22 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677491793 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.677491793
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_sec_cm.4170983116
Short name	T10
Test name
Test status
Simulation time	58610000 ps
CPU time	1.3 seconds
Started	Sep 09 06:29:06 AM UTC 24
Finished	Sep 09 06:29:08 AM UTC 24
Peak memory	240132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170983116 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.4170983116
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_intr.433199497
Short name	T13
Test name
Test status
Simulation time	39224243103 ps
CPU time	25.34 seconds
Started	Sep 09 06:29:12 AM UTC 24
Finished	Sep 09 06:29:39 AM UTC 24
Peak memory	208712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433199497 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.433199497
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_stress_all.1920672843
Short name	T155
Test name
Test status
Simulation time	588690496817 ps
CPU time	925.88 seconds
Started	Sep 09 06:30:04 AM UTC 24
Finished	Sep 09 06:45:40 AM UTC 24
Peak memory	221180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920672843 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1920672843
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_fifo_reset.3394996887
Short name	T118
Test name
Test status
Simulation time	319541540268 ps
CPU time	87.02 seconds
Started	Sep 09 06:29:10 AM UTC 24
Finished	Sep 09 06:30:39 AM UTC 24
Peak memory	208876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394996887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3394996887
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.4145722899
Short name	T39
Test name
Test status
Simulation time	2127230532 ps
CPU time	27 seconds
Started	Sep 09 06:33:38 AM UTC 24
Finished	Sep 09 06:34:06 AM UTC 24
Peak memory	221824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4145722899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_ with_rand_reset.4145722899
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_stress_all.666632731
Short name	T310
Test name
Test status
Simulation time	693381520744 ps
CPU time	453.78 seconds
Started	Sep 09 06:33:40 AM UTC 24
Finished	Sep 09 06:41:19 AM UTC 24
Peak memory	219736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666632731 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.666632731
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.1144925616
Short name	T55
Test name
Test status
Simulation time	17683526 ps
CPU time	1.14 seconds
Started	Sep 09 07:08:33 AM UTC 24
Finished	Sep 09 07:08:35 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144925616 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.1144925616
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_fifo_reset.1575194958
Short name	T128
Test name
Test status
Simulation time	144017489414 ps
CPU time	130.42 seconds
Started	Sep 09 06:31:07 AM UTC 24
Finished	Sep 09 06:33:20 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575194958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1575194958
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3259408862
Short name	T30
Test name
Test status
Simulation time	33268243585 ps
CPU time	36.96 seconds
Started	Sep 09 06:30:03 AM UTC 24
Finished	Sep 09 06:30:41 AM UTC 24
Peak memory	217720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3259408862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_ with_rand_reset.3259408862
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.333178354
Short name	T99
Test name
Test status
Simulation time	154638551325 ps
CPU time	86.7 seconds
Started	Sep 09 06:31:06 AM UTC 24
Finished	Sep 09 06:32:35 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333178354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.333178354
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_stress_all.716034345
Short name	T199
Test name
Test status
Simulation time	134555994047 ps
CPU time	629.03 seconds
Started	Sep 09 06:32:36 AM UTC 24
Finished	Sep 09 06:43:12 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716034345 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.716034345
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.1045517508
Short name	T352
Test name
Test status
Simulation time	133733684284 ps
CPU time	979.9 seconds
Started	Sep 09 06:31:36 AM UTC 24
Finished	Sep 09 06:48:07 AM UTC 24
Peak memory	212220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045517508 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1045517508
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_fifo_full.3761443553
Short name	T29
Test name
Test status
Simulation time	40991566931 ps
CPU time	28.63 seconds
Started	Sep 09 06:29:09 AM UTC 24
Finished	Sep 09 06:29:39 AM UTC 24
Peak memory	208780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761443553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3761443553
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1714339415
Short name	T80
Test name
Test status
Simulation time	145124732 ps
CPU time	2.1 seconds
Started	Sep 09 07:08:34 AM UTC 24
Finished	Sep 09 07:08:37 AM UTC 24
Peak memory	202752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714339415 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1714339415
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.2074190929
Short name	T46
Test name
Test status
Simulation time	74280632339 ps
CPU time	42.22 seconds
Started	Sep 09 06:29:51 AM UTC 24
Finished	Sep 09 06:30:34 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074190929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2074190929
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_alert_test.4169518447
Short name	T32
Test name
Test status
Simulation time	14212022 ps
CPU time	0.81 seconds
Started	Sep 09 06:29:07 AM UTC 24
Finished	Sep 09 06:29:09 AM UTC 24
Peak memory	204380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169518447 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.4169518447
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_stress_all.2965419480
Short name	T153
Test name
Test status
Simulation time	518645961001 ps
CPU time	394.74 seconds
Started	Sep 09 06:42:22 AM UTC 24
Finished	Sep 09 06:49:02 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965419480 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2965419480
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_noise_filter.1100480803
Short name	T295
Test name
Test status
Simulation time	96967900876 ps
CPU time	189.44 seconds
Started	Sep 09 06:33:10 AM UTC 24
Finished	Sep 09 06:36:22 AM UTC 24
Peak memory	208840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100480803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1100480803
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.3425254206
Short name	T276
Test name
Test status
Simulation time	89934692632 ps
CPU time	81.84 seconds
Started	Sep 09 06:35:18 AM UTC 24
Finished	Sep 09 06:36:42 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425254206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3425254206
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2599555240
Short name	T136
Test name
Test status
Simulation time	36544455049 ps
CPU time	125.31 seconds
Started	Sep 09 06:35:55 AM UTC 24
Finished	Sep 09 06:38:03 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599555240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2599555240
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_stress_all.1014839286
Short name	T112
Test name
Test status
Simulation time	111175265417 ps
CPU time	114.52 seconds
Started	Sep 09 06:39:58 AM UTC 24
Finished	Sep 09 06:41:54 AM UTC 24
Peak memory	208920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014839286 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1014839286
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.3424812437
Short name	T14
Test name
Test status
Simulation time	91785852641 ps
CPU time	41.26 seconds
Started	Sep 09 06:29:09 AM UTC 24
Finished	Sep 09 06:29:52 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424812437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3424812437
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.593539781
Short name	T42
Test name
Test status
Simulation time	14964566581 ps
CPU time	74.48 seconds
Started	Sep 09 06:35:48 AM UTC 24
Finished	Sep 09 06:37:04 AM UTC 24
Peak memory	219968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=593539781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_w ith_rand_reset.593539781
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.1915016437
Short name	T67
Test name
Test status
Simulation time	141678248 ps
CPU time	0.9 seconds
Started	Sep 09 07:08:27 AM UTC 24
Finished	Sep 09 07:08:29 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915016437 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.1915016437
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_stress_all.4101487754
Short name	T149
Test name
Test status
Simulation time	109898181449 ps
CPU time	492.32 seconds
Started	Sep 09 06:37:51 AM UTC 24
Finished	Sep 09 06:46:09 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101487754 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.4101487754
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.1962822556
Short name	T131
Test name
Test status
Simulation time	153927194284 ps
CPU time	175.89 seconds
Started	Sep 09 06:32:20 AM UTC 24
Finished	Sep 09 06:35:19 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962822556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1962822556
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2024612065
Short name	T4
Test name
Test status
Simulation time	13503255608 ps
CPU time	23 seconds
Started	Sep 09 06:28:28 AM UTC 24
Finished	Sep 09 06:28:52 AM UTC 24
Peak memory	208420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024612065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2024612065
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_stress_all.1363333920
Short name	T109
Test name
Test status
Simulation time	361101141568 ps
CPU time	382.33 seconds
Started	Sep 09 06:39:18 AM UTC 24
Finished	Sep 09 06:45:45 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363333920 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1363333920
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_fifo_full.1329150761
Short name	T179
Test name
Test status
Simulation time	251429336363 ps
CPU time	81.94 seconds
Started	Sep 09 06:42:01 AM UTC 24
Finished	Sep 09 06:43:25 AM UTC 24
Peak memory	208872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329150761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1329150761
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_fifo_reset.2653272845
Short name	T135
Test name
Test status
Simulation time	37141129384 ps
CPU time	127.95 seconds
Started	Sep 09 06:35:57 AM UTC 24
Finished	Sep 09 06:38:08 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653272845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2653272845
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.465310815
Short name	T133
Test name
Test status
Simulation time	43253131326 ps
CPU time	30.39 seconds
Started	Sep 09 06:39:08 AM UTC 24
Finished	Sep 09 06:39:40 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465310815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.465310815
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.3139691025
Short name	T115
Test name
Test status
Simulation time	6887579788 ps
CPU time	51.63 seconds
Started	Sep 09 06:41:28 AM UTC 24
Finished	Sep 09 06:42:21 AM UTC 24
Peak memory	217588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3139691025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all _with_rand_reset.3139691025
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/87.uart_fifo_reset.970372563
Short name	T177
Test name
Test status
Simulation time	78411378650 ps
CPU time	51.32 seconds
Started	Sep 09 07:02:42 AM UTC 24
Finished	Sep 09 07:03:35 AM UTC 24
Peak memory	208632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970372563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.970372563
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/87.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1664256498
Short name	T84
Test name
Test status
Simulation time	197545306 ps
CPU time	0.85 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	201752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664256498 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1664256498
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_fifo_full.862612256
Short name	T151
Test name
Test status
Simulation time	328745657329 ps
CPU time	37.83 seconds
Started	Sep 09 06:35:55 AM UTC 24
Finished	Sep 09 06:36:35 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862612256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.862612256
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.3386100238
Short name	T142
Test name
Test status
Simulation time	30551626212 ps
CPU time	51.87 seconds
Started	Sep 09 06:40:04 AM UTC 24
Finished	Sep 09 06:40:57 AM UTC 24
Peak memory	208744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386100238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.3386100238
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.454443134
Short name	T171
Test name
Test status
Simulation time	18174871740 ps
CPU time	56.17 seconds
Started	Sep 09 06:52:18 AM UTC 24
Finished	Sep 09 06:53:15 AM UTC 24
Peak memory	208856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454443134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.454443134
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_noise_filter.3566003602
Short name	T300
Test name
Test status
Simulation time	162891267223 ps
CPU time	428.94 seconds
Started	Sep 09 06:34:39 AM UTC 24
Finished	Sep 09 06:41:53 AM UTC 24
Peak memory	217588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566003602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3566003602
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.4096008648
Short name	T11
Test name
Test status
Simulation time	25919982150 ps
CPU time	55.56 seconds
Started	Sep 09 06:28:24 AM UTC 24
Finished	Sep 09 06:29:21 AM UTC 24
Peak memory	208900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096008648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.4096008648
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_fifo_reset.1347557991
Short name	T185
Test name
Test status
Simulation time	64800904115 ps
CPU time	90.55 seconds
Started	Sep 09 06:42:03 AM UTC 24
Finished	Sep 09 06:43:35 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347557991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1347557991
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_fifo_reset.3921901417
Short name	T188
Test name
Test status
Simulation time	196952707306 ps
CPU time	215.28 seconds
Started	Sep 09 06:54:57 AM UTC 24
Finished	Sep 09 06:58:35 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921901417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3921901417
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/115.uart_fifo_reset.28176609
Short name	T218
Test name
Test status
Simulation time	9575580699 ps
CPU time	13.98 seconds
Started	Sep 09 07:03:46 AM UTC 24
Finished	Sep 09 07:04:01 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28176609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.28176609
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/115.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/119.uart_fifo_reset.2636203850
Short name	T223
Test name
Test status
Simulation time	107632186060 ps
CPU time	62.47 seconds
Started	Sep 09 07:03:52 AM UTC 24
Finished	Sep 09 07:04:56 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636203850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2636203850
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/119.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/165.uart_fifo_reset.785331649
Short name	T226
Test name
Test status
Simulation time	128109160870 ps
CPU time	55.76 seconds
Started	Sep 09 07:04:53 AM UTC 24
Finished	Sep 09 07:05:50 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785331649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.785331649
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/165.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.402959416
Short name	T490
Test name
Test status
Simulation time	20374008564 ps
CPU time	53.81 seconds
Started	Sep 09 06:42:21 AM UTC 24
Finished	Sep 09 06:43:16 AM UTC 24
Peak memory	221820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=402959416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all_ with_rand_reset.402959416
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_noise_filter.3486874809
Short name	T278
Test name
Test status
Simulation time	23338933784 ps
CPU time	56.32 seconds
Started	Sep 09 06:29:47 AM UTC 24
Finished	Sep 09 06:30:44 AM UTC 24
Peak memory	217628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486874809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3486874809
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_fifo_reset.3521272727
Short name	T960
Test name
Test status
Simulation time	98842658499 ps
CPU time	185.53 seconds
Started	Sep 09 06:59:27 AM UTC 24
Finished	Sep 09 07:02:35 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521272727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3521272727
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_fifo_reset.2644570134
Short name	T130
Test name
Test status
Simulation time	57936406928 ps
CPU time	52.52 seconds
Started	Sep 09 06:32:05 AM UTC 24
Finished	Sep 09 06:32:59 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644570134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.2644570134
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.884023532
Short name	T312
Test name
Test status
Simulation time	185169049026 ps
CPU time	211.07 seconds
Started	Sep 09 06:29:28 AM UTC 24
Finished	Sep 09 06:33:02 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884023532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.884023532
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_tx_rx.2770725369
Short name	T296
Test name
Test status
Simulation time	80967518541 ps
CPU time	93.68 seconds
Started	Sep 09 06:36:53 AM UTC 24
Finished	Sep 09 06:38:29 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770725369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2770725369
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_fifo_reset.637842672
Short name	T195
Test name
Test status
Simulation time	53152263794 ps
CPU time	75.84 seconds
Started	Sep 09 06:38:04 AM UTC 24
Finished	Sep 09 06:39:22 AM UTC 24
Peak memory	208724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637842672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.637842672
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/158.uart_fifo_reset.1245134757
Short name	T206
Test name
Test status
Simulation time	22976418332 ps
CPU time	43.47 seconds
Started	Sep 09 07:04:48 AM UTC 24
Finished	Sep 09 07:05:33 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245134757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1245134757
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/158.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/233.uart_fifo_reset.3577871097
Short name	T216
Test name
Test status
Simulation time	30098039534 ps
CPU time	81.93 seconds
Started	Sep 09 07:06:19 AM UTC 24
Finished	Sep 09 07:07:42 AM UTC 24
Peak memory	208900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577871097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.3577871097
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/233.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/285.uart_fifo_reset.3583474494
Short name	T248
Test name
Test status
Simulation time	149492714431 ps
CPU time	52.52 seconds
Started	Sep 09 07:07:48 AM UTC 24
Finished	Sep 09 07:08:42 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583474494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.3583474494
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/285.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_tx_rx.1817439763
Short name	T309
Test name
Test status
Simulation time	74375680601 ps
CPU time	45.56 seconds
Started	Sep 09 06:35:05 AM UTC 24
Finished	Sep 09 06:35:52 AM UTC 24
Peak memory	208732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817439763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1817439763
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1561848334
Short name	T272
Test name
Test status
Simulation time	325837285 ps
CPU time	1.38 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:59 AM UTC 24
Peak memory	201708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561848334 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1561848334
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.154966449
Short name	T8
Test name
Test status
Simulation time	4883044619 ps
CPU time	17.47 seconds
Started	Sep 09 06:28:46 AM UTC 24
Finished	Sep 09 06:29:05 AM UTC 24
Peak memory	205100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154966449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.154966449
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.2618147818
Short name	T324
Test name
Test status
Simulation time	12210699468 ps
CPU time	32.12 seconds
Started	Sep 09 06:36:19 AM UTC 24
Finished	Sep 09 06:36:52 AM UTC 24
Peak memory	208724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618147818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2618147818
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/103.uart_fifo_reset.732595481
Short name	T1090
Test name
Test status
Simulation time	76661544268 ps
CPU time	179.25 seconds
Started	Sep 09 07:03:26 AM UTC 24
Finished	Sep 09 07:06:28 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732595481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.732595481
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/103.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.4040886199
Short name	T88
Test name
Test status
Simulation time	5263509575 ps
CPU time	32.15 seconds
Started	Sep 09 06:37:45 AM UTC 24
Finished	Sep 09 06:38:18 AM UTC 24
Peak memory	217744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4040886199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all _with_rand_reset.4040886199
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/113.uart_fifo_reset.2198759403
Short name	T211
Test name
Test status
Simulation time	61446423323 ps
CPU time	54.44 seconds
Started	Sep 09 07:03:45 AM UTC 24
Finished	Sep 09 07:04:41 AM UTC 24
Peak memory	208752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198759403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2198759403
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/113.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/116.uart_fifo_reset.2337144240
Short name	T263
Test name
Test status
Simulation time	29316130499 ps
CPU time	25.04 seconds
Started	Sep 09 07:03:49 AM UTC 24
Finished	Sep 09 07:04:15 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337144240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2337144240
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/116.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/117.uart_fifo_reset.3422138599
Short name	T1024
Test name
Test status
Simulation time	30616107847 ps
CPU time	55.46 seconds
Started	Sep 09 07:03:49 AM UTC 24
Finished	Sep 09 07:04:46 AM UTC 24
Peak memory	208484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422138599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3422138599
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/117.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/120.uart_fifo_reset.2578939718
Short name	T240
Test name
Test status
Simulation time	64706602588 ps
CPU time	31.9 seconds
Started	Sep 09 07:03:55 AM UTC 24
Finished	Sep 09 07:04:28 AM UTC 24
Peak memory	208740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578939718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2578939718
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/120.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/130.uart_fifo_reset.3128658330
Short name	T261
Test name
Test status
Simulation time	137481486616 ps
CPU time	55.16 seconds
Started	Sep 09 07:04:04 AM UTC 24
Finished	Sep 09 07:05:01 AM UTC 24
Peak memory	208680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128658330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3128658330
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/130.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/133.uart_fifo_reset.3199416613
Short name	T238
Test name
Test status
Simulation time	71413822516 ps
CPU time	22.63 seconds
Started	Sep 09 07:04:10 AM UTC 24
Finished	Sep 09 07:04:34 AM UTC 24
Peak memory	208916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199416613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3199416613
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/133.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/136.uart_fifo_reset.3570843478
Short name	T1029
Test name
Test status
Simulation time	14299523086 ps
CPU time	32.2 seconds
Started	Sep 09 07:04:17 AM UTC 24
Finished	Sep 09 07:04:51 AM UTC 24
Peak memory	208716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570843478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3570843478
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/136.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.196487889
Short name	T606
Test name
Test status
Simulation time	182840177274 ps
CPU time	608.94 seconds
Started	Sep 09 06:39:50 AM UTC 24
Finished	Sep 09 06:50:07 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196487889 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.196487889
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/141.uart_fifo_reset.2970442602
Short name	T267
Test name
Test status
Simulation time	133286265228 ps
CPU time	193.06 seconds
Started	Sep 09 07:04:28 AM UTC 24
Finished	Sep 09 07:07:44 AM UTC 24
Peak memory	208920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970442602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2970442602
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/141.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/142.uart_fifo_reset.1508114098
Short name	T1045
Test name
Test status
Simulation time	17742416959 ps
CPU time	38.44 seconds
Started	Sep 09 07:04:29 AM UTC 24
Finished	Sep 09 07:05:09 AM UTC 24
Peak memory	208680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508114098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1508114098
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/142.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/143.uart_fifo_reset.1649967389
Short name	T244
Test name
Test status
Simulation time	38711726013 ps
CPU time	35.52 seconds
Started	Sep 09 07:04:29 AM UTC 24
Finished	Sep 09 07:05:06 AM UTC 24
Peak memory	208608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649967389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1649967389
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/143.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/150.uart_fifo_reset.1615457787
Short name	T246
Test name
Test status
Simulation time	36939759921 ps
CPU time	113.83 seconds
Started	Sep 09 07:04:40 AM UTC 24
Finished	Sep 09 07:06:36 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615457787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1615457787
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/150.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_fifo_full.2119271398
Short name	T152
Test name
Test status
Simulation time	443760088019 ps
CPU time	88.03 seconds
Started	Sep 09 06:40:50 AM UTC 24
Finished	Sep 09 06:42:20 AM UTC 24
Peak memory	208956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119271398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2119271398
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/178.uart_fifo_reset.1073829270
Short name	T252
Test name
Test status
Simulation time	62384017459 ps
CPU time	58.84 seconds
Started	Sep 09 07:05:04 AM UTC 24
Finished	Sep 09 07:06:04 AM UTC 24
Peak memory	208592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073829270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1073829270
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/178.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1675768646
Short name	T254
Test name
Test status
Simulation time	93921550061 ps
CPU time	94.88 seconds
Started	Sep 09 07:05:09 AM UTC 24
Finished	Sep 09 07:06:47 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675768646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1675768646
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/183.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2225205135
Short name	T256
Test name
Test status
Simulation time	13010738567 ps
CPU time	31.13 seconds
Started	Sep 09 07:05:43 AM UTC 24
Finished	Sep 09 07:06:15 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225205135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2225205135
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/208.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_intr.1304238591
Short name	T394
Test name
Test status
Simulation time	40996326077 ps
CPU time	18.95 seconds
Started	Sep 09 06:44:19 AM UTC 24
Finished	Sep 09 06:44:39 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304238591 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1304238591
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/223.uart_fifo_reset.2593363105
Short name	T257
Test name
Test status
Simulation time	78909295770 ps
CPU time	41.34 seconds
Started	Sep 09 07:06:01 AM UTC 24
Finished	Sep 09 07:06:44 AM UTC 24
Peak memory	208776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593363105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2593363105
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/223.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/227.uart_fifo_reset.375273891
Short name	T260
Test name
Test status
Simulation time	87646112384 ps
CPU time	60.07 seconds
Started	Sep 09 07:06:06 AM UTC 24
Finished	Sep 09 07:07:08 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375273891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.375273891
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/227.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/231.uart_fifo_reset.241348080
Short name	T225
Test name
Test status
Simulation time	89543826490 ps
CPU time	157.05 seconds
Started	Sep 09 07:06:16 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241348080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.241348080
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/231.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3972191783
Short name	T249
Test name
Test status
Simulation time	81480530380 ps
CPU time	64.84 seconds
Started	Sep 09 07:06:48 AM UTC 24
Finished	Sep 09 07:07:55 AM UTC 24
Peak memory	208532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972191783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3972191783
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/245.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/254.uart_fifo_reset.3243386666
Short name	T236
Test name
Test status
Simulation time	219856295387 ps
CPU time	63.19 seconds
Started	Sep 09 07:06:59 AM UTC 24
Finished	Sep 09 07:08:04 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243386666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3243386666
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/254.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/261.uart_fifo_reset.3667415526
Short name	T243
Test name
Test status
Simulation time	11979513477 ps
CPU time	23.16 seconds
Started	Sep 09 07:07:09 AM UTC 24
Finished	Sep 09 07:07:33 AM UTC 24
Peak memory	208588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667415526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3667415526
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/261.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/268.uart_fifo_reset.1830145400
Short name	T219
Test name
Test status
Simulation time	37746489059 ps
CPU time	99.69 seconds
Started	Sep 09 07:07:18 AM UTC 24
Finished	Sep 09 07:09:00 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830145400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1830145400
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/268.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/278.uart_fifo_reset.413387833
Short name	T242
Test name
Test status
Simulation time	96247184317 ps
CPU time	51.07 seconds
Started	Sep 09 07:07:38 AM UTC 24
Finished	Sep 09 07:08:31 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413387833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.413387833
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/278.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/294.uart_fifo_reset.998549447
Short name	T266
Test name
Test status
Simulation time	60363426104 ps
CPU time	43.74 seconds
Started	Sep 09 07:08:02 AM UTC 24
Finished	Sep 09 07:08:47 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998549447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.998549447
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/294.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_fifo_reset.1920990018
Short name	T156
Test name
Test status
Simulation time	75752766927 ps
CPU time	161.48 seconds
Started	Sep 09 06:50:21 AM UTC 24
Finished	Sep 09 06:53:06 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920990018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1920990018
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.2903826293
Short name	T259
Test name
Test status
Simulation time	19669296741 ps
CPU time	65.13 seconds
Started	Sep 09 07:02:52 AM UTC 24
Finished	Sep 09 07:03:59 AM UTC 24
Peak memory	217656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2903826293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all _with_rand_reset.2903826293
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.93154521
Short name	T1193
Test name
Test status
Simulation time	33544888 ps
CPU time	1.13 seconds
Started	Sep 09 07:08:27 AM UTC 24
Finished	Sep 09 07:08:30 AM UTC 24
Peak memory	201752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93154521 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08 /uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.93154521
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.3029168079
Short name	T63
Test name
Test status
Simulation time	3139112230 ps
CPU time	3.68 seconds
Started	Sep 09 07:08:26 AM UTC 24
Finished	Sep 09 07:08:31 AM UTC 24
Peak memory	202820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029168079 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3029168079
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.2749718969
Short name	T53
Test name
Test status
Simulation time	28656889 ps
CPU time	0.89 seconds
Started	Sep 09 07:08:24 AM UTC 24
Finished	Sep 09 07:08:26 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749718969 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2749718969
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2259608804
Short name	T1194
Test name
Test status
Simulation time	20295051 ps
CPU time	1.32 seconds
Started	Sep 09 07:08:28 AM UTC 24
Finished	Sep 09 07:08:31 AM UTC 24
Peak memory	201696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2259608804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r eset.2259608804
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1432394736
Short name	T1192
Test name
Test status
Simulation time	13805036 ps
CPU time	0.86 seconds
Started	Sep 09 07:08:26 AM UTC 24
Finished	Sep 09 07:08:28 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432394736 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1432394736
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2943955159
Short name	T1190
Test name
Test status
Simulation time	43676145 ps
CPU time	0.85 seconds
Started	Sep 09 07:08:23 AM UTC 24
Finished	Sep 09 07:08:25 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943955159 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2943955159
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.3004956540
Short name	T1191
Test name
Test status
Simulation time	197957966 ps
CPU time	3.31 seconds
Started	Sep 09 07:08:22 AM UTC 24
Finished	Sep 09 07:08:26 AM UTC 24
Peak memory	204664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004956540 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3004956540
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.2127258498
Short name	T77
Test name
Test status
Simulation time	99379964 ps
CPU time	1.99 seconds
Started	Sep 09 07:08:22 AM UTC 24
Finished	Sep 09 07:08:25 AM UTC 24
Peak memory	202164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127258498 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2127258498
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.2761691727
Short name	T54
Test name
Test status
Simulation time	23210299 ps
CPU time	0.92 seconds
Started	Sep 09 07:08:31 AM UTC 24
Finished	Sep 09 07:08:33 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761691727 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2761691727
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.3955158847
Short name	T64
Test name
Test status
Simulation time	131266329 ps
CPU time	2.02 seconds
Started	Sep 09 07:08:30 AM UTC 24
Finished	Sep 09 07:08:33 AM UTC 24
Peak memory	202696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955158847 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3955158847
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3409182017
Short name	T1197
Test name
Test status
Simulation time	28588524 ps
CPU time	0.88 seconds
Started	Sep 09 07:08:30 AM UTC 24
Finished	Sep 09 07:08:32 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409182017 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3409182017
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1011746060
Short name	T1199
Test name
Test status
Simulation time	332303217 ps
CPU time	1.07 seconds
Started	Sep 09 07:08:32 AM UTC 24
Finished	Sep 09 07:08:35 AM UTC 24
Peak memory	201696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1011746060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r eset.1011746060
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.2575919340
Short name	T68
Test name
Test status
Simulation time	34674292 ps
CPU time	0.88 seconds
Started	Sep 09 07:08:30 AM UTC 24
Finished	Sep 09 07:08:32 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575919340 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2575919340
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.55940754
Short name	T1196
Test name
Test status
Simulation time	15129193 ps
CPU time	0.77 seconds
Started	Sep 09 07:08:30 AM UTC 24
Finished	Sep 09 07:08:31 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55940754 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.55940754
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.4034081630
Short name	T69
Test name
Test status
Simulation time	49740788 ps
CPU time	0.93 seconds
Started	Sep 09 07:08:31 AM UTC 24
Finished	Sep 09 07:08:33 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034081630 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.4034081630
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.3107075640
Short name	T1195
Test name
Test status
Simulation time	70745560 ps
CPU time	1.42 seconds
Started	Sep 09 07:08:29 AM UTC 24
Finished	Sep 09 07:08:31 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107075640 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.3107075640
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3911796059
Short name	T78
Test name
Test status
Simulation time	52323360 ps
CPU time	1.46 seconds
Started	Sep 09 07:08:29 AM UTC 24
Finished	Sep 09 07:08:31 AM UTC 24
Peak memory	201648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911796059 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3911796059
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3593327975
Short name	T1242
Test name
Test status
Simulation time	146376459 ps
CPU time	0.94 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	201632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3593327975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_ reset.3593327975
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1528668996
Short name	T1238
Test name
Test status
Simulation time	22826599 ps
CPU time	0.89 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528668996 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1528668996
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1974541932
Short name	T1237
Test name
Test status
Simulation time	16309658 ps
CPU time	0.75 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974541932 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1974541932
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2849556892
Short name	T1243
Test name
Test status
Simulation time	54712436 ps
CPU time	1 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	201820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849556892 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.2849556892
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1080673179
Short name	T1245
Test name
Test status
Simulation time	109829541 ps
CPU time	1.71 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:50 AM UTC 24
Peak memory	201644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080673179 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1080673179
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2016955577
Short name	T83
Test name
Test status
Simulation time	152326681 ps
CPU time	1.29 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	201748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016955577 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2016955577
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3454532882
Short name	T1251
Test name
Test status
Simulation time	178353207 ps
CPU time	1.31 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:51 AM UTC 24
Peak memory	201632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3454532882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_ reset.3454532882
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.1834042292
Short name	T1239
Test name
Test status
Simulation time	73296435 ps
CPU time	0.75 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834042292 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1834042292
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.2043581768
Short name	T1241
Test name
Test status
Simulation time	15795465 ps
CPU time	0.82 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043581768 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2043581768
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.2922903756
Short name	T1240
Test name
Test status
Simulation time	37557526 ps
CPU time	0.73 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	203740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922903756 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.2922903756
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3582126610
Short name	T1244
Test name
Test status
Simulation time	26026198 ps
CPU time	1.35 seconds
Started	Sep 09 07:08:47 AM UTC 24
Finished	Sep 09 07:08:49 AM UTC 24
Peak memory	201648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582126610 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3582126610
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.4138064255
Short name	T1250
Test name
Test status
Simulation time	32693718 ps
CPU time	1.08 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:51 AM UTC 24
Peak memory	201632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=4138064255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_ reset.4138064255
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.4115240246
Short name	T1247
Test name
Test status
Simulation time	122795551 ps
CPU time	0.87 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:51 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115240246 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4115240246
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.3781332771
Short name	T1248
Test name
Test status
Simulation time	33123673 ps
CPU time	0.82 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:51 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781332771 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3781332771
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.894512705
Short name	T1249
Test name
Test status
Simulation time	51472900 ps
CPU time	0.84 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:51 AM UTC 24
Peak memory	205728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894512705 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.894512705
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.3499998260
Short name	T1254
Test name
Test status
Simulation time	436060559 ps
CPU time	2.24 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:52 AM UTC 24
Peak memory	204740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499998260 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3499998260
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.861140867
Short name	T1253
Test name
Test status
Simulation time	89896844 ps
CPU time	1.73 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:52 AM UTC 24
Peak memory	201648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861140867 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.861140867
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2082979322
Short name	T1256
Test name
Test status
Simulation time	54193530 ps
CPU time	0.61 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:54 AM UTC 24
Peak memory	201632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2082979322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_ reset.2082979322
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.1524082151
Short name	T1257
Test name
Test status
Simulation time	29645213 ps
CPU time	0.77 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:54 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524082151 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1524082151
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.4005514734
Short name	T1246
Test name
Test status
Simulation time	14482888 ps
CPU time	0.51 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:51 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005514734 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4005514734
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2157008192
Short name	T1259
Test name
Test status
Simulation time	17194574 ps
CPU time	0.94 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157008192 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.2157008192
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.201660653
Short name	T1255
Test name
Test status
Simulation time	45897751 ps
CPU time	2.2 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:53 AM UTC 24
Peak memory	204664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201660653 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.201660653
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1828945184
Short name	T1252
Test name
Test status
Simulation time	125354540 ps
CPU time	1.33 seconds
Started	Sep 09 07:08:49 AM UTC 24
Finished	Sep 09 07:08:52 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828945184 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1828945184
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.904116337
Short name	T1266
Test name
Test status
Simulation time	31062059 ps
CPU time	1.21 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	201632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=904116337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_r eset.904116337
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3011273523
Short name	T1260
Test name
Test status
Simulation time	25075823 ps
CPU time	0.75 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011273523 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3011273523
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.2224077507
Short name	T1258
Test name
Test status
Simulation time	14153662 ps
CPU time	0.81 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:54 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224077507 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2224077507
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.1498721045
Short name	T1261
Test name
Test status
Simulation time	80464987 ps
CPU time	0.91 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	201820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498721045 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.1498721045
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.435688041
Short name	T1268
Test name
Test status
Simulation time	460623206 ps
CPU time	1.89 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:56 AM UTC 24
Peak memory	201580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435688041 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.435688041
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.2978602899
Short name	T1263
Test name
Test status
Simulation time	161610194 ps
CPU time	1.25 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	201752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978602899 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2978602899
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1557301614
Short name	T1264
Test name
Test status
Simulation time	26708201 ps
CPU time	0.81 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	201632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1557301614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_ reset.1557301614
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3147667713
Short name	T61
Test name
Test status
Simulation time	56703380 ps
CPU time	0.67 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	201372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147667713 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3147667713
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.83034010
Short name	T1262
Test name
Test status
Simulation time	38042973 ps
CPU time	0.8 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83034010 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.83034010
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.3583778461
Short name	T1265
Test name
Test status
Simulation time	40408153 ps
CPU time	0.98 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:55 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583778461 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.3583778461
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.1062279067
Short name	T1270
Test name
Test status
Simulation time	38803548 ps
CPU time	1.97 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:56 AM UTC 24
Peak memory	203356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062279067 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1062279067
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.901446683
Short name	T1267
Test name
Test status
Simulation time	378569761 ps
CPU time	1.55 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:56 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901446683 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.901446683
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.33298176
Short name	T1274
Test name
Test status
Simulation time	64732944 ps
CPU time	0.85 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=33298176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.33298176
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.4099224647
Short name	T62
Test name
Test status
Simulation time	16669467 ps
CPU time	0.74 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099224647 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.4099224647
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.874037611
Short name	T1272
Test name
Test status
Simulation time	26833295 ps
CPU time	0.75 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874037611 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.874037611
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.3142565131
Short name	T1275
Test name
Test status
Simulation time	23643228 ps
CPU time	0.82 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142565131 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.3142565131
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.918475462
Short name	T1271
Test name
Test status
Simulation time	125767649 ps
CPU time	2.91 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:57 AM UTC 24
Peak memory	202632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918475462 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.918475462
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3092218132
Short name	T1269
Test name
Test status
Simulation time	345908811 ps
CPU time	1.43 seconds
Started	Sep 09 07:08:53 AM UTC 24
Finished	Sep 09 07:08:56 AM UTC 24
Peak memory	201704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092218132 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3092218132
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2476113189
Short name	T1279
Test name
Test status
Simulation time	84635198 ps
CPU time	0.95 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2476113189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_ reset.2476113189
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3243802755
Short name	T1276
Test name
Test status
Simulation time	12624683 ps
CPU time	0.73 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243802755 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3243802755
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.2931642969
Short name	T1273
Test name
Test status
Simulation time	25049652 ps
CPU time	0.65 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931642969 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2931642969
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2862517080
Short name	T1278
Test name
Test status
Simulation time	17142469 ps
CPU time	1.03 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862517080 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.2862517080
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.4237136868
Short name	T1282
Test name
Test status
Simulation time	71342847 ps
CPU time	2.09 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:59 AM UTC 24
Peak memory	202580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237136868 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4237136868
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.434993108
Short name	T1280
Test name
Test status
Simulation time	146027791 ps
CPU time	1.12 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434993108 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.434993108
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3618977915
Short name	T1290
Test name
Test status
Simulation time	30149088 ps
CPU time	1.06 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3618977915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_ reset.3618977915
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2212945736
Short name	T1283
Test name
Test status
Simulation time	21517557 ps
CPU time	0.77 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212945736 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2212945736
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.1932908309
Short name	T1277
Test name
Test status
Simulation time	38167198 ps
CPU time	0.55 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:58 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932908309 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1932908309
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2348668785
Short name	T1285
Test name
Test status
Simulation time	61212829 ps
CPU time	0.83 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	205788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348668785 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.2348668785
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.4213400811
Short name	T1281
Test name
Test status
Simulation time	89596454 ps
CPU time	1.51 seconds
Started	Sep 09 07:08:56 AM UTC 24
Finished	Sep 09 07:08:59 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213400811 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.4213400811
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1017583453
Short name	T1287
Test name
Test status
Simulation time	44085244 ps
CPU time	0.74 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1017583453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_ reset.1017583453
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.3793157600
Short name	T66
Test name
Test status
Simulation time	40080131 ps
CPU time	0.78 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793157600 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3793157600
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.3539090532
Short name	T1284
Test name
Test status
Simulation time	85348651 ps
CPU time	0.58 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539090532 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3539090532
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.830364106
Short name	T1286
Test name
Test status
Simulation time	125388418 ps
CPU time	0.76 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	205728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830364106 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.830364106
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2987552932
Short name	T1301
Test name
Test status
Simulation time	257056298 ps
CPU time	1.97 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:03 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987552932 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2987552932
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.1020093983
Short name	T273
Test name
Test status
Simulation time	576580003 ps
CPU time	1.25 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020093983 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1020093983
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.2560851614
Short name	T65
Test name
Test status
Simulation time	70786468 ps
CPU time	2.01 seconds
Started	Sep 09 07:08:33 AM UTC 24
Finished	Sep 09 07:08:36 AM UTC 24
Peak memory	205860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560851614 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2560851614
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2771138202
Short name	T1200
Test name
Test status
Simulation time	82393790 ps
CPU time	0.87 seconds
Started	Sep 09 07:08:33 AM UTC 24
Finished	Sep 09 07:08:35 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771138202 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2771138202
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3645272967
Short name	T1202
Test name
Test status
Simulation time	41398632 ps
CPU time	1.21 seconds
Started	Sep 09 07:08:34 AM UTC 24
Finished	Sep 09 07:08:36 AM UTC 24
Peak memory	201696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3645272967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_r eset.3645272967
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.3904860960
Short name	T70
Test name
Test status
Simulation time	67108082 ps
CPU time	0.85 seconds
Started	Sep 09 07:08:33 AM UTC 24
Finished	Sep 09 07:08:35 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904860960 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3904860960
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.108051688
Short name	T1198
Test name
Test status
Simulation time	85047309 ps
CPU time	0.81 seconds
Started	Sep 09 07:08:32 AM UTC 24
Finished	Sep 09 07:08:35 AM UTC 24
Peak memory	201684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108051688 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.108051688
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.1022354414
Short name	T71
Test name
Test status
Simulation time	71235324 ps
CPU time	0.92 seconds
Started	Sep 09 07:08:33 AM UTC 24
Finished	Sep 09 07:08:35 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022354414 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.1022354414
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.1562145635
Short name	T1201
Test name
Test status
Simulation time	97413280 ps
CPU time	2.22 seconds
Started	Sep 09 07:08:32 AM UTC 24
Finished	Sep 09 07:08:36 AM UTC 24
Peak memory	202628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562145635 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1562145635
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.2826916330
Short name	T79
Test name
Test status
Simulation time	163756593 ps
CPU time	1.39 seconds
Started	Sep 09 07:08:32 AM UTC 24
Finished	Sep 09 07:08:35 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826916330 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2826916330
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.2830696942
Short name	T1291
Test name
Test status
Simulation time	12894954 ps
CPU time	0.69 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830696942 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2830696942
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.504134160
Short name	T1288
Test name
Test status
Simulation time	20614217 ps
CPU time	0.65 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504134160 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.504134160
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1574609620
Short name	T1292
Test name
Test status
Simulation time	45471525 ps
CPU time	0.73 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574609620 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1574609620
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.1683901508
Short name	T1289
Test name
Test status
Simulation time	37561105 ps
CPU time	0.69 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683901508 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.1683901508
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.665616614
Short name	T1294
Test name
Test status
Simulation time	12694291 ps
CPU time	0.65 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665616614 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.665616614
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.3028956686
Short name	T1296
Test name
Test status
Simulation time	17370360 ps
CPU time	0.73 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028956686 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3028956686
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2788259007
Short name	T1295
Test name
Test status
Simulation time	11710022 ps
CPU time	0.57 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788259007 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2788259007
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.3021344075
Short name	T1293
Test name
Test status
Simulation time	15113021 ps
CPU time	0.63 seconds
Started	Sep 09 07:09:00 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021344075 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3021344075
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.4152748338
Short name	T1298
Test name
Test status
Simulation time	15647155 ps
CPU time	0.68 seconds
Started	Sep 09 07:09:01 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152748338 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.4152748338
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.750858428
Short name	T1299
Test name
Test status
Simulation time	33340758 ps
CPU time	0.62 seconds
Started	Sep 09 07:09:01 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750858428 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.750858428
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1256223318
Short name	T1206
Test name
Test status
Simulation time	92419462 ps
CPU time	1.12 seconds
Started	Sep 09 07:08:36 AM UTC 24
Finished	Sep 09 07:08:38 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256223318 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1256223318
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2989487266
Short name	T1208
Test name
Test status
Simulation time	59351657 ps
CPU time	1.63 seconds
Started	Sep 09 07:08:35 AM UTC 24
Finished	Sep 09 07:08:38 AM UTC 24
Peak memory	201888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989487266 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2989487266
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.2557709016
Short name	T1205
Test name
Test status
Simulation time	35549673 ps
CPU time	0.86 seconds
Started	Sep 09 07:08:35 AM UTC 24
Finished	Sep 09 07:08:37 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557709016 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2557709016
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1175661922
Short name	T1207
Test name
Test status
Simulation time	68270157 ps
CPU time	1.29 seconds
Started	Sep 09 07:08:36 AM UTC 24
Finished	Sep 09 07:08:38 AM UTC 24
Peak memory	201696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1175661922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r eset.1175661922
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.1021065490
Short name	T56
Test name
Test status
Simulation time	16239904 ps
CPU time	0.87 seconds
Started	Sep 09 07:08:35 AM UTC 24
Finished	Sep 09 07:08:38 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021065490 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1021065490
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3622157343
Short name	T1204
Test name
Test status
Simulation time	22923866 ps
CPU time	0.83 seconds
Started	Sep 09 07:08:35 AM UTC 24
Finished	Sep 09 07:08:37 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622157343 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3622157343
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.3736324105
Short name	T72
Test name
Test status
Simulation time	36250460 ps
CPU time	1.17 seconds
Started	Sep 09 07:08:36 AM UTC 24
Finished	Sep 09 07:08:38 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736324105 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.3736324105
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.621004006
Short name	T1203
Test name
Test status
Simulation time	157860066 ps
CPU time	1.66 seconds
Started	Sep 09 07:08:34 AM UTC 24
Finished	Sep 09 07:08:37 AM UTC 24
Peak memory	201684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621004006 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.621004006
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.94470921
Short name	T1297
Test name
Test status
Simulation time	44886074 ps
CPU time	0.64 seconds
Started	Sep 09 07:09:01 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94470921 -assert nopostproc +UVM_TESTNAME=uart_base_te st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim -vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.94470921
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.3459428313
Short name	T1300
Test name
Test status
Simulation time	16537440 ps
CPU time	0.71 seconds
Started	Sep 09 07:09:01 AM UTC 24
Finished	Sep 09 07:09:02 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459428313 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3459428313
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.740681263
Short name	T1302
Test name
Test status
Simulation time	14035486 ps
CPU time	0.6 seconds
Started	Sep 09 07:09:05 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740681263 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.740681263
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.1628955073
Short name	T1305
Test name
Test status
Simulation time	12374845 ps
CPU time	0.66 seconds
Started	Sep 09 07:09:05 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628955073 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1628955073
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.3979434662
Short name	T1303
Test name
Test status
Simulation time	13379540 ps
CPU time	0.6 seconds
Started	Sep 09 07:09:05 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979434662 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3979434662
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.758225888
Short name	T1304
Test name
Test status
Simulation time	33890506 ps
CPU time	0.57 seconds
Started	Sep 09 07:09:05 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	200688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758225888 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.758225888
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.1033536714
Short name	T1308
Test name
Test status
Simulation time	11514516 ps
CPU time	0.68 seconds
Started	Sep 09 07:09:05 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033536714 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.1033536714
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.1085298097
Short name	T1306
Test name
Test status
Simulation time	67294805 ps
CPU time	0.54 seconds
Started	Sep 09 07:09:05 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085298097 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1085298097
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.489826335
Short name	T1312
Test name
Test status
Simulation time	15134116 ps
CPU time	0.65 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489826335 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.489826335
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3357269681
Short name	T1307
Test name
Test status
Simulation time	99428708 ps
CPU time	0.67 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357269681 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3357269681
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.2399705426
Short name	T59
Test name
Test status
Simulation time	22658885 ps
CPU time	0.95 seconds
Started	Sep 09 07:08:39 AM UTC 24
Finished	Sep 09 07:08:41 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399705426 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2399705426
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2458750975
Short name	T1218
Test name
Test status
Simulation time	1427870019 ps
CPU time	2.92 seconds
Started	Sep 09 07:08:39 AM UTC 24
Finished	Sep 09 07:08:43 AM UTC 24
Peak memory	202756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458750975 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2458750975
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3687725812
Short name	T57
Test name
Test status
Simulation time	17382530 ps
CPU time	0.9 seconds
Started	Sep 09 07:08:37 AM UTC 24
Finished	Sep 09 07:08:39 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687725812 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3687725812
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.689419821
Short name	T1211
Test name
Test status
Simulation time	180305388 ps
CPU time	0.95 seconds
Started	Sep 09 07:08:39 AM UTC 24
Finished	Sep 09 07:08:41 AM UTC 24
Peak memory	201572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=689419821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_re set.689419821
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.2841291581
Short name	T58
Test name
Test status
Simulation time	11802263 ps
CPU time	0.87 seconds
Started	Sep 09 07:08:37 AM UTC 24
Finished	Sep 09 07:08:39 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841291581 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2841291581
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2349612931
Short name	T1209
Test name
Test status
Simulation time	15125425 ps
CPU time	0.84 seconds
Started	Sep 09 07:08:37 AM UTC 24
Finished	Sep 09 07:08:39 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349612931 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2349612931
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2866812716
Short name	T73
Test name
Test status
Simulation time	15653207 ps
CPU time	0.94 seconds
Started	Sep 09 07:08:39 AM UTC 24
Finished	Sep 09 07:08:41 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866812716 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.2866812716
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.1406754643
Short name	T1210
Test name
Test status
Simulation time	424029256 ps
CPU time	2.14 seconds
Started	Sep 09 07:08:37 AM UTC 24
Finished	Sep 09 07:08:40 AM UTC 24
Peak memory	204568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406754643 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1406754643
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3283556584
Short name	T81
Test name
Test status
Simulation time	72460007 ps
CPU time	1.54 seconds
Started	Sep 09 07:08:37 AM UTC 24
Finished	Sep 09 07:08:40 AM UTC 24
Peak memory	201420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283556584 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3283556584
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1801782273
Short name	T1310
Test name
Test status
Simulation time	27510064 ps
CPU time	0.54 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801782273 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1801782273
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.859284791
Short name	T1309
Test name
Test status
Simulation time	15533383 ps
CPU time	0.59 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859284791 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.859284791
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1531664559
Short name	T1315
Test name
Test status
Simulation time	38927353 ps
CPU time	0.71 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531664559 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1531664559
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.617505784
Short name	T1314
Test name
Test status
Simulation time	35714118 ps
CPU time	0.52 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617505784 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.617505784
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.2227006805
Short name	T1311
Test name
Test status
Simulation time	43568386 ps
CPU time	0.55 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227006805 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2227006805
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1798086839
Short name	T1316
Test name
Test status
Simulation time	49130835 ps
CPU time	0.59 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798086839 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1798086839
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.3436840599
Short name	T1313
Test name
Test status
Simulation time	41256442 ps
CPU time	0.5 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436840599 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3436840599
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.1608928928
Short name	T1318
Test name
Test status
Simulation time	12597145 ps
CPU time	0.64 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:08 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608928928 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1608928928
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.518227496
Short name	T1317
Test name
Test status
Simulation time	43887920 ps
CPU time	0.6 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:08 AM UTC 24
Peak memory	201564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518227496 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.518227496
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.3225008988
Short name	T1319
Test name
Test status
Simulation time	50609607 ps
CPU time	0.58 seconds
Started	Sep 09 07:09:06 AM UTC 24
Finished	Sep 09 07:09:08 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225008988 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3225008988
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3394358908
Short name	T1215
Test name
Test status
Simulation time	91609769 ps
CPU time	0.94 seconds
Started	Sep 09 07:08:40 AM UTC 24
Finished	Sep 09 07:08:42 AM UTC 24
Peak memory	201696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=3394358908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r eset.3394358908
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2249961015
Short name	T74
Test name
Test status
Simulation time	46996819 ps
CPU time	0.86 seconds
Started	Sep 09 07:08:40 AM UTC 24
Finished	Sep 09 07:08:42 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249961015 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2249961015
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.583615205
Short name	T1212
Test name
Test status
Simulation time	36910536 ps
CPU time	0.82 seconds
Started	Sep 09 07:08:39 AM UTC 24
Finished	Sep 09 07:08:41 AM UTC 24
Peak memory	201684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583615205 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.583615205
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.3189388392
Short name	T75
Test name
Test status
Simulation time	36574599 ps
CPU time	0.95 seconds
Started	Sep 09 07:08:40 AM UTC 24
Finished	Sep 09 07:08:42 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189388392 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.3189388392
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.1895905360
Short name	T1214
Test name
Test status
Simulation time	93580084 ps
CPU time	1.75 seconds
Started	Sep 09 07:08:39 AM UTC 24
Finished	Sep 09 07:08:42 AM UTC 24
Peak memory	201644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895905360 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1895905360
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.457251020
Short name	T1213
Test name
Test status
Simulation time	152324633 ps
CPU time	1.35 seconds
Started	Sep 09 07:08:39 AM UTC 24
Finished	Sep 09 07:08:41 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457251020 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.457251020
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.2393160399
Short name	T1224
Test name
Test status
Simulation time	42086789 ps
CPU time	1.09 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:45 AM UTC 24
Peak memory	201496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2393160399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r eset.2393160399
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.582026457
Short name	T1216
Test name
Test status
Simulation time	44300434 ps
CPU time	0.73 seconds
Started	Sep 09 07:08:41 AM UTC 24
Finished	Sep 09 07:08:42 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582026457 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.582026457
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2455404782
Short name	T1217
Test name
Test status
Simulation time	13771288 ps
CPU time	0.84 seconds
Started	Sep 09 07:08:41 AM UTC 24
Finished	Sep 09 07:08:42 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455404782 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2455404782
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4271006027
Short name	T1222
Test name
Test status
Simulation time	97770712 ps
CPU time	1.02 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:45 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271006027 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.4271006027
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3986425556
Short name	T1220
Test name
Test status
Simulation time	41651795 ps
CPU time	2.4 seconds
Started	Sep 09 07:08:41 AM UTC 24
Finished	Sep 09 07:08:44 AM UTC 24
Peak memory	204664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986425556 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3986425556
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.4191135489
Short name	T1219
Test name
Test status
Simulation time	74158437 ps
CPU time	1.1 seconds
Started	Sep 09 07:08:41 AM UTC 24
Finished	Sep 09 07:08:43 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191135489 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.4191135489
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2331159890
Short name	T1227
Test name
Test status
Simulation time	80256633 ps
CPU time	1 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:45 AM UTC 24
Peak memory	201696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=2331159890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r eset.2331159890
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.3183969193
Short name	T1223
Test name
Test status
Simulation time	20483392 ps
CPU time	0.84 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:45 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183969193 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3183969193
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.1687205502
Short name	T1221
Test name
Test status
Simulation time	184533421 ps
CPU time	0.72 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:44 AM UTC 24
Peak memory	201680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687205502 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1687205502
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.840859731
Short name	T1225
Test name
Test status
Simulation time	65834383 ps
CPU time	0.92 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:45 AM UTC 24
Peak memory	201696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840859731 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.840859731
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.740320292
Short name	T1229
Test name
Test status
Simulation time	81479503 ps
CPU time	1.94 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:46 AM UTC 24
Peak memory	203688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740320292 -assert nopostproc +UVM_TESTNAME=uart_base_t est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.740320292
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.2894403090
Short name	T82
Test name
Test status
Simulation time	77582894 ps
CPU time	1.93 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:46 AM UTC 24
Peak memory	201648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894403090 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2894403090
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.199292295
Short name	T1235
Test name
Test status
Simulation time	420424297 ps
CPU time	1.81 seconds
Started	Sep 09 07:08:45 AM UTC 24
Finished	Sep 09 07:08:48 AM UTC 24
Peak memory	203620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=199292295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_re set.199292295
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.4281987255
Short name	T60
Test name
Test status
Simulation time	35411906 ps
CPU time	0.79 seconds
Started	Sep 09 07:08:45 AM UTC 24
Finished	Sep 09 07:08:47 AM UTC 24
Peak memory	201756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281987255 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.4281987255
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.4102406910
Short name	T1226
Test name
Test status
Simulation time	12181234 ps
CPU time	0.83 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:45 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102406910 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4102406910
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.1326459726
Short name	T1230
Test name
Test status
Simulation time	172062232 ps
CPU time	0.94 seconds
Started	Sep 09 07:08:45 AM UTC 24
Finished	Sep 09 07:08:47 AM UTC 24
Peak memory	201628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326459726 -assert nopostproc +UV M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.1326459726
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1494917019
Short name	T1228
Test name
Test status
Simulation time	275083540 ps
CPU time	1.49 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:45 AM UTC 24
Peak memory	201644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494917019 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1494917019
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3938765943
Short name	T274
Test name
Test status
Simulation time	64149581 ps
CPU time	1.46 seconds
Started	Sep 09 07:08:43 AM UTC 24
Finished	Sep 09 07:08:45 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938765943 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3938765943
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1755616990
Short name	T1234
Test name
Test status
Simulation time	22431281 ps
CPU time	1.38 seconds
Started	Sep 09 07:08:45 AM UTC 24
Finished	Sep 09 07:08:47 AM UTC 24
Peak memory	201696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb =0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see d=1755616990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r eset.1755616990
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.767616768
Short name	T1231
Test name
Test status
Simulation time	14052459 ps
CPU time	0.77 seconds
Started	Sep 09 07:08:45 AM UTC 24
Finished	Sep 09 07:08:47 AM UTC 24
Peak memory	201692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767616768 -assert nopostproc +UVM_TESTNAME=uart_bas e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.767616768
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.4090113722
Short name	T1232
Test name
Test status
Simulation time	15839808 ps
CPU time	0.88 seconds
Started	Sep 09 07:08:45 AM UTC 24
Finished	Sep 09 07:08:47 AM UTC 24
Peak memory	201656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090113722 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.4090113722
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.234785834
Short name	T1233
Test name
Test status
Simulation time	24887785 ps
CPU time	1.07 seconds
Started	Sep 09 07:08:45 AM UTC 24
Finished	Sep 09 07:08:47 AM UTC 24
Peak memory	205728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234785834 -assert nopostproc +UVM _TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.234785834
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.3880066544
Short name	T1236
Test name
Test status
Simulation time	59158834 ps
CPU time	1.85 seconds
Started	Sep 09 07:08:45 AM UTC 24
Finished	Sep 09 07:08:48 AM UTC 24
Peak memory	201688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880066544 -assert nopostproc +UVM_TESTNAME=uart_base_ test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3880066544
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.3886170250
Short name	T271
Test name
Test status
Simulation time	105526918 ps
CPU time	1.39 seconds
Started	Sep 09 07:08:45 AM UTC 24
Finished	Sep 09 07:08:47 AM UTC 24
Peak memory	201644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886170250 -assert nopostproc +UVM_TESTNAM E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.3886170250
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_intr.3251501707
Short name	T3
Test name
Test status
Simulation time	13284113156 ps
CPU time	10.52 seconds
Started	Sep 09 06:28:34 AM UTC 24
Finished	Sep 09 06:28:46 AM UTC 24
Peak memory	205224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251501707 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3251501707
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.884036096
Short name	T477
Test name
Test status
Simulation time	123235072835 ps
CPU time	790.09 seconds
Started	Sep 09 06:28:58 AM UTC 24
Finished	Sep 09 06:42:18 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884036096 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.884036096
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_loopback.2012622927
Short name	T7
Test name
Test status
Simulation time	7388187060 ps
CPU time	6.79 seconds
Started	Sep 09 06:28:54 AM UTC 24
Finished	Sep 09 06:29:02 AM UTC 24
Peak memory	207336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012622927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2012622927
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_noise_filter.3998203618
Short name	T116
Test name
Test status
Simulation time	344244822463 ps
CPU time	78.53 seconds
Started	Sep 09 06:28:42 AM UTC 24
Finished	Sep 09 06:30:02 AM UTC 24
Peak memory	217604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998203618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3998203618
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_perf.2146294530
Short name	T452
Test name
Test status
Simulation time	19804647819 ps
CPU time	652.85 seconds
Started	Sep 09 06:28:57 AM UTC 24
Finished	Sep 09 06:39:58 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146294530 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2146294530
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2301553717
Short name	T9
Test name
Test status
Simulation time	3535302483 ps
CPU time	38.54 seconds
Started	Sep 09 06:28:28 AM UTC 24
Finished	Sep 09 06:29:08 AM UTC 24
Peak memory	207480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301553717 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2301553717
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.2906889038
Short name	T18
Test name
Test status
Simulation time	133016126824 ps
CPU time	120.18 seconds
Started	Sep 09 06:28:48 AM UTC 24
Finished	Sep 09 06:30:51 AM UTC 24
Peak memory	208900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906889038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2906889038
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_smoke.3359863886
Short name	T1
Test name
Test status
Simulation time	709789404 ps
CPU time	1.87 seconds
Started	Sep 09 06:28:11 AM UTC 24
Finished	Sep 09 06:28:13 AM UTC 24
Peak memory	206664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359863886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3359863886
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.227417852
Short name	T6
Test name
Test status
Simulation time	967754198 ps
CPU time	1.84 seconds
Started	Sep 09 06:28:53 AM UTC 24
Finished	Sep 09 06:28:56 AM UTC 24
Peak memory	206484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227417852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.227417852
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/0.uart_tx_rx.2203132889
Short name	T2
Test name
Test status
Simulation time	20154442418 ps
CPU time	7.52 seconds
Started	Sep 09 06:28:15 AM UTC 24
Finished	Sep 09 06:28:23 AM UTC 24
Peak memory	207152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203132889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2203132889
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/0.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_alert_test.1651778355
Short name	T33
Test name
Test status
Simulation time	11636271 ps
CPU time	0.8 seconds
Started	Sep 09 06:29:37 AM UTC 24
Finished	Sep 09 06:29:39 AM UTC 24
Peak memory	204380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651778355 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1651778355
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.2460327876
Short name	T366
Test name
Test status
Simulation time	119686521991 ps
CPU time	675.8 seconds
Started	Sep 09 06:29:35 AM UTC 24
Finished	Sep 09 06:40:58 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460327876 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2460327876
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_loopback.4267910770
Short name	T25
Test name
Test status
Simulation time	3671470620 ps
CPU time	6.65 seconds
Started	Sep 09 06:29:35 AM UTC 24
Finished	Sep 09 06:29:42 AM UTC 24
Peak memory	208520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267910770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.4267910770
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_noise_filter.1980358965
Short name	T43
Test name
Test status
Simulation time	12894880975 ps
CPU time	12.84 seconds
Started	Sep 09 06:29:21 AM UTC 24
Finished	Sep 09 06:29:35 AM UTC 24
Peak memory	205236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980358965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1980358965
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_perf.1001763809
Short name	T294
Test name
Test status
Simulation time	10276907258 ps
CPU time	352.51 seconds
Started	Sep 09 06:29:35 AM UTC 24
Finished	Sep 09 06:35:32 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001763809 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1001763809
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_rx_oversample.974495875
Short name	T20
Test name
Test status
Simulation time	6565730159 ps
CPU time	39.63 seconds
Started	Sep 09 06:29:11 AM UTC 24
Finished	Sep 09 06:29:52 AM UTC 24
Peak memory	207880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974495875 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.974495875
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.2888283588
Short name	T16
Test name
Test status
Simulation time	3051568452 ps
CPU time	3.15 seconds
Started	Sep 09 06:29:23 AM UTC 24
Finished	Sep 09 06:29:27 AM UTC 24
Peak memory	205100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888283588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2888283588
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_sec_cm.3983133872
Short name	T31
Test name
Test status
Simulation time	210422635 ps
CPU time	1.27 seconds
Started	Sep 09 06:29:37 AM UTC 24
Finished	Sep 09 06:29:39 AM UTC 24
Peak memory	240132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983133872 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3983133872
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_smoke.2596719003
Short name	T15
Test name
Test status
Simulation time	629405098 ps
CPU time	2.48 seconds
Started	Sep 09 06:29:08 AM UTC 24
Finished	Sep 09 06:29:11 AM UTC 24
Peak memory	208104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596719003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2596719003
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.2398560588
Short name	T28
Test name
Test status
Simulation time	3007596070 ps
CPU time	14.4 seconds
Started	Sep 09 06:29:35 AM UTC 24
Finished	Sep 09 06:29:50 AM UTC 24
Peak memory	217772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2398560588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_ with_rand_reset.2398560588
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.1078452972
Short name	T22
Test name
Test status
Simulation time	473352076 ps
CPU time	2.85 seconds
Started	Sep 09 06:29:31 AM UTC 24
Finished	Sep 09 06:29:34 AM UTC 24
Peak memory	207836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078452972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1078452972
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/1.uart_tx_rx.2371640308
Short name	T283
Test name
Test status
Simulation time	116870990233 ps
CPU time	236.96 seconds
Started	Sep 09 06:29:09 AM UTC 24
Finished	Sep 09 06:33:09 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371640308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2371640308
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/1.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_alert_test.2656763997
Short name	T435
Test name
Test status
Simulation time	46820507 ps
CPU time	0.81 seconds
Started	Sep 09 06:36:42 AM UTC 24
Finished	Sep 09 06:36:44 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656763997 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.2656763997
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_intr.1549707036
Short name	T386
Test name
Test status
Simulation time	54059741215 ps
CPU time	81.87 seconds
Started	Sep 09 06:36:00 AM UTC 24
Finished	Sep 09 06:37:24 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549707036 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1549707036
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.3495158682
Short name	T474
Test name
Test status
Simulation time	102854978635 ps
CPU time	323.96 seconds
Started	Sep 09 06:36:34 AM UTC 24
Finished	Sep 09 06:42:03 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495158682 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.3495158682
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_loopback.2814331474
Short name	T434
Test name
Test status
Simulation time	11100536054 ps
CPU time	16.81 seconds
Started	Sep 09 06:36:23 AM UTC 24
Finished	Sep 09 06:36:41 AM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814331474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2814331474
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_noise_filter.2025466212
Short name	T307
Test name
Test status
Simulation time	63019566654 ps
CPU time	150.37 seconds
Started	Sep 09 06:36:09 AM UTC 24
Finished	Sep 09 06:38:42 AM UTC 24
Peak memory	208088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025466212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2025466212
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_perf.773047669
Short name	T491
Test name
Test status
Simulation time	11319057424 ps
CPU time	418.02 seconds
Started	Sep 09 06:36:26 AM UTC 24
Finished	Sep 09 06:43:29 AM UTC 24
Peak memory	208656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773047669 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.773047669
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_rx_oversample.1298862602
Short name	T433
Test name
Test status
Simulation time	2305354417 ps
CPU time	17.57 seconds
Started	Sep 09 06:35:59 AM UTC 24
Finished	Sep 09 06:36:18 AM UTC 24
Peak memory	207764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298862602 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1298862602
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.4202324791
Short name	T182
Test name
Test status
Simulation time	130540285426 ps
CPU time	36.66 seconds
Started	Sep 09 06:36:19 AM UTC 24
Finished	Sep 09 06:36:57 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202324791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.4202324791
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.665150640
Short name	T338
Test name
Test status
Simulation time	1857917538 ps
CPU time	3.18 seconds
Started	Sep 09 06:36:14 AM UTC 24
Finished	Sep 09 06:36:18 AM UTC 24
Peak memory	205160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665150640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.665150640
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_smoke.3418266131
Short name	T382
Test name
Test status
Simulation time	661958846 ps
CPU time	4.46 seconds
Started	Sep 09 06:35:53 AM UTC 24
Finished	Sep 09 06:35:59 AM UTC 24
Peak memory	207092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418266131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3418266131
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_stress_all.3061120420
Short name	T406
Test name
Test status
Simulation time	113478929591 ps
CPU time	675.44 seconds
Started	Sep 09 06:36:41 AM UTC 24
Finished	Sep 09 06:48:04 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061120420 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3061120420
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.585267206
Short name	T76
Test name
Test status
Simulation time	2279077000 ps
CPU time	37.34 seconds
Started	Sep 09 06:36:35 AM UTC 24
Finished	Sep 09 06:37:14 AM UTC 24
Peak memory	217804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=585267206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all_ with_rand_reset.585267206
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/10.uart_tx_rx.1523556255
Short name	T387
Test name
Test status
Simulation time	6544828170 ps
CPU time	12.11 seconds
Started	Sep 09 06:35:54 AM UTC 24
Finished	Sep 09 06:36:08 AM UTC 24
Peak memory	207072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523556255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1523556255
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/10.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/100.uart_fifo_reset.1255686156
Short name	T1012
Test name
Test status
Simulation time	36086577043 ps
CPU time	63.27 seconds
Started	Sep 09 07:03:19 AM UTC 24
Finished	Sep 09 07:04:23 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255686156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1255686156
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/100.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/101.uart_fifo_reset.2325444279
Short name	T999
Test name
Test status
Simulation time	66498134854 ps
CPU time	33.86 seconds
Started	Sep 09 07:03:21 AM UTC 24
Finished	Sep 09 07:03:56 AM UTC 24
Peak memory	208740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325444279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2325444279
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/101.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/102.uart_fifo_reset.3724010588
Short name	T1112
Test name
Test status
Simulation time	113445419704 ps
CPU time	225.13 seconds
Started	Sep 09 07:03:23 AM UTC 24
Finished	Sep 09 07:07:11 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724010588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3724010588
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/102.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/104.uart_fifo_reset.3835209668
Short name	T1020
Test name
Test status
Simulation time	68902594156 ps
CPU time	72.7 seconds
Started	Sep 09 07:03:26 AM UTC 24
Finished	Sep 09 07:04:41 AM UTC 24
Peak memory	208524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835209668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3835209668
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/104.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/105.uart_fifo_reset.3473628657
Short name	T1023
Test name
Test status
Simulation time	10823911737 ps
CPU time	74.04 seconds
Started	Sep 09 07:03:27 AM UTC 24
Finished	Sep 09 07:04:43 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473628657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3473628657
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/105.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/106.uart_fifo_reset.1369939178
Short name	T1016
Test name
Test status
Simulation time	73441369989 ps
CPU time	66.84 seconds
Started	Sep 09 07:03:27 AM UTC 24
Finished	Sep 09 07:04:36 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369939178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1369939178
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/106.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/107.uart_fifo_reset.958046339
Short name	T1122
Test name
Test status
Simulation time	127147329072 ps
CPU time	237.5 seconds
Started	Sep 09 07:03:31 AM UTC 24
Finished	Sep 09 07:07:32 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958046339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.958046339
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/107.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/108.uart_fifo_reset.3886020050
Short name	T1081
Test name
Test status
Simulation time	102994535199 ps
CPU time	146.5 seconds
Started	Sep 09 07:03:36 AM UTC 24
Finished	Sep 09 07:06:05 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886020050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3886020050
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/108.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/109.uart_fifo_reset.4084167332
Short name	T1035
Test name
Test status
Simulation time	138822061976 ps
CPU time	75.91 seconds
Started	Sep 09 07:03:39 AM UTC 24
Finished	Sep 09 07:04:57 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084167332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.4084167332
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/109.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_alert_test.4264944081
Short name	T438
Test name
Test status
Simulation time	13219788 ps
CPU time	0.83 seconds
Started	Sep 09 06:37:52 AM UTC 24
Finished	Sep 09 06:37:54 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264944081 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4264944081
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_fifo_full.182661235
Short name	T354
Test name
Test status
Simulation time	90090925870 ps
CPU time	191.74 seconds
Started	Sep 09 06:36:55 AM UTC 24
Finished	Sep 09 06:40:09 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182661235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.182661235
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.514083359
Short name	T124
Test name
Test status
Simulation time	18582821038 ps
CPU time	61.59 seconds
Started	Sep 09 06:36:58 AM UTC 24
Finished	Sep 09 06:38:01 AM UTC 24
Peak memory	208816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514083359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.514083359
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_fifo_reset.3833669012
Short name	T342
Test name
Test status
Simulation time	12258176806 ps
CPU time	38.17 seconds
Started	Sep 09 06:37:05 AM UTC 24
Finished	Sep 09 06:37:44 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833669012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3833669012
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.846181101
Short name	T287
Test name
Test status
Simulation time	323101923877 ps
CPU time	94.79 seconds
Started	Sep 09 06:37:38 AM UTC 24
Finished	Sep 09 06:39:15 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846181101 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.846181101
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_loopback.1893133230
Short name	T436
Test name
Test status
Simulation time	1860959194 ps
CPU time	8.59 seconds
Started	Sep 09 06:37:27 AM UTC 24
Finished	Sep 09 06:37:37 AM UTC 24
Peak memory	207252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893133230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1893133230
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_noise_filter.3958768802
Short name	T289
Test name
Test status
Simulation time	111980124638 ps
CPU time	88.78 seconds
Started	Sep 09 06:37:15 AM UTC 24
Finished	Sep 09 06:38:46 AM UTC 24
Peak memory	217528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958768802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3958768802
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_perf.2093796495
Short name	T332
Test name
Test status
Simulation time	32889263419 ps
CPU time	482.83 seconds
Started	Sep 09 06:37:29 AM UTC 24
Finished	Sep 09 06:45:38 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093796495 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2093796495
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_rx_oversample.3260625297
Short name	T437
Test name
Test status
Simulation time	4020869361 ps
CPU time	42.54 seconds
Started	Sep 09 06:37:07 AM UTC 24
Finished	Sep 09 06:37:51 AM UTC 24
Peak memory	208112 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260625297 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3260625297
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.2096884119
Short name	T325
Test name
Test status
Simulation time	101421881184 ps
CPU time	70.07 seconds
Started	Sep 09 06:37:25 AM UTC 24
Finished	Sep 09 06:38:37 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096884119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.2096884119
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.1259515929
Short name	T369
Test name
Test status
Simulation time	659596505 ps
CPU time	2.07 seconds
Started	Sep 09 06:37:21 AM UTC 24
Finished	Sep 09 06:37:24 AM UTC 24
Peak memory	205160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259515929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1259515929
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_smoke.4127441702
Short name	T357
Test name
Test status
Simulation time	6071775170 ps
CPU time	33.73 seconds
Started	Sep 09 06:36:45 AM UTC 24
Finished	Sep 09 06:37:20 AM UTC 24
Peak memory	208748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127441702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.4127441702
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.4122303166
Short name	T351
Test name
Test status
Simulation time	349600900 ps
CPU time	2.06 seconds
Started	Sep 09 06:37:25 AM UTC 24
Finished	Sep 09 06:37:28 AM UTC 24
Peak memory	207212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122303166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.4122303166
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/110.uart_fifo_reset.3418639889
Short name	T1018
Test name
Test status
Simulation time	51984019166 ps
CPU time	57.44 seconds
Started	Sep 09 07:03:39 AM UTC 24
Finished	Sep 09 07:04:39 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418639889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3418639889
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/110.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/111.uart_fifo_reset.4039144987
Short name	T1022
Test name
Test status
Simulation time	156667600012 ps
CPU time	61.14 seconds
Started	Sep 09 07:03:39 AM UTC 24
Finished	Sep 09 07:04:42 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039144987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.4039144987
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/111.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/112.uart_fifo_reset.3253062698
Short name	T1017
Test name
Test status
Simulation time	284487842080 ps
CPU time	52.88 seconds
Started	Sep 09 07:03:41 AM UTC 24
Finished	Sep 09 07:04:36 AM UTC 24
Peak memory	208568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253062698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3253062698
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/112.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/114.uart_fifo_reset.3160389722
Short name	T1010
Test name
Test status
Simulation time	15476629861 ps
CPU time	32.38 seconds
Started	Sep 09 07:03:46 AM UTC 24
Finished	Sep 09 07:04:20 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160389722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3160389722
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/114.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/118.uart_fifo_reset.2422576187
Short name	T1011
Test name
Test status
Simulation time	24574098219 ps
CPU time	28.09 seconds
Started	Sep 09 07:03:51 AM UTC 24
Finished	Sep 09 07:04:20 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422576187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2422576187
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/118.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_alert_test.1324253504
Short name	T442
Test name
Test status
Simulation time	12346131 ps
CPU time	0.82 seconds
Started	Sep 09 06:38:38 AM UTC 24
Finished	Sep 09 06:38:40 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324253504 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.1324253504
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_fifo_full.3310570626
Short name	T132
Test name
Test status
Simulation time	82594002324 ps
CPU time	53.81 seconds
Started	Sep 09 06:37:58 AM UTC 24
Finished	Sep 09 06:38:53 AM UTC 24
Peak memory	208632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310570626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3310570626
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.813794345
Short name	T143
Test name
Test status
Simulation time	51292678296 ps
CPU time	43.7 seconds
Started	Sep 09 06:38:02 AM UTC 24
Finished	Sep 09 06:38:47 AM UTC 24
Peak memory	208680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813794345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.813794345
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_intr.1437542625
Short name	T111
Test name
Test status
Simulation time	39195913945 ps
CPU time	81.36 seconds
Started	Sep 09 06:38:08 AM UTC 24
Finished	Sep 09 06:39:31 AM UTC 24
Peak memory	208680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437542625 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1437542625
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.1378597682
Short name	T583
Test name
Test status
Simulation time	110880327956 ps
CPU time	655.24 seconds
Started	Sep 09 06:38:23 AM UTC 24
Finished	Sep 09 06:49:25 AM UTC 24
Peak memory	208312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378597682 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1378597682
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_loopback.3964742888
Short name	T441
Test name
Test status
Simulation time	8430526143 ps
CPU time	17.69 seconds
Started	Sep 09 06:38:21 AM UTC 24
Finished	Sep 09 06:38:40 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964742888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3964742888
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_noise_filter.1042429539
Short name	T322
Test name
Test status
Simulation time	45246985190 ps
CPU time	137.93 seconds
Started	Sep 09 06:38:09 AM UTC 24
Finished	Sep 09 06:40:30 AM UTC 24
Peak memory	217596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042429539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1042429539
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_perf.1429772817
Short name	T578
Test name
Test status
Simulation time	19662105369 ps
CPU time	647.86 seconds
Started	Sep 09 06:38:23 AM UTC 24
Finished	Sep 09 06:49:18 AM UTC 24
Peak memory	209808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429772817 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1429772817
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_rx_oversample.3544286791
Short name	T439
Test name
Test status
Simulation time	5003636008 ps
CPU time	13.44 seconds
Started	Sep 09 06:38:05 AM UTC 24
Finished	Sep 09 06:38:20 AM UTC 24
Peak memory	207416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544286791 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3544286791
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.2672024028
Short name	T148
Test name
Test status
Simulation time	14998491092 ps
CPU time	55.52 seconds
Started	Sep 09 06:38:18 AM UTC 24
Finished	Sep 09 06:39:15 AM UTC 24
Peak memory	208716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672024028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2672024028
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.3484534626
Short name	T337
Test name
Test status
Simulation time	1664690638 ps
CPU time	4.24 seconds
Started	Sep 09 06:38:16 AM UTC 24
Finished	Sep 09 06:38:22 AM UTC 24
Peak memory	205032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484534626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3484534626
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_smoke.2521993346
Short name	T339
Test name
Test status
Simulation time	1015941948 ps
CPU time	1.78 seconds
Started	Sep 09 06:37:55 AM UTC 24
Finished	Sep 09 06:37:58 AM UTC 24
Peak memory	206244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521993346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2521993346
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_stress_all.4123315195
Short name	T173
Test name
Test status
Simulation time	101103758900 ps
CPU time	431.64 seconds
Started	Sep 09 06:38:30 AM UTC 24
Finished	Sep 09 06:45:47 AM UTC 24
Peak memory	208824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123315195 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4123315195
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.3836068804
Short name	T89
Test name
Test status
Simulation time	5218703099 ps
CPU time	71.35 seconds
Started	Sep 09 06:38:26 AM UTC 24
Finished	Sep 09 06:39:39 AM UTC 24
Peak memory	217852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3836068804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all _with_rand_reset.3836068804
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.3529189303
Short name	T440
Test name
Test status
Simulation time	3493231106 ps
CPU time	5.13 seconds
Started	Sep 09 06:38:19 AM UTC 24
Finished	Sep 09 06:38:25 AM UTC 24
Peak memory	207764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529189303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3529189303
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/12.uart_tx_rx.2157331769
Short name	T329
Test name
Test status
Simulation time	36501805970 ps
CPU time	19.94 seconds
Started	Sep 09 06:37:56 AM UTC 24
Finished	Sep 09 06:38:17 AM UTC 24
Peak memory	207348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157331769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2157331769
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/12.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/121.uart_fifo_reset.297937567
Short name	T1132
Test name
Test status
Simulation time	170027717117 ps
CPU time	233.42 seconds
Started	Sep 09 07:03:57 AM UTC 24
Finished	Sep 09 07:07:54 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297937567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.297937567
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/121.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/122.uart_fifo_reset.377471218
Short name	T1025
Test name
Test status
Simulation time	52135992742 ps
CPU time	48.38 seconds
Started	Sep 09 07:03:57 AM UTC 24
Finished	Sep 09 07:04:47 AM UTC 24
Peak memory	208756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377471218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.377471218
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/122.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/123.uart_fifo_reset.1175493991
Short name	T1021
Test name
Test status
Simulation time	59250232969 ps
CPU time	42.19 seconds
Started	Sep 09 07:03:58 AM UTC 24
Finished	Sep 09 07:04:42 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175493991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1175493991
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/123.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/124.uart_fifo_reset.2916147923
Short name	T413
Test name
Test status
Simulation time	14048707402 ps
CPU time	15.63 seconds
Started	Sep 09 07:03:58 AM UTC 24
Finished	Sep 09 07:04:15 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916147923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2916147923
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/124.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/125.uart_fifo_reset.3049704799
Short name	T1054
Test name
Test status
Simulation time	142133778757 ps
CPU time	76.53 seconds
Started	Sep 09 07:04:00 AM UTC 24
Finished	Sep 09 07:05:18 AM UTC 24
Peak memory	208880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049704799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3049704799
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/125.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/126.uart_fifo_reset.1200699914
Short name	T1073
Test name
Test status
Simulation time	139752513445 ps
CPU time	110.78 seconds
Started	Sep 09 07:04:00 AM UTC 24
Finished	Sep 09 07:05:52 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200699914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1200699914
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/126.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/127.uart_fifo_reset.1756768412
Short name	T1019
Test name
Test status
Simulation time	11873212726 ps
CPU time	36.38 seconds
Started	Sep 09 07:04:02 AM UTC 24
Finished	Sep 09 07:04:39 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756768412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1756768412
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/127.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/128.uart_fifo_reset.91802836
Short name	T1034
Test name
Test status
Simulation time	182931995346 ps
CPU time	51.54 seconds
Started	Sep 09 07:04:03 AM UTC 24
Finished	Sep 09 07:04:56 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91802836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.91802836
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/128.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/129.uart_fifo_reset.2253756934
Short name	T1013
Test name
Test status
Simulation time	48679220402 ps
CPU time	22.5 seconds
Started	Sep 09 07:04:04 AM UTC 24
Finished	Sep 09 07:04:28 AM UTC 24
Peak memory	208880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253756934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2253756934
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/129.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_alert_test.4051423021
Short name	T446
Test name
Test status
Simulation time	13171899 ps
CPU time	0.79 seconds
Started	Sep 09 06:39:19 AM UTC 24
Finished	Sep 09 06:39:21 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051423021 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.4051423021
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_fifo_full.1077586500
Short name	T408
Test name
Test status
Simulation time	240049227356 ps
CPU time	288.19 seconds
Started	Sep 09 06:38:42 AM UTC 24
Finished	Sep 09 06:43:34 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077586500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.1077586500
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.567070807
Short name	T367
Test name
Test status
Simulation time	32478391894 ps
CPU time	29.88 seconds
Started	Sep 09 06:38:45 AM UTC 24
Finished	Sep 09 06:39:17 AM UTC 24
Peak memory	208480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567070807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.567070807
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_fifo_reset.1215809522
Short name	T198
Test name
Test status
Simulation time	18902800883 ps
CPU time	52.56 seconds
Started	Sep 09 06:38:46 AM UTC 24
Finished	Sep 09 06:39:41 AM UTC 24
Peak memory	208352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215809522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1215809522
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_intr.1708445820
Short name	T389
Test name
Test status
Simulation time	101808719990 ps
CPU time	178.66 seconds
Started	Sep 09 06:38:53 AM UTC 24
Finished	Sep 09 06:41:54 AM UTC 24
Peak memory	207752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708445820 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1708445820
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.3213922473
Short name	T385
Test name
Test status
Simulation time	47068731060 ps
CPU time	154.46 seconds
Started	Sep 09 06:39:16 AM UTC 24
Finished	Sep 09 06:41:53 AM UTC 24
Peak memory	208724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213922473 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3213922473
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_loopback.2678596994
Short name	T445
Test name
Test status
Simulation time	5434116033 ps
CPU time	6.62 seconds
Started	Sep 09 06:39:11 AM UTC 24
Finished	Sep 09 06:39:19 AM UTC 24
Peak memory	208864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678596994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2678596994
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_noise_filter.3535822480
Short name	T379
Test name
Test status
Simulation time	104289162292 ps
CPU time	61.25 seconds
Started	Sep 09 06:38:54 AM UTC 24
Finished	Sep 09 06:39:56 AM UTC 24
Peak memory	207944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535822480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3535822480
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_perf.3974957798
Short name	T686
Test name
Test status
Simulation time	15236466191 ps
CPU time	808.76 seconds
Started	Sep 09 06:39:15 AM UTC 24
Finished	Sep 09 06:52:53 AM UTC 24
Peak memory	212368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974957798 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3974957798
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_rx_oversample.3630174887
Short name	T447
Test name
Test status
Simulation time	4952176390 ps
CPU time	45.3 seconds
Started	Sep 09 06:38:47 AM UTC 24
Finished	Sep 09 06:39:34 AM UTC 24
Peak memory	207212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630174887 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3630174887
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.2375058604
Short name	T443
Test name
Test status
Simulation time	6719336216 ps
CPU time	6.4 seconds
Started	Sep 09 06:39:03 AM UTC 24
Finished	Sep 09 06:39:10 AM UTC 24
Peak memory	207144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375058604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.2375058604
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_smoke.2519186044
Short name	T350
Test name
Test status
Simulation time	5318381133 ps
CPU time	10.93 seconds
Started	Sep 09 06:38:40 AM UTC 24
Finished	Sep 09 06:38:52 AM UTC 24
Peak memory	208928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519186044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2519186044
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.727364854
Short name	T90
Test name
Test status
Simulation time	2334821343 ps
CPU time	43.24 seconds
Started	Sep 09 06:39:17 AM UTC 24
Finished	Sep 09 06:40:02 AM UTC 24
Peak memory	217656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=727364854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all_ with_rand_reset.727364854
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.1685758079
Short name	T444
Test name
Test status
Simulation time	1077778694 ps
CPU time	6.91 seconds
Started	Sep 09 06:39:10 AM UTC 24
Finished	Sep 09 06:39:18 AM UTC 24
Peak memory	208492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685758079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.1685758079
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/13.uart_tx_rx.3652380401
Short name	T316
Test name
Test status
Simulation time	109141882157 ps
CPU time	66.64 seconds
Started	Sep 09 06:38:41 AM UTC 24
Finished	Sep 09 06:39:50 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652380401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3652380401
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/13.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/131.uart_fifo_reset.2298974530
Short name	T1111
Test name
Test status
Simulation time	66612234763 ps
CPU time	178.82 seconds
Started	Sep 09 07:04:08 AM UTC 24
Finished	Sep 09 07:07:10 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298974530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2298974530
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/131.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/132.uart_fifo_reset.1885312696
Short name	T1066
Test name
Test status
Simulation time	54886096371 ps
CPU time	92.39 seconds
Started	Sep 09 07:04:10 AM UTC 24
Finished	Sep 09 07:05:44 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885312696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1885312696
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/132.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/134.uart_fifo_reset.3824590645
Short name	T1078
Test name
Test status
Simulation time	115931934626 ps
CPU time	101.53 seconds
Started	Sep 09 07:04:16 AM UTC 24
Finished	Sep 09 07:06:00 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824590645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.3824590645
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/134.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/135.uart_fifo_reset.3354211124
Short name	T1028
Test name
Test status
Simulation time	16563460552 ps
CPU time	32.39 seconds
Started	Sep 09 07:04:16 AM UTC 24
Finished	Sep 09 07:04:50 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354211124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3354211124
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/135.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/137.uart_fifo_reset.3781480726
Short name	T1094
Test name
Test status
Simulation time	67232046409 ps
CPU time	141.03 seconds
Started	Sep 09 07:04:19 AM UTC 24
Finished	Sep 09 07:06:43 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781480726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3781480726
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/137.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/138.uart_fifo_reset.4147273650
Short name	T1033
Test name
Test status
Simulation time	66830840629 ps
CPU time	32.55 seconds
Started	Sep 09 07:04:21 AM UTC 24
Finished	Sep 09 07:04:54 AM UTC 24
Peak memory	208884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147273650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.4147273650
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/138.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/139.uart_fifo_reset.3136466286
Short name	T1042
Test name
Test status
Simulation time	51768512849 ps
CPU time	41.91 seconds
Started	Sep 09 07:04:21 AM UTC 24
Finished	Sep 09 07:05:04 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136466286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3136466286
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/139.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_alert_test.3318998384
Short name	T453
Test name
Test status
Simulation time	11987145 ps
CPU time	0.81 seconds
Started	Sep 09 06:39:58 AM UTC 24
Finished	Sep 09 06:39:59 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318998384 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.3318998384
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_fifo_full.1255216295
Short name	T374
Test name
Test status
Simulation time	157247314237 ps
CPU time	141.39 seconds
Started	Sep 09 06:39:22 AM UTC 24
Finished	Sep 09 06:41:45 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255216295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1255216295
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1458011506
Short name	T137
Test name
Test status
Simulation time	50577503303 ps
CPU time	47.71 seconds
Started	Sep 09 06:39:23 AM UTC 24
Finished	Sep 09 06:40:12 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458011506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1458011506
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_fifo_reset.2190353899
Short name	T384
Test name
Test status
Simulation time	28606670492 ps
CPU time	56.86 seconds
Started	Sep 09 06:39:33 AM UTC 24
Finished	Sep 09 06:40:32 AM UTC 24
Peak memory	208752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190353899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2190353899
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_intr.3926360659
Short name	T456
Test name
Test status
Simulation time	16489380171 ps
CPU time	57.6 seconds
Started	Sep 09 06:39:40 AM UTC 24
Finished	Sep 09 06:40:39 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926360659 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3926360659
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_loopback.4110218512
Short name	T451
Test name
Test status
Simulation time	5338760344 ps
CPU time	2.78 seconds
Started	Sep 09 06:39:46 AM UTC 24
Finished	Sep 09 06:39:50 AM UTC 24
Peak memory	207148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110218512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.4110218512
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_noise_filter.3628266353
Short name	T398
Test name
Test status
Simulation time	10422900244 ps
CPU time	35.24 seconds
Started	Sep 09 06:39:41 AM UTC 24
Finished	Sep 09 06:40:18 AM UTC 24
Peak memory	204496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628266353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3628266353
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_perf.251097495
Short name	T553
Test name
Test status
Simulation time	9241678980 ps
CPU time	483.41 seconds
Started	Sep 09 06:39:47 AM UTC 24
Finished	Sep 09 06:47:57 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251097495 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.251097495
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_rx_oversample.2571600645
Short name	T448
Test name
Test status
Simulation time	2351137175 ps
CPU time	4.76 seconds
Started	Sep 09 06:39:35 AM UTC 24
Finished	Sep 09 06:39:41 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571600645 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2571600645
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.2356150442
Short name	T466
Test name
Test status
Simulation time	42848304814 ps
CPU time	114.63 seconds
Started	Sep 09 06:39:41 AM UTC 24
Finished	Sep 09 06:41:38 AM UTC 24
Peak memory	208900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356150442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2356150442
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.3757576184
Short name	T449
Test name
Test status
Simulation time	1678652138 ps
CPU time	3.24 seconds
Started	Sep 09 06:39:41 AM UTC 24
Finished	Sep 09 06:39:45 AM UTC 24
Peak memory	205160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757576184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3757576184
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_smoke.1046035609
Short name	T375
Test name
Test status
Simulation time	5770074094 ps
CPU time	19.4 seconds
Started	Sep 09 06:39:19 AM UTC 24
Finished	Sep 09 06:39:40 AM UTC 24
Peak memory	207984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046035609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.1046035609
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.2232656340
Short name	T113
Test name
Test status
Simulation time	10459920922 ps
CPU time	63.44 seconds
Started	Sep 09 06:39:52 AM UTC 24
Finished	Sep 09 06:40:57 AM UTC 24
Peak memory	221884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2232656340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all _with_rand_reset.2232656340
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.156503891
Short name	T450
Test name
Test status
Simulation time	1764252176 ps
CPU time	3.26 seconds
Started	Sep 09 06:39:42 AM UTC 24
Finished	Sep 09 06:39:47 AM UTC 24
Peak memory	207584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156503891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.156503891
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/14.uart_tx_rx.631415099
Short name	T319
Test name
Test status
Simulation time	27659565101 ps
CPU time	34.8 seconds
Started	Sep 09 06:39:21 AM UTC 24
Finished	Sep 09 06:39:57 AM UTC 24
Peak memory	208680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631415099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.631415099
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/14.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/140.uart_fifo_reset.155923527
Short name	T202
Test name
Test status
Simulation time	20978782929 ps
CPU time	32.37 seconds
Started	Sep 09 07:04:25 AM UTC 24
Finished	Sep 09 07:04:58 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155923527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.155923527
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/140.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/144.uart_fifo_reset.2396620055
Short name	T1082
Test name
Test status
Simulation time	152382023654 ps
CPU time	93.9 seconds
Started	Sep 09 07:04:31 AM UTC 24
Finished	Sep 09 07:06:07 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396620055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2396620055
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/144.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/145.uart_fifo_reset.3821576695
Short name	T1041
Test name
Test status
Simulation time	38938378753 ps
CPU time	30.29 seconds
Started	Sep 09 07:04:31 AM UTC 24
Finished	Sep 09 07:05:03 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821576695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3821576695
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/145.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/146.uart_fifo_reset.2536702113
Short name	T1060
Test name
Test status
Simulation time	51736470003 ps
CPU time	56.04 seconds
Started	Sep 09 07:04:35 AM UTC 24
Finished	Sep 09 07:05:33 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536702113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2536702113
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/146.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/147.uart_fifo_reset.3936554689
Short name	T1055
Test name
Test status
Simulation time	36451592520 ps
CPU time	42.24 seconds
Started	Sep 09 07:04:37 AM UTC 24
Finished	Sep 09 07:05:21 AM UTC 24
Peak memory	208656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936554689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3936554689
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/147.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/148.uart_fifo_reset.404631294
Short name	T1086
Test name
Test status
Simulation time	59615464726 ps
CPU time	98.4 seconds
Started	Sep 09 07:04:37 AM UTC 24
Finished	Sep 09 07:06:18 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404631294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.404631294
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/148.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/149.uart_fifo_reset.1069159116
Short name	T1039
Test name
Test status
Simulation time	134814780205 ps
CPU time	19.52 seconds
Started	Sep 09 07:04:39 AM UTC 24
Finished	Sep 09 07:05:00 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069159116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1069159116
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/149.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_alert_test.1574302689
Short name	T458
Test name
Test status
Simulation time	36310153 ps
CPU time	0.81 seconds
Started	Sep 09 06:40:43 AM UTC 24
Finished	Sep 09 06:40:45 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574302689 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1574302689
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_fifo_full.4039756249
Short name	T359
Test name
Test status
Simulation time	174033209038 ps
CPU time	157.46 seconds
Started	Sep 09 06:40:03 AM UTC 24
Finished	Sep 09 06:42:43 AM UTC 24
Peak memory	208716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039756249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.4039756249
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_fifo_reset.4006752467
Short name	T126
Test name
Test status
Simulation time	27406861128 ps
CPU time	66.69 seconds
Started	Sep 09 06:40:10 AM UTC 24
Finished	Sep 09 06:41:18 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006752467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4006752467
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_intr.375312736
Short name	T108
Test name
Test status
Simulation time	30059117925 ps
CPU time	55 seconds
Started	Sep 09 06:40:18 AM UTC 24
Finished	Sep 09 06:41:15 AM UTC 24
Peak memory	208752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375312736 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.375312736
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.2401235837
Short name	T786
Test name
Test status
Simulation time	100430388538 ps
CPU time	922.46 seconds
Started	Sep 09 06:40:40 AM UTC 24
Finished	Sep 09 06:56:12 AM UTC 24
Peak memory	212276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401235837 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2401235837
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_loopback.2487509335
Short name	T457
Test name
Test status
Simulation time	1293547809 ps
CPU time	1.41 seconds
Started	Sep 09 06:40:38 AM UTC 24
Finished	Sep 09 06:40:40 AM UTC 24
Peak memory	204440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487509335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2487509335
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_noise_filter.2948360279
Short name	T531
Test name
Test status
Simulation time	87892180113 ps
CPU time	353.7 seconds
Started	Sep 09 06:40:21 AM UTC 24
Finished	Sep 09 06:46:20 AM UTC 24
Peak memory	217580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948360279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2948360279
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_perf.3807384599
Short name	T543
Test name
Test status
Simulation time	11915315296 ps
CPU time	400.88 seconds
Started	Sep 09 06:40:38 AM UTC 24
Finished	Sep 09 06:47:24 AM UTC 24
Peak memory	208956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807384599 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3807384599
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_rx_oversample.3946513898
Short name	T454
Test name
Test status
Simulation time	5015856671 ps
CPU time	21.99 seconds
Started	Sep 09 06:40:13 AM UTC 24
Finished	Sep 09 06:40:36 AM UTC 24
Peak memory	207460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946513898 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3946513898
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.356782575
Short name	T308
Test name
Test status
Simulation time	79492074355 ps
CPU time	73.37 seconds
Started	Sep 09 06:40:31 AM UTC 24
Finished	Sep 09 06:41:46 AM UTC 24
Peak memory	207400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356782575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.356782575
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.390376413
Short name	T371
Test name
Test status
Simulation time	73580824589 ps
CPU time	68.31 seconds
Started	Sep 09 06:40:23 AM UTC 24
Finished	Sep 09 06:41:33 AM UTC 24
Peak memory	207272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390376413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.390376413
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_smoke.1156110877
Short name	T380
Test name
Test status
Simulation time	432469591 ps
CPU time	3.16 seconds
Started	Sep 09 06:39:59 AM UTC 24
Finished	Sep 09 06:40:03 AM UTC 24
Peak memory	207268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156110877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.1156110877
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_stress_all.3513067931
Short name	T186
Test name
Test status
Simulation time	181835102398 ps
CPU time	342.82 seconds
Started	Sep 09 06:40:43 AM UTC 24
Finished	Sep 09 06:46:30 AM UTC 24
Peak memory	208624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513067931 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3513067931
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.1607207243
Short name	T91
Test name
Test status
Simulation time	9325133902 ps
CPU time	46.72 seconds
Started	Sep 09 06:40:41 AM UTC 24
Finished	Sep 09 06:41:29 AM UTC 24
Peak memory	217788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1607207243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all _with_rand_reset.1607207243
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.782546778
Short name	T455
Test name
Test status
Simulation time	1295944192 ps
CPU time	2.85 seconds
Started	Sep 09 06:40:33 AM UTC 24
Finished	Sep 09 06:40:37 AM UTC 24
Peak memory	207812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782546778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.782546778
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/15.uart_tx_rx.3808408468
Short name	T381
Test name
Test status
Simulation time	66322431866 ps
CPU time	40.52 seconds
Started	Sep 09 06:40:00 AM UTC 24
Finished	Sep 09 06:40:42 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808408468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3808408468
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/15.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/151.uart_fifo_reset.1864495114
Short name	T1046
Test name
Test status
Simulation time	42139798883 ps
CPU time	29.06 seconds
Started	Sep 09 07:04:42 AM UTC 24
Finished	Sep 09 07:05:12 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864495114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1864495114
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/151.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/152.uart_fifo_reset.3285863808
Short name	T1106
Test name
Test status
Simulation time	85194002668 ps
CPU time	137.18 seconds
Started	Sep 09 07:04:42 AM UTC 24
Finished	Sep 09 07:07:01 AM UTC 24
Peak memory	208680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285863808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3285863808
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/152.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1842686716
Short name	T1040
Test name
Test status
Simulation time	22218515165 ps
CPU time	16.67 seconds
Started	Sep 09 07:04:43 AM UTC 24
Finished	Sep 09 07:05:01 AM UTC 24
Peak memory	207800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842686716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1842686716
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/153.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/154.uart_fifo_reset.3730297401
Short name	T1047
Test name
Test status
Simulation time	107518051404 ps
CPU time	28.18 seconds
Started	Sep 09 07:04:43 AM UTC 24
Finished	Sep 09 07:05:12 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730297401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3730297401
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/154.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/155.uart_fifo_reset.3027183609
Short name	T201
Test name
Test status
Simulation time	54880093952 ps
CPU time	22.23 seconds
Started	Sep 09 07:04:44 AM UTC 24
Finished	Sep 09 07:05:07 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027183609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3027183609
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/155.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/156.uart_fifo_reset.3797757037
Short name	T1049
Test name
Test status
Simulation time	12710264851 ps
CPU time	26.45 seconds
Started	Sep 09 07:04:45 AM UTC 24
Finished	Sep 09 07:05:13 AM UTC 24
Peak memory	208712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797757037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3797757037
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/156.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/157.uart_fifo_reset.4195335734
Short name	T1179
Test name
Test status
Simulation time	190309063822 ps
CPU time	358.48 seconds
Started	Sep 09 07:04:47 AM UTC 24
Finished	Sep 09 07:10:50 AM UTC 24
Peak memory	212368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195335734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.4195335734
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/157.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/159.uart_fifo_reset.2447951500
Short name	T1062
Test name
Test status
Simulation time	157047910851 ps
CPU time	42.89 seconds
Started	Sep 09 07:04:49 AM UTC 24
Finished	Sep 09 07:05:33 AM UTC 24
Peak memory	208980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447951500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2447951500
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/159.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_alert_test.2540000006
Short name	T465
Test name
Test status
Simulation time	27914072 ps
CPU time	0.82 seconds
Started	Sep 09 06:41:32 AM UTC 24
Finished	Sep 09 06:41:34 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540000006 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2540000006
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.3976480820
Short name	T140
Test name
Test status
Simulation time	61403223649 ps
CPU time	53.1 seconds
Started	Sep 09 06:40:57 AM UTC 24
Finished	Sep 09 06:41:52 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976480820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3976480820
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_fifo_reset.3851622978
Short name	T462
Test name
Test status
Simulation time	19261218514 ps
CPU time	25.19 seconds
Started	Sep 09 06:40:58 AM UTC 24
Finished	Sep 09 06:41:25 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851622978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3851622978
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_intr.1362169269
Short name	T468
Test name
Test status
Simulation time	19275955969 ps
CPU time	46.72 seconds
Started	Sep 09 06:41:03 AM UTC 24
Finished	Sep 09 06:41:51 AM UTC 24
Peak memory	207148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362169269 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1362169269
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.4091290530
Short name	T643
Test name
Test status
Simulation time	78893261188 ps
CPU time	590.97 seconds
Started	Sep 09 06:41:25 AM UTC 24
Finished	Sep 09 06:51:23 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091290530 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.4091290530
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_loopback.1196204317
Short name	T461
Test name
Test status
Simulation time	66103919 ps
CPU time	0.95 seconds
Started	Sep 09 06:41:20 AM UTC 24
Finished	Sep 09 06:41:22 AM UTC 24
Peak memory	204440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196204317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1196204317
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_noise_filter.580225401
Short name	T480
Test name
Test status
Simulation time	33004677229 ps
CPU time	78.54 seconds
Started	Sep 09 06:41:04 AM UTC 24
Finished	Sep 09 06:42:24 AM UTC 24
Peak memory	208848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580225401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.580225401
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_perf.1898133772
Short name	T400
Test name
Test status
Simulation time	13914859515 ps
CPU time	906.62 seconds
Started	Sep 09 06:41:23 AM UTC 24
Finished	Sep 09 06:56:40 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898133772 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.1898133772
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_rx_oversample.1455481832
Short name	T463
Test name
Test status
Simulation time	2718585123 ps
CPU time	26.81 seconds
Started	Sep 09 06:41:00 AM UTC 24
Finished	Sep 09 06:41:28 AM UTC 24
Peak memory	207212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455481832 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1455481832
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.481302436
Short name	T364
Test name
Test status
Simulation time	15964950303 ps
CPU time	51.69 seconds
Started	Sep 09 06:41:16 AM UTC 24
Finished	Sep 09 06:42:09 AM UTC 24
Peak memory	208676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481302436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.481302436
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3678724497
Short name	T390
Test name
Test status
Simulation time	38826188007 ps
CPU time	99.71 seconds
Started	Sep 09 06:41:14 AM UTC 24
Finished	Sep 09 06:42:55 AM UTC 24
Peak memory	205096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678724497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3678724497
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_smoke.3677886071
Short name	T459
Test name
Test status
Simulation time	485193229 ps
CPU time	1.98 seconds
Started	Sep 09 06:40:45 AM UTC 24
Finished	Sep 09 06:40:48 AM UTC 24
Peak memory	207872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677886071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3677886071
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_stress_all.1847787136
Short name	T212
Test name
Test status
Simulation time	221057378819 ps
CPU time	90.96 seconds
Started	Sep 09 06:41:29 AM UTC 24
Finished	Sep 09 06:43:02 AM UTC 24
Peak memory	208868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847787136 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.1847787136
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.658125936
Short name	T464
Test name
Test status
Simulation time	7442837707 ps
CPU time	11.65 seconds
Started	Sep 09 06:41:19 AM UTC 24
Finished	Sep 09 06:41:32 AM UTC 24
Peak memory	208592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658125936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.658125936
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/16.uart_tx_rx.2100676027
Short name	T460
Test name
Test status
Simulation time	3981199218 ps
CPU time	11.78 seconds
Started	Sep 09 06:40:49 AM UTC 24
Finished	Sep 09 06:41:02 AM UTC 24
Peak memory	207072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100676027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2100676027
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/16.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/160.uart_fifo_reset.1458291850
Short name	T1125
Test name
Test status
Simulation time	113602570316 ps
CPU time	166.55 seconds
Started	Sep 09 07:04:49 AM UTC 24
Finished	Sep 09 07:07:38 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458291850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1458291850
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/160.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/161.uart_fifo_reset.2948490520
Short name	T1059
Test name
Test status
Simulation time	64126410313 ps
CPU time	40.21 seconds
Started	Sep 09 07:04:50 AM UTC 24
Finished	Sep 09 07:05:32 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948490520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2948490520
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/161.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/162.uart_fifo_reset.2111504557
Short name	T1099
Test name
Test status
Simulation time	213154568788 ps
CPU time	120.57 seconds
Started	Sep 09 07:04:50 AM UTC 24
Finished	Sep 09 07:06:53 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111504557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2111504557
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/162.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/163.uart_fifo_reset.105381398
Short name	T1038
Test name
Test status
Simulation time	28288063754 ps
CPU time	7.31 seconds
Started	Sep 09 07:04:51 AM UTC 24
Finished	Sep 09 07:05:00 AM UTC 24
Peak memory	208628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105381398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.105381398
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/163.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/164.uart_fifo_reset.599403584
Short name	T1085
Test name
Test status
Simulation time	186446008973 ps
CPU time	82.79 seconds
Started	Sep 09 07:04:53 AM UTC 24
Finished	Sep 09 07:06:17 AM UTC 24
Peak memory	208712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599403584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.599403584
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/164.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/166.uart_fifo_reset.1720896266
Short name	T1053
Test name
Test status
Simulation time	25093882418 ps
CPU time	23.97 seconds
Started	Sep 09 07:04:53 AM UTC 24
Finished	Sep 09 07:05:18 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720896266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1720896266
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/166.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/167.uart_fifo_reset.1255344708
Short name	T1050
Test name
Test status
Simulation time	22324820972 ps
CPU time	17.23 seconds
Started	Sep 09 07:04:55 AM UTC 24
Finished	Sep 09 07:05:13 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255344708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1255344708
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/167.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/168.uart_fifo_reset.2798064864
Short name	T1044
Test name
Test status
Simulation time	5422936930 ps
CPU time	10.84 seconds
Started	Sep 09 07:04:57 AM UTC 24
Finished	Sep 09 07:05:09 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798064864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2798064864
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/168.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/169.uart_fifo_reset.853529667
Short name	T1103
Test name
Test status
Simulation time	162576734038 ps
CPU time	119.33 seconds
Started	Sep 09 07:04:57 AM UTC 24
Finished	Sep 09 07:06:58 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853529667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.853529667
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/169.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_alert_test.351728054
Short name	T471
Test name
Test status
Simulation time	56497479 ps
CPU time	0.8 seconds
Started	Sep 09 06:41:58 AM UTC 24
Finished	Sep 09 06:42:00 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351728054 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.351728054
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_fifo_full.1278564442
Short name	T383
Test name
Test status
Simulation time	49638239609 ps
CPU time	16.49 seconds
Started	Sep 09 06:41:39 AM UTC 24
Finished	Sep 09 06:41:57 AM UTC 24
Peak memory	208552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278564442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1278564442
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.497729193
Short name	T138
Test name
Test status
Simulation time	196946906211 ps
CPU time	156.1 seconds
Started	Sep 09 06:41:39 AM UTC 24
Finished	Sep 09 06:44:18 AM UTC 24
Peak memory	208920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497729193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.497729193
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_fifo_reset.668803895
Short name	T231
Test name
Test status
Simulation time	45063032560 ps
CPU time	18.29 seconds
Started	Sep 09 06:41:46 AM UTC 24
Finished	Sep 09 06:42:06 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668803895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.668803895
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_intr.3110799930
Short name	T388
Test name
Test status
Simulation time	15486740805 ps
CPU time	26.15 seconds
Started	Sep 09 06:41:52 AM UTC 24
Finished	Sep 09 06:42:19 AM UTC 24
Peak memory	207276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110799930 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3110799930
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.645219289
Short name	T645
Test name
Test status
Simulation time	96722942353 ps
CPU time	565.5 seconds
Started	Sep 09 06:41:55 AM UTC 24
Finished	Sep 09 06:51:28 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645219289 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.645219289
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_loopback.155656581
Short name	T472
Test name
Test status
Simulation time	2343518695 ps
CPU time	4.52 seconds
Started	Sep 09 06:41:54 AM UTC 24
Finished	Sep 09 06:42:00 AM UTC 24
Peak memory	207596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155656581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.uart_loopback.155656581
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_noise_filter.87113391
Short name	T502
Test name
Test status
Simulation time	143258685598 ps
CPU time	157.16 seconds
Started	Sep 09 06:41:52 AM UTC 24
Finished	Sep 09 06:44:32 AM UTC 24
Peak memory	217560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87113391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.87113391
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_perf.1371614989
Short name	T495
Test name
Test status
Simulation time	7729546297 ps
CPU time	110.73 seconds
Started	Sep 09 06:41:54 AM UTC 24
Finished	Sep 09 06:43:47 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371614989 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1371614989
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_rx_oversample.2679950663
Short name	T473
Test name
Test status
Simulation time	2095456323 ps
CPU time	13.65 seconds
Started	Sep 09 06:41:46 AM UTC 24
Finished	Sep 09 06:42:01 AM UTC 24
Peak memory	207204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679950663 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.2679950663
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.1222934273
Short name	T164
Test name
Test status
Simulation time	114803936777 ps
CPU time	34.36 seconds
Started	Sep 09 06:41:53 AM UTC 24
Finished	Sep 09 06:42:29 AM UTC 24
Peak memory	208660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222934273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1222934273
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.322264149
Short name	T469
Test name
Test status
Simulation time	4490415099 ps
CPU time	1.98 seconds
Started	Sep 09 06:41:52 AM UTC 24
Finished	Sep 09 06:41:55 AM UTC 24
Peak memory	204492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322264149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.322264149
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_smoke.1589302330
Short name	T467
Test name
Test status
Simulation time	738908325 ps
CPU time	2.66 seconds
Started	Sep 09 06:41:35 AM UTC 24
Finished	Sep 09 06:41:38 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589302330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1589302330
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_stress_all.4293252245
Short name	T794
Test name
Test status
Simulation time	398711682465 ps
CPU time	861.05 seconds
Started	Sep 09 06:41:57 AM UTC 24
Finished	Sep 09 06:56:27 AM UTC 24
Peak memory	212224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293252245 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.4293252245
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.1907211017
Short name	T92
Test name
Test status
Simulation time	2625943604 ps
CPU time	26.17 seconds
Started	Sep 09 06:41:55 AM UTC 24
Finished	Sep 09 06:42:23 AM UTC 24
Peak memory	224120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1907211017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all _with_rand_reset.1907211017
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.2323529073
Short name	T470
Test name
Test status
Simulation time	1874102637 ps
CPU time	3.78 seconds
Started	Sep 09 06:41:54 AM UTC 24
Finished	Sep 09 06:41:59 AM UTC 24
Peak memory	207452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323529073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2323529073
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/17.uart_tx_rx.4183122473
Short name	T370
Test name
Test status
Simulation time	9452616612 ps
CPU time	18.68 seconds
Started	Sep 09 06:41:36 AM UTC 24
Finished	Sep 09 06:41:55 AM UTC 24
Peak memory	208856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183122473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.4183122473
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/17.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/170.uart_fifo_reset.2321468033
Short name	T412
Test name
Test status
Simulation time	9967276813 ps
CPU time	8.59 seconds
Started	Sep 09 07:04:58 AM UTC 24
Finished	Sep 09 07:05:08 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321468033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2321468033
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/170.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/171.uart_fifo_reset.1622770274
Short name	T1130
Test name
Test status
Simulation time	163696665739 ps
CPU time	167.9 seconds
Started	Sep 09 07:04:59 AM UTC 24
Finished	Sep 09 07:07:49 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622770274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1622770274
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/171.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2205802496
Short name	T1052
Test name
Test status
Simulation time	11155470176 ps
CPU time	17.47 seconds
Started	Sep 09 07:04:59 AM UTC 24
Finished	Sep 09 07:05:18 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205802496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2205802496
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/172.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/173.uart_fifo_reset.1679577849
Short name	T1071
Test name
Test status
Simulation time	16238216561 ps
CPU time	46.25 seconds
Started	Sep 09 07:05:00 AM UTC 24
Finished	Sep 09 07:05:48 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679577849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1679577849
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/173.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/174.uart_fifo_reset.2013308547
Short name	T1064
Test name
Test status
Simulation time	76092613645 ps
CPU time	33.99 seconds
Started	Sep 09 07:05:00 AM UTC 24
Finished	Sep 09 07:05:35 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013308547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2013308547
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/174.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/175.uart_fifo_reset.2898166604
Short name	T1063
Test name
Test status
Simulation time	35363953020 ps
CPU time	32.76 seconds
Started	Sep 09 07:05:01 AM UTC 24
Finished	Sep 09 07:05:35 AM UTC 24
Peak memory	208632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898166604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2898166604
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/175.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/176.uart_fifo_reset.4261882007
Short name	T1084
Test name
Test status
Simulation time	33883361512 ps
CPU time	68.3 seconds
Started	Sep 09 07:05:01 AM UTC 24
Finished	Sep 09 07:06:11 AM UTC 24
Peak memory	208880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261882007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.4261882007
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/176.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/177.uart_fifo_reset.3756221161
Short name	T1058
Test name
Test status
Simulation time	39002825981 ps
CPU time	24.75 seconds
Started	Sep 09 07:05:01 AM UTC 24
Finished	Sep 09 07:05:27 AM UTC 24
Peak memory	208604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756221161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3756221161
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/177.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/179.uart_fifo_reset.2791507224
Short name	T239
Test name
Test status
Simulation time	14890321555 ps
CPU time	35.91 seconds
Started	Sep 09 07:05:05 AM UTC 24
Finished	Sep 09 07:05:42 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791507224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2791507224
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/179.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_alert_test.3894998099
Short name	T481
Test name
Test status
Simulation time	39781386 ps
CPU time	0.8 seconds
Started	Sep 09 06:42:23 AM UTC 24
Finished	Sep 09 06:42:25 AM UTC 24
Peak memory	204436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894998099 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3894998099
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.2672599969
Short name	T487
Test name
Test status
Simulation time	19566402101 ps
CPU time	62.26 seconds
Started	Sep 09 06:42:02 AM UTC 24
Finished	Sep 09 06:43:06 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672599969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2672599969
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_intr.1344852744
Short name	T373
Test name
Test status
Simulation time	20598878686 ps
CPU time	21.91 seconds
Started	Sep 09 06:42:06 AM UTC 24
Finished	Sep 09 06:42:29 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344852744 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1344852744
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.675958123
Short name	T515
Test name
Test status
Simulation time	123647651337 ps
CPU time	184.6 seconds
Started	Sep 09 06:42:21 AM UTC 24
Finished	Sep 09 06:45:28 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675958123 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.675958123
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_loopback.3936526591
Short name	T483
Test name
Test status
Simulation time	4505988565 ps
CPU time	15.38 seconds
Started	Sep 09 06:42:20 AM UTC 24
Finished	Sep 09 06:42:36 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936526591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3936526591
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_noise_filter.3924759912
Short name	T410
Test name
Test status
Simulation time	104927604838 ps
CPU time	155.1 seconds
Started	Sep 09 06:42:09 AM UTC 24
Finished	Sep 09 06:44:47 AM UTC 24
Peak memory	208804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924759912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3924759912
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_perf.2997979460
Short name	T772
Test name
Test status
Simulation time	14952938471 ps
CPU time	785.87 seconds
Started	Sep 09 06:42:21 AM UTC 24
Finished	Sep 09 06:55:35 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997979460 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2997979460
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_rx_oversample.1473679510
Short name	T486
Test name
Test status
Simulation time	6315882238 ps
CPU time	57.78 seconds
Started	Sep 09 06:42:05 AM UTC 24
Finished	Sep 09 06:43:04 AM UTC 24
Peak memory	207216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473679510 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1473679510
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.3738793013
Short name	T147
Test name
Test status
Simulation time	22236866493 ps
CPU time	65.08 seconds
Started	Sep 09 06:42:16 AM UTC 24
Finished	Sep 09 06:43:23 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738793013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3738793013
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.1324222203
Short name	T476
Test name
Test status
Simulation time	847788320 ps
CPU time	4.3 seconds
Started	Sep 09 06:42:10 AM UTC 24
Finished	Sep 09 06:42:16 AM UTC 24
Peak memory	205032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324222203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1324222203
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_smoke.3996928419
Short name	T478
Test name
Test status
Simulation time	5534818249 ps
CPU time	18.84 seconds
Started	Sep 09 06:42:00 AM UTC 24
Finished	Sep 09 06:42:20 AM UTC 24
Peak memory	208592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996928419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3996928419
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.1806422934
Short name	T479
Test name
Test status
Simulation time	2183456728 ps
CPU time	3.08 seconds
Started	Sep 09 06:42:19 AM UTC 24
Finished	Sep 09 06:42:23 AM UTC 24
Peak memory	207788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806422934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1806422934
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/18.uart_tx_rx.4220394485
Short name	T334
Test name
Test status
Simulation time	28123858872 ps
CPU time	47.38 seconds
Started	Sep 09 06:42:01 AM UTC 24
Finished	Sep 09 06:42:50 AM UTC 24
Peak memory	208620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220394485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.4220394485
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/18.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/180.uart_fifo_reset.1523158124
Short name	T1056
Test name
Test status
Simulation time	27486403895 ps
CPU time	15.56 seconds
Started	Sep 09 07:05:07 AM UTC 24
Finished	Sep 09 07:05:23 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523158124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1523158124
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/180.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/181.uart_fifo_reset.2194170459
Short name	T1083
Test name
Test status
Simulation time	20645947570 ps
CPU time	57.87 seconds
Started	Sep 09 07:05:08 AM UTC 24
Finished	Sep 09 07:06:07 AM UTC 24
Peak memory	208956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194170459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.2194170459
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/181.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/182.uart_fifo_reset.1639942220
Short name	T247
Test name
Test status
Simulation time	18793326443 ps
CPU time	16.5 seconds
Started	Sep 09 07:05:09 AM UTC 24
Finished	Sep 09 07:05:28 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639942220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1639942220
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/182.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/184.uart_fifo_reset.2698246691
Short name	T1068
Test name
Test status
Simulation time	42156728351 ps
CPU time	34.72 seconds
Started	Sep 09 07:05:10 AM UTC 24
Finished	Sep 09 07:05:47 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698246691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2698246691
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/184.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/185.uart_fifo_reset.2396211787
Short name	T1151
Test name
Test status
Simulation time	100090766038 ps
CPU time	207.23 seconds
Started	Sep 09 07:05:10 AM UTC 24
Finished	Sep 09 07:08:41 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396211787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2396211787
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/185.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/186.uart_fifo_reset.595801035
Short name	T1057
Test name
Test status
Simulation time	20288508681 ps
CPU time	11.76 seconds
Started	Sep 09 07:05:13 AM UTC 24
Finished	Sep 09 07:05:26 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595801035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.595801035
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/186.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2242325805
Short name	T1061
Test name
Test status
Simulation time	36089496523 ps
CPU time	18.12 seconds
Started	Sep 09 07:05:13 AM UTC 24
Finished	Sep 09 07:05:33 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242325805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2242325805
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/187.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/188.uart_fifo_reset.1460760634
Short name	T1159
Test name
Test status
Simulation time	353479326467 ps
CPU time	231.03 seconds
Started	Sep 09 07:05:13 AM UTC 24
Finished	Sep 09 07:09:08 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460760634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.1460760634
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/188.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/189.uart_fifo_reset.899950065
Short name	T1079
Test name
Test status
Simulation time	56481580690 ps
CPU time	45.01 seconds
Started	Sep 09 07:05:13 AM UTC 24
Finished	Sep 09 07:06:00 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899950065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.899950065
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/189.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_alert_test.2081187505
Short name	T488
Test name
Test status
Simulation time	14208088 ps
CPU time	0.85 seconds
Started	Sep 09 06:43:07 AM UTC 24
Finished	Sep 09 06:43:09 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081187505 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2081187505
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_fifo_full.953020864
Short name	T513
Test name
Test status
Simulation time	97839382403 ps
CPU time	166.51 seconds
Started	Sep 09 06:42:25 AM UTC 24
Finished	Sep 09 06:45:14 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953020864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.953020864
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.4162519772
Short name	T356
Test name
Test status
Simulation time	26309503523 ps
CPU time	19.03 seconds
Started	Sep 09 06:42:30 AM UTC 24
Finished	Sep 09 06:42:51 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162519772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.4162519772
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_fifo_reset.1457020054
Short name	T251
Test name
Test status
Simulation time	136595768909 ps
CPU time	153.01 seconds
Started	Sep 09 06:42:30 AM UTC 24
Finished	Sep 09 06:45:06 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457020054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1457020054
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_intr.1603525937
Short name	T107
Test name
Test status
Simulation time	31808825679 ps
CPU time	26.01 seconds
Started	Sep 09 06:42:36 AM UTC 24
Finished	Sep 09 06:43:04 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603525937 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.1603525937
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.228817473
Short name	T605
Test name
Test status
Simulation time	192912371788 ps
CPU time	414.78 seconds
Started	Sep 09 06:43:04 AM UTC 24
Finished	Sep 09 06:50:04 AM UTC 24
Peak memory	208852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228817473 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.228817473
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_loopback.4275591033
Short name	T493
Test name
Test status
Simulation time	12517155136 ps
CPU time	35.96 seconds
Started	Sep 09 06:43:03 AM UTC 24
Finished	Sep 09 06:43:40 AM UTC 24
Peak memory	208468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275591033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4275591033
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_noise_filter.2664026261
Short name	T499
Test name
Test status
Simulation time	150507757179 ps
CPU time	89.08 seconds
Started	Sep 09 06:42:44 AM UTC 24
Finished	Sep 09 06:44:14 AM UTC 24
Peak memory	208804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664026261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2664026261
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_perf.3906827862
Short name	T801
Test name
Test status
Simulation time	33130213491 ps
CPU time	806.7 seconds
Started	Sep 09 06:43:03 AM UTC 24
Finished	Sep 09 06:56:39 AM UTC 24
Peak memory	212204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906827862 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3906827862
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_rx_oversample.1683727979
Short name	T484
Test name
Test status
Simulation time	5867246358 ps
CPU time	30.24 seconds
Started	Sep 09 06:42:30 AM UTC 24
Finished	Sep 09 06:43:02 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683727979 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1683727979
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.3394810921
Short name	T552
Test name
Test status
Simulation time	207747792954 ps
CPU time	300.03 seconds
Started	Sep 09 06:42:52 AM UTC 24
Finished	Sep 09 06:47:55 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394810921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3394810921
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.75878889
Short name	T485
Test name
Test status
Simulation time	3211415881 ps
CPU time	12.1 seconds
Started	Sep 09 06:42:51 AM UTC 24
Finished	Sep 09 06:43:04 AM UTC 24
Peak memory	207152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75878889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.75878889
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_smoke.4162849065
Short name	T482
Test name
Test status
Simulation time	470617582 ps
CPU time	3.91 seconds
Started	Sep 09 06:42:24 AM UTC 24
Finished	Sep 09 06:42:29 AM UTC 24
Peak memory	207508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162849065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.4162849065
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_stress_all.3023143610
Short name	T145
Test name
Test status
Simulation time	306122275930 ps
CPU time	631.66 seconds
Started	Sep 09 06:43:05 AM UTC 24
Finished	Sep 09 06:53:44 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023143610 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.3023143610
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.2722407168
Short name	T114
Test name
Test status
Simulation time	2179503941 ps
CPU time	28.34 seconds
Started	Sep 09 06:43:05 AM UTC 24
Finished	Sep 09 06:43:35 AM UTC 24
Peak memory	217780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2722407168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all _with_rand_reset.2722407168
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.666134644
Short name	T376
Test name
Test status
Simulation time	12426969335 ps
CPU time	51.36 seconds
Started	Sep 09 06:42:56 AM UTC 24
Finished	Sep 09 06:43:49 AM UTC 24
Peak memory	208736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666134644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.666134644
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/19.uart_tx_rx.1430361517
Short name	T372
Test name
Test status
Simulation time	18744095990 ps
CPU time	44.74 seconds
Started	Sep 09 06:42:25 AM UTC 24
Finished	Sep 09 06:43:11 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430361517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.1430361517
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/19.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/190.uart_fifo_reset.1718543095
Short name	T1069
Test name
Test status
Simulation time	16858969480 ps
CPU time	31.94 seconds
Started	Sep 09 07:05:14 AM UTC 24
Finished	Sep 09 07:05:48 AM UTC 24
Peak memory	208548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718543095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1718543095
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/190.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/191.uart_fifo_reset.3793868542
Short name	T1088
Test name
Test status
Simulation time	32434540034 ps
CPU time	65.74 seconds
Started	Sep 09 07:05:14 AM UTC 24
Finished	Sep 09 07:06:22 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793868542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3793868542
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/191.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/192.uart_fifo_reset.535133407
Short name	T245
Test name
Test status
Simulation time	39199779782 ps
CPU time	17.46 seconds
Started	Sep 09 07:05:19 AM UTC 24
Finished	Sep 09 07:05:37 AM UTC 24
Peak memory	208640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535133407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.535133407
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/192.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3493433435
Short name	T1074
Test name
Test status
Simulation time	44106842022 ps
CPU time	32.4 seconds
Started	Sep 09 07:05:19 AM UTC 24
Finished	Sep 09 07:05:52 AM UTC 24
Peak memory	208728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493433435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3493433435
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/193.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3251130030
Short name	T1089
Test name
Test status
Simulation time	33786900232 ps
CPU time	64.98 seconds
Started	Sep 09 07:05:19 AM UTC 24
Finished	Sep 09 07:06:25 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251130030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3251130030
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/194.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/195.uart_fifo_reset.2088738641
Short name	T1137
Test name
Test status
Simulation time	108661912088 ps
CPU time	157.81 seconds
Started	Sep 09 07:05:22 AM UTC 24
Finished	Sep 09 07:08:02 AM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088738641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2088738641
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/195.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/196.uart_fifo_reset.450449209
Short name	T1153
Test name
Test status
Simulation time	192174212101 ps
CPU time	209.63 seconds
Started	Sep 09 07:05:24 AM UTC 24
Finished	Sep 09 07:08:57 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450449209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.450449209
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/196.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/197.uart_fifo_reset.3849999295
Short name	T1098
Test name
Test status
Simulation time	161418827514 ps
CPU time	83.03 seconds
Started	Sep 09 07:05:27 AM UTC 24
Finished	Sep 09 07:06:52 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849999295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3849999295
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/197.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/198.uart_fifo_reset.3326566610
Short name	T1065
Test name
Test status
Simulation time	30434055253 ps
CPU time	13.47 seconds
Started	Sep 09 07:05:28 AM UTC 24
Finished	Sep 09 07:05:43 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326566610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3326566610
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/198.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1621695194
Short name	T1124
Test name
Test status
Simulation time	36080597634 ps
CPU time	126.31 seconds
Started	Sep 09 07:05:29 AM UTC 24
Finished	Sep 09 07:07:38 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621695194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1621695194
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/199.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_alert_test.3462435872
Short name	T34
Test name
Test status
Simulation time	30218486 ps
CPU time	0.78 seconds
Started	Sep 09 06:30:10 AM UTC 24
Finished	Sep 09 06:30:12 AM UTC 24
Peak memory	204380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462435872 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3462435872
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_fifo_full.3616956846
Short name	T313
Test name
Test status
Simulation time	22916604098 ps
CPU time	78.8 seconds
Started	Sep 09 06:29:40 AM UTC 24
Finished	Sep 09 06:31:01 AM UTC 24
Peak memory	208752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616956846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3616956846
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.1576955749
Short name	T17
Test name
Test status
Simulation time	28214935587 ps
CPU time	43.65 seconds
Started	Sep 09 06:29:40 AM UTC 24
Finished	Sep 09 06:30:25 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576955749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1576955749
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_fifo_reset.3042909826
Short name	T121
Test name
Test status
Simulation time	64765961707 ps
CPU time	141.2 seconds
Started	Sep 09 06:29:40 AM UTC 24
Finished	Sep 09 06:32:04 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042909826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3042909826
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_intr.5551368
Short name	T27
Test name
Test status
Simulation time	17925723800 ps
CPU time	43.67 seconds
Started	Sep 09 06:29:44 AM UTC 24
Finished	Sep 09 06:30:29 AM UTC 24
Peak memory	207796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5551368 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.5551368
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_loopback.2989515633
Short name	T26
Test name
Test status
Simulation time	7335398827 ps
CPU time	9.19 seconds
Started	Sep 09 06:29:53 AM UTC 24
Finished	Sep 09 06:30:03 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989515633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2989515633
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_perf.4093737313
Short name	T305
Test name
Test status
Simulation time	15354168849 ps
CPU time	275.56 seconds
Started	Sep 09 06:29:58 AM UTC 24
Finished	Sep 09 06:34:37 AM UTC 24
Peak memory	208976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093737313 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.4093737313
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_rx_oversample.1912035340
Short name	T45
Test name
Test status
Simulation time	1503779523 ps
CPU time	2.27 seconds
Started	Sep 09 06:29:42 AM UTC 24
Finished	Sep 09 06:29:46 AM UTC 24
Peak memory	207224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912035340 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1912035340
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.2426555416
Short name	T292
Test name
Test status
Simulation time	21860298977 ps
CPU time	69.74 seconds
Started	Sep 09 06:29:48 AM UTC 24
Finished	Sep 09 06:30:59 AM UTC 24
Peak memory	207148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426555416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2426555416
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_sec_cm.976011884
Short name	T35
Test name
Test status
Simulation time	207899224 ps
CPU time	1.22 seconds
Started	Sep 09 06:30:07 AM UTC 24
Finished	Sep 09 06:30:10 AM UTC 24
Peak memory	237448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976011884 -assert nopostproc +UVM_TESTNAME=uart_ba se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.976011884
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_smoke.2461224868
Short name	T44
Test name
Test status
Simulation time	104729569 ps
CPU time	1.36 seconds
Started	Sep 09 06:29:39 AM UTC 24
Finished	Sep 09 06:29:42 AM UTC 24
Peak memory	206512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461224868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2461224868
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.751349631
Short name	T23
Test name
Test status
Simulation time	1996061675 ps
CPU time	3.67 seconds
Started	Sep 09 06:29:53 AM UTC 24
Finished	Sep 09 06:29:57 AM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751349631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.751349631
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/2.uart_tx_rx.567830649
Short name	T117
Test name
Test status
Simulation time	32354756056 ps
CPU time	48.21 seconds
Started	Sep 09 06:29:39 AM UTC 24
Finished	Sep 09 06:30:29 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567830649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.567830649
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/2.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_alert_test.3692510415
Short name	T497
Test name
Test status
Simulation time	147786192 ps
CPU time	0.8 seconds
Started	Sep 09 06:43:50 AM UTC 24
Finished	Sep 09 06:43:52 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692510415 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3692510415
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_fifo_full.3949600969
Short name	T784
Test name
Test status
Simulation time	283324381639 ps
CPU time	763.24 seconds
Started	Sep 09 06:43:12 AM UTC 24
Finished	Sep 09 06:56:04 AM UTC 24
Peak memory	212496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949600969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3949600969
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.3161826138
Short name	T353
Test name
Test status
Simulation time	126234581693 ps
CPU time	129.91 seconds
Started	Sep 09 06:43:15 AM UTC 24
Finished	Sep 09 06:45:27 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161826138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.3161826138
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_fifo_reset.2813013209
Short name	T190
Test name
Test status
Simulation time	93701161677 ps
CPU time	65.8 seconds
Started	Sep 09 06:43:17 AM UTC 24
Finished	Sep 09 06:44:24 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813013209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2813013209
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_intr.3368521583
Short name	T610
Test name
Test status
Simulation time	92284501483 ps
CPU time	404.48 seconds
Started	Sep 09 06:43:26 AM UTC 24
Finished	Sep 09 06:50:15 AM UTC 24
Peak memory	208676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368521583 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3368521583
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.3820102006
Short name	T574
Test name
Test status
Simulation time	171733353888 ps
CPU time	316.69 seconds
Started	Sep 09 06:43:41 AM UTC 24
Finished	Sep 09 06:49:02 AM UTC 24
Peak memory	208852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820102006 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3820102006
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_loopback.557075360
Short name	T496
Test name
Test status
Simulation time	2990531466 ps
CPU time	9.04 seconds
Started	Sep 09 06:43:40 AM UTC 24
Finished	Sep 09 06:43:50 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557075360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.uart_loopback.557075360
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_noise_filter.2675637141
Short name	T569
Test name
Test status
Simulation time	107502318703 ps
CPU time	319.24 seconds
Started	Sep 09 06:43:30 AM UTC 24
Finished	Sep 09 06:48:53 AM UTC 24
Peak memory	209028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675637141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2675637141
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_perf.1927923304
Short name	T577
Test name
Test status
Simulation time	27308980237 ps
CPU time	330.24 seconds
Started	Sep 09 06:43:41 AM UTC 24
Finished	Sep 09 06:49:16 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927923304 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1927923304
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_rx_oversample.1297385442
Short name	T503
Test name
Test status
Simulation time	6547917829 ps
CPU time	70.03 seconds
Started	Sep 09 06:43:24 AM UTC 24
Finished	Sep 09 06:44:35 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297385442 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1297385442
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.999139783
Short name	T501
Test name
Test status
Simulation time	13879407810 ps
CPU time	53.74 seconds
Started	Sep 09 06:43:36 AM UTC 24
Finished	Sep 09 06:44:32 AM UTC 24
Peak memory	208488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999139783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.999139783
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.2898236798
Short name	T492
Test name
Test status
Simulation time	765330654 ps
CPU time	3.27 seconds
Started	Sep 09 06:43:35 AM UTC 24
Finished	Sep 09 06:43:39 AM UTC 24
Peak memory	205032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898236798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2898236798
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_smoke.2198082806
Short name	T489
Test name
Test status
Simulation time	435160690 ps
CPU time	2.28 seconds
Started	Sep 09 06:43:10 AM UTC 24
Finished	Sep 09 06:43:14 AM UTC 24
Peak memory	207168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198082806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2198082806
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_stress_all.3875371467
Short name	T694
Test name
Test status
Simulation time	42918862304 ps
CPU time	558.22 seconds
Started	Sep 09 06:43:49 AM UTC 24
Finished	Sep 09 06:53:14 AM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875371467 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3875371467
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.1018303857
Short name	T336
Test name
Test status
Simulation time	2948463974 ps
CPU time	78.82 seconds
Started	Sep 09 06:43:44 AM UTC 24
Finished	Sep 09 06:45:05 AM UTC 24
Peak memory	217740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1018303857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all _with_rand_reset.1018303857
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1000571814
Short name	T494
Test name
Test status
Simulation time	570296929 ps
CPU time	3.47 seconds
Started	Sep 09 06:43:36 AM UTC 24
Finished	Sep 09 06:43:41 AM UTC 24
Peak memory	207212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000571814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1000571814
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/20.uart_tx_rx.1567365830
Short name	T539
Test name
Test status
Simulation time	79689708176 ps
CPU time	212.94 seconds
Started	Sep 09 06:43:12 AM UTC 24
Finished	Sep 09 06:46:49 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567365830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1567365830
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/20.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/200.uart_fifo_reset.2755344427
Short name	T1105
Test name
Test status
Simulation time	144820641923 ps
CPU time	85.34 seconds
Started	Sep 09 07:05:33 AM UTC 24
Finished	Sep 09 07:07:00 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755344427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2755344427
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/200.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3485751376
Short name	T1075
Test name
Test status
Simulation time	37020574776 ps
CPU time	20.51 seconds
Started	Sep 09 07:05:33 AM UTC 24
Finished	Sep 09 07:05:55 AM UTC 24
Peak memory	207748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485751376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3485751376
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/201.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3110342920
Short name	T1110
Test name
Test status
Simulation time	43453033141 ps
CPU time	94.1 seconds
Started	Sep 09 07:05:33 AM UTC 24
Finished	Sep 09 07:07:09 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110342920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3110342920
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/202.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2699845991
Short name	T1093
Test name
Test status
Simulation time	39311446388 ps
CPU time	65.25 seconds
Started	Sep 09 07:05:34 AM UTC 24
Finished	Sep 09 07:06:41 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699845991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2699845991
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/203.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/204.uart_fifo_reset.1024504508
Short name	T1162
Test name
Test status
Simulation time	107262686076 ps
CPU time	213.87 seconds
Started	Sep 09 07:05:34 AM UTC 24
Finished	Sep 09 07:09:11 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024504508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1024504508
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/204.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/205.uart_fifo_reset.3391519189
Short name	T1080
Test name
Test status
Simulation time	51624752389 ps
CPU time	23.01 seconds
Started	Sep 09 07:05:37 AM UTC 24
Finished	Sep 09 07:06:01 AM UTC 24
Peak memory	208668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391519189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3391519189
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/205.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/206.uart_fifo_reset.345049601
Short name	T1109
Test name
Test status
Simulation time	161781502780 ps
CPU time	85.46 seconds
Started	Sep 09 07:05:37 AM UTC 24
Finished	Sep 09 07:07:04 AM UTC 24
Peak memory	208332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345049601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.345049601
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/206.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2139001638
Short name	T1188
Test name
Test status
Simulation time	157380496867 ps
CPU time	879.32 seconds
Started	Sep 09 07:05:38 AM UTC 24
Finished	Sep 09 07:20:27 AM UTC 24
Peak memory	212228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139001638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2139001638
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/207.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2275915887
Short name	T1095
Test name
Test status
Simulation time	43111824833 ps
CPU time	61.91 seconds
Started	Sep 09 07:05:44 AM UTC 24
Finished	Sep 09 07:06:47 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275915887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2275915887
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/209.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_alert_test.1375555127
Short name	T507
Test name
Test status
Simulation time	111156645 ps
CPU time	0.81 seconds
Started	Sep 09 06:44:48 AM UTC 24
Finished	Sep 09 06:44:50 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375555127 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1375555127
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_fifo_full.3770899378
Short name	T514
Test name
Test status
Simulation time	43571057738 ps
CPU time	88.98 seconds
Started	Sep 09 06:43:57 AM UTC 24
Finished	Sep 09 06:45:28 AM UTC 24
Peak memory	208856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770899378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3770899378
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.3928904103
Short name	T150
Test name
Test status
Simulation time	107111083880 ps
CPU time	116.31 seconds
Started	Sep 09 06:44:15 AM UTC 24
Finished	Sep 09 06:46:13 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928904103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3928904103
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_fifo_reset.391026914
Short name	T530
Test name
Test status
Simulation time	33776317043 ps
CPU time	115.74 seconds
Started	Sep 09 06:44:19 AM UTC 24
Finished	Sep 09 06:46:17 AM UTC 24
Peak memory	208680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391026914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.391026914
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.794080413
Short name	T348
Test name
Test status
Simulation time	73581370051 ps
CPU time	271.28 seconds
Started	Sep 09 06:44:42 AM UTC 24
Finished	Sep 09 06:49:17 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794080413 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.794080413
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_loopback.3566573383
Short name	T512
Test name
Test status
Simulation time	10406536701 ps
CPU time	30.73 seconds
Started	Sep 09 06:44:38 AM UTC 24
Finished	Sep 09 06:45:10 AM UTC 24
Peak memory	208084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566573383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.3566573383
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_noise_filter.2893963732
Short name	T399
Test name
Test status
Simulation time	38657934276 ps
CPU time	28.15 seconds
Started	Sep 09 06:44:25 AM UTC 24
Finished	Sep 09 06:44:55 AM UTC 24
Peak memory	207372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893963732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2893963732
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_perf.3139081108
Short name	T751
Test name
Test status
Simulation time	9039541868 ps
CPU time	617.89 seconds
Started	Sep 09 06:44:40 AM UTC 24
Finished	Sep 09 06:55:05 AM UTC 24
Peak memory	210376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139081108 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3139081108
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_rx_oversample.3072083943
Short name	T509
Test name
Test status
Simulation time	6096272387 ps
CPU time	34.41 seconds
Started	Sep 09 06:44:19 AM UTC 24
Finished	Sep 09 06:44:55 AM UTC 24
Peak memory	207064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072083943 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3072083943
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.2626893114
Short name	T510
Test name
Test status
Simulation time	176631298007 ps
CPU time	21.77 seconds
Started	Sep 09 06:44:32 AM UTC 24
Finished	Sep 09 06:44:55 AM UTC 24
Peak memory	208636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626893114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2626893114
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.2634554785
Short name	T504
Test name
Test status
Simulation time	3435755929 ps
CPU time	3.48 seconds
Started	Sep 09 06:44:32 AM UTC 24
Finished	Sep 09 06:44:37 AM UTC 24
Peak memory	205224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634554785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2634554785
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_smoke.2594771011
Short name	T498
Test name
Test status
Simulation time	554004372 ps
CPU time	3.64 seconds
Started	Sep 09 06:43:52 AM UTC 24
Finished	Sep 09 06:43:57 AM UTC 24
Peak memory	208560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594771011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2594771011
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_stress_all.3358943998
Short name	T321
Test name
Test status
Simulation time	180866266385 ps
CPU time	151.22 seconds
Started	Sep 09 06:44:46 AM UTC 24
Finished	Sep 09 06:47:19 AM UTC 24
Peak memory	217784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358943998 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.3358943998
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.3237942463
Short name	T522
Test name
Test status
Simulation time	21227668359 ps
CPU time	55.4 seconds
Started	Sep 09 06:44:42 AM UTC 24
Finished	Sep 09 06:45:39 AM UTC 24
Peak memory	225324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3237942463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all _with_rand_reset.3237942463
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.2772201332
Short name	T506
Test name
Test status
Simulation time	621105420 ps
CPU time	3.64 seconds
Started	Sep 09 06:44:36 AM UTC 24
Finished	Sep 09 06:44:41 AM UTC 24
Peak memory	207504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772201332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2772201332
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/21.uart_tx_rx.1493218672
Short name	T500
Test name
Test status
Simulation time	17327928596 ps
CPU time	24.76 seconds
Started	Sep 09 06:43:53 AM UTC 24
Finished	Sep 09 06:44:19 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493218672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1493218672
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/21.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/210.uart_fifo_reset.3396442485
Short name	T1091
Test name
Test status
Simulation time	34841298403 ps
CPU time	45.08 seconds
Started	Sep 09 07:05:45 AM UTC 24
Finished	Sep 09 07:06:31 AM UTC 24
Peak memory	208480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396442485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3396442485
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/210.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/211.uart_fifo_reset.365759935
Short name	T1077
Test name
Test status
Simulation time	28997677223 ps
CPU time	12.36 seconds
Started	Sep 09 07:05:46 AM UTC 24
Finished	Sep 09 07:06:00 AM UTC 24
Peak memory	208496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365759935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.365759935
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/211.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/212.uart_fifo_reset.193048681
Short name	T1087
Test name
Test status
Simulation time	313769661030 ps
CPU time	31.18 seconds
Started	Sep 09 07:05:48 AM UTC 24
Finished	Sep 09 07:06:20 AM UTC 24
Peak memory	208604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193048681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.193048681
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/212.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/213.uart_fifo_reset.3020590829
Short name	T1150
Test name
Test status
Simulation time	65010937953 ps
CPU time	169.26 seconds
Started	Sep 09 07:05:48 AM UTC 24
Finished	Sep 09 07:08:40 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020590829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3020590829
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/213.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1540977288
Short name	T1119
Test name
Test status
Simulation time	95393206408 ps
CPU time	91.2 seconds
Started	Sep 09 07:05:49 AM UTC 24
Finished	Sep 09 07:07:22 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540977288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1540977288
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/214.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/215.uart_fifo_reset.1977548617
Short name	T1076
Test name
Test status
Simulation time	9156407858 ps
CPU time	4.69 seconds
Started	Sep 09 07:05:49 AM UTC 24
Finished	Sep 09 07:05:55 AM UTC 24
Peak memory	207948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977548617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1977548617
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/215.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/216.uart_fifo_reset.761282569
Short name	T1120
Test name
Test status
Simulation time	76467203171 ps
CPU time	95.08 seconds
Started	Sep 09 07:05:50 AM UTC 24
Finished	Sep 09 07:07:27 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761282569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.761282569
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/216.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3137545745
Short name	T1121
Test name
Test status
Simulation time	39796044418 ps
CPU time	96.34 seconds
Started	Sep 09 07:05:50 AM UTC 24
Finished	Sep 09 07:07:29 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137545745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3137545745
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/217.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/218.uart_fifo_reset.431755160
Short name	T253
Test name
Test status
Simulation time	95913575126 ps
CPU time	26.79 seconds
Started	Sep 09 07:05:54 AM UTC 24
Finished	Sep 09 07:06:21 AM UTC 24
Peak memory	208592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431755160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.431755160
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/218.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/219.uart_fifo_reset.2352645034
Short name	T1184
Test name
Test status
Simulation time	104716385018 ps
CPU time	478.99 seconds
Started	Sep 09 07:05:54 AM UTC 24
Finished	Sep 09 07:13:59 AM UTC 24
Peak memory	212136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352645034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2352645034
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/219.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_alert_test.2308183001
Short name	T519
Test name
Test status
Simulation time	48221761 ps
CPU time	0.82 seconds
Started	Sep 09 06:45:30 AM UTC 24
Finished	Sep 09 06:45:32 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308183001 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2308183001
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_fifo_full.2918075066
Short name	T134
Test name
Test status
Simulation time	34941097274 ps
CPU time	12.12 seconds
Started	Sep 09 06:44:55 AM UTC 24
Finished	Sep 09 06:45:08 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918075066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2918075066
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.542567280
Short name	T157
Test name
Test status
Simulation time	257103451928 ps
CPU time	77.21 seconds
Started	Sep 09 06:44:55 AM UTC 24
Finished	Sep 09 06:46:14 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542567280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.542567280
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_fifo_reset.1634866292
Short name	T229
Test name
Test status
Simulation time	132550423196 ps
CPU time	54.78 seconds
Started	Sep 09 06:44:56 AM UTC 24
Finished	Sep 09 06:45:53 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634866292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1634866292
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_intr.3029621616
Short name	T511
Test name
Test status
Simulation time	4893460138 ps
CPU time	2.36 seconds
Started	Sep 09 06:45:05 AM UTC 24
Finished	Sep 09 06:45:09 AM UTC 24
Peak memory	207148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029621616 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3029621616
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.842217107
Short name	T595
Test name
Test status
Simulation time	80984022565 ps
CPU time	250.5 seconds
Started	Sep 09 06:45:29 AM UTC 24
Finished	Sep 09 06:49:44 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842217107 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.842217107
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_loopback.1202406488
Short name	T520
Test name
Test status
Simulation time	11329837827 ps
CPU time	19.21 seconds
Started	Sep 09 06:45:15 AM UTC 24
Finished	Sep 09 06:45:35 AM UTC 24
Peak memory	207912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202406488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1202406488
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_noise_filter.87692763
Short name	T562
Test name
Test status
Simulation time	78590700752 ps
CPU time	203.19 seconds
Started	Sep 09 06:45:07 AM UTC 24
Finished	Sep 09 06:48:33 AM UTC 24
Peak memory	208560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87692763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.87692763
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_perf.1897168064
Short name	T566
Test name
Test status
Simulation time	4385555397 ps
CPU time	190.34 seconds
Started	Sep 09 06:45:28 AM UTC 24
Finished	Sep 09 06:48:42 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897168064 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1897168064
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_rx_oversample.2498763573
Short name	T523
Test name
Test status
Simulation time	4828851630 ps
CPU time	35.38 seconds
Started	Sep 09 06:45:02 AM UTC 24
Finished	Sep 09 06:45:39 AM UTC 24
Peak memory	208612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498763573 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2498763573
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.3496987445
Short name	T518
Test name
Test status
Simulation time	12938413584 ps
CPU time	20.05 seconds
Started	Sep 09 06:45:10 AM UTC 24
Finished	Sep 09 06:45:31 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496987445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.3496987445
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.1980158299
Short name	T517
Test name
Test status
Simulation time	44936047229 ps
CPU time	18.61 seconds
Started	Sep 09 06:45:10 AM UTC 24
Finished	Sep 09 06:45:29 AM UTC 24
Peak memory	205096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980158299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1980158299
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_smoke.195072167
Short name	T508
Test name
Test status
Simulation time	332007365 ps
CPU time	1.76 seconds
Started	Sep 09 06:44:50 AM UTC 24
Finished	Sep 09 06:44:53 AM UTC 24
Peak memory	206384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195072167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 22.uart_smoke.195072167
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_stress_all.3612077062
Short name	T670
Test name
Test status
Simulation time	284787072322 ps
CPU time	402.17 seconds
Started	Sep 09 06:45:29 AM UTC 24
Finished	Sep 09 06:52:16 AM UTC 24
Peak memory	221820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612077062 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3612077062
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.3913339089
Short name	T93
Test name
Test status
Simulation time	2957483988 ps
CPU time	30.21 seconds
Started	Sep 09 06:45:29 AM UTC 24
Finished	Sep 09 06:46:01 AM UTC 24
Peak memory	208840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3913339089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all _with_rand_reset.3913339089
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.3583981706
Short name	T516
Test name
Test status
Simulation time	9194583150 ps
CPU time	16.49 seconds
Started	Sep 09 06:45:11 AM UTC 24
Finished	Sep 09 06:45:28 AM UTC 24
Peak memory	208344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583981706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3583981706
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/22.uart_tx_rx.1189917192
Short name	T598
Test name
Test status
Simulation time	58271156133 ps
CPU time	300.3 seconds
Started	Sep 09 06:44:53 AM UTC 24
Finished	Sep 09 06:49:57 AM UTC 24
Peak memory	208728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189917192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1189917192
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/22.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/220.uart_fifo_reset.3733497364
Short name	T1152
Test name
Test status
Simulation time	362185232653 ps
CPU time	165.51 seconds
Started	Sep 09 07:05:56 AM UTC 24
Finished	Sep 09 07:08:44 AM UTC 24
Peak memory	208432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733497364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.3733497364
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/220.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/221.uart_fifo_reset.148269042
Short name	T1178
Test name
Test status
Simulation time	93900892879 ps
CPU time	284.31 seconds
Started	Sep 09 07:05:56 AM UTC 24
Finished	Sep 09 07:10:44 AM UTC 24
Peak memory	208292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148269042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.148269042
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/221.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/222.uart_fifo_reset.415598953
Short name	T1097
Test name
Test status
Simulation time	18560184895 ps
CPU time	49.48 seconds
Started	Sep 09 07:06:01 AM UTC 24
Finished	Sep 09 07:06:52 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415598953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.415598953
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/222.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/224.uart_fifo_reset.52522041
Short name	T207
Test name
Test status
Simulation time	119256114495 ps
CPU time	182.77 seconds
Started	Sep 09 07:06:01 AM UTC 24
Finished	Sep 09 07:09:06 AM UTC 24
Peak memory	208800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52522041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.52522041
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/224.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/225.uart_fifo_reset.2363922344
Short name	T1104
Test name
Test status
Simulation time	136016379115 ps
CPU time	56.11 seconds
Started	Sep 09 07:06:02 AM UTC 24
Finished	Sep 09 07:07:00 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363922344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.2363922344
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/225.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2023810434
Short name	T1116
Test name
Test status
Simulation time	212478899086 ps
CPU time	71.37 seconds
Started	Sep 09 07:06:05 AM UTC 24
Finished	Sep 09 07:07:18 AM UTC 24
Peak memory	208628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023810434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2023810434
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/226.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/228.uart_fifo_reset.1319482969
Short name	T1096
Test name
Test status
Simulation time	81455470740 ps
CPU time	41.43 seconds
Started	Sep 09 07:06:07 AM UTC 24
Finished	Sep 09 07:06:50 AM UTC 24
Peak memory	208812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319482969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1319482969
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/228.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/229.uart_fifo_reset.47938023
Short name	T1163
Test name
Test status
Simulation time	76007057532 ps
CPU time	183.08 seconds
Started	Sep 09 07:06:08 AM UTC 24
Finished	Sep 09 07:09:14 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47938023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.47938023
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/229.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_alert_test.2481237919
Short name	T528
Test name
Test status
Simulation time	15393642 ps
CPU time	0.84 seconds
Started	Sep 09 06:46:10 AM UTC 24
Finished	Sep 09 06:46:11 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481237919 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2481237919
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_fifo_full.92459903
Short name	T415
Test name
Test status
Simulation time	33341985347 ps
CPU time	68.48 seconds
Started	Sep 09 06:45:36 AM UTC 24
Finished	Sep 09 06:46:47 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92459903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.92459903
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.2604337952
Short name	T535
Test name
Test status
Simulation time	138676363741 ps
CPU time	54.48 seconds
Started	Sep 09 06:45:38 AM UTC 24
Finished	Sep 09 06:46:34 AM UTC 24
Peak memory	208312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604337952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2604337952
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_fifo_reset.4165144043
Short name	T191
Test name
Test status
Simulation time	68244293146 ps
CPU time	159.97 seconds
Started	Sep 09 06:45:40 AM UTC 24
Finished	Sep 09 06:48:22 AM UTC 24
Peak memory	208732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165144043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.4165144043
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_intr.1021627917
Short name	T110
Test name
Test status
Simulation time	39609567364 ps
CPU time	80.72 seconds
Started	Sep 09 06:45:40 AM UTC 24
Finished	Sep 09 06:47:02 AM UTC 24
Peak memory	208916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021627917 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1021627917
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.4103702150
Short name	T1070
Test name
Test status
Simulation time	123703261925 ps
CPU time	1181.4 seconds
Started	Sep 09 06:45:53 AM UTC 24
Finished	Sep 09 07:05:48 AM UTC 24
Peak memory	212344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103702150 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.4103702150
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_loopback.1923701062
Short name	T526
Test name
Test status
Simulation time	9330659084 ps
CPU time	6.39 seconds
Started	Sep 09 06:45:53 AM UTC 24
Finished	Sep 09 06:46:01 AM UTC 24
Peak memory	208716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923701062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1923701062
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_noise_filter.2748726740
Short name	T532
Test name
Test status
Simulation time	41822962479 ps
CPU time	41.15 seconds
Started	Sep 09 06:45:41 AM UTC 24
Finished	Sep 09 06:46:24 AM UTC 24
Peak memory	208840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748726740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2748726740
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_perf.2751065347
Short name	T551
Test name
Test status
Simulation time	19445511557 ps
CPU time	118.93 seconds
Started	Sep 09 06:45:53 AM UTC 24
Finished	Sep 09 06:47:54 AM UTC 24
Peak memory	208728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751065347 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2751065347
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_rx_oversample.3243060617
Short name	T527
Test name
Test status
Simulation time	2960474891 ps
CPU time	27.78 seconds
Started	Sep 09 06:45:40 AM UTC 24
Finished	Sep 09 06:46:09 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243060617 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.3243060617
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.2458837317
Short name	T624
Test name
Test status
Simulation time	164764164287 ps
CPU time	289.82 seconds
Started	Sep 09 06:45:46 AM UTC 24
Finished	Sep 09 06:50:40 AM UTC 24
Peak memory	208772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458837317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2458837317
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.811940215
Short name	T524
Test name
Test status
Simulation time	3426383368 ps
CPU time	6.13 seconds
Started	Sep 09 06:45:45 AM UTC 24
Finished	Sep 09 06:45:52 AM UTC 24
Peak memory	205096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811940215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.811940215
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_smoke.715693472
Short name	T521
Test name
Test status
Simulation time	658129782 ps
CPU time	3.85 seconds
Started	Sep 09 06:45:31 AM UTC 24
Finished	Sep 09 06:45:36 AM UTC 24
Peak memory	208100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715693472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 23.uart_smoke.715693472
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_stress_all.2681756286
Short name	T840
Test name
Test status
Simulation time	185942139757 ps
CPU time	713.72 seconds
Started	Sep 09 06:46:01 AM UTC 24
Finished	Sep 09 06:58:03 AM UTC 24
Peak memory	212428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681756286 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2681756286
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.843792410
Short name	T94
Test name
Test status
Simulation time	10398430604 ps
CPU time	54.39 seconds
Started	Sep 09 06:46:01 AM UTC 24
Finished	Sep 09 06:46:57 AM UTC 24
Peak memory	217720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=843792410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all_ with_rand_reset.843792410
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.459384079
Short name	T525
Test name
Test status
Simulation time	1102426260 ps
CPU time	3.19 seconds
Started	Sep 09 06:45:48 AM UTC 24
Finished	Sep 09 06:45:52 AM UTC 24
Peak memory	207912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459384079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.459384079
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/23.uart_tx_rx.3830697664
Short name	T311
Test name
Test status
Simulation time	47570172662 ps
CPU time	33.71 seconds
Started	Sep 09 06:45:33 AM UTC 24
Finished	Sep 09 06:46:09 AM UTC 24
Peak memory	208812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830697664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3830697664
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/23.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/230.uart_fifo_reset.1409251320
Short name	T1157
Test name
Test status
Simulation time	183270177083 ps
CPU time	169.06 seconds
Started	Sep 09 07:06:12 AM UTC 24
Finished	Sep 09 07:09:04 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409251320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1409251320
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/230.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/232.uart_fifo_reset.1524399218
Short name	T1101
Test name
Test status
Simulation time	20303256093 ps
CPU time	36.17 seconds
Started	Sep 09 07:06:18 AM UTC 24
Finished	Sep 09 07:06:55 AM UTC 24
Peak memory	207160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524399218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1524399218
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/232.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/234.uart_fifo_reset.4006149504
Short name	T1114
Test name
Test status
Simulation time	23472827969 ps
CPU time	50.56 seconds
Started	Sep 09 07:06:21 AM UTC 24
Finished	Sep 09 07:07:13 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006149504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.4006149504
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/234.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3866250465
Short name	T1155
Test name
Test status
Simulation time	101787289734 ps
CPU time	155.6 seconds
Started	Sep 09 07:06:22 AM UTC 24
Finished	Sep 09 07:09:00 AM UTC 24
Peak memory	207996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866250465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3866250465
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/235.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/236.uart_fifo_reset.1199983796
Short name	T1107
Test name
Test status
Simulation time	53487772947 ps
CPU time	37.71 seconds
Started	Sep 09 07:06:23 AM UTC 24
Finished	Sep 09 07:07:02 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199983796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1199983796
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/236.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/237.uart_fifo_reset.4189687328
Short name	T1118
Test name
Test status
Simulation time	73087876157 ps
CPU time	54.34 seconds
Started	Sep 09 07:06:26 AM UTC 24
Finished	Sep 09 07:07:22 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189687328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.4189687328
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/237.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/238.uart_fifo_reset.1983891770
Short name	T1117
Test name
Test status
Simulation time	29470210959 ps
CPU time	51.15 seconds
Started	Sep 09 07:06:29 AM UTC 24
Finished	Sep 09 07:07:22 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983891770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1983891770
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/238.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/239.uart_fifo_reset.440300513
Short name	T1181
Test name
Test status
Simulation time	145831487097 ps
CPU time	296.46 seconds
Started	Sep 09 07:06:32 AM UTC 24
Finished	Sep 09 07:11:33 AM UTC 24
Peak memory	212164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440300513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.440300513
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/239.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_alert_test.466788958
Short name	T538
Test name
Test status
Simulation time	20884591 ps
CPU time	0.83 seconds
Started	Sep 09 06:46:46 AM UTC 24
Finished	Sep 09 06:46:48 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466788958 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.466788958
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_fifo_full.970240708
Short name	T548
Test name
Test status
Simulation time	42432466628 ps
CPU time	74.95 seconds
Started	Sep 09 06:46:13 AM UTC 24
Finished	Sep 09 06:47:29 AM UTC 24
Peak memory	208592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970240708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.970240708
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3489052237
Short name	T377
Test name
Test status
Simulation time	136712461105 ps
CPU time	133 seconds
Started	Sep 09 06:46:14 AM UTC 24
Finished	Sep 09 06:48:29 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489052237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3489052237
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_fifo_reset.2082190522
Short name	T618
Test name
Test status
Simulation time	122455887815 ps
CPU time	248.58 seconds
Started	Sep 09 06:46:14 AM UTC 24
Finished	Sep 09 06:50:26 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082190522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2082190522
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_intr.3428455196
Short name	T536
Test name
Test status
Simulation time	7024154277 ps
CPU time	19.94 seconds
Started	Sep 09 06:46:18 AM UTC 24
Finished	Sep 09 06:46:39 AM UTC 24
Peak memory	208676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428455196 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3428455196
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.2054903862
Short name	T739
Test name
Test status
Simulation time	62804842552 ps
CPU time	485.28 seconds
Started	Sep 09 06:46:34 AM UTC 24
Finished	Sep 09 06:54:45 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054903862 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2054903862
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_loopback.1420483374
Short name	T537
Test name
Test status
Simulation time	4966744559 ps
CPU time	13.64 seconds
Started	Sep 09 06:46:30 AM UTC 24
Finished	Sep 09 06:46:45 AM UTC 24
Peak memory	208728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420483374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1420483374
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_noise_filter.3244013624
Short name	T403
Test name
Test status
Simulation time	36120733427 ps
CPU time	79.86 seconds
Started	Sep 09 06:46:20 AM UTC 24
Finished	Sep 09 06:47:42 AM UTC 24
Peak memory	208852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244013624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3244013624
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_perf.2134642816
Short name	T719
Test name
Test status
Simulation time	8285403190 ps
CPU time	448 seconds
Started	Sep 09 06:46:31 AM UTC 24
Finished	Sep 09 06:54:04 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134642816 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2134642816
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_rx_oversample.2681171866
Short name	T533
Test name
Test status
Simulation time	1885357016 ps
CPU time	8.52 seconds
Started	Sep 09 06:46:15 AM UTC 24
Finished	Sep 09 06:46:24 AM UTC 24
Peak memory	207352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681171866 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.2681171866
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.601010981
Short name	T154
Test name
Test status
Simulation time	28778111440 ps
CPU time	45.95 seconds
Started	Sep 09 06:46:25 AM UTC 24
Finished	Sep 09 06:47:13 AM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601010981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.601010981
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.1319329035
Short name	T365
Test name
Test status
Simulation time	2109438514 ps
CPU time	4.68 seconds
Started	Sep 09 06:46:24 AM UTC 24
Finished	Sep 09 06:46:30 AM UTC 24
Peak memory	205032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319329035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1319329035
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_smoke.1113292553
Short name	T529
Test name
Test status
Simulation time	754599342 ps
CPU time	2.29 seconds
Started	Sep 09 06:46:10 AM UTC 24
Finished	Sep 09 06:46:13 AM UTC 24
Peak memory	207528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113292553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1113292553
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_stress_all.3847535495
Short name	T839
Test name
Test status
Simulation time	291391948813 ps
CPU time	674.71 seconds
Started	Sep 09 06:46:40 AM UTC 24
Finished	Sep 09 06:58:02 AM UTC 24
Peak memory	212276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847535495 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3847535495
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.3619310248
Short name	T568
Test name
Test status
Simulation time	9852143823 ps
CPU time	135.31 seconds
Started	Sep 09 06:46:35 AM UTC 24
Finished	Sep 09 06:48:52 AM UTC 24
Peak memory	217616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3619310248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all _with_rand_reset.3619310248
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.2688629746
Short name	T534
Test name
Test status
Simulation time	7607214134 ps
CPU time	5.33 seconds
Started	Sep 09 06:46:26 AM UTC 24
Finished	Sep 09 06:46:33 AM UTC 24
Peak memory	208148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688629746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2688629746
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/24.uart_tx_rx.2222727623
Short name	T565
Test name
Test status
Simulation time	53880139323 ps
CPU time	145.55 seconds
Started	Sep 09 06:46:10 AM UTC 24
Finished	Sep 09 06:48:38 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222727623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2222727623
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/24.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/240.uart_fifo_reset.2769670908
Short name	T1102
Test name
Test status
Simulation time	20989779184 ps
CPU time	24.59 seconds
Started	Sep 09 07:06:32 AM UTC 24
Finished	Sep 09 07:06:58 AM UTC 24
Peak memory	208632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769670908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2769670908
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/240.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/241.uart_fifo_reset.2785538677
Short name	T1140
Test name
Test status
Simulation time	119836753983 ps
CPU time	101.76 seconds
Started	Sep 09 07:06:37 AM UTC 24
Finished	Sep 09 07:08:21 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785538677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2785538677
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/241.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/242.uart_fifo_reset.2920554924
Short name	T1154
Test name
Test status
Simulation time	132707848573 ps
CPU time	135.31 seconds
Started	Sep 09 07:06:41 AM UTC 24
Finished	Sep 09 07:08:59 AM UTC 24
Peak memory	208632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920554924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2920554924
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/242.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1187337773
Short name	T1161
Test name
Test status
Simulation time	64732936653 ps
CPU time	143.33 seconds
Started	Sep 09 07:06:44 AM UTC 24
Finished	Sep 09 07:09:10 AM UTC 24
Peak memory	208816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187337773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1187337773
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/243.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/244.uart_fifo_reset.421627686
Short name	T1108
Test name
Test status
Simulation time	29833065354 ps
CPU time	16.44 seconds
Started	Sep 09 07:06:45 AM UTC 24
Finished	Sep 09 07:07:03 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421627686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.421627686
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/244.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/246.uart_fifo_reset.2406562258
Short name	T1113
Test name
Test status
Simulation time	21499079531 ps
CPU time	23.21 seconds
Started	Sep 09 07:06:48 AM UTC 24
Finished	Sep 09 07:07:13 AM UTC 24
Peak memory	208672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406562258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2406562258
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/246.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/247.uart_fifo_reset.983527142
Short name	T1165
Test name
Test status
Simulation time	144118986160 ps
CPU time	150.24 seconds
Started	Sep 09 07:06:51 AM UTC 24
Finished	Sep 09 07:09:24 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983527142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.983527142
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/247.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/248.uart_fifo_reset.950065966
Short name	T264
Test name
Test status
Simulation time	21484281541 ps
CPU time	22.52 seconds
Started	Sep 09 07:06:53 AM UTC 24
Finished	Sep 09 07:07:17 AM UTC 24
Peak memory	208720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950065966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.950065966
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/248.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/249.uart_fifo_reset.1179249343
Short name	T268
Test name
Test status
Simulation time	91846612989 ps
CPU time	146.45 seconds
Started	Sep 09 07:06:53 AM UTC 24
Finished	Sep 09 07:09:22 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179249343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1179249343
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/249.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_alert_test.4087576641
Short name	T549
Test name
Test status
Simulation time	131634493 ps
CPU time	0.83 seconds
Started	Sep 09 06:47:29 AM UTC 24
Finished	Sep 09 06:47:31 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087576641 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.4087576641
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_fifo_full.819557500
Short name	T161
Test name
Test status
Simulation time	140352636481 ps
CPU time	30.53 seconds
Started	Sep 09 06:46:49 AM UTC 24
Finished	Sep 09 06:47:21 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819557500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.819557500
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.472923395
Short name	T162
Test name
Test status
Simulation time	137285539385 ps
CPU time	349 seconds
Started	Sep 09 06:46:52 AM UTC 24
Finished	Sep 09 06:52:46 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472923395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.472923395
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_fifo_reset.972163905
Short name	T196
Test name
Test status
Simulation time	20495221375 ps
CPU time	35.61 seconds
Started	Sep 09 06:46:58 AM UTC 24
Finished	Sep 09 06:47:35 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972163905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.972163905
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_intr.2289726441
Short name	T564
Test name
Test status
Simulation time	49312163360 ps
CPU time	91.68 seconds
Started	Sep 09 06:47:03 AM UTC 24
Finished	Sep 09 06:48:37 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289726441 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2289726441
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.938830516
Short name	T629
Test name
Test status
Simulation time	134247715102 ps
CPU time	199.3 seconds
Started	Sep 09 06:47:26 AM UTC 24
Finished	Sep 09 06:50:49 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938830516 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.938830516
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_loopback.1081707400
Short name	T546
Test name
Test status
Simulation time	2920556123 ps
CPU time	2.64 seconds
Started	Sep 09 06:47:24 AM UTC 24
Finished	Sep 09 06:47:28 AM UTC 24
Peak memory	207148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081707400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1081707400
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_noise_filter.1062519116
Short name	T545
Test name
Test status
Simulation time	4498963133 ps
CPU time	12.08 seconds
Started	Sep 09 06:47:14 AM UTC 24
Finished	Sep 09 06:47:27 AM UTC 24
Peak memory	205240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062519116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1062519116
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_perf.2849696617
Short name	T404
Test name
Test status
Simulation time	6152851220 ps
CPU time	102.88 seconds
Started	Sep 09 06:47:25 AM UTC 24
Finished	Sep 09 06:49:10 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849696617 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2849696617
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1358457170
Short name	T547
Test name
Test status
Simulation time	4526314165 ps
CPU time	24.18 seconds
Started	Sep 09 06:47:03 AM UTC 24
Finished	Sep 09 06:47:29 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358457170 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1358457170
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.1382850071
Short name	T554
Test name
Test status
Simulation time	25695598618 ps
CPU time	39.9 seconds
Started	Sep 09 06:47:22 AM UTC 24
Finished	Sep 09 06:48:03 AM UTC 24
Peak memory	207812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382850071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1382850071
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.3047689759
Short name	T542
Test name
Test status
Simulation time	7178636380 ps
CPU time	1.7 seconds
Started	Sep 09 06:47:21 AM UTC 24
Finished	Sep 09 06:47:24 AM UTC 24
Peak memory	204500 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047689759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3047689759
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_smoke.1232072664
Short name	T540
Test name
Test status
Simulation time	296959387 ps
CPU time	2.32 seconds
Started	Sep 09 06:46:48 AM UTC 24
Finished	Sep 09 06:46:51 AM UTC 24
Peak memory	207592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232072664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 25.uart_smoke.1232072664
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_stress_all.3873849612
Short name	T395
Test name
Test status
Simulation time	42867834082 ps
CPU time	47.52 seconds
Started	Sep 09 06:47:29 AM UTC 24
Finished	Sep 09 06:48:18 AM UTC 24
Peak memory	208744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873849612 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3873849612
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.3850893530
Short name	T563
Test name
Test status
Simulation time	14806327091 ps
CPU time	65.48 seconds
Started	Sep 09 06:47:27 AM UTC 24
Finished	Sep 09 06:48:34 AM UTC 24
Peak memory	221696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3850893530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all _with_rand_reset.3850893530
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.3219041943
Short name	T544
Test name
Test status
Simulation time	304871256 ps
CPU time	1.48 seconds
Started	Sep 09 06:47:23 AM UTC 24
Finished	Sep 09 06:47:25 AM UTC 24
Peak memory	206488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219041943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.3219041943
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/25.uart_tx_rx.929237926
Short name	T411
Test name
Test status
Simulation time	36910049619 ps
CPU time	31.96 seconds
Started	Sep 09 06:46:49 AM UTC 24
Finished	Sep 09 06:47:22 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929237926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.929237926
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/25.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1485299858
Short name	T1169
Test name
Test status
Simulation time	77181282381 ps
CPU time	154.75 seconds
Started	Sep 09 07:06:54 AM UTC 24
Finished	Sep 09 07:09:32 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485299858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1485299858
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/250.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/251.uart_fifo_reset.259096520
Short name	T1149
Test name
Test status
Simulation time	178079425235 ps
CPU time	102.04 seconds
Started	Sep 09 07:06:54 AM UTC 24
Finished	Sep 09 07:08:38 AM UTC 24
Peak memory	208640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259096520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.259096520
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/251.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/252.uart_fifo_reset.646599067
Short name	T1115
Test name
Test status
Simulation time	9433603227 ps
CPU time	19.97 seconds
Started	Sep 09 07:06:56 AM UTC 24
Finished	Sep 09 07:07:17 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646599067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.646599067
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/252.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/253.uart_fifo_reset.4096904230
Short name	T241
Test name
Test status
Simulation time	27897183225 ps
CPU time	62.87 seconds
Started	Sep 09 07:06:59 AM UTC 24
Finished	Sep 09 07:08:04 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096904230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.4096904230
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/253.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/255.uart_fifo_reset.2172424411
Short name	T255
Test name
Test status
Simulation time	62885041963 ps
CPU time	36.84 seconds
Started	Sep 09 07:07:00 AM UTC 24
Finished	Sep 09 07:07:39 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172424411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2172424411
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/255.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/256.uart_fifo_reset.3650944858
Short name	T1186
Test name
Test status
Simulation time	229030947019 ps
CPU time	598.01 seconds
Started	Sep 09 07:07:01 AM UTC 24
Finished	Sep 09 07:17:07 AM UTC 24
Peak memory	212216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650944858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3650944858
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/256.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/257.uart_fifo_reset.3381398901
Short name	T1171
Test name
Test status
Simulation time	275375894899 ps
CPU time	149.83 seconds
Started	Sep 09 07:07:01 AM UTC 24
Finished	Sep 09 07:09:34 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381398901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3381398901
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/257.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/258.uart_fifo_reset.3334061354
Short name	T250
Test name
Test status
Simulation time	102473420715 ps
CPU time	267.67 seconds
Started	Sep 09 07:07:03 AM UTC 24
Finished	Sep 09 07:11:34 AM UTC 24
Peak memory	208956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334061354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3334061354
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/258.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/259.uart_fifo_reset.2347733828
Short name	T1123
Test name
Test status
Simulation time	14991770146 ps
CPU time	29.87 seconds
Started	Sep 09 07:07:04 AM UTC 24
Finished	Sep 09 07:07:35 AM UTC 24
Peak memory	208916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347733828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.2347733828
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/259.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_alert_test.1780572470
Short name	T559
Test name
Test status
Simulation time	12619464 ps
CPU time	0.82 seconds
Started	Sep 09 06:48:19 AM UTC 24
Finished	Sep 09 06:48:20 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780572470 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1780572470
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.829588946
Short name	T557
Test name
Test status
Simulation time	16167921902 ps
CPU time	36.28 seconds
Started	Sep 09 06:47:36 AM UTC 24
Finished	Sep 09 06:48:13 AM UTC 24
Peak memory	208900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829588946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.829588946
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_fifo_reset.3857775645
Short name	T397
Test name
Test status
Simulation time	98053077602 ps
CPU time	135.59 seconds
Started	Sep 09 06:47:43 AM UTC 24
Finished	Sep 09 06:50:01 AM UTC 24
Peak memory	208724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857775645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3857775645
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_intr.1363345778
Short name	T592
Test name
Test status
Simulation time	106062047765 ps
CPU time	97.2 seconds
Started	Sep 09 06:47:56 AM UTC 24
Finished	Sep 09 06:49:35 AM UTC 24
Peak memory	205100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363345778 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1363345778
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.3540910209
Short name	T622
Test name
Test status
Simulation time	27900691342 ps
CPU time	140.73 seconds
Started	Sep 09 06:48:11 AM UTC 24
Finished	Sep 09 06:50:35 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540910209 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3540910209
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_loopback.2327841825
Short name	T558
Test name
Test status
Simulation time	3181192562 ps
CPU time	7.6 seconds
Started	Sep 09 06:48:08 AM UTC 24
Finished	Sep 09 06:48:17 AM UTC 24
Peak memory	207484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327841825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.2327841825
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_noise_filter.70364879
Short name	T632
Test name
Test status
Simulation time	125696742117 ps
CPU time	174.26 seconds
Started	Sep 09 06:47:58 AM UTC 24
Finished	Sep 09 06:50:55 AM UTC 24
Peak memory	217660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70364879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.70364879
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_perf.3621682925
Short name	T806
Test name
Test status
Simulation time	18997520325 ps
CPU time	520.32 seconds
Started	Sep 09 06:48:09 AM UTC 24
Finished	Sep 09 06:56:56 AM UTC 24
Peak memory	208916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621682925 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3621682925
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_rx_oversample.213365356
Short name	T555
Test name
Test status
Simulation time	5392754593 ps
CPU time	13.19 seconds
Started	Sep 09 06:47:55 AM UTC 24
Finished	Sep 09 06:48:09 AM UTC 24
Peak memory	207228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213365356 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.213365356
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.3646949912
Short name	T169
Test name
Test status
Simulation time	85080857688 ps
CPU time	105.41 seconds
Started	Sep 09 06:48:05 AM UTC 24
Finished	Sep 09 06:49:53 AM UTC 24
Peak memory	208920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646949912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.3646949912
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.4093283573
Short name	T591
Test name
Test status
Simulation time	44773071518 ps
CPU time	88.48 seconds
Started	Sep 09 06:48:04 AM UTC 24
Finished	Sep 09 06:49:34 AM UTC 24
Peak memory	205096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093283573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.4093283573
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_smoke.508946119
Short name	T550
Test name
Test status
Simulation time	453980390 ps
CPU time	2.06 seconds
Started	Sep 09 06:47:30 AM UTC 24
Finished	Sep 09 06:47:33 AM UTC 24
Peak memory	208572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508946119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 26.uart_smoke.508946119
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_stress_all.2181611172
Short name	T769
Test name
Test status
Simulation time	594605405868 ps
CPU time	427.72 seconds
Started	Sep 09 06:48:18 AM UTC 24
Finished	Sep 09 06:55:30 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181611172 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2181611172
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.2011727338
Short name	T581
Test name
Test status
Simulation time	20031993695 ps
CPU time	68.15 seconds
Started	Sep 09 06:48:14 AM UTC 24
Finished	Sep 09 06:49:23 AM UTC 24
Peak memory	225408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2011727338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all _with_rand_reset.2011727338
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.733252875
Short name	T560
Test name
Test status
Simulation time	7059018727 ps
CPU time	12.78 seconds
Started	Sep 09 06:48:07 AM UTC 24
Finished	Sep 09 06:48:21 AM UTC 24
Peak memory	208744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733252875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.733252875
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/26.uart_tx_rx.1459861253
Short name	T556
Test name
Test status
Simulation time	9194306513 ps
CPU time	36.45 seconds
Started	Sep 09 06:47:32 AM UTC 24
Finished	Sep 09 06:48:10 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459861253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.1459861253
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/26.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3444550757
Short name	T1129
Test name
Test status
Simulation time	14763863972 ps
CPU time	42.9 seconds
Started	Sep 09 07:07:05 AM UTC 24
Finished	Sep 09 07:07:49 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444550757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3444550757
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/260.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/262.uart_fifo_reset.2491434205
Short name	T265
Test name
Test status
Simulation time	125826174636 ps
CPU time	223.23 seconds
Started	Sep 09 07:07:10 AM UTC 24
Finished	Sep 09 07:10:56 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491434205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2491434205
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/262.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/263.uart_fifo_reset.1153435695
Short name	T1134
Test name
Test status
Simulation time	24772446432 ps
CPU time	43.71 seconds
Started	Sep 09 07:07:11 AM UTC 24
Finished	Sep 09 07:07:56 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153435695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1153435695
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/263.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/264.uart_fifo_reset.292912688
Short name	T1139
Test name
Test status
Simulation time	26535508479 ps
CPU time	67.02 seconds
Started	Sep 09 07:07:12 AM UTC 24
Finished	Sep 09 07:08:21 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292912688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.292912688
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/264.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/265.uart_fifo_reset.3847913841
Short name	T1131
Test name
Test status
Simulation time	24926905208 ps
CPU time	38.18 seconds
Started	Sep 09 07:07:13 AM UTC 24
Finished	Sep 09 07:07:53 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847913841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3847913841
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/265.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/266.uart_fifo_reset.683683477
Short name	T1126
Test name
Test status
Simulation time	15217305569 ps
CPU time	27.3 seconds
Started	Sep 09 07:07:13 AM UTC 24
Finished	Sep 09 07:07:42 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683683477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.683683477
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/266.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/267.uart_fifo_reset.1461608615
Short name	T1185
Test name
Test status
Simulation time	204092921295 ps
CPU time	499.56 seconds
Started	Sep 09 07:07:17 AM UTC 24
Finished	Sep 09 07:15:44 AM UTC 24
Peak memory	212280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461608615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1461608615
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/267.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/269.uart_fifo_reset.1935522522
Short name	T1173
Test name
Test status
Simulation time	130086779771 ps
CPU time	145.9 seconds
Started	Sep 09 07:07:19 AM UTC 24
Finished	Sep 09 07:09:48 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935522522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1935522522
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/269.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_alert_test.2546375486
Short name	T573
Test name
Test status
Simulation time	43612111 ps
CPU time	0.8 seconds
Started	Sep 09 06:48:56 AM UTC 24
Finished	Sep 09 06:48:58 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546375486 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2546375486
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_fifo_full.3501606718
Short name	T609
Test name
Test status
Simulation time	56745253673 ps
CPU time	108.32 seconds
Started	Sep 09 06:48:23 AM UTC 24
Finished	Sep 09 06:50:13 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501606718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3501606718
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.3082247838
Short name	T572
Test name
Test status
Simulation time	115417088305 ps
CPU time	31.85 seconds
Started	Sep 09 06:48:24 AM UTC 24
Finished	Sep 09 06:48:57 AM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082247838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3082247838
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_fifo_reset.2639441199
Short name	T210
Test name
Test status
Simulation time	156990014888 ps
CPU time	306.35 seconds
Started	Sep 09 06:48:24 AM UTC 24
Finished	Sep 09 06:53:34 AM UTC 24
Peak memory	208668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639441199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2639441199
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_intr.3026569785
Short name	T582
Test name
Test status
Simulation time	28513600008 ps
CPU time	50.75 seconds
Started	Sep 09 06:48:33 AM UTC 24
Finished	Sep 09 06:49:25 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026569785 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3026569785
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2341590649
Short name	T737
Test name
Test status
Simulation time	76293811504 ps
CPU time	346.24 seconds
Started	Sep 09 06:48:54 AM UTC 24
Finished	Sep 09 06:54:45 AM UTC 24
Peak memory	208848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341590649 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2341590649
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_loopback.499497397
Short name	T579
Test name
Test status
Simulation time	12789839849 ps
CPU time	29.23 seconds
Started	Sep 09 06:48:50 AM UTC 24
Finished	Sep 09 06:49:20 AM UTC 24
Peak memory	208620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499497397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 27.uart_loopback.499497397
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_noise_filter.1387986851
Short name	T588
Test name
Test status
Simulation time	79263636873 ps
CPU time	52.65 seconds
Started	Sep 09 06:48:35 AM UTC 24
Finished	Sep 09 06:49:29 AM UTC 24
Peak memory	208796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387986851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1387986851
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_perf.2388815829
Short name	T649
Test name
Test status
Simulation time	11474666279 ps
CPU time	161.92 seconds
Started	Sep 09 06:48:53 AM UTC 24
Finished	Sep 09 06:51:37 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388815829 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2388815829
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_rx_oversample.2944298362
Short name	T571
Test name
Test status
Simulation time	2548914396 ps
CPU time	23.7 seconds
Started	Sep 09 06:48:30 AM UTC 24
Finished	Sep 09 06:48:55 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944298362 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.2944298362
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.1361622562
Short name	T575
Test name
Test status
Simulation time	43095355013 ps
CPU time	23.54 seconds
Started	Sep 09 06:48:38 AM UTC 24
Finished	Sep 09 06:49:04 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361622562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1361622562
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.1914902545
Short name	T570
Test name
Test status
Simulation time	5427936507 ps
CPU time	15.62 seconds
Started	Sep 09 06:48:37 AM UTC 24
Finished	Sep 09 06:48:54 AM UTC 24
Peak memory	205096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914902545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1914902545
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_smoke.11157243
Short name	T561
Test name
Test status
Simulation time	90845839 ps
CPU time	1.39 seconds
Started	Sep 09 06:48:21 AM UTC 24
Finished	Sep 09 06:48:23 AM UTC 24
Peak memory	208004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11157243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_smoke.11157243
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_stress_all.77702139
Short name	T644
Test name
Test status
Simulation time	195578922317 ps
CPU time	148.47 seconds
Started	Sep 09 06:48:55 AM UTC 24
Finished	Sep 09 06:51:26 AM UTC 24
Peak memory	217660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77702139 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.77702139
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.826047520
Short name	T584
Test name
Test status
Simulation time	1510906856 ps
CPU time	30.51 seconds
Started	Sep 09 06:48:54 AM UTC 24
Finished	Sep 09 06:49:26 AM UTC 24
Peak memory	223876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=826047520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all_ with_rand_reset.826047520
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.1478268103
Short name	T567
Test name
Test status
Simulation time	870359065 ps
CPU time	5.15 seconds
Started	Sep 09 06:48:43 AM UTC 24
Finished	Sep 09 06:48:49 AM UTC 24
Peak memory	207452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478268103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1478268103
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/27.uart_tx_rx.3825366611
Short name	T587
Test name
Test status
Simulation time	33240180469 ps
CPU time	65.74 seconds
Started	Sep 09 06:48:22 AM UTC 24
Finished	Sep 09 06:49:29 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825366611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.3825366611
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/27.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/270.uart_fifo_reset.2313695311
Short name	T1158
Test name
Test status
Simulation time	104094667775 ps
CPU time	102.46 seconds
Started	Sep 09 07:07:23 AM UTC 24
Finished	Sep 09 07:09:07 AM UTC 24
Peak memory	208428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313695311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2313695311
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/270.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1149283659
Short name	T1148
Test name
Test status
Simulation time	64880888157 ps
CPU time	70.4 seconds
Started	Sep 09 07:07:23 AM UTC 24
Finished	Sep 09 07:08:35 AM UTC 24
Peak memory	208780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149283659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1149283659
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/271.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/272.uart_fifo_reset.2474983259
Short name	T1170
Test name
Test status
Simulation time	144242346098 ps
CPU time	125.74 seconds
Started	Sep 09 07:07:24 AM UTC 24
Finished	Sep 09 07:09:32 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474983259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2474983259
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/272.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/273.uart_fifo_reset.2568072635
Short name	T1138
Test name
Test status
Simulation time	19544808720 ps
CPU time	36.27 seconds
Started	Sep 09 07:07:28 AM UTC 24
Finished	Sep 09 07:08:05 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568072635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.2568072635
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/273.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2285626398
Short name	T1142
Test name
Test status
Simulation time	50947796051 ps
CPU time	52.14 seconds
Started	Sep 09 07:07:30 AM UTC 24
Finished	Sep 09 07:08:23 AM UTC 24
Peak memory	208596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285626398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2285626398
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/274.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/275.uart_fifo_reset.1504641811
Short name	T1172
Test name
Test status
Simulation time	68843689825 ps
CPU time	121.98 seconds
Started	Sep 09 07:07:33 AM UTC 24
Finished	Sep 09 07:09:37 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504641811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1504641811
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/275.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/276.uart_fifo_reset.191453441
Short name	T227
Test name
Test status
Simulation time	46848489585 ps
CPU time	52.92 seconds
Started	Sep 09 07:07:34 AM UTC 24
Finished	Sep 09 07:08:28 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191453441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.191453441
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/276.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/277.uart_fifo_reset.3139405865
Short name	T1141
Test name
Test status
Simulation time	28226252969 ps
CPU time	45.18 seconds
Started	Sep 09 07:07:36 AM UTC 24
Finished	Sep 09 07:08:23 AM UTC 24
Peak memory	208916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139405865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3139405865
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/277.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/279.uart_fifo_reset.1168511655
Short name	T1136
Test name
Test status
Simulation time	11132350151 ps
CPU time	21.28 seconds
Started	Sep 09 07:07:39 AM UTC 24
Finished	Sep 09 07:08:02 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168511655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1168511655
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/279.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_alert_test.2448533343
Short name	T586
Test name
Test status
Simulation time	28496460 ps
CPU time	0.8 seconds
Started	Sep 09 06:49:26 AM UTC 24
Finished	Sep 09 06:49:28 AM UTC 24
Peak memory	202392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448533343 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.2448533343
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_fifo_full.3225308288
Short name	T621
Test name
Test status
Simulation time	45916699028 ps
CPU time	90.14 seconds
Started	Sep 09 06:49:02 AM UTC 24
Finished	Sep 09 06:50:35 AM UTC 24
Peak memory	208916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225308288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3225308288
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.3156840934
Short name	T163
Test name
Test status
Simulation time	50010157814 ps
CPU time	88.43 seconds
Started	Sep 09 06:49:03 AM UTC 24
Finished	Sep 09 06:50:34 AM UTC 24
Peak memory	208772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156840934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3156840934
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_fifo_reset.3551799698
Short name	T416
Test name
Test status
Simulation time	27888944283 ps
CPU time	26.51 seconds
Started	Sep 09 06:49:04 AM UTC 24
Finished	Sep 09 06:49:32 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551799698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3551799698
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_intr.2530580910
Short name	T658
Test name
Test status
Simulation time	93111104368 ps
CPU time	147.58 seconds
Started	Sep 09 06:49:15 AM UTC 24
Finished	Sep 09 06:51:45 AM UTC 24
Peak memory	208916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530580910 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.2530580910
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.2819932226
Short name	T661
Test name
Test status
Simulation time	46888676190 ps
CPU time	143.8 seconds
Started	Sep 09 06:49:24 AM UTC 24
Finished	Sep 09 06:51:51 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819932226 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2819932226
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_loopback.1061481586
Short name	T585
Test name
Test status
Simulation time	4061153409 ps
CPU time	3.99 seconds
Started	Sep 09 06:49:21 AM UTC 24
Finished	Sep 09 06:49:26 AM UTC 24
Peak memory	207148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061481586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1061481586
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_noise_filter.3465780141
Short name	T603
Test name
Test status
Simulation time	44608889286 ps
CPU time	45.82 seconds
Started	Sep 09 06:49:16 AM UTC 24
Finished	Sep 09 06:50:03 AM UTC 24
Peak memory	208756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465780141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3465780141
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_perf.2086459677
Short name	T1009
Test name
Test status
Simulation time	13772855425 ps
CPU time	885.28 seconds
Started	Sep 09 06:49:23 AM UTC 24
Finished	Sep 09 07:04:19 AM UTC 24
Peak memory	212408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086459677 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2086459677
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_rx_oversample.578206166
Short name	T601
Test name
Test status
Simulation time	6126538664 ps
CPU time	49.69 seconds
Started	Sep 09 06:49:10 AM UTC 24
Finished	Sep 09 06:50:02 AM UTC 24
Peak memory	208012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578206166 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.578206166
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.2057468541
Short name	T634
Test name
Test status
Simulation time	118886893462 ps
CPU time	98.54 seconds
Started	Sep 09 06:49:18 AM UTC 24
Finished	Sep 09 06:50:59 AM UTC 24
Peak memory	208636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057468541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2057468541
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.2211155426
Short name	T580
Test name
Test status
Simulation time	1932972793 ps
CPU time	3.94 seconds
Started	Sep 09 06:49:17 AM UTC 24
Finished	Sep 09 06:49:22 AM UTC 24
Peak memory	205032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211155426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2211155426
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_smoke.1699044215
Short name	T576
Test name
Test status
Simulation time	5383931224 ps
CPU time	15.67 seconds
Started	Sep 09 06:48:58 AM UTC 24
Finished	Sep 09 06:49:15 AM UTC 24
Peak memory	208552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699044215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1699044215
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_stress_all.3097829908
Short name	T160
Test name
Test status
Simulation time	359253622949 ps
CPU time	242.64 seconds
Started	Sep 09 06:49:26 AM UTC 24
Finished	Sep 09 06:53:32 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097829908 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3097829908
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.566770269
Short name	T608
Test name
Test status
Simulation time	2537455986 ps
CPU time	43.29 seconds
Started	Sep 09 06:49:26 AM UTC 24
Finished	Sep 09 06:50:11 AM UTC 24
Peak memory	208820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=566770269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all_ with_rand_reset.566770269
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.2816990157
Short name	T593
Test name
Test status
Simulation time	5961387584 ps
CPU time	15.27 seconds
Started	Sep 09 06:49:19 AM UTC 24
Finished	Sep 09 06:49:36 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816990157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2816990157
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/28.uart_tx_rx.281104515
Short name	T612
Test name
Test status
Simulation time	63919706253 ps
CPU time	76.21 seconds
Started	Sep 09 06:48:59 AM UTC 24
Finished	Sep 09 06:50:17 AM UTC 24
Peak memory	208712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281104515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.281104515
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/28.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/280.uart_fifo_reset.1420550984
Short name	T258
Test name
Test status
Simulation time	106022516899 ps
CPU time	49.15 seconds
Started	Sep 09 07:07:39 AM UTC 24
Finished	Sep 09 07:08:30 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420550984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.1420550984
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/280.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/281.uart_fifo_reset.745756104
Short name	T1133
Test name
Test status
Simulation time	31390148588 ps
CPU time	12.45 seconds
Started	Sep 09 07:07:42 AM UTC 24
Finished	Sep 09 07:07:56 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745756104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.745756104
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/281.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2042055486
Short name	T1177
Test name
Test status
Simulation time	82607276160 ps
CPU time	157.95 seconds
Started	Sep 09 07:07:43 AM UTC 24
Finished	Sep 09 07:10:24 AM UTC 24
Peak memory	208908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042055486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2042055486
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/282.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3987952158
Short name	T1135
Test name
Test status
Simulation time	48088469433 ps
CPU time	13.65 seconds
Started	Sep 09 07:07:44 AM UTC 24
Finished	Sep 09 07:07:59 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987952158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3987952158
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/283.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/284.uart_fifo_reset.388872082
Short name	T1176
Test name
Test status
Simulation time	251198597612 ps
CPU time	147.79 seconds
Started	Sep 09 07:07:47 AM UTC 24
Finished	Sep 09 07:10:17 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388872082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.388872082
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/284.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/286.uart_fifo_reset.1869223418
Short name	T1180
Test name
Test status
Simulation time	97027271888 ps
CPU time	190.95 seconds
Started	Sep 09 07:07:50 AM UTC 24
Finished	Sep 09 07:11:04 AM UTC 24
Peak memory	208640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869223418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1869223418
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/286.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/287.uart_fifo_reset.3011256575
Short name	T1160
Test name
Test status
Simulation time	47890830662 ps
CPU time	77.18 seconds
Started	Sep 09 07:07:50 AM UTC 24
Finished	Sep 09 07:09:09 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011256575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3011256575
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/287.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/288.uart_fifo_reset.1505306653
Short name	T1146
Test name
Test status
Simulation time	42397334355 ps
CPU time	34.07 seconds
Started	Sep 09 07:07:54 AM UTC 24
Finished	Sep 09 07:08:29 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505306653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1505306653
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/288.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/289.uart_fifo_reset.3803368917
Short name	T1166
Test name
Test status
Simulation time	48395816081 ps
CPU time	87.8 seconds
Started	Sep 09 07:07:55 AM UTC 24
Finished	Sep 09 07:09:25 AM UTC 24
Peak memory	208424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803368917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3803368917
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/289.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_alert_test.2530031825
Short name	T600
Test name
Test status
Simulation time	39768646 ps
CPU time	0.79 seconds
Started	Sep 09 06:49:59 AM UTC 24
Finished	Sep 09 06:50:00 AM UTC 24
Peak memory	204440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530031825 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2530031825
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_fifo_full.43723822
Short name	T599
Test name
Test status
Simulation time	11229809251 ps
CPU time	28.16 seconds
Started	Sep 09 06:49:30 AM UTC 24
Finished	Sep 09 06:49:59 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43723822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.43723822
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.4007859797
Short name	T648
Test name
Test status
Simulation time	74245550151 ps
CPU time	124.17 seconds
Started	Sep 09 06:49:31 AM UTC 24
Finished	Sep 09 06:51:37 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007859797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.4007859797
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_fifo_reset.2676780303
Short name	T607
Test name
Test status
Simulation time	10855579701 ps
CPU time	36.55 seconds
Started	Sep 09 06:49:32 AM UTC 24
Finished	Sep 09 06:50:10 AM UTC 24
Peak memory	208900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676780303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2676780303
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_intr.1121098023
Short name	T594
Test name
Test status
Simulation time	5270627593 ps
CPU time	5.95 seconds
Started	Sep 09 06:49:34 AM UTC 24
Finished	Sep 09 06:49:41 AM UTC 24
Peak memory	207336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121098023 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1121098023
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.2474654058
Short name	T841
Test name
Test status
Simulation time	90814625061 ps
CPU time	490.53 seconds
Started	Sep 09 06:49:47 AM UTC 24
Finished	Sep 09 06:58:04 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474654058 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2474654058
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_loopback.3655007285
Short name	T597
Test name
Test status
Simulation time	352746282 ps
CPU time	1.78 seconds
Started	Sep 09 06:49:44 AM UTC 24
Finished	Sep 09 06:49:47 AM UTC 24
Peak memory	206488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655007285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3655007285
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_noise_filter.1910274346
Short name	T614
Test name
Test status
Simulation time	78477181649 ps
CPU time	41.85 seconds
Started	Sep 09 06:49:35 AM UTC 24
Finished	Sep 09 06:50:18 AM UTC 24
Peak memory	208160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910274346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1910274346
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_perf.377003757
Short name	T681
Test name
Test status
Simulation time	13329929382 ps
CPU time	174.59 seconds
Started	Sep 09 06:49:45 AM UTC 24
Finished	Sep 09 06:52:43 AM UTC 24
Peak memory	208660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377003757 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.377003757
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_rx_oversample.1399717283
Short name	T604
Test name
Test status
Simulation time	6699079821 ps
CPU time	29.68 seconds
Started	Sep 09 06:49:33 AM UTC 24
Finished	Sep 09 06:50:04 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399717283 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1399717283
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.3586127776
Short name	T158
Test name
Test status
Simulation time	49335960920 ps
CPU time	38.71 seconds
Started	Sep 09 06:49:37 AM UTC 24
Finished	Sep 09 06:50:17 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586127776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3586127776
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.2252577599
Short name	T596
Test name
Test status
Simulation time	4319285573 ps
CPU time	7.29 seconds
Started	Sep 09 06:49:36 AM UTC 24
Finished	Sep 09 06:49:44 AM UTC 24
Peak memory	205096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252577599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2252577599
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_smoke.3338771318
Short name	T589
Test name
Test status
Simulation time	271784669 ps
CPU time	2.45 seconds
Started	Sep 09 06:49:27 AM UTC 24
Finished	Sep 09 06:49:31 AM UTC 24
Peak memory	207324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338771318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3338771318
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_stress_all.2849044521
Short name	T900
Test name
Test status
Simulation time	154237775485 ps
CPU time	597.17 seconds
Started	Sep 09 06:49:54 AM UTC 24
Finished	Sep 09 06:59:58 AM UTC 24
Peak memory	212216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849044521 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2849044521
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.3240390212
Short name	T391
Test name
Test status
Simulation time	10054968269 ps
CPU time	31.89 seconds
Started	Sep 09 06:49:53 AM UTC 24
Finished	Sep 09 06:50:26 AM UTC 24
Peak memory	225224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3240390212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all _with_rand_reset.3240390212
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.1488665933
Short name	T368
Test name
Test status
Simulation time	6524175656 ps
CPU time	29.36 seconds
Started	Sep 09 06:49:41 AM UTC 24
Finished	Sep 09 06:50:12 AM UTC 24
Peak memory	208912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488665933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1488665933
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/29.uart_tx_rx.2734574421
Short name	T654
Test name
Test status
Simulation time	63046109494 ps
CPU time	130.3 seconds
Started	Sep 09 06:49:29 AM UTC 24
Finished	Sep 09 06:51:41 AM UTC 24
Peak memory	208628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734574421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2734574421
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/29.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2009478826
Short name	T228
Test name
Test status
Simulation time	44545642940 ps
CPU time	34.47 seconds
Started	Sep 09 07:07:55 AM UTC 24
Finished	Sep 09 07:08:31 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009478826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2009478826
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/290.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/291.uart_fifo_reset.2183387360
Short name	T1145
Test name
Test status
Simulation time	12453813258 ps
CPU time	29.94 seconds
Started	Sep 09 07:07:57 AM UTC 24
Finished	Sep 09 07:08:28 AM UTC 24
Peak memory	207148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183387360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2183387360
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/291.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3992775989
Short name	T262
Test name
Test status
Simulation time	33330162230 ps
CPU time	21.57 seconds
Started	Sep 09 07:07:57 AM UTC 24
Finished	Sep 09 07:08:20 AM UTC 24
Peak memory	208756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992775989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3992775989
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/292.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/293.uart_fifo_reset.4044679883
Short name	T1144
Test name
Test status
Simulation time	38750926338 ps
CPU time	26.58 seconds
Started	Sep 09 07:08:00 AM UTC 24
Finished	Sep 09 07:08:28 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044679883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4044679883
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/293.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/295.uart_fifo_reset.2040883292
Short name	T1182
Test name
Test status
Simulation time	181207328316 ps
CPU time	308.36 seconds
Started	Sep 09 07:08:03 AM UTC 24
Finished	Sep 09 07:13:16 AM UTC 24
Peak memory	210376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040883292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2040883292
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/295.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/296.uart_fifo_reset.3821614907
Short name	T1164
Test name
Test status
Simulation time	169211503358 ps
CPU time	75.42 seconds
Started	Sep 09 07:08:04 AM UTC 24
Finished	Sep 09 07:09:22 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821614907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3821614907
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/296.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/297.uart_fifo_reset.467523442
Short name	T1183
Test name
Test status
Simulation time	117040137689 ps
CPU time	311.96 seconds
Started	Sep 09 07:08:05 AM UTC 24
Finished	Sep 09 07:13:21 AM UTC 24
Peak memory	208812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467523442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.467523442
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/297.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/298.uart_fifo_reset.3635675705
Short name	T1147
Test name
Test status
Simulation time	17940320274 ps
CPU time	25.96 seconds
Started	Sep 09 07:08:07 AM UTC 24
Finished	Sep 09 07:08:34 AM UTC 24
Peak memory	207516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635675705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3635675705
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/298.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/299.uart_fifo_reset.2745031525
Short name	T1156
Test name
Test status
Simulation time	41332292310 ps
CPU time	37.54 seconds
Started	Sep 09 07:08:21 AM UTC 24
Finished	Sep 09 07:09:00 AM UTC 24
Peak memory	208824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745031525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2745031525
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/299.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_alert_test.2032325976
Short name	T85
Test name
Test status
Simulation time	43326009 ps
CPU time	0.81 seconds
Started	Sep 09 06:31:02 AM UTC 24
Finished	Sep 09 06:31:04 AM UTC 24
Peak memory	204380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032325976 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2032325976
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_fifo_full.2551653250
Short name	T47
Test name
Test status
Simulation time	107521980714 ps
CPU time	27.5 seconds
Started	Sep 09 06:30:27 AM UTC 24
Finished	Sep 09 06:30:55 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551653250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2551653250
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.915165424
Short name	T123
Test name
Test status
Simulation time	186030832112 ps
CPU time	90.69 seconds
Started	Sep 09 06:30:28 AM UTC 24
Finished	Sep 09 06:32:00 AM UTC 24
Peak memory	208484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915165424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.915165424
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_fifo_reset.3225663778
Short name	T102
Test name
Test status
Simulation time	37864769554 ps
CPU time	76.91 seconds
Started	Sep 09 06:30:30 AM UTC 24
Finished	Sep 09 06:31:48 AM UTC 24
Peak memory	208960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225663778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3225663778
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_intr.2474213404
Short name	T320
Test name
Test status
Simulation time	296665051797 ps
CPU time	303.58 seconds
Started	Sep 09 06:30:35 AM UTC 24
Finished	Sep 09 06:35:42 AM UTC 24
Peak memory	208624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474213404 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.2474213404
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.3841833366
Short name	T362
Test name
Test status
Simulation time	120145966399 ps
CPU time	647.2 seconds
Started	Sep 09 06:30:56 AM UTC 24
Finished	Sep 09 06:41:52 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841833366 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3841833366
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_loopback.2828177722
Short name	T418
Test name
Test status
Simulation time	10829881798 ps
CPU time	16.87 seconds
Started	Sep 09 06:30:48 AM UTC 24
Finished	Sep 09 06:31:07 AM UTC 24
Peak memory	207908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828177722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2828177722
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_noise_filter.621687487
Short name	T48
Test name
Test status
Simulation time	70857611884 ps
CPU time	28.15 seconds
Started	Sep 09 06:30:40 AM UTC 24
Finished	Sep 09 06:31:10 AM UTC 24
Peak memory	208900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621687487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.621687487
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_perf.101225008
Short name	T378
Test name
Test status
Simulation time	20180177276 ps
CPU time	197.14 seconds
Started	Sep 09 06:30:51 AM UTC 24
Finished	Sep 09 06:34:12 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101225008 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.101225008
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_rx_oversample.704270709
Short name	T417
Test name
Test status
Simulation time	2002255793 ps
CPU time	13.52 seconds
Started	Sep 09 06:30:30 AM UTC 24
Finished	Sep 09 06:30:44 AM UTC 24
Peak memory	207332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704270709 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.704270709
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.2075529339
Short name	T19
Test name
Test status
Simulation time	47952998298 ps
CPU time	22.72 seconds
Started	Sep 09 06:30:45 AM UTC 24
Finished	Sep 09 06:31:09 AM UTC 24
Peak memory	208652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075529339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2075529339
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.3490420662
Short name	T360
Test name
Test status
Simulation time	5364058368 ps
CPU time	16.38 seconds
Started	Sep 09 06:30:42 AM UTC 24
Finished	Sep 09 06:31:00 AM UTC 24
Peak memory	207276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490420662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3490420662
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_sec_cm.3034303713
Short name	T86
Test name
Test status
Simulation time	128455807 ps
CPU time	1.12 seconds
Started	Sep 09 06:31:01 AM UTC 24
Finished	Sep 09 06:31:03 AM UTC 24
Peak memory	239512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034303713 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3034303713
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_smoke.3134905391
Short name	T298
Test name
Test status
Simulation time	6214225017 ps
CPU time	12.63 seconds
Started	Sep 09 06:30:13 AM UTC 24
Finished	Sep 09 06:30:27 AM UTC 24
Peak memory	208804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134905391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.uart_smoke.3134905391
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.874636960
Short name	T36
Test name
Test status
Simulation time	3129929525 ps
CPU time	70.69 seconds
Started	Sep 09 06:30:58 AM UTC 24
Finished	Sep 09 06:32:10 AM UTC 24
Peak memory	217724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=874636960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_w ith_rand_reset.874636960
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2670274555
Short name	T288
Test name
Test status
Simulation time	449044990 ps
CPU time	1.71 seconds
Started	Sep 09 06:30:45 AM UTC 24
Finished	Sep 09 06:30:48 AM UTC 24
Peak memory	206488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670274555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2670274555
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/3.uart_tx_rx.2901237104
Short name	T119
Test name
Test status
Simulation time	22892941396 ps
CPU time	31.38 seconds
Started	Sep 09 06:30:24 AM UTC 24
Finished	Sep 09 06:30:56 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901237104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2901237104
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/3.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_alert_test.3868204397
Short name	T615
Test name
Test status
Simulation time	45385477 ps
CPU time	0.84 seconds
Started	Sep 09 06:50:18 AM UTC 24
Finished	Sep 09 06:50:20 AM UTC 24
Peak memory	204332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868204397 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3868204397
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_fifo_full.3660617551
Short name	T626
Test name
Test status
Simulation time	55916796827 ps
CPU time	38.91 seconds
Started	Sep 09 06:50:02 AM UTC 24
Finished	Sep 09 06:50:42 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660617551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3660617551
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.1236827217
Short name	T159
Test name
Test status
Simulation time	83497112369 ps
CPU time	61.17 seconds
Started	Sep 09 06:50:03 AM UTC 24
Finished	Sep 09 06:51:06 AM UTC 24
Peak memory	208600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236827217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1236827217
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_fifo_reset.4286709754
Short name	T402
Test name
Test status
Simulation time	39675607745 ps
CPU time	21.02 seconds
Started	Sep 09 06:50:03 AM UTC 24
Finished	Sep 09 06:50:25 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286709754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.4286709754
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_intr.4060811203
Short name	T617
Test name
Test status
Simulation time	33855255186 ps
CPU time	16.94 seconds
Started	Sep 09 06:50:04 AM UTC 24
Finished	Sep 09 06:50:22 AM UTC 24
Peak memory	208680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060811203 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4060811203
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.2731390567
Short name	T915
Test name
Test status
Simulation time	84631854403 ps
CPU time	620.27 seconds
Started	Sep 09 06:50:14 AM UTC 24
Finished	Sep 09 07:00:41 AM UTC 24
Peak memory	212124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731390567 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2731390567
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_loopback.3415204400
Short name	T620
Test name
Test status
Simulation time	7126973962 ps
CPU time	21.32 seconds
Started	Sep 09 06:50:12 AM UTC 24
Finished	Sep 09 06:50:34 AM UTC 24
Peak memory	208736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415204400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3415204400
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_noise_filter.3184450146
Short name	T660
Test name
Test status
Simulation time	48662933705 ps
CPU time	102.21 seconds
Started	Sep 09 06:50:05 AM UTC 24
Finished	Sep 09 06:51:50 AM UTC 24
Peak memory	208576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184450146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3184450146
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_perf.2689734387
Short name	T816
Test name
Test status
Simulation time	9075023063 ps
CPU time	416.06 seconds
Started	Sep 09 06:50:13 AM UTC 24
Finished	Sep 09 06:57:14 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689734387 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2689734387
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_rx_oversample.3767637014
Short name	T619
Test name
Test status
Simulation time	4404281817 ps
CPU time	25.94 seconds
Started	Sep 09 06:50:04 AM UTC 24
Finished	Sep 09 06:50:31 AM UTC 24
Peak memory	207416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767637014 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3767637014
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.3137759500
Short name	T184
Test name
Test status
Simulation time	102840727425 ps
CPU time	120.44 seconds
Started	Sep 09 06:50:11 AM UTC 24
Finished	Sep 09 06:52:13 AM UTC 24
Peak memory	208672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137759500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3137759500
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.1172439287
Short name	T613
Test name
Test status
Simulation time	3327011096 ps
CPU time	8.94 seconds
Started	Sep 09 06:50:08 AM UTC 24
Finished	Sep 09 06:50:17 AM UTC 24
Peak memory	205028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172439287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1172439287
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_smoke.441420290
Short name	T602
Test name
Test status
Simulation time	102947360 ps
CPU time	1.35 seconds
Started	Sep 09 06:50:00 AM UTC 24
Finished	Sep 09 06:50:02 AM UTC 24
Peak memory	206492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441420290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 30.uart_smoke.441420290
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_stress_all.195045373
Short name	T798
Test name
Test status
Simulation time	594027099605 ps
CPU time	372.6 seconds
Started	Sep 09 06:50:16 AM UTC 24
Finished	Sep 09 06:56:33 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195045373 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.195045373
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.930088563
Short name	T166
Test name
Test status
Simulation time	21723873198 ps
CPU time	68.17 seconds
Started	Sep 09 06:50:16 AM UTC 24
Finished	Sep 09 06:51:26 AM UTC 24
Peak memory	221812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=930088563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all_ with_rand_reset.930088563
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.99953703
Short name	T611
Test name
Test status
Simulation time	1107946935 ps
CPU time	3.59 seconds
Started	Sep 09 06:50:11 AM UTC 24
Finished	Sep 09 06:50:15 AM UTC 24
Peak memory	207588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99953703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.99953703
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/30.uart_tx_rx.1220513407
Short name	T653
Test name
Test status
Simulation time	40581389576 ps
CPU time	96.26 seconds
Started	Sep 09 06:50:01 AM UTC 24
Finished	Sep 09 06:51:39 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220513407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1220513407
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/30.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_alert_test.614135562
Short name	T627
Test name
Test status
Simulation time	38330148 ps
CPU time	0.8 seconds
Started	Sep 09 06:50:41 AM UTC 24
Finished	Sep 09 06:50:43 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614135562 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.614135562
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_fifo_full.1648737607
Short name	T635
Test name
Test status
Simulation time	35671185587 ps
CPU time	42.27 seconds
Started	Sep 09 06:50:19 AM UTC 24
Finished	Sep 09 06:51:03 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648737607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1648737607
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.556930877
Short name	T633
Test name
Test status
Simulation time	24796173924 ps
CPU time	35.96 seconds
Started	Sep 09 06:50:20 AM UTC 24
Finished	Sep 09 06:50:58 AM UTC 24
Peak memory	208616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556930877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.556930877
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_intr.2390110233
Short name	T731
Test name
Test status
Simulation time	129495369377 ps
CPU time	241.42 seconds
Started	Sep 09 06:50:26 AM UTC 24
Finished	Sep 09 06:54:30 AM UTC 24
Peak memory	208588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390110233 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2390110233
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.45532489
Short name	T666
Test name
Test status
Simulation time	26895108082 ps
CPU time	94.09 seconds
Started	Sep 09 06:50:36 AM UTC 24
Finished	Sep 09 06:52:13 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45532489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.45532489
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_loopback.821482582
Short name	T636
Test name
Test status
Simulation time	6585423394 ps
CPU time	27.23 seconds
Started	Sep 09 06:50:35 AM UTC 24
Finished	Sep 09 06:51:04 AM UTC 24
Peak memory	208596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821482582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 31.uart_loopback.821482582
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_noise_filter.2893329849
Short name	T732
Test name
Test status
Simulation time	114312202569 ps
CPU time	240.85 seconds
Started	Sep 09 06:50:27 AM UTC 24
Finished	Sep 09 06:54:31 AM UTC 24
Peak memory	217600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893329849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2893329849
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_perf.296462203
Short name	T757
Test name
Test status
Simulation time	28432870896 ps
CPU time	275.51 seconds
Started	Sep 09 06:50:36 AM UTC 24
Finished	Sep 09 06:55:16 AM UTC 24
Peak memory	208872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296462203 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.296462203
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_rx_oversample.3701000950
Short name	T631
Test name
Test status
Simulation time	3070705504 ps
CPU time	27.51 seconds
Started	Sep 09 06:50:24 AM UTC 24
Finished	Sep 09 06:50:52 AM UTC 24
Peak memory	207212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701000950 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3701000950
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.3987153856
Short name	T167
Test name
Test status
Simulation time	174179134041 ps
CPU time	89.91 seconds
Started	Sep 09 06:50:32 AM UTC 24
Finished	Sep 09 06:52:04 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987153856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3987153856
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.3560675057
Short name	T623
Test name
Test status
Simulation time	5772552878 ps
CPU time	9.98 seconds
Started	Sep 09 06:50:27 AM UTC 24
Finished	Sep 09 06:50:38 AM UTC 24
Peak memory	207336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560675057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3560675057
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_smoke.4144133795
Short name	T616
Test name
Test status
Simulation time	726460911 ps
CPU time	1.44 seconds
Started	Sep 09 06:50:18 AM UTC 24
Finished	Sep 09 06:50:20 AM UTC 24
Peak memory	206204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144133795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.4144133795
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_stress_all.2110272513
Short name	T704
Test name
Test status
Simulation time	68313382888 ps
CPU time	162.33 seconds
Started	Sep 09 06:50:40 AM UTC 24
Finished	Sep 09 06:53:25 AM UTC 24
Peak memory	208824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110272513 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2110272513
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1562483226
Short name	T642
Test name
Test status
Simulation time	8813039397 ps
CPU time	40.41 seconds
Started	Sep 09 06:50:38 AM UTC 24
Finished	Sep 09 06:51:20 AM UTC 24
Peak memory	217856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1562483226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all _with_rand_reset.1562483226
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.3656214729
Short name	T625
Test name
Test status
Simulation time	1223674171 ps
CPU time	4.47 seconds
Started	Sep 09 06:50:35 AM UTC 24
Finished	Sep 09 06:50:41 AM UTC 24
Peak memory	207900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656214729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3656214729
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/31.uart_tx_rx.1681771955
Short name	T630
Test name
Test status
Simulation time	37623421057 ps
CPU time	31.12 seconds
Started	Sep 09 06:50:18 AM UTC 24
Finished	Sep 09 06:50:51 AM UTC 24
Peak memory	208272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681771955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1681771955
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/31.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_alert_test.4285959150
Short name	T641
Test name
Test status
Simulation time	40549966 ps
CPU time	0.81 seconds
Started	Sep 09 06:51:17 AM UTC 24
Finished	Sep 09 06:51:18 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285959150 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.4285959150
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_fifo_full.119507158
Short name	T678
Test name
Test status
Simulation time	125510261409 ps
CPU time	112.42 seconds
Started	Sep 09 06:50:44 AM UTC 24
Finished	Sep 09 06:52:38 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119507158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.119507158
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.777721507
Short name	T170
Test name
Test status
Simulation time	35649214469 ps
CPU time	73.53 seconds
Started	Sep 09 06:50:46 AM UTC 24
Finished	Sep 09 06:52:01 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777721507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.777721507
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_fifo_reset.315794960
Short name	T407
Test name
Test status
Simulation time	81185541803 ps
CPU time	52.7 seconds
Started	Sep 09 06:50:50 AM UTC 24
Finished	Sep 09 06:51:44 AM UTC 24
Peak memory	208856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315794960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.315794960
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_intr.2901039414
Short name	T639
Test name
Test status
Simulation time	23377810461 ps
CPU time	21.42 seconds
Started	Sep 09 06:50:53 AM UTC 24
Finished	Sep 09 06:51:16 AM UTC 24
Peak memory	208168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901039414 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2901039414
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.3373365221
Short name	T782
Test name
Test status
Simulation time	324353371222 ps
CPU time	286.47 seconds
Started	Sep 09 06:51:08 AM UTC 24
Finished	Sep 09 06:55:59 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373365221 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.3373365221
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_loopback.225528003
Short name	T640
Test name
Test status
Simulation time	6906969702 ps
CPU time	10.5 seconds
Started	Sep 09 06:51:05 AM UTC 24
Finished	Sep 09 06:51:17 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225528003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.uart_loopback.225528003
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_noise_filter.1457056899
Short name	T664
Test name
Test status
Simulation time	57545909304 ps
CPU time	63.06 seconds
Started	Sep 09 06:50:56 AM UTC 24
Finished	Sep 09 06:52:01 AM UTC 24
Peak memory	208412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457056899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1457056899
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_perf.4188959554
Short name	T695
Test name
Test status
Simulation time	8661488285 ps
CPU time	125.72 seconds
Started	Sep 09 06:51:06 AM UTC 24
Finished	Sep 09 06:53:14 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188959554 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.4188959554
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_rx_oversample.326992438
Short name	T667
Test name
Test status
Simulation time	7160569540 ps
CPU time	80.18 seconds
Started	Sep 09 06:50:52 AM UTC 24
Finished	Sep 09 06:52:14 AM UTC 24
Peak memory	207724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326992438 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.326992438
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.2096100752
Short name	T183
Test name
Test status
Simulation time	80616628332 ps
CPU time	15.05 seconds
Started	Sep 09 06:50:59 AM UTC 24
Finished	Sep 09 06:51:15 AM UTC 24
Peak memory	208960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096100752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2096100752
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.4113132510
Short name	T638
Test name
Test status
Simulation time	3419500387 ps
CPU time	13.81 seconds
Started	Sep 09 06:50:58 AM UTC 24
Finished	Sep 09 06:51:13 AM UTC 24
Peak memory	205224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113132510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.4113132510
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_smoke.3673566097
Short name	T628
Test name
Test status
Simulation time	106468328 ps
CPU time	1.49 seconds
Started	Sep 09 06:50:42 AM UTC 24
Finished	Sep 09 06:50:45 AM UTC 24
Peak memory	206488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673566097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3673566097
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_stress_all.142811985
Short name	T706
Test name
Test status
Simulation time	58342676863 ps
CPU time	130.89 seconds
Started	Sep 09 06:51:17 AM UTC 24
Finished	Sep 09 06:53:30 AM UTC 24
Peak memory	208820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142811985 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.142811985
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2049302205
Short name	T663
Test name
Test status
Simulation time	2484714412 ps
CPU time	41.5 seconds
Started	Sep 09 06:51:14 AM UTC 24
Finished	Sep 09 06:51:57 AM UTC 24
Peak memory	209044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2049302205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all _with_rand_reset.2049302205
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.2545649236
Short name	T637
Test name
Test status
Simulation time	1870784251 ps
CPU time	1.91 seconds
Started	Sep 09 06:51:04 AM UTC 24
Finished	Sep 09 06:51:07 AM UTC 24
Peak memory	206308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545649236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2545649236
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/32.uart_tx_rx.3484575937
Short name	T396
Test name
Test status
Simulation time	43141155008 ps
CPU time	32.46 seconds
Started	Sep 09 06:50:44 AM UTC 24
Finished	Sep 09 06:51:17 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484575937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3484575937
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/32.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_alert_test.2358434752
Short name	T659
Test name
Test status
Simulation time	20050431 ps
CPU time	0.81 seconds
Started	Sep 09 06:51:43 AM UTC 24
Finished	Sep 09 06:51:45 AM UTC 24
Peak memory	202392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358434752 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2358434752
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_fifo_full.4099246226
Short name	T743
Test name
Test status
Simulation time	170348822888 ps
CPU time	211.01 seconds
Started	Sep 09 06:51:19 AM UTC 24
Finished	Sep 09 06:54:53 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099246226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4099246226
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.868220119
Short name	T677
Test name
Test status
Simulation time	62382503421 ps
CPU time	72.51 seconds
Started	Sep 09 06:51:21 AM UTC 24
Finished	Sep 09 06:52:35 AM UTC 24
Peak memory	208460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868220119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.868220119
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_fifo_reset.3305058426
Short name	T647
Test name
Test status
Simulation time	22815888578 ps
CPU time	11.04 seconds
Started	Sep 09 06:51:24 AM UTC 24
Finished	Sep 09 06:51:36 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305058426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3305058426
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_intr.2086856657
Short name	T646
Test name
Test status
Simulation time	17161849653 ps
CPU time	5.8 seconds
Started	Sep 09 06:51:27 AM UTC 24
Finished	Sep 09 06:51:34 AM UTC 24
Peak memory	207072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086856657 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2086856657
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.1318691498
Short name	T703
Test name
Test status
Simulation time	39779743877 ps
CPU time	100.75 seconds
Started	Sep 09 06:51:40 AM UTC 24
Finished	Sep 09 06:53:23 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318691498 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1318691498
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_loopback.299817366
Short name	T656
Test name
Test status
Simulation time	3302773795 ps
CPU time	2.62 seconds
Started	Sep 09 06:51:39 AM UTC 24
Finished	Sep 09 06:51:42 AM UTC 24
Peak memory	208240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299817366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.uart_loopback.299817366
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_noise_filter.3706631463
Short name	T675
Test name
Test status
Simulation time	132528677182 ps
CPU time	60.1 seconds
Started	Sep 09 06:51:28 AM UTC 24
Finished	Sep 09 06:52:30 AM UTC 24
Peak memory	207356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706631463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3706631463
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_perf.3071532760
Short name	T829
Test name
Test status
Simulation time	9275082852 ps
CPU time	362.73 seconds
Started	Sep 09 06:51:39 AM UTC 24
Finished	Sep 09 06:57:47 AM UTC 24
Peak memory	208628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071532760 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3071532760
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_rx_oversample.2815620468
Short name	T651
Test name
Test status
Simulation time	2537392869 ps
CPU time	11.35 seconds
Started	Sep 09 06:51:26 AM UTC 24
Finished	Sep 09 06:51:38 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815620468 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2815620468
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.2825719042
Short name	T652
Test name
Test status
Simulation time	28195794639 ps
CPU time	23.07 seconds
Started	Sep 09 06:51:37 AM UTC 24
Finished	Sep 09 06:52:02 AM UTC 24
Peak memory	208608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825719042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2825719042
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.1355562225
Short name	T657
Test name
Test status
Simulation time	2374379969 ps
CPU time	7.12 seconds
Started	Sep 09 06:51:34 AM UTC 24
Finished	Sep 09 06:51:43 AM UTC 24
Peak memory	205096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355562225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.1355562225
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_smoke.3882509461
Short name	T650
Test name
Test status
Simulation time	5894930819 ps
CPU time	19.29 seconds
Started	Sep 09 06:51:18 AM UTC 24
Finished	Sep 09 06:51:38 AM UTC 24
Peak memory	208464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882509461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3882509461
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_stress_all.176285781
Short name	T1067
Test name
Test status
Simulation time	364854706323 ps
CPU time	834.37 seconds
Started	Sep 09 06:51:42 AM UTC 24
Finished	Sep 09 07:05:46 AM UTC 24
Peak memory	222576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176285781 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.176285781
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.840810158
Short name	T168
Test name
Test status
Simulation time	3800551471 ps
CPU time	28.46 seconds
Started	Sep 09 06:51:40 AM UTC 24
Finished	Sep 09 06:52:09 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=840810158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all_ with_rand_reset.840810158
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.1234644511
Short name	T655
Test name
Test status
Simulation time	1375392332 ps
CPU time	3.58 seconds
Started	Sep 09 06:51:37 AM UTC 24
Finished	Sep 09 06:51:42 AM UTC 24
Peak memory	207524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234644511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1234644511
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/33.uart_tx_rx.2820850517
Short name	T672
Test name
Test status
Simulation time	95055153942 ps
CPU time	62.18 seconds
Started	Sep 09 06:51:18 AM UTC 24
Finished	Sep 09 06:52:22 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820850517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2820850517
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/33.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_alert_test.787136865
Short name	T669
Test name
Test status
Simulation time	48863514 ps
CPU time	0.82 seconds
Started	Sep 09 06:52:14 AM UTC 24
Finished	Sep 09 06:52:16 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787136865 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.787136865
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_fifo_full.4210278689
Short name	T720
Test name
Test status
Simulation time	124251878230 ps
CPU time	139.17 seconds
Started	Sep 09 06:51:45 AM UTC 24
Finished	Sep 09 06:54:07 AM UTC 24
Peak memory	208652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210278689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.4210278689
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.1761925848
Short name	T409
Test name
Test status
Simulation time	28273299985 ps
CPU time	34 seconds
Started	Sep 09 06:51:45 AM UTC 24
Finished	Sep 09 06:52:21 AM UTC 24
Peak memory	208716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761925848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.1761925848
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_fifo_reset.1629689877
Short name	T693
Test name
Test status
Simulation time	143673395866 ps
CPU time	80.11 seconds
Started	Sep 09 06:51:45 AM UTC 24
Finished	Sep 09 06:53:07 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629689877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1629689877
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_intr.2833832431
Short name	T687
Test name
Test status
Simulation time	77297114301 ps
CPU time	62.67 seconds
Started	Sep 09 06:51:51 AM UTC 24
Finished	Sep 09 06:52:56 AM UTC 24
Peak memory	208976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833832431 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2833832431
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.1328214827
Short name	T918
Test name
Test status
Simulation time	90881462386 ps
CPU time	513.59 seconds
Started	Sep 09 06:52:07 AM UTC 24
Finished	Sep 09 07:00:47 AM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328214827 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1328214827
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_loopback.967214827
Short name	T665
Test name
Test status
Simulation time	1586500456 ps
CPU time	2.1 seconds
Started	Sep 09 06:52:03 AM UTC 24
Finished	Sep 09 06:52:06 AM UTC 24
Peak memory	204956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967214827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.uart_loopback.967214827
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_noise_filter.2121332139
Short name	T684
Test name
Test status
Simulation time	105375226461 ps
CPU time	53.64 seconds
Started	Sep 09 06:51:54 AM UTC 24
Finished	Sep 09 06:52:50 AM UTC 24
Peak memory	217600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121332139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2121332139
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_perf.2136432839
Short name	T1187
Test name
Test status
Simulation time	29356640972 ps
CPU time	1649.01 seconds
Started	Sep 09 06:52:04 AM UTC 24
Finished	Sep 09 07:19:51 AM UTC 24
Peak memory	212412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136432839 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2136432839
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_rx_oversample.3510454657
Short name	T690
Test name
Test status
Simulation time	6598232596 ps
CPU time	67.5 seconds
Started	Sep 09 06:51:50 AM UTC 24
Finished	Sep 09 06:52:59 AM UTC 24
Peak memory	207216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510454657 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3510454657
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.2799805034
Short name	T673
Test name
Test status
Simulation time	10417448254 ps
CPU time	21.41 seconds
Started	Sep 09 06:52:02 AM UTC 24
Finished	Sep 09 06:52:24 AM UTC 24
Peak memory	208080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799805034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2799805034
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.852858508
Short name	T679
Test name
Test status
Simulation time	36736255828 ps
CPU time	40.3 seconds
Started	Sep 09 06:51:58 AM UTC 24
Finished	Sep 09 06:52:39 AM UTC 24
Peak memory	207144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852858508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.852858508
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_smoke.3976100751
Short name	T662
Test name
Test status
Simulation time	5573759600 ps
CPU time	9.64 seconds
Started	Sep 09 06:51:43 AM UTC 24
Finished	Sep 09 06:51:54 AM UTC 24
Peak memory	208164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976100751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3976100751
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_stress_all.350518074
Short name	T800
Test name
Test status
Simulation time	72995210961 ps
CPU time	261.6 seconds
Started	Sep 09 06:52:13 AM UTC 24
Finished	Sep 09 06:56:38 AM UTC 24
Peak memory	208724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350518074 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.350518074
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.1256198615
Short name	T710
Test name
Test status
Simulation time	19460175540 ps
CPU time	84.23 seconds
Started	Sep 09 06:52:10 AM UTC 24
Finished	Sep 09 06:53:36 AM UTC 24
Peak memory	219724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1256198615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all _with_rand_reset.1256198615
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.1530077890
Short name	T668
Test name
Test status
Simulation time	11060909329 ps
CPU time	11.89 seconds
Started	Sep 09 06:52:02 AM UTC 24
Finished	Sep 09 06:52:15 AM UTC 24
Peak memory	208504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530077890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1530077890
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/34.uart_tx_rx.2722613456
Short name	T674
Test name
Test status
Simulation time	94161539500 ps
CPU time	42.84 seconds
Started	Sep 09 06:51:43 AM UTC 24
Finished	Sep 09 06:52:27 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722613456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.2722613456
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/34.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_alert_test.2435287348
Short name	T683
Test name
Test status
Simulation time	17161812 ps
CPU time	0.86 seconds
Started	Sep 09 06:52:46 AM UTC 24
Finished	Sep 09 06:52:47 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435287348 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.2435287348
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_fifo_full.2905340661
Short name	T709
Test name
Test status
Simulation time	106965714577 ps
CPU time	74.82 seconds
Started	Sep 09 06:52:16 AM UTC 24
Finished	Sep 09 06:53:33 AM UTC 24
Peak memory	208628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905340661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.2905340661
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_fifo_reset.992452832
Short name	T716
Test name
Test status
Simulation time	33813394513 ps
CPU time	85.52 seconds
Started	Sep 09 06:52:19 AM UTC 24
Finished	Sep 09 06:53:46 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992452832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.992452832
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_intr.912469636
Short name	T676
Test name
Test status
Simulation time	11498854092 ps
CPU time	10.69 seconds
Started	Sep 09 06:52:23 AM UTC 24
Finished	Sep 09 06:52:35 AM UTC 24
Peak memory	205024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912469636 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.912469636
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.4095740081
Short name	T778
Test name
Test status
Simulation time	131099216687 ps
CPU time	183.51 seconds
Started	Sep 09 06:52:40 AM UTC 24
Finished	Sep 09 06:55:47 AM UTC 24
Peak memory	208720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095740081 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.4095740081
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_loopback.1913357673
Short name	T689
Test name
Test status
Simulation time	6012404408 ps
CPU time	19.64 seconds
Started	Sep 09 06:52:36 AM UTC 24
Finished	Sep 09 06:52:57 AM UTC 24
Peak memory	207932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913357673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1913357673
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_noise_filter.1882097078
Short name	T701
Test name
Test status
Simulation time	267546339141 ps
CPU time	53.81 seconds
Started	Sep 09 06:52:25 AM UTC 24
Finished	Sep 09 06:53:20 AM UTC 24
Peak memory	208916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882097078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1882097078
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_perf.1269093114
Short name	T850
Test name
Test status
Simulation time	16670710970 ps
CPU time	337.93 seconds
Started	Sep 09 06:52:39 AM UTC 24
Finished	Sep 09 06:58:22 AM UTC 24
Peak memory	208956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269093114 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1269093114
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_rx_oversample.828652687
Short name	T696
Test name
Test status
Simulation time	5897757272 ps
CPU time	50.96 seconds
Started	Sep 09 06:52:22 AM UTC 24
Finished	Sep 09 06:53:15 AM UTC 24
Peak memory	207260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828652687 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.828652687
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.733593325
Short name	T714
Test name
Test status
Simulation time	186736933837 ps
CPU time	70.65 seconds
Started	Sep 09 06:52:31 AM UTC 24
Finished	Sep 09 06:53:44 AM UTC 24
Peak memory	208416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733593325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.733593325
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.2817772167
Short name	T682
Test name
Test status
Simulation time	4512298312 ps
CPU time	16.1 seconds
Started	Sep 09 06:52:28 AM UTC 24
Finished	Sep 09 06:52:45 AM UTC 24
Peak memory	205160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817772167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2817772167
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_smoke.4208765908
Short name	T671
Test name
Test status
Simulation time	127314868 ps
CPU time	1.2 seconds
Started	Sep 09 06:52:15 AM UTC 24
Finished	Sep 09 06:52:18 AM UTC 24
Peak memory	206484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208765908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4208765908
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_stress_all.2290748240
Short name	T907
Test name
Test status
Simulation time	225855645300 ps
CPU time	455.18 seconds
Started	Sep 09 06:52:43 AM UTC 24
Finished	Sep 09 07:00:24 AM UTC 24
Peak memory	208820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290748240 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2290748240
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.3719080595
Short name	T692
Test name
Test status
Simulation time	1269733438 ps
CPU time	22.45 seconds
Started	Sep 09 06:52:42 AM UTC 24
Finished	Sep 09 06:53:06 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3719080595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all _with_rand_reset.3719080595
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.3992796244
Short name	T680
Test name
Test status
Simulation time	953126929 ps
CPU time	4.18 seconds
Started	Sep 09 06:52:36 AM UTC 24
Finished	Sep 09 06:52:41 AM UTC 24
Peak memory	207096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992796244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3992796244
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/35.uart_tx_rx.3634121341
Short name	T688
Test name
Test status
Simulation time	26057788602 ps
CPU time	38.85 seconds
Started	Sep 09 06:52:15 AM UTC 24
Finished	Sep 09 06:52:56 AM UTC 24
Peak memory	208852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634121341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3634121341
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/35.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_alert_test.2757650629
Short name	T699
Test name
Test status
Simulation time	33698499 ps
CPU time	0.82 seconds
Started	Sep 09 06:53:16 AM UTC 24
Finished	Sep 09 06:53:18 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757650629 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2757650629
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_fifo_full.2226887461
Short name	T749
Test name
Test status
Simulation time	133013020491 ps
CPU time	130.2 seconds
Started	Sep 09 06:52:51 AM UTC 24
Finished	Sep 09 06:55:03 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226887461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2226887461
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.3425311502
Short name	T700
Test name
Test status
Simulation time	26094558383 ps
CPU time	23.66 seconds
Started	Sep 09 06:52:53 AM UTC 24
Finished	Sep 09 06:53:18 AM UTC 24
Peak memory	208816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425311502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3425311502
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_fifo_reset.1377008210
Short name	T213
Test name
Test status
Simulation time	126835433803 ps
CPU time	17.03 seconds
Started	Sep 09 06:52:54 AM UTC 24
Finished	Sep 09 06:53:12 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377008210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1377008210
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_intr.497326404
Short name	T705
Test name
Test status
Simulation time	37339383882 ps
CPU time	30.28 seconds
Started	Sep 09 06:52:57 AM UTC 24
Finished	Sep 09 06:53:29 AM UTC 24
Peak memory	208624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497326404 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.497326404
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.1181405903
Short name	T803
Test name
Test status
Simulation time	124809323076 ps
CPU time	208.55 seconds
Started	Sep 09 06:53:13 AM UTC 24
Finished	Sep 09 06:56:44 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181405903 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1181405903
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_loopback.963016624
Short name	T698
Test name
Test status
Simulation time	7151457122 ps
CPU time	9.16 seconds
Started	Sep 09 06:53:06 AM UTC 24
Finished	Sep 09 06:53:17 AM UTC 24
Peak memory	208612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963016624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 36.uart_loopback.963016624
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_noise_filter.2159230236
Short name	T405
Test name
Test status
Simulation time	97871025116 ps
CPU time	220.52 seconds
Started	Sep 09 06:52:58 AM UTC 24
Finished	Sep 09 06:56:42 AM UTC 24
Peak memory	208904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159230236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2159230236
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_perf.1995757608
Short name	T867
Test name
Test status
Simulation time	6135412147 ps
CPU time	339.78 seconds
Started	Sep 09 06:53:09 AM UTC 24
Finished	Sep 09 06:58:53 AM UTC 24
Peak memory	208824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995757608 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1995757608
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_rx_oversample.2220332076
Short name	T713
Test name
Test status
Simulation time	4984981643 ps
CPU time	42.62 seconds
Started	Sep 09 06:52:56 AM UTC 24
Finished	Sep 09 06:53:40 AM UTC 24
Peak memory	207480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220332076 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.2220332076
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.1344117994
Short name	T746
Test name
Test status
Simulation time	196379224927 ps
CPU time	110.68 seconds
Started	Sep 09 06:53:05 AM UTC 24
Finished	Sep 09 06:54:58 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344117994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1344117994
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.2950702945
Short name	T691
Test name
Test status
Simulation time	732333455 ps
CPU time	3.08 seconds
Started	Sep 09 06:53:00 AM UTC 24
Finished	Sep 09 06:53:04 AM UTC 24
Peak memory	205160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950702945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2950702945
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_smoke.2528819693
Short name	T685
Test name
Test status
Simulation time	551136550 ps
CPU time	4.18 seconds
Started	Sep 09 06:52:47 AM UTC 24
Finished	Sep 09 06:52:52 AM UTC 24
Peak memory	207228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528819693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2528819693
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_stress_all.665642665
Short name	T808
Test name
Test status
Simulation time	44488971789 ps
CPU time	224.13 seconds
Started	Sep 09 06:53:15 AM UTC 24
Finished	Sep 09 06:57:02 AM UTC 24
Peak memory	208912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665642665 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.665642665
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.1090365869
Short name	T750
Test name
Test status
Simulation time	4500723199 ps
CPU time	106.35 seconds
Started	Sep 09 06:53:15 AM UTC 24
Finished	Sep 09 06:55:03 AM UTC 24
Peak memory	221812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1090365869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all _with_rand_reset.1090365869
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.1247660445
Short name	T697
Test name
Test status
Simulation time	6895390221 ps
CPU time	7.95 seconds
Started	Sep 09 06:53:06 AM UTC 24
Finished	Sep 09 06:53:15 AM UTC 24
Peak memory	208912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247660445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1247660445
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/36.uart_tx_rx.237699982
Short name	T707
Test name
Test status
Simulation time	14991449512 ps
CPU time	41.71 seconds
Started	Sep 09 06:52:48 AM UTC 24
Finished	Sep 09 06:53:31 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237699982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.237699982
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/36.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_alert_test.331995495
Short name	T712
Test name
Test status
Simulation time	12325928 ps
CPU time	0.81 seconds
Started	Sep 09 06:53:37 AM UTC 24
Finished	Sep 09 06:53:39 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331995495 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.331995495
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_fifo_full.2934787102
Short name	T726
Test name
Test status
Simulation time	28188249337 ps
CPU time	64.81 seconds
Started	Sep 09 06:53:17 AM UTC 24
Finished	Sep 09 06:54:23 AM UTC 24
Peak memory	208612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934787102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2934787102
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.3325445605
Short name	T721
Test name
Test status
Simulation time	146485948123 ps
CPU time	47.61 seconds
Started	Sep 09 06:53:18 AM UTC 24
Finished	Sep 09 06:54:07 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325445605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.3325445605
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_fifo_reset.768889296
Short name	T180
Test name
Test status
Simulation time	44050826869 ps
CPU time	62.54 seconds
Started	Sep 09 06:53:18 AM UTC 24
Finished	Sep 09 06:54:22 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768889296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.768889296
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_intr.2536566654
Short name	T953
Test name
Test status
Simulation time	523556368571 ps
CPU time	515.5 seconds
Started	Sep 09 06:53:21 AM UTC 24
Finished	Sep 09 07:02:03 AM UTC 24
Peak memory	209080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536566654 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.2536566654
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.2317015158
Short name	T768
Test name
Test status
Simulation time	57685354218 ps
CPU time	112.72 seconds
Started	Sep 09 06:53:33 AM UTC 24
Finished	Sep 09 06:55:28 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317015158 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2317015158
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_loopback.280225563
Short name	T718
Test name
Test status
Simulation time	9440224002 ps
CPU time	30.27 seconds
Started	Sep 09 06:53:32 AM UTC 24
Finished	Sep 09 06:54:03 AM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280225563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 37.uart_loopback.280225563
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_noise_filter.2075705976
Short name	T755
Test name
Test status
Simulation time	58945525478 ps
CPU time	104.74 seconds
Started	Sep 09 06:53:23 AM UTC 24
Finished	Sep 09 06:55:10 AM UTC 24
Peak memory	208388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075705976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2075705976
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_perf.1581617
Short name	T1031
Test name
Test status
Simulation time	18015111852 ps
CPU time	672.35 seconds
Started	Sep 09 06:53:32 AM UTC 24
Finished	Sep 09 07:04:52 AM UTC 24
Peak memory	212348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM _TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1581617
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_rx_oversample.2441000488
Short name	T717
Test name
Test status
Simulation time	3260290482 ps
CPU time	25.7 seconds
Started	Sep 09 06:53:21 AM UTC 24
Finished	Sep 09 06:53:48 AM UTC 24
Peak memory	207212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441000488 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2441000488
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.3273300062
Short name	T758
Test name
Test status
Simulation time	257525678089 ps
CPU time	104.19 seconds
Started	Sep 09 06:53:30 AM UTC 24
Finished	Sep 09 06:55:16 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273300062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3273300062
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.758943727
Short name	T708
Test name
Test status
Simulation time	4077561179 ps
CPU time	4.33 seconds
Started	Sep 09 06:53:26 AM UTC 24
Finished	Sep 09 06:53:31 AM UTC 24
Peak memory	207144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758943727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.758943727
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_smoke.270375459
Short name	T702
Test name
Test status
Simulation time	846847666 ps
CPU time	3.54 seconds
Started	Sep 09 06:53:16 AM UTC 24
Finished	Sep 09 06:53:20 AM UTC 24
Peak memory	208644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270375459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 37.uart_smoke.270375459
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_stress_all.3052644500
Short name	T1167
Test name
Test status
Simulation time	229875343964 ps
CPU time	939.68 seconds
Started	Sep 09 06:53:35 AM UTC 24
Finished	Sep 09 07:09:26 AM UTC 24
Peak memory	221036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052644500 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3052644500
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.1720523619
Short name	T733
Test name
Test status
Simulation time	4947826683 ps
CPU time	59.16 seconds
Started	Sep 09 06:53:34 AM UTC 24
Finished	Sep 09 06:54:35 AM UTC 24
Peak memory	219832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1720523619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all _with_rand_reset.1720523619
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.380349523
Short name	T711
Test name
Test status
Simulation time	979888930 ps
CPU time	6.3 seconds
Started	Sep 09 06:53:31 AM UTC 24
Finished	Sep 09 06:53:38 AM UTC 24
Peak memory	207356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380349523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.380349523
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/37.uart_tx_rx.20244634
Short name	T728
Test name
Test status
Simulation time	28677578225 ps
CPU time	68.36 seconds
Started	Sep 09 06:53:16 AM UTC 24
Finished	Sep 09 06:54:26 AM UTC 24
Peak memory	208840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20244634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.20244634
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/37.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_alert_test.3049976099
Short name	T727
Test name
Test status
Simulation time	14587736 ps
CPU time	0.84 seconds
Started	Sep 09 06:54:23 AM UTC 24
Finished	Sep 09 06:54:25 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049976099 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3049976099
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_fifo_full.236263354
Short name	T730
Test name
Test status
Simulation time	85709141720 ps
CPU time	47.25 seconds
Started	Sep 09 06:53:40 AM UTC 24
Finished	Sep 09 06:54:29 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236263354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.236263354
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.438993454
Short name	T738
Test name
Test status
Simulation time	64633664981 ps
CPU time	58.89 seconds
Started	Sep 09 06:53:44 AM UTC 24
Finished	Sep 09 06:54:45 AM UTC 24
Peak memory	208856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438993454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.438993454
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_fifo_reset.2203695640
Short name	T165
Test name
Test status
Simulation time	43392088851 ps
CPU time	20.83 seconds
Started	Sep 09 06:53:44 AM UTC 24
Finished	Sep 09 06:54:07 AM UTC 24
Peak memory	208628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203695640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2203695640
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_intr.2772920428
Short name	T771
Test name
Test status
Simulation time	47714906219 ps
CPU time	101.73 seconds
Started	Sep 09 06:53:48 AM UTC 24
Finished	Sep 09 06:55:32 AM UTC 24
Peak memory	207668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772920428 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2772920428
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.3488534693
Short name	T792
Test name
Test status
Simulation time	58649564360 ps
CPU time	133.3 seconds
Started	Sep 09 06:54:09 AM UTC 24
Finished	Sep 09 06:56:25 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488534693 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3488534693
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_loopback.3177627979
Short name	T734
Test name
Test status
Simulation time	8398874478 ps
CPU time	27.76 seconds
Started	Sep 09 06:54:07 AM UTC 24
Finished	Sep 09 06:54:36 AM UTC 24
Peak memory	207868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177627979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3177627979
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_noise_filter.2588176706
Short name	T740
Test name
Test status
Simulation time	110295761336 ps
CPU time	55.42 seconds
Started	Sep 09 06:53:49 AM UTC 24
Finished	Sep 09 06:54:46 AM UTC 24
Peak memory	208744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588176706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2588176706
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_perf.35989956
Short name	T812
Test name
Test status
Simulation time	14197428221 ps
CPU time	177.95 seconds
Started	Sep 09 06:54:08 AM UTC 24
Finished	Sep 09 06:57:09 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35989956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.35989956
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1595084812
Short name	T724
Test name
Test status
Simulation time	3081442149 ps
CPU time	29.47 seconds
Started	Sep 09 06:53:48 AM UTC 24
Finished	Sep 09 06:54:19 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595084812 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1595084812
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.459235444
Short name	T753
Test name
Test status
Simulation time	86183278566 ps
CPU time	62.49 seconds
Started	Sep 09 06:54:05 AM UTC 24
Finished	Sep 09 06:55:09 AM UTC 24
Peak memory	208556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459235444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.459235444
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.546402924
Short name	T722
Test name
Test status
Simulation time	3680048165 ps
CPU time	3.12 seconds
Started	Sep 09 06:54:04 AM UTC 24
Finished	Sep 09 06:54:08 AM UTC 24
Peak memory	207272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546402924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.546402924
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_smoke.1010087073
Short name	T715
Test name
Test status
Simulation time	5828221167 ps
CPU time	6 seconds
Started	Sep 09 06:53:39 AM UTC 24
Finished	Sep 09 06:53:46 AM UTC 24
Peak memory	207900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010087073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1010087073
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_stress_all.1949678750
Short name	T882
Test name
Test status
Simulation time	148529468334 ps
CPU time	295.03 seconds
Started	Sep 09 06:54:19 AM UTC 24
Finished	Sep 09 06:59:18 AM UTC 24
Peak memory	208912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949678750 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1949678750
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.1681564456
Short name	T735
Test name
Test status
Simulation time	1871759206 ps
CPU time	26.12 seconds
Started	Sep 09 06:54:12 AM UTC 24
Finished	Sep 09 06:54:40 AM UTC 24
Peak memory	217716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1681564456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all _with_rand_reset.1681564456
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.185558895
Short name	T723
Test name
Test status
Simulation time	1256649289 ps
CPU time	3.17 seconds
Started	Sep 09 06:54:07 AM UTC 24
Finished	Sep 09 06:54:11 AM UTC 24
Peak memory	207536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185558895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.185558895
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/38.uart_tx_rx.3471698982
Short name	T725
Test name
Test status
Simulation time	56471788917 ps
CPU time	41.88 seconds
Started	Sep 09 06:53:39 AM UTC 24
Finished	Sep 09 06:54:23 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471698982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3471698982
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/38.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_alert_test.3268608555
Short name	T742
Test name
Test status
Simulation time	21120321 ps
CPU time	0.82 seconds
Started	Sep 09 06:54:50 AM UTC 24
Finished	Sep 09 06:54:51 AM UTC 24
Peak memory	202392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268608555 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3268608555
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_fifo_full.2898443517
Short name	T783
Test name
Test status
Simulation time	253743699390 ps
CPU time	92.63 seconds
Started	Sep 09 06:54:26 AM UTC 24
Finished	Sep 09 06:56:00 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898443517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2898443517
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.4222026153
Short name	T831
Test name
Test status
Simulation time	108111593477 ps
CPU time	199.46 seconds
Started	Sep 09 06:54:27 AM UTC 24
Finished	Sep 09 06:57:49 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222026153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4222026153
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_fifo_reset.1424459101
Short name	T747
Test name
Test status
Simulation time	26284423192 ps
CPU time	29.23 seconds
Started	Sep 09 06:54:30 AM UTC 24
Finished	Sep 09 06:55:00 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424459101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1424459101
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_intr.944021822
Short name	T821
Test name
Test status
Simulation time	327351269866 ps
CPU time	181.68 seconds
Started	Sep 09 06:54:31 AM UTC 24
Finished	Sep 09 06:57:35 AM UTC 24
Peak memory	207332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944021822 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.944021822
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.577283455
Short name	T996
Test name
Test status
Simulation time	131384082034 ps
CPU time	538.51 seconds
Started	Sep 09 06:54:45 AM UTC 24
Finished	Sep 09 07:03:50 AM UTC 24
Peak memory	208632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577283455 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.577283455
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_loopback.456260937
Short name	T752
Test name
Test status
Simulation time	4956309513 ps
CPU time	22.88 seconds
Started	Sep 09 06:54:44 AM UTC 24
Finished	Sep 09 06:55:08 AM UTC 24
Peak memory	208628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456260937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 39.uart_loopback.456260937
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_noise_filter.3714603507
Short name	T761
Test name
Test status
Simulation time	106188492228 ps
CPU time	45.04 seconds
Started	Sep 09 06:54:32 AM UTC 24
Finished	Sep 09 06:55:19 AM UTC 24
Peak memory	207372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714603507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3714603507
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_perf.3028020277
Short name	T868
Test name
Test status
Simulation time	4469416318 ps
CPU time	245.45 seconds
Started	Sep 09 06:54:45 AM UTC 24
Finished	Sep 09 06:58:54 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028020277 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3028020277
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_rx_oversample.3182935387
Short name	T745
Test name
Test status
Simulation time	3056220614 ps
CPU time	24.71 seconds
Started	Sep 09 06:54:30 AM UTC 24
Finished	Sep 09 06:54:56 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182935387 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3182935387
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.2140083054
Short name	T174
Test name
Test status
Simulation time	93642155533 ps
CPU time	176.06 seconds
Started	Sep 09 06:54:37 AM UTC 24
Finished	Sep 09 06:57:36 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140083054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.2140083054
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.1147740080
Short name	T741
Test name
Test status
Simulation time	33425828500 ps
CPU time	12.37 seconds
Started	Sep 09 06:54:35 AM UTC 24
Finished	Sep 09 06:54:49 AM UTC 24
Peak memory	207272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147740080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1147740080
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_smoke.2136641647
Short name	T729
Test name
Test status
Simulation time	741744606 ps
CPU time	4.15 seconds
Started	Sep 09 06:54:23 AM UTC 24
Finished	Sep 09 06:54:29 AM UTC 24
Peak memory	207296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136641647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2136641647
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_stress_all.1604453657
Short name	T1143
Test name
Test status
Simulation time	365137528374 ps
CPU time	812.02 seconds
Started	Sep 09 06:54:47 AM UTC 24
Finished	Sep 09 07:08:28 AM UTC 24
Peak memory	212140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604453657 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1604453657
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.3660319800
Short name	T762
Test name
Test status
Simulation time	3367511613 ps
CPU time	32.93 seconds
Started	Sep 09 06:54:46 AM UTC 24
Finished	Sep 09 06:55:20 AM UTC 24
Peak memory	217860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3660319800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all _with_rand_reset.3660319800
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1797118056
Short name	T736
Test name
Test status
Simulation time	707336066 ps
CPU time	2.65 seconds
Started	Sep 09 06:54:40 AM UTC 24
Finished	Sep 09 06:54:44 AM UTC 24
Peak memory	207312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797118056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1797118056
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/39.uart_tx_rx.4235962654
Short name	T748
Test name
Test status
Simulation time	14393794589 ps
CPU time	35.22 seconds
Started	Sep 09 06:54:25 AM UTC 24
Finished	Sep 09 06:55:01 AM UTC 24
Peak memory	208664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235962654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4235962654
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/39.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_alert_test.951337882
Short name	T420
Test name
Test status
Simulation time	61770977 ps
CPU time	0.81 seconds
Started	Sep 09 06:31:52 AM UTC 24
Finished	Sep 09 06:31:54 AM UTC 24
Peak memory	204372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951337882 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.951337882
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_fifo_full.4000078315
Short name	T101
Test name
Test status
Simulation time	29058656188 ps
CPU time	105.68 seconds
Started	Sep 09 06:31:04 AM UTC 24
Finished	Sep 09 06:32:52 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000078315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.4000078315
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_intr.3684108307
Short name	T317
Test name
Test status
Simulation time	20960121308 ps
CPU time	58.48 seconds
Started	Sep 09 06:31:10 AM UTC 24
Finished	Sep 09 06:32:10 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684108307 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3684108307
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_loopback.177428486
Short name	T419
Test name
Test status
Simulation time	1059717185 ps
CPU time	1.75 seconds
Started	Sep 09 06:31:29 AM UTC 24
Finished	Sep 09 06:31:32 AM UTC 24
Peak memory	204440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177428486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.uart_loopback.177428486
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_noise_filter.182476211
Short name	T277
Test name
Test status
Simulation time	109722046709 ps
CPU time	188.79 seconds
Started	Sep 09 06:31:14 AM UTC 24
Finished	Sep 09 06:34:25 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182476211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.182476211
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_perf.3544163194
Short name	T303
Test name
Test status
Simulation time	6325605730 ps
CPU time	198.67 seconds
Started	Sep 09 06:31:32 AM UTC 24
Finished	Sep 09 06:34:54 AM UTC 24
Peak memory	208824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544163194 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3544163194
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_rx_oversample.3652715989
Short name	T49
Test name
Test status
Simulation time	2273874310 ps
CPU time	7.66 seconds
Started	Sep 09 06:31:10 AM UTC 24
Finished	Sep 09 06:31:19 AM UTC 24
Peak memory	207288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652715989 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3652715989
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.88430836
Short name	T120
Test name
Test status
Simulation time	15823472640 ps
CPU time	8.78 seconds
Started	Sep 09 06:31:25 AM UTC 24
Finished	Sep 09 06:31:35 AM UTC 24
Peak memory	208536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88430836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.88430836
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.1179012089
Short name	T345
Test name
Test status
Simulation time	53237067968 ps
CPU time	39.02 seconds
Started	Sep 09 06:31:20 AM UTC 24
Finished	Sep 09 06:32:00 AM UTC 24
Peak memory	205100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179012089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1179012089
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_sec_cm.2709705748
Short name	T87
Test name
Test status
Simulation time	52585381 ps
CPU time	1.22 seconds
Started	Sep 09 06:31:49 AM UTC 24
Finished	Sep 09 06:31:51 AM UTC 24
Peak memory	240196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709705748 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2709705748
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_smoke.2031273528
Short name	T50
Test name
Test status
Simulation time	5326803869 ps
CPU time	18.42 seconds
Started	Sep 09 06:31:04 AM UTC 24
Finished	Sep 09 06:31:24 AM UTC 24
Peak memory	208616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031273528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2031273528
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.3230337162
Short name	T37
Test name
Test status
Simulation time	14477054175 ps
CPU time	40.55 seconds
Started	Sep 09 06:31:37 AM UTC 24
Finished	Sep 09 06:32:19 AM UTC 24
Peak memory	221908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3230337162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_ with_rand_reset.3230337162
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.1145637525
Short name	T333
Test name
Test status
Simulation time	145495865 ps
CPU time	1.13 seconds
Started	Sep 09 06:31:26 AM UTC 24
Finished	Sep 09 06:31:28 AM UTC 24
Peak memory	206488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145637525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1145637525
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/4.uart_tx_rx.3197834569
Short name	T304
Test name
Test status
Simulation time	9523948139 ps
CPU time	35.27 seconds
Started	Sep 09 06:31:04 AM UTC 24
Finished	Sep 09 06:31:41 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197834569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3197834569
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/4.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_alert_test.3350536894
Short name	T760
Test name
Test status
Simulation time	15047247 ps
CPU time	0.85 seconds
Started	Sep 09 06:55:16 AM UTC 24
Finished	Sep 09 06:55:19 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350536894 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3350536894
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_fifo_full.1484186801
Short name	T765
Test name
Test status
Simulation time	199434275893 ps
CPU time	25.83 seconds
Started	Sep 09 06:54:54 AM UTC 24
Finished	Sep 09 06:55:21 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484186801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.1484186801
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.3728892523
Short name	T910
Test name
Test status
Simulation time	209420735491 ps
CPU time	327.92 seconds
Started	Sep 09 06:54:56 AM UTC 24
Finished	Sep 09 07:00:28 AM UTC 24
Peak memory	208792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728892523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3728892523
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_intr.3161555842
Short name	T805
Test name
Test status
Simulation time	48554128870 ps
CPU time	107.96 seconds
Started	Sep 09 06:55:01 AM UTC 24
Finished	Sep 09 06:56:51 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161555842 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3161555842
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3700628650
Short name	T909
Test name
Test status
Simulation time	79604916868 ps
CPU time	311.33 seconds
Started	Sep 09 06:55:10 AM UTC 24
Finished	Sep 09 07:00:26 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700628650 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3700628650
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_loopback.3200630050
Short name	T774
Test name
Test status
Simulation time	8805765937 ps
CPU time	26.64 seconds
Started	Sep 09 06:55:10 AM UTC 24
Finished	Sep 09 06:55:38 AM UTC 24
Peak memory	208524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200630050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.3200630050
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_noise_filter.281917432
Short name	T824
Test name
Test status
Simulation time	85293491784 ps
CPU time	152.94 seconds
Started	Sep 09 06:55:02 AM UTC 24
Finished	Sep 09 06:57:38 AM UTC 24
Peak memory	208844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281917432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.281917432
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_perf.2050713345
Short name	T925
Test name
Test status
Simulation time	7809881722 ps
CPU time	347.8 seconds
Started	Sep 09 06:55:10 AM UTC 24
Finished	Sep 09 07:01:02 AM UTC 24
Peak memory	208732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050713345 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.2050713345
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_rx_oversample.179072704
Short name	T756
Test name
Test status
Simulation time	4350778482 ps
CPU time	13.93 seconds
Started	Sep 09 06:54:59 AM UTC 24
Finished	Sep 09 06:55:14 AM UTC 24
Peak memory	207420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179072704 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.179072704
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.26899762
Short name	T759
Test name
Test status
Simulation time	11644579946 ps
CPU time	12.06 seconds
Started	Sep 09 06:55:04 AM UTC 24
Finished	Sep 09 06:55:18 AM UTC 24
Peak memory	208920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26899762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.26899762
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.972047297
Short name	T790
Test name
Test status
Simulation time	36115615362 ps
CPU time	70.71 seconds
Started	Sep 09 06:55:04 AM UTC 24
Finished	Sep 09 06:56:17 AM UTC 24
Peak memory	205224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972047297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.972047297
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_smoke.3684801597
Short name	T744
Test name
Test status
Simulation time	960738716 ps
CPU time	2.26 seconds
Started	Sep 09 06:54:52 AM UTC 24
Finished	Sep 09 06:54:55 AM UTC 24
Peak memory	207576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684801597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3684801597
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_stress_all.2686063775
Short name	T1189
Test name
Test status
Simulation time	191116889920 ps
CPU time	2001.2 seconds
Started	Sep 09 06:55:15 AM UTC 24
Finished	Sep 09 07:28:59 AM UTC 24
Peak memory	221120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686063775 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2686063775
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.1632588883
Short name	T766
Test name
Test status
Simulation time	1934065020 ps
CPU time	11.18 seconds
Started	Sep 09 06:55:11 AM UTC 24
Finished	Sep 09 06:55:24 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1632588883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all _with_rand_reset.1632588883
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.1417690496
Short name	T754
Test name
Test status
Simulation time	3032860138 ps
CPU time	2.8 seconds
Started	Sep 09 06:55:06 AM UTC 24
Finished	Sep 09 06:55:09 AM UTC 24
Peak memory	207628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417690496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1417690496
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/40.uart_tx_rx.2100122494
Short name	T902
Test name
Test status
Simulation time	110039016733 ps
CPU time	303.39 seconds
Started	Sep 09 06:54:53 AM UTC 24
Finished	Sep 09 07:00:00 AM UTC 24
Peak memory	208652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100122494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2100122494
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/40.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_alert_test.2244319024
Short name	T775
Test name
Test status
Simulation time	14825141 ps
CPU time	0.86 seconds
Started	Sep 09 06:55:38 AM UTC 24
Finished	Sep 09 06:55:40 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244319024 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2244319024
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_fifo_full.3470015817
Short name	T787
Test name
Test status
Simulation time	53573330894 ps
CPU time	53.18 seconds
Started	Sep 09 06:55:19 AM UTC 24
Finished	Sep 09 06:56:14 AM UTC 24
Peak memory	208716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470015817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3470015817
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.1439326345
Short name	T795
Test name
Test status
Simulation time	39371891422 ps
CPU time	66.92 seconds
Started	Sep 09 06:55:19 AM UTC 24
Finished	Sep 09 06:56:28 AM UTC 24
Peak memory	208856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439326345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1439326345
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_fifo_reset.2796555957
Short name	T203
Test name
Test status
Simulation time	77282714995 ps
CPU time	155.02 seconds
Started	Sep 09 06:55:20 AM UTC 24
Finished	Sep 09 06:57:58 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796555957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2796555957
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_intr.1695388588
Short name	T773
Test name
Test status
Simulation time	5947461889 ps
CPU time	13.88 seconds
Started	Sep 09 06:55:22 AM UTC 24
Finished	Sep 09 06:55:37 AM UTC 24
Peak memory	207148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695388588 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1695388588
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.2876588749
Short name	T931
Test name
Test status
Simulation time	98637548031 ps
CPU time	337.8 seconds
Started	Sep 09 06:55:33 AM UTC 24
Finished	Sep 09 07:01:15 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876588749 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2876588749
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_loopback.4078453426
Short name	T780
Test name
Test status
Simulation time	5380792433 ps
CPU time	22.08 seconds
Started	Sep 09 06:55:31 AM UTC 24
Finished	Sep 09 06:55:54 AM UTC 24
Peak memory	207148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078453426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4078453426
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_noise_filter.45968061
Short name	T799
Test name
Test status
Simulation time	43482979614 ps
CPU time	70.26 seconds
Started	Sep 09 06:55:22 AM UTC 24
Finished	Sep 09 06:56:34 AM UTC 24
Peak memory	208772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45968061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.45968061
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_perf.326908358
Short name	T1003
Test name
Test status
Simulation time	20728423457 ps
CPU time	502.3 seconds
Started	Sep 09 06:55:33 AM UTC 24
Finished	Sep 09 07:04:02 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326908358 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.326908358
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_rx_oversample.420520864
Short name	T770
Test name
Test status
Simulation time	4702710279 ps
CPU time	10.01 seconds
Started	Sep 09 06:55:20 AM UTC 24
Finished	Sep 09 06:55:32 AM UTC 24
Peak memory	207292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420520864 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.420520864
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.2654831392
Short name	T781
Test name
Test status
Simulation time	30266089667 ps
CPU time	25.51 seconds
Started	Sep 09 06:55:29 AM UTC 24
Finished	Sep 09 06:55:56 AM UTC 24
Peak memory	208676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654831392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2654831392
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.205439084
Short name	T776
Test name
Test status
Simulation time	78835211793 ps
CPU time	17.29 seconds
Started	Sep 09 06:55:25 AM UTC 24
Finished	Sep 09 06:55:43 AM UTC 24
Peak memory	207144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205439084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.205439084
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_smoke.51413343
Short name	T764
Test name
Test status
Simulation time	483639240 ps
CPU time	2.24 seconds
Started	Sep 09 06:55:17 AM UTC 24
Finished	Sep 09 06:55:21 AM UTC 24
Peak memory	207204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51413343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 41.uart_smoke.51413343
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_stress_all.1558942121
Short name	T1037
Test name
Test status
Simulation time	255994874331 ps
CPU time	555.79 seconds
Started	Sep 09 06:55:37 AM UTC 24
Finished	Sep 09 07:04:59 AM UTC 24
Peak memory	208716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558942121 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1558942121
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.2561229401
Short name	T802
Test name
Test status
Simulation time	66670416947 ps
CPU time	65.03 seconds
Started	Sep 09 06:55:36 AM UTC 24
Finished	Sep 09 06:56:43 AM UTC 24
Peak memory	217596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2561229401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all _with_rand_reset.2561229401
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.3113046965
Short name	T777
Test name
Test status
Simulation time	7746482991 ps
CPU time	15.03 seconds
Started	Sep 09 06:55:29 AM UTC 24
Finished	Sep 09 06:55:45 AM UTC 24
Peak memory	208648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113046965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3113046965
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/41.uart_tx_rx.3061575958
Short name	T767
Test name
Test status
Simulation time	36525789430 ps
CPU time	8.01 seconds
Started	Sep 09 06:55:18 AM UTC 24
Finished	Sep 09 06:55:27 AM UTC 24
Peak memory	208748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061575958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3061575958
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/41.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_alert_test.2457129429
Short name	T793
Test name
Test status
Simulation time	64195700 ps
CPU time	0.82 seconds
Started	Sep 09 06:56:25 AM UTC 24
Finished	Sep 09 06:56:26 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457129429 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.2457129429
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_fifo_full.3184848385
Short name	T788
Test name
Test status
Simulation time	16119912798 ps
CPU time	27.47 seconds
Started	Sep 09 06:55:46 AM UTC 24
Finished	Sep 09 06:56:15 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184848385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3184848385
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.3521700944
Short name	T891
Test name
Test status
Simulation time	88870817018 ps
CPU time	225.05 seconds
Started	Sep 09 06:55:48 AM UTC 24
Finished	Sep 09 06:59:36 AM UTC 24
Peak memory	208860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521700944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.3521700944
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_fifo_reset.3763749311
Short name	T204
Test name
Test status
Simulation time	61957357936 ps
CPU time	130.54 seconds
Started	Sep 09 06:55:49 AM UTC 24
Finished	Sep 09 06:58:01 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763749311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3763749311
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_intr.259229718
Short name	T817
Test name
Test status
Simulation time	203794948434 ps
CPU time	85.52 seconds
Started	Sep 09 06:55:57 AM UTC 24
Finished	Sep 09 06:57:24 AM UTC 24
Peak memory	207624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259229718 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.259229718
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.3310450176
Short name	T894
Test name
Test status
Simulation time	77130595028 ps
CPU time	198.55 seconds
Started	Sep 09 06:56:16 AM UTC 24
Finished	Sep 09 06:59:38 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310450176 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3310450176
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_loopback.799472520
Short name	T791
Test name
Test status
Simulation time	8643280342 ps
CPU time	9.5 seconds
Started	Sep 09 06:56:13 AM UTC 24
Finished	Sep 09 06:56:24 AM UTC 24
Peak memory	208652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799472520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.uart_loopback.799472520
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_noise_filter.1696612
Short name	T970
Test name
Test status
Simulation time	127500356416 ps
CPU time	406.51 seconds
Started	Sep 09 06:56:00 AM UTC 24
Finished	Sep 09 07:02:51 AM UTC 24
Peak memory	208800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1696612
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_perf.2386753499
Short name	T1072
Test name
Test status
Simulation time	10173030378 ps
CPU time	567.06 seconds
Started	Sep 09 06:56:15 AM UTC 24
Finished	Sep 09 07:05:49 AM UTC 24
Peak memory	210376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386753499 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2386753499
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_rx_oversample.604435402
Short name	T822
Test name
Test status
Simulation time	7718544308 ps
CPU time	98.55 seconds
Started	Sep 09 06:55:56 AM UTC 24
Finished	Sep 09 06:57:36 AM UTC 24
Peak memory	207420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604435402 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.604435402
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.3434586059
Short name	T181
Test name
Test status
Simulation time	174182962138 ps
CPU time	165.39 seconds
Started	Sep 09 06:56:04 AM UTC 24
Finished	Sep 09 06:58:52 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434586059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3434586059
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.2499912866
Short name	T785
Test name
Test status
Simulation time	38240948574 ps
CPU time	9.96 seconds
Started	Sep 09 06:56:01 AM UTC 24
Finished	Sep 09 06:56:12 AM UTC 24
Peak memory	205224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499912866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2499912866
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_smoke.1225523685
Short name	T779
Test name
Test status
Simulation time	5641066610 ps
CPU time	5.12 seconds
Started	Sep 09 06:55:41 AM UTC 24
Finished	Sep 09 06:55:47 AM UTC 24
Peak memory	207968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225523685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1225523685
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_stress_all.1565723168
Short name	T921
Test name
Test status
Simulation time	379952507154 ps
CPU time	269.33 seconds
Started	Sep 09 06:56:18 AM UTC 24
Finished	Sep 09 07:00:51 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565723168 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1565723168
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.969790708
Short name	T797
Test name
Test status
Simulation time	1198800767 ps
CPU time	13.05 seconds
Started	Sep 09 06:56:17 AM UTC 24
Finished	Sep 09 06:56:32 AM UTC 24
Peak memory	225136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=969790708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all_ with_rand_reset.969790708
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.3974668560
Short name	T789
Test name
Test status
Simulation time	6953425080 ps
CPU time	2.64 seconds
Started	Sep 09 06:56:13 AM UTC 24
Finished	Sep 09 06:56:17 AM UTC 24
Peak memory	207476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974668560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3974668560
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/42.uart_tx_rx.4183469697
Short name	T809
Test name
Test status
Simulation time	115878591769 ps
CPU time	79.2 seconds
Started	Sep 09 06:55:44 AM UTC 24
Finished	Sep 09 06:57:05 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183469697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.4183469697
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/42.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_alert_test.3869957102
Short name	T807
Test name
Test status
Simulation time	11771812 ps
CPU time	0.83 seconds
Started	Sep 09 06:56:57 AM UTC 24
Finished	Sep 09 06:56:59 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869957102 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3869957102
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_fifo_full.492706619
Short name	T908
Test name
Test status
Simulation time	120099677067 ps
CPU time	232.89 seconds
Started	Sep 09 06:56:28 AM UTC 24
Finished	Sep 09 07:00:24 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492706619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.492706619
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.3107938620
Short name	T814
Test name
Test status
Simulation time	20233821384 ps
CPU time	42.24 seconds
Started	Sep 09 06:56:29 AM UTC 24
Finished	Sep 09 06:57:13 AM UTC 24
Peak memory	208772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107938620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.3107938620
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_fifo_reset.552407721
Short name	T220
Test name
Test status
Simulation time	87992549621 ps
CPU time	60.66 seconds
Started	Sep 09 06:56:30 AM UTC 24
Finished	Sep 09 06:57:32 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552407721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.552407721
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_intr.3767341816
Short name	T820
Test name
Test status
Simulation time	54957954285 ps
CPU time	59.13 seconds
Started	Sep 09 06:56:34 AM UTC 24
Finished	Sep 09 06:57:35 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767341816 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3767341816
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.374962319
Short name	T939
Test name
Test status
Simulation time	97099437449 ps
CPU time	286.39 seconds
Started	Sep 09 06:56:45 AM UTC 24
Finished	Sep 09 07:01:35 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374962319 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.374962319
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_loopback.3068795451
Short name	T804
Test name
Test status
Simulation time	2936617699 ps
CPU time	5.61 seconds
Started	Sep 09 06:56:43 AM UTC 24
Finished	Sep 09 06:56:49 AM UTC 24
Peak memory	208232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068795451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3068795451
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_noise_filter.2400171290
Short name	T848
Test name
Test status
Simulation time	104865774187 ps
CPU time	103.97 seconds
Started	Sep 09 06:56:34 AM UTC 24
Finished	Sep 09 06:58:21 AM UTC 24
Peak memory	217596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400171290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2400171290
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_perf.7689589
Short name	T1032
Test name
Test status
Simulation time	7751262866 ps
CPU time	482.06 seconds
Started	Sep 09 06:56:44 AM UTC 24
Finished	Sep 09 07:04:52 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7689589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM _TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.7689589
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_rx_oversample.659723738
Short name	T830
Test name
Test status
Simulation time	7051028803 ps
CPU time	72.54 seconds
Started	Sep 09 06:56:32 AM UTC 24
Finished	Sep 09 06:57:47 AM UTC 24
Peak memory	207756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659723738 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.659723738
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.1111644772
Short name	T811
Test name
Test status
Simulation time	54039699068 ps
CPU time	26.19 seconds
Started	Sep 09 06:56:40 AM UTC 24
Finished	Sep 09 06:57:08 AM UTC 24
Peak memory	208860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111644772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1111644772
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.1571347364
Short name	T813
Test name
Test status
Simulation time	39038348636 ps
CPU time	31.01 seconds
Started	Sep 09 06:56:39 AM UTC 24
Finished	Sep 09 06:57:12 AM UTC 24
Peak memory	207272 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571347364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1571347364
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_smoke.2767556285
Short name	T796
Test name
Test status
Simulation time	468059590 ps
CPU time	2.18 seconds
Started	Sep 09 06:56:26 AM UTC 24
Finished	Sep 09 06:56:29 AM UTC 24
Peak memory	207380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767556285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2767556285
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_stress_all.2192347512
Short name	T969
Test name
Test status
Simulation time	278898547373 ps
CPU time	352.07 seconds
Started	Sep 09 06:56:52 AM UTC 24
Finished	Sep 09 07:02:49 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192347512 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2192347512
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.4124632518
Short name	T392
Test name
Test status
Simulation time	12508164599 ps
CPU time	92.42 seconds
Started	Sep 09 06:56:50 AM UTC 24
Finished	Sep 09 06:58:25 AM UTC 24
Peak memory	225540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4124632518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all _with_rand_reset.4124632518
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.595531160
Short name	T815
Test name
Test status
Simulation time	6928053805 ps
CPU time	31.31 seconds
Started	Sep 09 06:56:41 AM UTC 24
Finished	Sep 09 06:57:13 AM UTC 24
Peak memory	208604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595531160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.595531160
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/43.uart_tx_rx.1941714295
Short name	T871
Test name
Test status
Simulation time	117408586491 ps
CPU time	146.86 seconds
Started	Sep 09 06:56:27 AM UTC 24
Finished	Sep 09 06:58:56 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941714295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1941714295
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/43.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_alert_test.3814609008
Short name	T825
Test name
Test status
Simulation time	26954163 ps
CPU time	0.83 seconds
Started	Sep 09 06:57:36 AM UTC 24
Finished	Sep 09 06:57:38 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814609008 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3814609008
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_fifo_full.4220543033
Short name	T172
Test name
Test status
Simulation time	103544897308 ps
CPU time	46.88 seconds
Started	Sep 09 06:57:06 AM UTC 24
Finished	Sep 09 06:57:55 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220543033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.4220543033
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.2945431514
Short name	T845
Test name
Test status
Simulation time	32208174366 ps
CPU time	65.32 seconds
Started	Sep 09 06:57:06 AM UTC 24
Finished	Sep 09 06:58:13 AM UTC 24
Peak memory	208612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945431514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.2945431514
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_fifo_reset.362939988
Short name	T208
Test name
Test status
Simulation time	61162436380 ps
CPU time	79.8 seconds
Started	Sep 09 06:57:08 AM UTC 24
Finished	Sep 09 06:58:30 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362939988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.362939988
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_intr.1677165451
Short name	T1002
Test name
Test status
Simulation time	261410610276 ps
CPU time	450.74 seconds
Started	Sep 09 06:57:13 AM UTC 24
Finished	Sep 09 07:04:49 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677165451 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1677165451
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.1481050759
Short name	T1051
Test name
Test status
Simulation time	211763277471 ps
CPU time	454.21 seconds
Started	Sep 09 06:57:33 AM UTC 24
Finished	Sep 09 07:05:13 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481050759 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1481050759
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_loopback.3133898262
Short name	T827
Test name
Test status
Simulation time	10244363303 ps
CPU time	13.72 seconds
Started	Sep 09 06:57:26 AM UTC 24
Finished	Sep 09 06:57:41 AM UTC 24
Peak memory	208644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133898262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3133898262
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_noise_filter.1417876057
Short name	T838
Test name
Test status
Simulation time	102201692665 ps
CPU time	46.05 seconds
Started	Sep 09 06:57:14 AM UTC 24
Finished	Sep 09 06:58:01 AM UTC 24
Peak memory	208900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417876057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1417876057
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_perf.2709148484
Short name	T895
Test name
Test status
Simulation time	21045112889 ps
CPU time	128.03 seconds
Started	Sep 09 06:57:30 AM UTC 24
Finished	Sep 09 06:59:41 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709148484 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2709148484
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_rx_oversample.279429007
Short name	T833
Test name
Test status
Simulation time	5243193476 ps
CPU time	41.51 seconds
Started	Sep 09 06:57:10 AM UTC 24
Finished	Sep 09 06:57:52 AM UTC 24
Peak memory	207484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279429007 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.279429007
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.2119771261
Short name	T828
Test name
Test status
Simulation time	37483003986 ps
CPU time	25.16 seconds
Started	Sep 09 06:57:15 AM UTC 24
Finished	Sep 09 06:57:41 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119771261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.2119771261
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.3108244470
Short name	T818
Test name
Test status
Simulation time	3672920484 ps
CPU time	10.58 seconds
Started	Sep 09 06:57:14 AM UTC 24
Finished	Sep 09 06:57:25 AM UTC 24
Peak memory	205288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108244470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3108244470
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_smoke.2595245167
Short name	T810
Test name
Test status
Simulation time	693807959 ps
CPU time	4.44 seconds
Started	Sep 09 06:57:00 AM UTC 24
Finished	Sep 09 06:57:06 AM UTC 24
Peak memory	207252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595245167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2595245167
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_stress_all.3940847257
Short name	T1168
Test name
Test status
Simulation time	223591573037 ps
CPU time	702.87 seconds
Started	Sep 09 06:57:36 AM UTC 24
Finished	Sep 09 07:09:27 AM UTC 24
Peak memory	212240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940847257 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3940847257
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.3809950578
Short name	T862
Test name
Test status
Simulation time	4246466139 ps
CPU time	69.13 seconds
Started	Sep 09 06:57:36 AM UTC 24
Finished	Sep 09 06:58:47 AM UTC 24
Peak memory	221944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3809950578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all _with_rand_reset.3809950578
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.319305834
Short name	T819
Test name
Test status
Simulation time	567982323 ps
CPU time	3.18 seconds
Started	Sep 09 06:57:25 AM UTC 24
Finished	Sep 09 06:57:29 AM UTC 24
Peak memory	207472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319305834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.319305834
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/44.uart_tx_rx.3960285956
Short name	T876
Test name
Test status
Simulation time	70785879087 ps
CPU time	120.91 seconds
Started	Sep 09 06:57:03 AM UTC 24
Finished	Sep 09 06:59:06 AM UTC 24
Peak memory	208712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960285956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3960285956
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/44.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_alert_test.4040532944
Short name	T842
Test name
Test status
Simulation time	10428519 ps
CPU time	0.81 seconds
Started	Sep 09 06:58:03 AM UTC 24
Finished	Sep 09 06:58:04 AM UTC 24
Peak memory	202392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040532944 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.4040532944
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_fifo_full.127216146
Short name	T855
Test name
Test status
Simulation time	129459503408 ps
CPU time	53.37 seconds
Started	Sep 09 06:57:39 AM UTC 24
Finished	Sep 09 06:58:34 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127216146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.127216146
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.2907852579
Short name	T852
Test name
Test status
Simulation time	26788903235 ps
CPU time	45.24 seconds
Started	Sep 09 06:57:41 AM UTC 24
Finished	Sep 09 06:58:27 AM UTC 24
Peak memory	208936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907852579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.2907852579
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_fifo_reset.4037934293
Short name	T237
Test name
Test status
Simulation time	19889186914 ps
CPU time	47.85 seconds
Started	Sep 09 06:57:42 AM UTC 24
Finished	Sep 09 06:58:31 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037934293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4037934293
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_intr.2137001367
Short name	T832
Test name
Test status
Simulation time	5484772288 ps
CPU time	3.18 seconds
Started	Sep 09 06:57:48 AM UTC 24
Finished	Sep 09 06:57:52 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137001367 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2137001367
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.3140014422
Short name	T966
Test name
Test status
Simulation time	145072791615 ps
CPU time	281.68 seconds
Started	Sep 09 06:57:59 AM UTC 24
Finished	Sep 09 07:02:45 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140014422 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3140014422
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_loopback.1595551876
Short name	T846
Test name
Test status
Simulation time	5230369596 ps
CPU time	21.84 seconds
Started	Sep 09 06:57:54 AM UTC 24
Finished	Sep 09 06:58:17 AM UTC 24
Peak memory	207968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595551876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1595551876
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_noise_filter.258420191
Short name	T859
Test name
Test status
Simulation time	35128371076 ps
CPU time	53.98 seconds
Started	Sep 09 06:57:48 AM UTC 24
Finished	Sep 09 06:58:43 AM UTC 24
Peak memory	208840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258420191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.258420191
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_perf.395947512
Short name	T1092
Test name
Test status
Simulation time	18428003200 ps
CPU time	509.79 seconds
Started	Sep 09 06:57:55 AM UTC 24
Finished	Sep 09 07:06:31 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395947512 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.395947512
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_rx_oversample.87348649
Short name	T837
Test name
Test status
Simulation time	5852910219 ps
CPU time	15.63 seconds
Started	Sep 09 06:57:42 AM UTC 24
Finished	Sep 09 06:57:59 AM UTC 24
Peak memory	207700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87348649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.87348649
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.754845397
Short name	T869
Test name
Test status
Simulation time	105229376773 ps
CPU time	61.1 seconds
Started	Sep 09 06:57:53 AM UTC 24
Finished	Sep 09 06:58:56 AM UTC 24
Peak memory	208984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754845397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.754845397
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2458765361
Short name	T834
Test name
Test status
Simulation time	1596370136 ps
CPU time	2.49 seconds
Started	Sep 09 06:57:50 AM UTC 24
Finished	Sep 09 06:57:53 AM UTC 24
Peak memory	205160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458765361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2458765361
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_smoke.1143542796
Short name	T826
Test name
Test status
Simulation time	265033790 ps
CPU time	1.38 seconds
Started	Sep 09 06:57:37 AM UTC 24
Finished	Sep 09 06:57:40 AM UTC 24
Peak memory	206436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143542796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1143542796
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_stress_all.362231665
Short name	T961
Test name
Test status
Simulation time	250236768672 ps
CPU time	268.98 seconds
Started	Sep 09 06:58:02 AM UTC 24
Finished	Sep 09 07:02:35 AM UTC 24
Peak memory	217808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362231665 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.362231665
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.1794732281
Short name	T860
Test name
Test status
Simulation time	3994159577 ps
CPU time	43.53 seconds
Started	Sep 09 06:57:59 AM UTC 24
Finished	Sep 09 06:58:45 AM UTC 24
Peak memory	217768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1794732281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all _with_rand_reset.1794732281
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.220480069
Short name	T847
Test name
Test status
Simulation time	6062221168 ps
CPU time	25.95 seconds
Started	Sep 09 06:57:53 AM UTC 24
Finished	Sep 09 06:58:20 AM UTC 24
Peak memory	208732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220480069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.220480069
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/45.uart_tx_rx.2093449321
Short name	T844
Test name
Test status
Simulation time	71919027493 ps
CPU time	29.49 seconds
Started	Sep 09 06:57:39 AM UTC 24
Finished	Sep 09 06:58:09 AM UTC 24
Peak memory	208636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093449321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2093449321
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/45.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_alert_test.1004671384
Short name	T854
Test name
Test status
Simulation time	17255377 ps
CPU time	0.84 seconds
Started	Sep 09 06:58:31 AM UTC 24
Finished	Sep 09 06:58:33 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004671384 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1004671384
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_fifo_full.4013370013
Short name	T863
Test name
Test status
Simulation time	16492430139 ps
CPU time	41.92 seconds
Started	Sep 09 06:58:05 AM UTC 24
Finished	Sep 09 06:58:49 AM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013370013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.4013370013
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.3928763722
Short name	T883
Test name
Test status
Simulation time	27881136186 ps
CPU time	75 seconds
Started	Sep 09 06:58:05 AM UTC 24
Finished	Sep 09 06:59:22 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928763722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3928763722
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_fifo_reset.2912958095
Short name	T221
Test name
Test status
Simulation time	24267301699 ps
CPU time	52.11 seconds
Started	Sep 09 06:58:08 AM UTC 24
Finished	Sep 09 06:59:02 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912958095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2912958095
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_intr.2475406277
Short name	T857
Test name
Test status
Simulation time	38299360901 ps
CPU time	21.01 seconds
Started	Sep 09 06:58:14 AM UTC 24
Finished	Sep 09 06:58:36 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475406277 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2475406277
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.3426972759
Short name	T1036
Test name
Test status
Simulation time	251196748408 ps
CPU time	385.53 seconds
Started	Sep 09 06:58:28 AM UTC 24
Finished	Sep 09 07:04:58 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426972759 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3426972759
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_loopback.3654296613
Short name	T853
Test name
Test status
Simulation time	6031184822 ps
CPU time	6.36 seconds
Started	Sep 09 06:58:22 AM UTC 24
Finished	Sep 09 06:58:30 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654296613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3654296613
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_noise_filter.324272435
Short name	T922
Test name
Test status
Simulation time	72971522449 ps
CPU time	150.73 seconds
Started	Sep 09 06:58:18 AM UTC 24
Finished	Sep 09 07:00:52 AM UTC 24
Peak memory	208772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324272435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.324272435
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_perf.3391674528
Short name	T1100
Test name
Test status
Simulation time	9399489086 ps
CPU time	501.45 seconds
Started	Sep 09 06:58:26 AM UTC 24
Finished	Sep 09 07:06:53 AM UTC 24
Peak memory	210172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391674528 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3391674528
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_rx_oversample.1371362360
Short name	T849
Test name
Test status
Simulation time	1697833196 ps
CPU time	9.44 seconds
Started	Sep 09 06:58:10 AM UTC 24
Finished	Sep 09 06:58:21 AM UTC 24
Peak memory	207224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371362360 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.1371362360
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.892164554
Short name	T892
Test name
Test status
Simulation time	92125093809 ps
CPU time	73.36 seconds
Started	Sep 09 06:58:21 AM UTC 24
Finished	Sep 09 06:59:37 AM UTC 24
Peak memory	208664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892164554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.892164554
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.3537883594
Short name	T858
Test name
Test status
Simulation time	41019153592 ps
CPU time	18.01 seconds
Started	Sep 09 06:58:21 AM UTC 24
Finished	Sep 09 06:58:41 AM UTC 24
Peak memory	205024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537883594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3537883594
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_smoke.708492012
Short name	T843
Test name
Test status
Simulation time	505862077 ps
CPU time	1.79 seconds
Started	Sep 09 06:58:04 AM UTC 24
Finished	Sep 09 06:58:07 AM UTC 24
Peak memory	206384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708492012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 46.uart_smoke.708492012
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_stress_all.1395372350
Short name	T175
Test name
Test status
Simulation time	112245722193 ps
CPU time	68.38 seconds
Started	Sep 09 06:58:31 AM UTC 24
Finished	Sep 09 06:59:41 AM UTC 24
Peak memory	208808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395372350 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1395372350
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.3620149513
Short name	T875
Test name
Test status
Simulation time	1727716309 ps
CPU time	32.89 seconds
Started	Sep 09 06:58:28 AM UTC 24
Finished	Sep 09 06:59:02 AM UTC 24
Peak memory	208852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3620149513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all _with_rand_reset.3620149513
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.1416727330
Short name	T851
Test name
Test status
Simulation time	2232507987 ps
CPU time	3.59 seconds
Started	Sep 09 06:58:21 AM UTC 24
Finished	Sep 09 06:58:26 AM UTC 24
Peak memory	207336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416727330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.1416727330
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/46.uart_tx_rx.3940106603
Short name	T864
Test name
Test status
Simulation time	61806908779 ps
CPU time	43.31 seconds
Started	Sep 09 06:58:04 AM UTC 24
Finished	Sep 09 06:58:49 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940106603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3940106603
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/46.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_alert_test.3055854841
Short name	T870
Test name
Test status
Simulation time	29274723 ps
CPU time	0.82 seconds
Started	Sep 09 06:58:54 AM UTC 24
Finished	Sep 09 06:58:56 AM UTC 24
Peak memory	204440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055854841 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3055854841
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_fifo_full.214879885
Short name	T890
Test name
Test status
Simulation time	33289557332 ps
CPU time	57.68 seconds
Started	Sep 09 06:58:34 AM UTC 24
Finished	Sep 09 06:59:33 AM UTC 24
Peak memory	208684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214879885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.214879885
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.1323008374
Short name	T866
Test name
Test status
Simulation time	12652772005 ps
CPU time	16.43 seconds
Started	Sep 09 06:58:35 AM UTC 24
Finished	Sep 09 06:58:53 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323008374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.1323008374
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_fifo_reset.1137035338
Short name	T898
Test name
Test status
Simulation time	22594978978 ps
CPU time	66.8 seconds
Started	Sep 09 06:58:36 AM UTC 24
Finished	Sep 09 06:59:45 AM UTC 24
Peak memory	208624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137035338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1137035338
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_intr.2154999648
Short name	T886
Test name
Test status
Simulation time	32618656514 ps
CPU time	40.93 seconds
Started	Sep 09 06:58:41 AM UTC 24
Finished	Sep 09 06:59:24 AM UTC 24
Peak memory	208812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154999648 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2154999648
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.3473594709
Short name	T1175
Test name
Test status
Simulation time	118803153041 ps
CPU time	667.35 seconds
Started	Sep 09 06:58:53 AM UTC 24
Finished	Sep 09 07:10:08 AM UTC 24
Peak memory	212228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473594709 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.3473594709
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_loopback.2991321654
Short name	T865
Test name
Test status
Simulation time	535454655 ps
CPU time	1.57 seconds
Started	Sep 09 06:58:50 AM UTC 24
Finished	Sep 09 06:58:52 AM UTC 24
Peak memory	206440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991321654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2991321654
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_noise_filter.851455314
Short name	T884
Test name
Test status
Simulation time	18340278147 ps
CPU time	37.27 seconds
Started	Sep 09 06:58:44 AM UTC 24
Finished	Sep 09 06:59:23 AM UTC 24
Peak memory	208196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851455314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.851455314
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_perf.1997720855
Short name	T934
Test name
Test status
Simulation time	11011983933 ps
CPU time	156.82 seconds
Started	Sep 09 06:58:50 AM UTC 24
Finished	Sep 09 07:01:29 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997720855 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1997720855
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_rx_oversample.2104781254
Short name	T861
Test name
Test status
Simulation time	2328529417 ps
CPU time	7.12 seconds
Started	Sep 09 06:58:37 AM UTC 24
Finished	Sep 09 06:58:45 AM UTC 24
Peak memory	207352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104781254 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2104781254
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.1148113290
Short name	T920
Test name
Test status
Simulation time	140602074439 ps
CPU time	119.37 seconds
Started	Sep 09 06:58:47 AM UTC 24
Finished	Sep 09 07:00:48 AM UTC 24
Peak memory	208732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148113290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.1148113290
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.2139554089
Short name	T873
Test name
Test status
Simulation time	5195594234 ps
CPU time	10.59 seconds
Started	Sep 09 06:58:46 AM UTC 24
Finished	Sep 09 06:58:57 AM UTC 24
Peak memory	207208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139554089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2139554089
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_smoke.747737197
Short name	T856
Test name
Test status
Simulation time	585955281 ps
CPU time	1.63 seconds
Started	Sep 09 06:58:32 AM UTC 24
Finished	Sep 09 06:58:35 AM UTC 24
Peak memory	207956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747737197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 47.uart_smoke.747737197
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_stress_all.2175710662
Short name	T903
Test name
Test status
Simulation time	90643346421 ps
CPU time	69.74 seconds
Started	Sep 09 06:58:54 AM UTC 24
Finished	Sep 09 07:00:05 AM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175710662 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2175710662
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.2156858529
Short name	T893
Test name
Test status
Simulation time	15309143283 ps
CPU time	43.02 seconds
Started	Sep 09 06:58:53 AM UTC 24
Finished	Sep 09 06:59:37 AM UTC 24
Peak memory	217844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2156858529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all _with_rand_reset.2156858529
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.3664968713
Short name	T874
Test name
Test status
Simulation time	8279680492 ps
CPU time	10.45 seconds
Started	Sep 09 06:58:48 AM UTC 24
Finished	Sep 09 06:58:59 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664968713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.3664968713
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/47.uart_tx_rx.199876085
Short name	T878
Test name
Test status
Simulation time	53138160759 ps
CPU time	35.75 seconds
Started	Sep 09 06:58:34 AM UTC 24
Finished	Sep 09 06:59:11 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199876085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.199876085
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/47.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_alert_test.988212013
Short name	T887
Test name
Test status
Simulation time	12155203 ps
CPU time	0.8 seconds
Started	Sep 09 06:59:22 AM UTC 24
Finished	Sep 09 06:59:24 AM UTC 24
Peak memory	202392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988212013 -assert nopostproc +UVM_TESTNAME=uart_b ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.988212013
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_fifo_full.3922893557
Short name	T1014
Test name
Test status
Simulation time	119753081440 ps
CPU time	329.34 seconds
Started	Sep 09 06:58:56 AM UTC 24
Finished	Sep 09 07:04:30 AM UTC 24
Peak memory	208960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922893557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3922893557
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.3603041964
Short name	T913
Test name
Test status
Simulation time	110513733936 ps
CPU time	99.44 seconds
Started	Sep 09 06:58:57 AM UTC 24
Finished	Sep 09 07:00:39 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603041964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3603041964
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_fifo_reset.3627142987
Short name	T880
Test name
Test status
Simulation time	130545377992 ps
CPU time	17.22 seconds
Started	Sep 09 06:58:58 AM UTC 24
Finished	Sep 09 06:59:17 AM UTC 24
Peak memory	208772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627142987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3627142987
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_intr.1941917150
Short name	T889
Test name
Test status
Simulation time	42803484252 ps
CPU time	28.78 seconds
Started	Sep 09 06:59:00 AM UTC 24
Finished	Sep 09 06:59:30 AM UTC 24
Peak memory	208572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941917150 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1941917150
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.4060679973
Short name	T1026
Test name
Test status
Simulation time	97641720953 ps
CPU time	325.29 seconds
Started	Sep 09 06:59:18 AM UTC 24
Finished	Sep 09 07:04:48 AM UTC 24
Peak memory	208724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060679973 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4060679973
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_loopback.1798017541
Short name	T888
Test name
Test status
Simulation time	4974650999 ps
CPU time	13.19 seconds
Started	Sep 09 06:59:12 AM UTC 24
Finished	Sep 09 06:59:26 AM UTC 24
Peak memory	207924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798017541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1798017541
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_noise_filter.4263443933
Short name	T938
Test name
Test status
Simulation time	98401542097 ps
CPU time	148.55 seconds
Started	Sep 09 06:59:03 AM UTC 24
Finished	Sep 09 07:01:34 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263443933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.4263443933
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_perf.2824731648
Short name	T954
Test name
Test status
Simulation time	11604420578 ps
CPU time	174.04 seconds
Started	Sep 09 06:59:14 AM UTC 24
Finished	Sep 09 07:02:11 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824731648 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2824731648
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_rx_oversample.3063944827
Short name	T885
Test name
Test status
Simulation time	3786343455 ps
CPU time	23.51 seconds
Started	Sep 09 06:58:59 AM UTC 24
Finished	Sep 09 06:59:23 AM UTC 24
Peak memory	207428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063944827 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3063944827
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.3041654124
Short name	T998
Test name
Test status
Simulation time	135800656250 ps
CPU time	283.36 seconds
Started	Sep 09 06:59:07 AM UTC 24
Finished	Sep 09 07:03:54 AM UTC 24
Peak memory	208860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041654124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3041654124
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.2827189130
Short name	T881
Test name
Test status
Simulation time	58775894506 ps
CPU time	14.4 seconds
Started	Sep 09 06:59:03 AM UTC 24
Finished	Sep 09 06:59:18 AM UTC 24
Peak memory	207144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827189130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2827189130
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_smoke.3377952177
Short name	T872
Test name
Test status
Simulation time	113424476 ps
CPU time	1.01 seconds
Started	Sep 09 06:58:55 AM UTC 24
Finished	Sep 09 06:58:57 AM UTC 24
Peak memory	206484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377952177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3377952177
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_stress_all.3921108158
Short name	T1174
Test name
Test status
Simulation time	276276952305 ps
CPU time	635.76 seconds
Started	Sep 09 06:59:19 AM UTC 24
Finished	Sep 09 07:10:02 AM UTC 24
Peak memory	212164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921108158 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3921108158
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.3581559653
Short name	T923
Test name
Test status
Simulation time	2772623774 ps
CPU time	94.21 seconds
Started	Sep 09 06:59:19 AM UTC 24
Finished	Sep 09 07:00:55 AM UTC 24
Peak memory	225392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3581559653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all _with_rand_reset.3581559653
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.4089041686
Short name	T879
Test name
Test status
Simulation time	2774674168 ps
CPU time	3.18 seconds
Started	Sep 09 06:59:09 AM UTC 24
Finished	Sep 09 06:59:13 AM UTC 24
Peak memory	207828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089041686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.4089041686
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/48.uart_tx_rx.1263249387
Short name	T877
Test name
Test status
Simulation time	25846571433 ps
CPU time	11.07 seconds
Started	Sep 09 06:58:56 AM UTC 24
Finished	Sep 09 06:59:08 AM UTC 24
Peak memory	208860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263249387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1263249387
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/48.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_alert_test.1111783489
Short name	T835
Test name
Test status
Simulation time	11545110 ps
CPU time	0.82 seconds
Started	Sep 09 06:59:48 AM UTC 24
Finished	Sep 09 06:59:49 AM UTC 24
Peak memory	204376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111783489 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1111783489
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_fifo_full.1599900891
Short name	T980
Test name
Test status
Simulation time	118542405183 ps
CPU time	224.7 seconds
Started	Sep 09 06:59:25 AM UTC 24
Finished	Sep 09 07:03:12 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599900891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1599900891
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.494803431
Short name	T942
Test name
Test status
Simulation time	139279973178 ps
CPU time	134.61 seconds
Started	Sep 09 06:59:25 AM UTC 24
Finished	Sep 09 07:01:42 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494803431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.494803431
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_intr.3482102301
Short name	T896
Test name
Test status
Simulation time	6978438864 ps
CPU time	7.79 seconds
Started	Sep 09 06:59:34 AM UTC 24
Finished	Sep 09 06:59:43 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482102301 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3482102301
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3539315936
Short name	T1027
Test name
Test status
Simulation time	133253176908 ps
CPU time	301.73 seconds
Started	Sep 09 06:59:43 AM UTC 24
Finished	Sep 09 07:04:49 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539315936 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3539315936
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_loopback.2582552654
Short name	T836
Test name
Test status
Simulation time	4172269054 ps
CPU time	16.15 seconds
Started	Sep 09 06:59:41 AM UTC 24
Finished	Sep 09 06:59:59 AM UTC 24
Peak memory	208044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582552654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2582552654
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_noise_filter.2029081575
Short name	T924
Test name
Test status
Simulation time	163163442429 ps
CPU time	82.88 seconds
Started	Sep 09 06:59:37 AM UTC 24
Finished	Sep 09 07:01:02 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029081575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.2029081575
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_perf.2408914120
Short name	T1048
Test name
Test status
Simulation time	10563861762 ps
CPU time	326.69 seconds
Started	Sep 09 06:59:41 AM UTC 24
Finished	Sep 09 07:05:12 AM UTC 24
Peak memory	208628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408914120 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2408914120
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_rx_oversample.1702355250
Short name	T904
Test name
Test status
Simulation time	6701308820 ps
CPU time	34.4 seconds
Started	Sep 09 06:59:31 AM UTC 24
Finished	Sep 09 07:00:07 AM UTC 24
Peak memory	207480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702355250 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1702355250
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.3928450880
Short name	T912
Test name
Test status
Simulation time	30041832736 ps
CPU time	58.18 seconds
Started	Sep 09 06:59:38 AM UTC 24
Finished	Sep 09 07:00:38 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928450880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3928450880
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.1353685250
Short name	T899
Test name
Test status
Simulation time	4040350312 ps
CPU time	7.46 seconds
Started	Sep 09 06:59:38 AM UTC 24
Finished	Sep 09 06:59:47 AM UTC 24
Peak memory	205032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353685250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1353685250
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_smoke.3088967033
Short name	T823
Test name
Test status
Simulation time	6218561808 ps
CPU time	34 seconds
Started	Sep 09 06:59:23 AM UTC 24
Finished	Sep 09 06:59:59 AM UTC 24
Peak memory	208804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088967033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3088967033
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_stress_all.492711642
Short name	T1128
Test name
Test status
Simulation time	143813033294 ps
CPU time	475.01 seconds
Started	Sep 09 06:59:46 AM UTC 24
Finished	Sep 09 07:07:47 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492711642 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.492711642
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.1097450194
Short name	T901
Test name
Test status
Simulation time	2254601519 ps
CPU time	13.2 seconds
Started	Sep 09 06:59:44 AM UTC 24
Finished	Sep 09 06:59:59 AM UTC 24
Peak memory	217728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1097450194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all _with_rand_reset.1097450194
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.1393390690
Short name	T897
Test name
Test status
Simulation time	2062497875 ps
CPU time	3.03 seconds
Started	Sep 09 06:59:39 AM UTC 24
Finished	Sep 09 06:59:43 AM UTC 24
Peak memory	208452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393390690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1393390690
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/49.uart_tx_rx.2623916939
Short name	T905
Test name
Test status
Simulation time	61397172249 ps
CPU time	50.12 seconds
Started	Sep 09 06:59:25 AM UTC 24
Finished	Sep 09 07:00:16 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623916939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2623916939
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/49.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_alert_test.2496122721
Short name	T100
Test name
Test status
Simulation time	46128707 ps
CPU time	0.83 seconds
Started	Sep 09 06:32:50 AM UTC 24
Finished	Sep 09 06:32:52 AM UTC 24
Peak memory	204380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496122721 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2496122721
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_fifo_full.1648166878
Short name	T127
Test name
Test status
Simulation time	65936627108 ps
CPU time	62.62 seconds
Started	Sep 09 06:32:02 AM UTC 24
Finished	Sep 09 06:33:06 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648166878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1648166878
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.1095496881
Short name	T103
Test name
Test status
Simulation time	10909819123 ps
CPU time	12.86 seconds
Started	Sep 09 06:32:02 AM UTC 24
Finished	Sep 09 06:32:16 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095496881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1095496881
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_intr.2448875337
Short name	T21
Test name
Test status
Simulation time	20988700111 ps
CPU time	36.97 seconds
Started	Sep 09 06:32:11 AM UTC 24
Finished	Sep 09 06:32:49 AM UTC 24
Peak memory	208908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448875337 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.2448875337
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.740557581
Short name	T763
Test name
Test status
Simulation time	146439716086 ps
CPU time	1354.06 seconds
Started	Sep 09 06:32:30 AM UTC 24
Finished	Sep 09 06:55:20 AM UTC 24
Peak memory	212280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740557581 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.740557581
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_loopback.1394805209
Short name	T98
Test name
Test status
Simulation time	5313180846 ps
CPU time	7.42 seconds
Started	Sep 09 06:32:21 AM UTC 24
Finished	Sep 09 06:32:30 AM UTC 24
Peak memory	208540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394805209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1394805209
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_noise_filter.1161118053
Short name	T284
Test name
Test status
Simulation time	51765733595 ps
CPU time	119.91 seconds
Started	Sep 09 06:32:11 AM UTC 24
Finished	Sep 09 06:34:13 AM UTC 24
Peak memory	217440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161118053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.1161118053
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_perf.3356582438
Short name	T328
Test name
Test status
Simulation time	14504701166 ps
CPU time	172.55 seconds
Started	Sep 09 06:32:24 AM UTC 24
Finished	Sep 09 06:35:20 AM UTC 24
Peak memory	208824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356582438 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.3356582438
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_rx_oversample.2133904212
Short name	T52
Test name
Test status
Simulation time	5909540272 ps
CPU time	13.18 seconds
Started	Sep 09 06:32:06 AM UTC 24
Finished	Sep 09 06:32:20 AM UTC 24
Peak memory	207312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133904212 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2133904212
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.1534728208
Short name	T95
Test name
Test status
Simulation time	4448567922 ps
CPU time	1.8 seconds
Started	Sep 09 06:32:16 AM UTC 24
Finished	Sep 09 06:32:19 AM UTC 24
Peak memory	204440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534728208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1534728208
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_smoke.527926629
Short name	T51
Test name
Test status
Simulation time	690219371 ps
CPU time	4.89 seconds
Started	Sep 09 06:31:54 AM UTC 24
Finished	Sep 09 06:32:00 AM UTC 24
Peak memory	208092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527926629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default .vdb -cm_log /dev/null -cm_name 5.uart_smoke.527926629
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.3153191211
Short name	T38
Test name
Test status
Simulation time	3050670107 ps
CPU time	83.39 seconds
Started	Sep 09 06:32:31 AM UTC 24
Finished	Sep 09 06:33:57 AM UTC 24
Peak memory	217784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3153191211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_ with_rand_reset.3153191211
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.50780737
Short name	T96
Test name
Test status
Simulation time	4798562103 ps
CPU time	2.32 seconds
Started	Sep 09 06:32:20 AM UTC 24
Finished	Sep 09 06:32:24 AM UTC 24
Peak memory	208752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50780737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.50780737
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/5.uart_tx_rx.2420445606
Short name	T97
Test name
Test status
Simulation time	30870320952 ps
CPU time	28.35 seconds
Started	Sep 09 06:32:00 AM UTC 24
Finished	Sep 09 06:32:30 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420445606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2420445606
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/5.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/50.uart_fifo_reset.3193365284
Short name	T189
Test name
Test status
Simulation time	154316455700 ps
CPU time	166.75 seconds
Started	Sep 09 06:59:51 AM UTC 24
Finished	Sep 09 07:02:40 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193365284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3193365284
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/50.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.3590639411
Short name	T906
Test name
Test status
Simulation time	1403865534 ps
CPU time	20.13 seconds
Started	Sep 09 06:59:59 AM UTC 24
Finished	Sep 09 07:00:20 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3590639411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all _with_rand_reset.3590639411
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/51.uart_fifo_reset.599426579
Short name	T200
Test name
Test status
Simulation time	46410666867 ps
CPU time	79.18 seconds
Started	Sep 09 07:00:00 AM UTC 24
Finished	Sep 09 07:01:21 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599426579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.599426579
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/51.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.2656947751
Short name	T916
Test name
Test status
Simulation time	2471090834 ps
CPU time	40 seconds
Started	Sep 09 07:00:00 AM UTC 24
Finished	Sep 09 07:00:41 AM UTC 24
Peak memory	224636 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2656947751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all _with_rand_reset.2656947751
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/52.uart_fifo_reset.2052068941
Short name	T224
Test name
Test status
Simulation time	49248603467 ps
CPU time	221.41 seconds
Started	Sep 09 07:00:00 AM UTC 24
Finished	Sep 09 07:03:45 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052068941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2052068941
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/52.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.3796952271
Short name	T927
Test name
Test status
Simulation time	17105929441 ps
CPU time	59.19 seconds
Started	Sep 09 07:00:01 AM UTC 24
Finished	Sep 09 07:01:06 AM UTC 24
Peak memory	222008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3796952271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all _with_rand_reset.3796952271
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/53.uart_fifo_reset.850159385
Short name	T950
Test name
Test status
Simulation time	159130848294 ps
CPU time	111.76 seconds
Started	Sep 09 07:00:06 AM UTC 24
Finished	Sep 09 07:02:00 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850159385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.850159385
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/53.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.203490961
Short name	T929
Test name
Test status
Simulation time	4362209271 ps
CPU time	58.46 seconds
Started	Sep 09 07:00:07 AM UTC 24
Finished	Sep 09 07:01:07 AM UTC 24
Peak memory	217616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=203490961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all_ with_rand_reset.203490961
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/54.uart_fifo_reset.4156967349
Short name	T952
Test name
Test status
Simulation time	81920716770 ps
CPU time	102.31 seconds
Started	Sep 09 07:00:17 AM UTC 24
Finished	Sep 09 07:02:02 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156967349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.4156967349
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/54.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.1811385674
Short name	T926
Test name
Test status
Simulation time	2127986454 ps
CPU time	40.35 seconds
Started	Sep 09 07:00:21 AM UTC 24
Finished	Sep 09 07:01:03 AM UTC 24
Peak memory	224000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1811385674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all _with_rand_reset.1811385674
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/55.uart_fifo_reset.676082218
Short name	T911
Test name
Test status
Simulation time	12513034304 ps
CPU time	10.11 seconds
Started	Sep 09 07:00:25 AM UTC 24
Finished	Sep 09 07:00:36 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676082218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.676082218
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/55.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.2450414518
Short name	T917
Test name
Test status
Simulation time	5326191465 ps
CPU time	21.2 seconds
Started	Sep 09 07:00:25 AM UTC 24
Finished	Sep 09 07:00:47 AM UTC 24
Peak memory	217576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2450414518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all _with_rand_reset.2450414518
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/56.uart_fifo_reset.477046570
Short name	T914
Test name
Test status
Simulation time	39303599405 ps
CPU time	13.17 seconds
Started	Sep 09 07:00:27 AM UTC 24
Finished	Sep 09 07:00:41 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477046570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.477046570
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/56.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.1048301176
Short name	T946
Test name
Test status
Simulation time	2761329897 ps
CPU time	74.23 seconds
Started	Sep 09 07:00:29 AM UTC 24
Finished	Sep 09 07:01:45 AM UTC 24
Peak memory	217516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1048301176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all _with_rand_reset.1048301176
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/57.uart_fifo_reset.3569712595
Short name	T919
Test name
Test status
Simulation time	54765655256 ps
CPU time	10.11 seconds
Started	Sep 09 07:00:37 AM UTC 24
Finished	Sep 09 07:00:48 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569712595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3569712595
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/57.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.1794360418
Short name	T930
Test name
Test status
Simulation time	2412815600 ps
CPU time	29.9 seconds
Started	Sep 09 07:00:39 AM UTC 24
Finished	Sep 09 07:01:10 AM UTC 24
Peak memory	208964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1794360418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all _with_rand_reset.1794360418
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/58.uart_fifo_reset.90268851
Short name	T194
Test name
Test status
Simulation time	93093443886 ps
CPU time	194.65 seconds
Started	Sep 09 07:00:40 AM UTC 24
Finished	Sep 09 07:03:57 AM UTC 24
Peak memory	208688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90268851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.90268851
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/58.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.2113077981
Short name	T972
Test name
Test status
Simulation time	3747357214 ps
CPU time	129.68 seconds
Started	Sep 09 07:00:42 AM UTC 24
Finished	Sep 09 07:02:54 AM UTC 24
Peak memory	224816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2113077981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all _with_rand_reset.2113077981
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/59.uart_fifo_reset.4106818930
Short name	T222
Test name
Test status
Simulation time	33443514797 ps
CPU time	26.12 seconds
Started	Sep 09 07:00:42 AM UTC 24
Finished	Sep 09 07:01:10 AM UTC 24
Peak memory	208552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106818930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.4106818930
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/59.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.2701232365
Short name	T928
Test name
Test status
Simulation time	2795462584 ps
CPU time	23.27 seconds
Started	Sep 09 07:00:42 AM UTC 24
Finished	Sep 09 07:01:07 AM UTC 24
Peak memory	217604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2701232365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all _with_rand_reset.2701232365
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_alert_test.2877597456
Short name	T422
Test name
Test status
Simulation time	17202032 ps
CPU time	0.79 seconds
Started	Sep 09 06:33:42 AM UTC 24
Finished	Sep 09 06:33:44 AM UTC 24
Peak memory	204380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877597456 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2877597456
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_fifo_full.2092734692
Short name	T104
Test name
Test status
Simulation time	17228431066 ps
CPU time	42.57 seconds
Started	Sep 09 06:33:00 AM UTC 24
Finished	Sep 09 06:33:44 AM UTC 24
Peak memory	208756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092734692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2092734692
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.3599115283
Short name	T344
Test name
Test status
Simulation time	30930441545 ps
CPU time	90.44 seconds
Started	Sep 09 06:33:02 AM UTC 24
Finished	Sep 09 06:34:34 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599115283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3599115283
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_fifo_reset.2714289619
Short name	T197
Test name
Test status
Simulation time	17611214629 ps
CPU time	55.84 seconds
Started	Sep 09 06:33:02 AM UTC 24
Finished	Sep 09 06:33:59 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714289619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2714289619
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_intr.2066784774
Short name	T105
Test name
Test status
Simulation time	63960174715 ps
CPU time	147.78 seconds
Started	Sep 09 06:33:10 AM UTC 24
Finished	Sep 09 06:35:41 AM UTC 24
Peak memory	207432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066784774 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2066784774
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.3013926472
Short name	T505
Test name
Test status
Simulation time	137755207578 ps
CPU time	655.08 seconds
Started	Sep 09 06:33:38 AM UTC 24
Finished	Sep 09 06:44:41 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013926472 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3013926472
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_loopback.2445261284
Short name	T393
Test name
Test status
Simulation time	8186991149 ps
CPU time	9.9 seconds
Started	Sep 09 06:33:26 AM UTC 24
Finished	Sep 09 06:33:37 AM UTC 24
Peak memory	208800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445261284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2445261284
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_perf.434834814
Short name	T330
Test name
Test status
Simulation time	12486687459 ps
CPU time	877 seconds
Started	Sep 09 06:33:36 AM UTC 24
Finished	Sep 09 06:48:23 AM UTC 24
Peak memory	212408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434834814 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.434834814
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_rx_oversample.4056242979
Short name	T421
Test name
Test status
Simulation time	3497630647 ps
CPU time	10.84 seconds
Started	Sep 09 06:33:06 AM UTC 24
Finished	Sep 09 06:33:18 AM UTC 24
Peak memory	208436 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056242979 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.4056242979
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.3962289498
Short name	T141
Test name
Test status
Simulation time	116727046946 ps
CPU time	72.63 seconds
Started	Sep 09 06:33:19 AM UTC 24
Finished	Sep 09 06:34:34 AM UTC 24
Peak memory	208512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962289498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.3962289498
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.841241017
Short name	T335
Test name
Test status
Simulation time	32532524925 ps
CPU time	76.65 seconds
Started	Sep 09 06:33:18 AM UTC 24
Finished	Sep 09 06:34:37 AM UTC 24
Peak memory	207212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841241017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.841241017
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_smoke.3028703246
Short name	T341
Test name
Test status
Simulation time	6055681668 ps
CPU time	23.3 seconds
Started	Sep 09 06:32:53 AM UTC 24
Finished	Sep 09 06:33:17 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028703246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3028703246
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.4220950592
Short name	T358
Test name
Test status
Simulation time	1759555113 ps
CPU time	3.35 seconds
Started	Sep 09 06:33:21 AM UTC 24
Finished	Sep 09 06:33:25 AM UTC 24
Peak memory	208824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220950592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.4220950592
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/6.uart_tx_rx.1903574789
Short name	T318
Test name
Test status
Simulation time	15197126305 ps
CPU time	40.56 seconds
Started	Sep 09 06:32:53 AM UTC 24
Finished	Sep 09 06:33:35 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903574789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1903574789
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/6.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/60.uart_fifo_reset.41318066
Short name	T955
Test name
Test status
Simulation time	42998804075 ps
CPU time	117.57 seconds
Started	Sep 09 07:00:48 AM UTC 24
Finished	Sep 09 07:02:48 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41318066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.41318066
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/60.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.173784145
Short name	T943
Test name
Test status
Simulation time	2034850617 ps
CPU time	52.49 seconds
Started	Sep 09 07:00:48 AM UTC 24
Finished	Sep 09 07:01:42 AM UTC 24
Peak memory	223872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=173784145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all_ with_rand_reset.173784145
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/61.uart_fifo_reset.317005872
Short name	T269
Test name
Test status
Simulation time	168802587450 ps
CPU time	118.38 seconds
Started	Sep 09 07:00:49 AM UTC 24
Finished	Sep 09 07:02:50 AM UTC 24
Peak memory	208716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317005872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.317005872
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/61.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.3952385220
Short name	T932
Test name
Test status
Simulation time	1926543724 ps
CPU time	28.31 seconds
Started	Sep 09 07:00:49 AM UTC 24
Finished	Sep 09 07:01:19 AM UTC 24
Peak memory	208828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3952385220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all _with_rand_reset.3952385220
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/62.uart_fifo_reset.4104442234
Short name	T270
Test name
Test status
Simulation time	16048187218 ps
CPU time	47.27 seconds
Started	Sep 09 07:00:52 AM UTC 24
Finished	Sep 09 07:01:40 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104442234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.4104442234
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/62.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.1108893422
Short name	T933
Test name
Test status
Simulation time	4756280471 ps
CPU time	33.97 seconds
Started	Sep 09 07:00:53 AM UTC 24
Finished	Sep 09 07:01:28 AM UTC 24
Peak memory	217576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1108893422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all _with_rand_reset.1108893422
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/63.uart_fifo_reset.157161597
Short name	T958
Test name
Test status
Simulation time	192238266928 ps
CPU time	84.26 seconds
Started	Sep 09 07:00:57 AM UTC 24
Finished	Sep 09 07:02:23 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157161597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.157161597
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/63.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.4142848271
Short name	T935
Test name
Test status
Simulation time	1981666050 ps
CPU time	28.04 seconds
Started	Sep 09 07:01:03 AM UTC 24
Finished	Sep 09 07:01:32 AM UTC 24
Peak memory	217672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4142848271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all _with_rand_reset.4142848271
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/64.uart_fifo_reset.2589497358
Short name	T234
Test name
Test status
Simulation time	20531695225 ps
CPU time	41.5 seconds
Started	Sep 09 07:01:03 AM UTC 24
Finished	Sep 09 07:01:46 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589497358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2589497358
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/64.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.4287787661
Short name	T940
Test name
Test status
Simulation time	5410932819 ps
CPU time	32.78 seconds
Started	Sep 09 07:01:04 AM UTC 24
Finished	Sep 09 07:01:38 AM UTC 24
Peak memory	217660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=4287787661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all _with_rand_reset.4287787661
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/65.uart_fifo_reset.84843464
Short name	T987
Test name
Test status
Simulation time	70392453976 ps
CPU time	136.32 seconds
Started	Sep 09 07:01:06 AM UTC 24
Finished	Sep 09 07:03:25 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84843464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.84843464
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/65.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.1917218063
Short name	T937
Test name
Test status
Simulation time	6567437035 ps
CPU time	25.19 seconds
Started	Sep 09 07:01:07 AM UTC 24
Finished	Sep 09 07:01:34 AM UTC 24
Peak memory	217676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1917218063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all _with_rand_reset.1917218063
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/66.uart_fifo_reset.3500410605
Short name	T979
Test name
Test status
Simulation time	110282564037 ps
CPU time	116.99 seconds
Started	Sep 09 07:01:08 AM UTC 24
Finished	Sep 09 07:03:07 AM UTC 24
Peak memory	208744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500410605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3500410605
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/66.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.402854260
Short name	T948
Test name
Test status
Simulation time	3994655324 ps
CPU time	44.46 seconds
Started	Sep 09 07:01:10 AM UTC 24
Finished	Sep 09 07:01:56 AM UTC 24
Peak memory	221752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=402854260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all_ with_rand_reset.402854260
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/67.uart_fifo_reset.1093194560
Short name	T233
Test name
Test status
Simulation time	72757568546 ps
CPU time	32.15 seconds
Started	Sep 09 07:01:11 AM UTC 24
Finished	Sep 09 07:01:45 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093194560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1093194560
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/67.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.1910757476
Short name	T944
Test name
Test status
Simulation time	989969652 ps
CPU time	25.88 seconds
Started	Sep 09 07:01:16 AM UTC 24
Finished	Sep 09 07:01:44 AM UTC 24
Peak memory	217528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1910757476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all _with_rand_reset.1910757476
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/68.uart_fifo_reset.2442873287
Short name	T945
Test name
Test status
Simulation time	42291663834 ps
CPU time	22.75 seconds
Started	Sep 09 07:01:19 AM UTC 24
Finished	Sep 09 07:01:44 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442873287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2442873287
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/68.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.1466694532
Short name	T936
Test name
Test status
Simulation time	1295370610 ps
CPU time	10.51 seconds
Started	Sep 09 07:01:22 AM UTC 24
Finished	Sep 09 07:01:33 AM UTC 24
Peak memory	217804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1466694532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all _with_rand_reset.1466694532
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/69.uart_fifo_reset.2524896988
Short name	T941
Test name
Test status
Simulation time	38054367841 ps
CPU time	9.51 seconds
Started	Sep 09 07:01:29 AM UTC 24
Finished	Sep 09 07:01:39 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524896988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2524896988
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/69.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.1460411633
Short name	T963
Test name
Test status
Simulation time	14677025450 ps
CPU time	69.58 seconds
Started	Sep 09 07:01:30 AM UTC 24
Finished	Sep 09 07:02:41 AM UTC 24
Peak memory	220032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1460411633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all _with_rand_reset.1460411633
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_alert_test.2870808827
Short name	T425
Test name
Test status
Simulation time	10952509 ps
CPU time	0.82 seconds
Started	Sep 09 06:34:28 AM UTC 24
Finished	Sep 09 06:34:30 AM UTC 24
Peak memory	204380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870808827 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2870808827
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_fifo_full.917601193
Short name	T281
Test name
Test status
Simulation time	133576983893 ps
CPU time	193.65 seconds
Started	Sep 09 06:33:49 AM UTC 24
Finished	Sep 09 06:37:06 AM UTC 24
Peak memory	208388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917601193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.917601193
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.1694341638
Short name	T302
Test name
Test status
Simulation time	12429726614 ps
CPU time	37.16 seconds
Started	Sep 09 06:33:53 AM UTC 24
Finished	Sep 09 06:34:32 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694341638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1694341638
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2498682219
Short name	T299
Test name
Test status
Simulation time	90210691417 ps
CPU time	234.93 seconds
Started	Sep 09 06:33:56 AM UTC 24
Finished	Sep 09 06:37:55 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498682219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2498682219
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_intr.705572287
Short name	T24
Test name
Test status
Simulation time	21277273215 ps
CPU time	52.36 seconds
Started	Sep 09 06:34:01 AM UTC 24
Finished	Sep 09 06:34:55 AM UTC 24
Peak memory	208948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705572287 -assert nopostproc +UVM_TESTNAME=uart _base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.705572287
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.118072545
Short name	T475
Test name
Test status
Simulation time	50428435738 ps
CPU time	460.78 seconds
Started	Sep 09 06:34:22 AM UTC 24
Finished	Sep 09 06:42:09 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118072545 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.118072545
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_loopback.3333522560
Short name	T424
Test name
Test status
Simulation time	5368144172 ps
CPU time	6.67 seconds
Started	Sep 09 06:34:20 AM UTC 24
Finished	Sep 09 06:34:28 AM UTC 24
Peak memory	208036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333522560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3333522560
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_noise_filter.2203136780
Short name	T286
Test name
Test status
Simulation time	50804409121 ps
CPU time	21.9 seconds
Started	Sep 09 06:34:05 AM UTC 24
Finished	Sep 09 06:34:28 AM UTC 24
Peak memory	208752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203136780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2203136780
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_perf.1121494488
Short name	T590
Test name
Test status
Simulation time	28140755211 ps
CPU time	900.99 seconds
Started	Sep 09 06:34:22 AM UTC 24
Finished	Sep 09 06:49:33 AM UTC 24
Peak memory	212140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121494488 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.1121494488
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_rx_oversample.581640165
Short name	T423
Test name
Test status
Simulation time	4277702411 ps
CPU time	5.47 seconds
Started	Sep 09 06:33:57 AM UTC 24
Finished	Sep 09 06:34:04 AM UTC 24
Peak memory	207832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581640165 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.581640165
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.2052668076
Short name	T129
Test name
Test status
Simulation time	77663884946 ps
CPU time	32.05 seconds
Started	Sep 09 06:34:13 AM UTC 24
Finished	Sep 09 06:34:46 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052668076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2052668076
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.1010786588
Short name	T326
Test name
Test status
Simulation time	7213735240 ps
CPU time	12.98 seconds
Started	Sep 09 06:34:07 AM UTC 24
Finished	Sep 09 06:34:21 AM UTC 24
Peak memory	205228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010786588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1010786588
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_smoke.4233639566
Short name	T340
Test name
Test status
Simulation time	308250486 ps
CPU time	2.75 seconds
Started	Sep 09 06:33:44 AM UTC 24
Finished	Sep 09 06:33:48 AM UTC 24
Peak memory	208336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233639566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4233639566
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_stress_all.3026717902
Short name	T541
Test name
Test status
Simulation time	108791078551 ps
CPU time	745 seconds
Started	Sep 09 06:34:28 AM UTC 24
Finished	Sep 09 06:47:02 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026717902 -assert nopostproc +UVM_TESTNAME=ua rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3026717902
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.807732730
Short name	T41
Test name
Test status
Simulation time	4816813109 ps
CPU time	78.78 seconds
Started	Sep 09 06:34:26 AM UTC 24
Finished	Sep 09 06:35:47 AM UTC 24
Peak memory	219780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=807732730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_w ith_rand_reset.807732730
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.4193420808
Short name	T355
Test name
Test status
Simulation time	2369546142 ps
CPU time	3.81 seconds
Started	Sep 09 06:34:14 AM UTC 24
Finished	Sep 09 06:34:19 AM UTC 24
Peak memory	207324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193420808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4193420808
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/7.uart_tx_rx.1087374220
Short name	T314
Test name
Test status
Simulation time	87563681598 ps
CPU time	89.9 seconds
Started	Sep 09 06:33:45 AM UTC 24
Finished	Sep 09 06:35:17 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087374220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.1087374220
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/7.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/70.uart_fifo_reset.3638234483
Short name	T957
Test name
Test status
Simulation time	16926065065 ps
CPU time	48.24 seconds
Started	Sep 09 07:01:33 AM UTC 24
Finished	Sep 09 07:02:23 AM UTC 24
Peak memory	208632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638234483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3638234483
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/70.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.2473583626
Short name	T947
Test name
Test status
Simulation time	1204182755 ps
CPU time	19.92 seconds
Started	Sep 09 07:01:34 AM UTC 24
Finished	Sep 09 07:01:55 AM UTC 24
Peak memory	217748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2473583626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all _with_rand_reset.2473583626
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/71.uart_fifo_reset.1155477563
Short name	T215
Test name
Test status
Simulation time	40644475262 ps
CPU time	93.47 seconds
Started	Sep 09 07:01:35 AM UTC 24
Finished	Sep 09 07:03:10 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155477563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1155477563
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/71.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.3999605470
Short name	T949
Test name
Test status
Simulation time	7285652114 ps
CPU time	21.84 seconds
Started	Sep 09 07:01:35 AM UTC 24
Finished	Sep 09 07:01:58 AM UTC 24
Peak memory	218004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3999605470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all _with_rand_reset.3999605470
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/72.uart_fifo_reset.3483795234
Short name	T214
Test name
Test status
Simulation time	37697299049 ps
CPU time	49.38 seconds
Started	Sep 09 07:01:36 AM UTC 24
Finished	Sep 09 07:02:27 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483795234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3483795234
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/72.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.384042294
Short name	T973
Test name
Test status
Simulation time	13044768620 ps
CPU time	73.72 seconds
Started	Sep 09 07:01:39 AM UTC 24
Finished	Sep 09 07:02:55 AM UTC 24
Peak memory	217680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=384042294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all_ with_rand_reset.384042294
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/73.uart_fifo_reset.681528103
Short name	T951
Test name
Test status
Simulation time	36241245737 ps
CPU time	18.74 seconds
Started	Sep 09 07:01:40 AM UTC 24
Finished	Sep 09 07:02:00 AM UTC 24
Peak memory	207928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681528103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.681528103
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/73.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.1238731583
Short name	T956
Test name
Test status
Simulation time	2414028302 ps
CPU time	31.45 seconds
Started	Sep 09 07:01:41 AM UTC 24
Finished	Sep 09 07:02:14 AM UTC 24
Peak memory	217652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1238731583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all _with_rand_reset.1238731583
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/74.uart_fifo_reset.3011624158
Short name	T217
Test name
Test status
Simulation time	57845387057 ps
CPU time	13.35 seconds
Started	Sep 09 07:01:42 AM UTC 24
Finished	Sep 09 07:01:57 AM UTC 24
Peak memory	208624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011624158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3011624158
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/74.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.1761661587
Short name	T1004
Test name
Test status
Simulation time	3704641092 ps
CPU time	137.19 seconds
Started	Sep 09 07:01:44 AM UTC 24
Finished	Sep 09 07:04:03 AM UTC 24
Peak memory	217792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1761661587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all _with_rand_reset.1761661587
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/75.uart_fifo_reset.2999995369
Short name	T959
Test name
Test status
Simulation time	70368761244 ps
CPU time	44.08 seconds
Started	Sep 09 07:01:45 AM UTC 24
Finished	Sep 09 07:02:30 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999995369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2999995369
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/75.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2051586380
Short name	T964
Test name
Test status
Simulation time	15557662519 ps
CPU time	55.69 seconds
Started	Sep 09 07:01:45 AM UTC 24
Finished	Sep 09 07:02:42 AM UTC 24
Peak memory	224540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2051586380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all _with_rand_reset.2051586380
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/76.uart_fifo_reset.1290047391
Short name	T975
Test name
Test status
Simulation time	113881077769 ps
CPU time	70.49 seconds
Started	Sep 09 07:01:46 AM UTC 24
Finished	Sep 09 07:02:58 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290047391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1290047391
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/76.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.1423899355
Short name	T965
Test name
Test status
Simulation time	3820027219 ps
CPU time	55.57 seconds
Started	Sep 09 07:01:46 AM UTC 24
Finished	Sep 09 07:02:43 AM UTC 24
Peak memory	217804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1423899355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all _with_rand_reset.1423899355
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/77.uart_fifo_reset.367770996
Short name	T193
Test name
Test status
Simulation time	124500698843 ps
CPU time	95.91 seconds
Started	Sep 09 07:01:47 AM UTC 24
Finished	Sep 09 07:03:25 AM UTC 24
Peak memory	208728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367770996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.367770996
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/77.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.3877905690
Short name	T967
Test name
Test status
Simulation time	6260105444 ps
CPU time	47.78 seconds
Started	Sep 09 07:01:56 AM UTC 24
Finished	Sep 09 07:02:45 AM UTC 24
Peak memory	223936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3877905690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all _with_rand_reset.3877905690
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/78.uart_fifo_reset.672530633
Short name	T178
Test name
Test status
Simulation time	65235045514 ps
CPU time	164.55 seconds
Started	Sep 09 07:01:57 AM UTC 24
Finished	Sep 09 07:04:44 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672530633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.672530633
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/78.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.3670214537
Short name	T971
Test name
Test status
Simulation time	11934537385 ps
CPU time	51.85 seconds
Started	Sep 09 07:01:58 AM UTC 24
Finished	Sep 09 07:02:52 AM UTC 24
Peak memory	223932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3670214537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all _with_rand_reset.3670214537
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/79.uart_fifo_reset.2732923802
Short name	T176
Test name
Test status
Simulation time	171443569056 ps
CPU time	75.57 seconds
Started	Sep 09 07:01:59 AM UTC 24
Finished	Sep 09 07:03:17 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732923802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2732923802
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/79.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.772212931
Short name	T962
Test name
Test status
Simulation time	3764592126 ps
CPU time	37.03 seconds
Started	Sep 09 07:02:01 AM UTC 24
Finished	Sep 09 07:02:40 AM UTC 24
Peak memory	217224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=772212931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all_ with_rand_reset.772212931
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_alert_test.2840069539
Short name	T428
Test name
Test status
Simulation time	32383497 ps
CPU time	0.8 seconds
Started	Sep 09 06:34:59 AM UTC 24
Finished	Sep 09 06:35:00 AM UTC 24
Peak memory	204380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840069539 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.2840069539
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_fifo_full.1017966598
Short name	T139
Test name
Test status
Simulation time	44914165372 ps
CPU time	29.03 seconds
Started	Sep 09 06:34:35 AM UTC 24
Finished	Sep 09 06:35:05 AM UTC 24
Peak memory	208696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017966598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1017966598
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1204613259
Short name	T306
Test name
Test status
Simulation time	32869345301 ps
CPU time	77.49 seconds
Started	Sep 09 06:34:36 AM UTC 24
Finished	Sep 09 06:35:55 AM UTC 24
Peak memory	208984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204613259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1204613259
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_fifo_reset.1921891586
Short name	T315
Test name
Test status
Simulation time	128917108175 ps
CPU time	80.44 seconds
Started	Sep 09 06:34:37 AM UTC 24
Finished	Sep 09 06:35:59 AM UTC 24
Peak memory	208728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921891586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1921891586
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_intr.1491405640
Short name	T275
Test name
Test status
Simulation time	29795092126 ps
CPU time	18.88 seconds
Started	Sep 09 06:34:38 AM UTC 24
Finished	Sep 09 06:34:58 AM UTC 24
Peak memory	208952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491405640 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1491405640
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.3938397396
Short name	T291
Test name
Test status
Simulation time	131253874595 ps
CPU time	373.53 seconds
Started	Sep 09 06:34:54 AM UTC 24
Finished	Sep 09 06:41:13 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938397396 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ua rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3938397396
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_loopback.2686652478
Short name	T427
Test name
Test status
Simulation time	2297091142 ps
CPU time	1.9 seconds
Started	Sep 09 06:34:51 AM UTC 24
Finished	Sep 09 06:34:54 AM UTC 24
Peak memory	206552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686652478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2686652478
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_perf.1390885875
Short name	T346
Test name
Test status
Simulation time	8505838572 ps
CPU time	252.27 seconds
Started	Sep 09 06:34:53 AM UTC 24
Finished	Sep 09 06:39:09 AM UTC 24
Peak memory	208760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390885875 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.1390885875
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_rx_oversample.2922934007
Short name	T426
Test name
Test status
Simulation time	3427521894 ps
CPU time	2.62 seconds
Started	Sep 09 06:34:38 AM UTC 24
Finished	Sep 09 06:34:41 AM UTC 24
Peak memory	207540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922934007 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2922934007
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1409750049
Short name	T301
Test name
Test status
Simulation time	45529256836 ps
CPU time	61.9 seconds
Started	Sep 09 06:34:45 AM UTC 24
Finished	Sep 09 06:35:49 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409750049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1409750049
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.1617676406
Short name	T297
Test name
Test status
Simulation time	539226624 ps
CPU time	1.43 seconds
Started	Sep 09 06:34:42 AM UTC 24
Finished	Sep 09 06:34:44 AM UTC 24
Peak memory	204440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617676406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1617676406
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_smoke.3683195285
Short name	T323
Test name
Test status
Simulation time	5477927919 ps
CPU time	17.25 seconds
Started	Sep 09 06:34:31 AM UTC 24
Finished	Sep 09 06:34:50 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683195285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.3683195285
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.3014966779
Short name	T40
Test name
Test status
Simulation time	6560756496 ps
CPU time	40.45 seconds
Started	Sep 09 06:34:55 AM UTC 24
Finished	Sep 09 06:35:37 AM UTC 24
Peak memory	217976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3014966779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_ with_rand_reset.3014966779
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2959248326
Short name	T363
Test name
Test status
Simulation time	2892488121 ps
CPU time	3.98 seconds
Started	Sep 09 06:34:47 AM UTC 24
Finished	Sep 09 06:34:52 AM UTC 24
Peak memory	207316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959248326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2959248326
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/8.uart_tx_rx.45692465
Short name	T290
Test name
Test status
Simulation time	20874824283 ps
CPU time	57.39 seconds
Started	Sep 09 06:34:32 AM UTC 24
Finished	Sep 09 06:35:32 AM UTC 24
Peak memory	208732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45692465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default. vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.45692465
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/8.uart_tx_rx/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/80.uart_fifo_reset.1160513406
Short name	T414
Test name
Test status
Simulation time	28670494341 ps
CPU time	59.98 seconds
Started	Sep 09 07:02:01 AM UTC 24
Finished	Sep 09 07:03:03 AM UTC 24
Peak memory	208232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160513406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1160513406
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/80.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.2089841297
Short name	T976
Test name
Test status
Simulation time	2483760353 ps
CPU time	56.33 seconds
Started	Sep 09 07:02:02 AM UTC 24
Finished	Sep 09 07:03:00 AM UTC 24
Peak memory	217784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2089841297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all _with_rand_reset.2089841297
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/81.uart_fifo_reset.467067017
Short name	T205
Test name
Test status
Simulation time	25686443674 ps
CPU time	110.4 seconds
Started	Sep 09 07:02:03 AM UTC 24
Finished	Sep 09 07:03:56 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467067017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.467067017
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/81.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.3010524957
Short name	T974
Test name
Test status
Simulation time	13783290033 ps
CPU time	42.59 seconds
Started	Sep 09 07:02:13 AM UTC 24
Finished	Sep 09 07:02:57 AM UTC 24
Peak memory	219756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3010524957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all _with_rand_reset.3010524957
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/82.uart_fifo_reset.630883413
Short name	T1000
Test name
Test status
Simulation time	62122326095 ps
CPU time	101.03 seconds
Started	Sep 09 07:02:15 AM UTC 24
Finished	Sep 09 07:03:58 AM UTC 24
Peak memory	208764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630883413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.630883413
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/82.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.2633040447
Short name	T968
Test name
Test status
Simulation time	7169898907 ps
CPU time	21.53 seconds
Started	Sep 09 07:02:24 AM UTC 24
Finished	Sep 09 07:02:46 AM UTC 24
Peak memory	223324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2633040447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all _with_rand_reset.2633040447
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/83.uart_fifo_reset.2414382406
Short name	T982
Test name
Test status
Simulation time	127119643663 ps
CPU time	47.97 seconds
Started	Sep 09 07:02:24 AM UTC 24
Finished	Sep 09 07:03:13 AM UTC 24
Peak memory	208920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414382406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2414382406
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/83.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.2091786068
Short name	T978
Test name
Test status
Simulation time	1961199649 ps
CPU time	35.37 seconds
Started	Sep 09 07:02:28 AM UTC 24
Finished	Sep 09 07:03:05 AM UTC 24
Peak memory	217940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2091786068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all _with_rand_reset.2091786068
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/84.uart_fifo_reset.1661750109
Short name	T401
Test name
Test status
Simulation time	51474355751 ps
CPU time	113.99 seconds
Started	Sep 09 07:02:31 AM UTC 24
Finished	Sep 09 07:04:27 AM UTC 24
Peak memory	208896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661750109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1661750109
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/84.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.3475731687
Short name	T990
Test name
Test status
Simulation time	18950202360 ps
CPU time	60.3 seconds
Started	Sep 09 07:02:36 AM UTC 24
Finished	Sep 09 07:03:38 AM UTC 24
Peak memory	219764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3475731687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all _with_rand_reset.3475731687
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/85.uart_fifo_reset.4284536083
Short name	T209
Test name
Test status
Simulation time	86728627460 ps
CPU time	25.28 seconds
Started	Sep 09 07:02:36 AM UTC 24
Finished	Sep 09 07:03:03 AM UTC 24
Peak memory	207152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284536083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.4284536083
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/85.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.1126832391
Short name	T984
Test name
Test status
Simulation time	5435762532 ps
CPU time	36.31 seconds
Started	Sep 09 07:02:40 AM UTC 24
Finished	Sep 09 07:03:18 AM UTC 24
Peak memory	224148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1126832391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all _with_rand_reset.1126832391
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3882682039
Short name	T192
Test name
Test status
Simulation time	31118698294 ps
CPU time	55.38 seconds
Started	Sep 09 07:02:41 AM UTC 24
Finished	Sep 09 07:03:38 AM UTC 24
Peak memory	208640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882682039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3882682039
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/86.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.2733498928
Short name	T989
Test name
Test status
Simulation time	25034633732 ps
CPU time	46.76 seconds
Started	Sep 09 07:02:42 AM UTC 24
Finished	Sep 09 07:03:31 AM UTC 24
Peak memory	219840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2733498928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all _with_rand_reset.2733498928
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.1098499290
Short name	T995
Test name
Test status
Simulation time	3358180772 ps
CPU time	62.75 seconds
Started	Sep 09 07:02:44 AM UTC 24
Finished	Sep 09 07:03:48 AM UTC 24
Peak memory	217656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1098499290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all _with_rand_reset.1098499290
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/88.uart_fifo_reset.2841696758
Short name	T992
Test name
Test status
Simulation time	71310814718 ps
CPU time	53.14 seconds
Started	Sep 09 07:02:46 AM UTC 24
Finished	Sep 09 07:03:40 AM UTC 24
Peak memory	208720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841696758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2841696758
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/88.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.3121728416
Short name	T983
Test name
Test status
Simulation time	2935821284 ps
CPU time	26.33 seconds
Started	Sep 09 07:02:47 AM UTC 24
Finished	Sep 09 07:03:14 AM UTC 24
Peak memory	217740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3121728416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all _with_rand_reset.3121728416
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/89.uart_fifo_reset.1399299731
Short name	T985
Test name
Test status
Simulation time	37160360931 ps
CPU time	30.47 seconds
Started	Sep 09 07:02:48 AM UTC 24
Finished	Sep 09 07:03:20 AM UTC 24
Peak memory	208308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399299731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1399299731
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/89.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.1325972072
Short name	T988
Test name
Test status
Simulation time	8353492297 ps
CPU time	35.64 seconds
Started	Sep 09 07:02:49 AM UTC 24
Finished	Sep 09 07:03:26 AM UTC 24
Peak memory	217784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1325972072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all _with_rand_reset.1325972072
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_alert_test.2004332533
Short name	T432
Test name
Test status
Simulation time	31055840 ps
CPU time	0.84 seconds
Started	Sep 09 06:35:51 AM UTC 24
Finished	Sep 09 06:35:53 AM UTC 24
Peak memory	204380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004332533 -assert nopostproc +UVM_TESTNAME=uart_ base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2004332533
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_fifo_full.2541796697
Short name	T293
Test name
Test status
Simulation time	126200980154 ps
CPU time	332.49 seconds
Started	Sep 09 06:35:06 AM UTC 24
Finished	Sep 09 06:40:43 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541796697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2541796697
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_fifo_full/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_fifo_reset.3173602337
Short name	T187
Test name
Test status
Simulation time	35226864394 ps
CPU time	72.05 seconds
Started	Sep 09 06:35:20 AM UTC 24
Finished	Sep 09 06:36:34 AM UTC 24
Peak memory	208692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173602337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3173602337
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_intr.4030592051
Short name	T430
Test name
Test status
Simulation time	10948238850 ps
CPU time	8.96 seconds
Started	Sep 09 06:35:32 AM UTC 24
Finished	Sep 09 06:35:43 AM UTC 24
Peak memory	207144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030592051 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/u art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.4030592051
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_intr/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.809389557
Short name	T282
Test name
Test status
Simulation time	62903730688 ps
CPU time	213.02 seconds
Started	Sep 09 06:35:44 AM UTC 24
Finished	Sep 09 06:39:20 AM UTC 24
Peak memory	208680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809389557 -assert nopostproc +UVM_TESTNAME=uart_base_test +U VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uar t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.809389557
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_loopback.214076975
Short name	T431
Test name
Test status
Simulation time	2754026618 ps
CPU time	6.2 seconds
Started	Sep 09 06:35:43 AM UTC 24
Finished	Sep 09 06:35:50 AM UTC 24
Peak memory	207632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214076975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.uart_loopback.214076975
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_loopback/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_noise_filter.3463569464
Short name	T349
Test name
Test status
Simulation time	155644020616 ps
CPU time	222.36 seconds
Started	Sep 09 06:35:33 AM UTC 24
Finished	Sep 09 06:39:19 AM UTC 24
Peak memory	208960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463569464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3463569464
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_noise_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_perf.45463919
Short name	T331
Test name
Test status
Simulation time	17182151252 ps
CPU time	273.08 seconds
Started	Sep 09 06:35:44 AM UTC 24
Finished	Sep 09 06:40:20 AM UTC 24
Peak memory	208624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45463919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.45463919
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_perf/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2479852218
Short name	T429
Test name
Test status
Simulation time	5933762861 ps
CPU time	16.35 seconds
Started	Sep 09 06:35:20 AM UTC 24
Finished	Sep 09 06:35:38 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479852218 -assert nopostproc +UVM_TESTNAME=uart_base_test + UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2479852218
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_rx_oversample/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.46006116
Short name	T279
Test name
Test status
Simulation time	29825865921 ps
CPU time	32.43 seconds
Started	Sep 09 06:35:38 AM UTC 24
Finished	Sep 09 06:36:13 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46006116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.46006116
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.2288605778
Short name	T327
Test name
Test status
Simulation time	4600920560 ps
CPU time	14.06 seconds
Started	Sep 09 06:35:38 AM UTC 24
Finished	Sep 09 06:35:54 AM UTC 24
Peak memory	205228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288605778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.2288605778
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_smoke.3311407454
Short name	T347
Test name
Test status
Simulation time	452998854 ps
CPU time	1.69 seconds
Started	Sep 09 06:35:02 AM UTC 24
Finished	Sep 09 06:35:04 AM UTC 24
Peak memory	206440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311407454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3311407454
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_stress_all.540872500
Short name	T146
Test name
Test status
Simulation time	109130734889 ps
CPU time	1129.46 seconds
Started	Sep 09 06:35:49 AM UTC 24
Finished	Sep 09 06:54:51 AM UTC 24
Peak memory	221180 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540872500 -assert nopostproc +UVM_TESTNAME=uar t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.540872500
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.3107925363
Short name	T361
Test name
Test status
Simulation time	7548690834 ps
CPU time	13.98 seconds
Started	Sep 09 06:35:42 AM UTC 24
Finished	Sep 09 06:35:57 AM UTC 24
Peak memory	208784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107925363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/defa ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.3107925363
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/90.uart_fifo_reset.555155083
Short name	T1005
Test name
Test status
Simulation time	62532148489 ps
CPU time	75.38 seconds
Started	Sep 09 07:02:50 AM UTC 24
Finished	Sep 09 07:04:07 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555155083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.555155083
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/90.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.2922081634
Short name	T981
Test name
Test status
Simulation time	17844386607 ps
CPU time	21.07 seconds
Started	Sep 09 07:02:51 AM UTC 24
Finished	Sep 09 07:03:13 AM UTC 24
Peak memory	217804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2922081634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all _with_rand_reset.2922081634
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/91.uart_fifo_reset.4001599858
Short name	T235
Test name
Test status
Simulation time	137651155654 ps
CPU time	54.31 seconds
Started	Sep 09 07:02:52 AM UTC 24
Finished	Sep 09 07:03:48 AM UTC 24
Peak memory	208836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001599858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.4001599858
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/91.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/92.uart_fifo_reset.375746519
Short name	T977
Test name
Test status
Simulation time	8685061436 ps
CPU time	4.55 seconds
Started	Sep 09 07:02:55 AM UTC 24
Finished	Sep 09 07:03:01 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375746519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.375746519
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/92.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.3945143943
Short name	T994
Test name
Test status
Simulation time	1422899594 ps
CPU time	46.85 seconds
Started	Sep 09 07:02:56 AM UTC 24
Finished	Sep 09 07:03:44 AM UTC 24
Peak memory	208852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3945143943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all _with_rand_reset.3945143943
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/93.uart_fifo_reset.2350127006
Short name	T230
Test name
Test status
Simulation time	26398821454 ps
CPU time	27.64 seconds
Started	Sep 09 07:02:57 AM UTC 24
Finished	Sep 09 07:03:26 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350127006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2350127006
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/93.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.841158903
Short name	T993
Test name
Test status
Simulation time	13304755060 ps
CPU time	44.12 seconds
Started	Sep 09 07:02:58 AM UTC 24
Finished	Sep 09 07:03:44 AM UTC 24
Peak memory	217788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=841158903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all_ with_rand_reset.841158903
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/94.uart_fifo_reset.3788301550
Short name	T986
Test name
Test status
Simulation time	14337329163 ps
CPU time	18.94 seconds
Started	Sep 09 07:03:02 AM UTC 24
Finished	Sep 09 07:03:22 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788301550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.3788301550
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/94.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.1268020566
Short name	T991
Test name
Test status
Simulation time	2889820024 ps
CPU time	35.44 seconds
Started	Sep 09 07:03:02 AM UTC 24
Finished	Sep 09 07:03:38 AM UTC 24
Peak memory	217652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1268020566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all _with_rand_reset.1268020566
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/95.uart_fifo_reset.74782280
Short name	T1127
Test name
Test status
Simulation time	159636714203 ps
CPU time	278.29 seconds
Started	Sep 09 07:03:04 AM UTC 24
Finished	Sep 09 07:07:45 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74782280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart _fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.74782280
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/95.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.2851636018
Short name	T1043
Test name
Test status
Simulation time	5936563244 ps
CPU time	121.85 seconds
Started	Sep 09 07:03:04 AM UTC 24
Finished	Sep 09 07:05:08 AM UTC 24
Peak memory	221908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2851636018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all _with_rand_reset.2851636018
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/96.uart_fifo_reset.1670884020
Short name	T1006
Test name
Test status
Simulation time	79593338128 ps
CPU time	61.54 seconds
Started	Sep 09 07:03:06 AM UTC 24
Finished	Sep 09 07:04:09 AM UTC 24
Peak memory	208920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670884020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1670884020
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/96.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.493696831
Short name	T1015
Test name
Test status
Simulation time	9131411800 ps
CPU time	80.53 seconds
Started	Sep 09 07:03:08 AM UTC 24
Finished	Sep 09 07:04:31 AM UTC 24
Peak memory	224068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=493696831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all_ with_rand_reset.493696831
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/97.uart_fifo_reset.374765580
Short name	T232
Test name
Test status
Simulation time	129607627964 ps
CPU time	50.95 seconds
Started	Sep 09 07:03:11 AM UTC 24
Finished	Sep 09 07:04:03 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374765580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.374765580
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/97.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2813527870
Short name	T997
Test name
Test status
Simulation time	2354175117 ps
CPU time	37.08 seconds
Started	Sep 09 07:03:13 AM UTC 24
Finished	Sep 09 07:03:51 AM UTC 24
Peak memory	208832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=2813527870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all _with_rand_reset.2813527870
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/98.uart_fifo_reset.3570740615
Short name	T1030
Test name
Test status
Simulation time	93445160842 ps
CPU time	95.05 seconds
Started	Sep 09 07:03:14 AM UTC 24
Finished	Sep 09 07:04:51 AM UTC 24
Peak memory	208768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570740615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3570740615
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/98.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.1708436175
Short name	T1001
Test name
Test status
Simulation time	2069975315 ps
CPU time	42.6 seconds
Started	Sep 09 07:03:14 AM UTC 24
Finished	Sep 09 07:03:58 AM UTC 24
Peak memory	223996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=1708436175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all _with_rand_reset.1708436175
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/99.uart_fifo_reset.1557689842
Short name	T1007
Test name
Test status
Simulation time	84409299380 ps
CPU time	52.08 seconds
Started	Sep 09 07:03:15 AM UTC 24
Finished	Sep 09 07:04:09 AM UTC 24
Peak memory	208708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557689842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1557689842
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/99.uart_fifo_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.3354526491
Short name	T1008
Test name
Test status
Simulation time	13860303098 ps
CPU time	56.96 seconds
Started	Sep 09 07:03:17 AM UTC 24
Finished	Sep 09 07:04:16 AM UTC 24
Peak memory	217716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc l +ntb_random_seed=3354526491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all _with_rand_reset.3354526491
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest