| T1052 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/173.uart_fifo_reset.2217900533 |
|
|
Sep 11 03:24:55 AM UTC 24 |
Sep 11 03:25:40 AM UTC 24 |
20039782625 ps |
| T1053 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/170.uart_fifo_reset.214811549 |
|
|
Sep 11 03:24:50 AM UTC 24 |
Sep 11 03:25:42 AM UTC 24 |
46942545551 ps |
| T1054 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3645718742 |
|
|
Sep 11 03:25:24 AM UTC 24 |
Sep 11 03:25:43 AM UTC 24 |
20331324473 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3981032279 |
|
|
Sep 11 03:25:31 AM UTC 24 |
Sep 11 03:25:45 AM UTC 24 |
29215722106 ps |
| T1055 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/112.uart_fifo_reset.276627574 |
|
|
Sep 11 03:23:22 AM UTC 24 |
Sep 11 03:25:45 AM UTC 24 |
29086011274 ps |
| T1056 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/113.uart_fifo_reset.2110774720 |
|
|
Sep 11 03:23:24 AM UTC 24 |
Sep 11 03:25:45 AM UTC 24 |
52795954473 ps |
| T1057 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3314327773 |
|
|
Sep 11 03:25:24 AM UTC 24 |
Sep 11 03:25:47 AM UTC 24 |
34154470991 ps |
| T1058 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/156.uart_fifo_reset.2275003612 |
|
|
Sep 11 03:24:32 AM UTC 24 |
Sep 11 03:25:48 AM UTC 24 |
154551276206 ps |
| T1059 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/188.uart_fifo_reset.2382032037 |
|
|
Sep 11 03:25:19 AM UTC 24 |
Sep 11 03:25:50 AM UTC 24 |
53927981659 ps |
| T1060 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/174.uart_fifo_reset.3675690234 |
|
|
Sep 11 03:24:57 AM UTC 24 |
Sep 11 03:25:52 AM UTC 24 |
41294826353 ps |
| T1061 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1553644775 |
|
|
Sep 11 03:24:32 AM UTC 24 |
Sep 11 03:25:53 AM UTC 24 |
134943850628 ps |
| T1062 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/149.uart_fifo_reset.78004672 |
|
|
Sep 11 03:24:24 AM UTC 24 |
Sep 11 03:25:54 AM UTC 24 |
52071521234 ps |
| T1063 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/189.uart_fifo_reset.126691072 |
|
|
Sep 11 03:25:21 AM UTC 24 |
Sep 11 03:25:55 AM UTC 24 |
54928350077 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/187.uart_fifo_reset.1455167286 |
|
|
Sep 11 03:25:17 AM UTC 24 |
Sep 11 03:26:00 AM UTC 24 |
18866790216 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/192.uart_fifo_reset.88679037 |
|
|
Sep 11 03:25:23 AM UTC 24 |
Sep 11 03:26:08 AM UTC 24 |
172513629692 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/148.uart_fifo_reset.702488307 |
|
|
Sep 11 03:24:22 AM UTC 24 |
Sep 11 03:26:08 AM UTC 24 |
124066040947 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3743089446 |
|
|
Sep 11 03:25:31 AM UTC 24 |
Sep 11 03:26:10 AM UTC 24 |
35721375758 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/219.uart_fifo_reset.3710015546 |
|
|
Sep 11 03:25:51 AM UTC 24 |
Sep 11 03:26:15 AM UTC 24 |
25387790394 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2360938992 |
|
|
Sep 11 03:25:07 AM UTC 24 |
Sep 11 03:26:16 AM UTC 24 |
164621152122 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3810034970 |
|
|
Sep 11 03:25:46 AM UTC 24 |
Sep 11 03:26:16 AM UTC 24 |
18137419365 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/222.uart_fifo_reset.3130112348 |
|
|
Sep 11 03:25:55 AM UTC 24 |
Sep 11 03:26:23 AM UTC 24 |
39081836955 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/226.uart_fifo_reset.1375685541 |
|
|
Sep 11 03:26:09 AM UTC 24 |
Sep 11 03:26:23 AM UTC 24 |
36089441811 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3926011036 |
|
|
Sep 11 03:25:48 AM UTC 24 |
Sep 11 03:26:24 AM UTC 24 |
30056258463 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/208.uart_fifo_reset.1893434916 |
|
|
Sep 11 03:25:39 AM UTC 24 |
Sep 11 03:26:26 AM UTC 24 |
89434850267 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1576855477 |
|
|
Sep 11 03:25:49 AM UTC 24 |
Sep 11 03:26:27 AM UTC 24 |
61879342377 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2477975399 |
|
|
Sep 11 03:25:39 AM UTC 24 |
Sep 11 03:26:28 AM UTC 24 |
168130304761 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_perf.1468417693 |
|
|
Sep 11 03:19:30 AM UTC 24 |
Sep 11 03:26:34 AM UTC 24 |
6581807203 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_stress_all.3418899007 |
|
|
Sep 11 03:19:35 AM UTC 24 |
Sep 11 03:26:34 AM UTC 24 |
195094751262 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/168.uart_fifo_reset.714677080 |
|
|
Sep 11 03:24:49 AM UTC 24 |
Sep 11 03:26:36 AM UTC 24 |
87145114199 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1568872701 |
|
|
Sep 11 03:25:53 AM UTC 24 |
Sep 11 03:26:37 AM UTC 24 |
48378077442 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/227.uart_fifo_reset.213387152 |
|
|
Sep 11 03:26:11 AM UTC 24 |
Sep 11 03:26:39 AM UTC 24 |
9111147369 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/223.uart_fifo_reset.3964152640 |
|
|
Sep 11 03:25:56 AM UTC 24 |
Sep 11 03:26:40 AM UTC 24 |
85790208555 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/212.uart_fifo_reset.493634058 |
|
|
Sep 11 03:25:42 AM UTC 24 |
Sep 11 03:26:40 AM UTC 24 |
20171127989 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/91.uart_fifo_reset.2310198375 |
|
|
Sep 11 03:22:42 AM UTC 24 |
Sep 11 03:26:44 AM UTC 24 |
194970797896 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2910300246 |
|
|
Sep 11 03:26:01 AM UTC 24 |
Sep 11 03:26:45 AM UTC 24 |
109995051284 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/229.uart_fifo_reset.4129677214 |
|
|
Sep 11 03:26:17 AM UTC 24 |
Sep 11 03:26:45 AM UTC 24 |
9016786311 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3809294513 |
|
|
Sep 11 03:25:24 AM UTC 24 |
Sep 11 03:26:45 AM UTC 24 |
48655873695 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2961887526 |
|
|
Sep 11 03:25:40 AM UTC 24 |
Sep 11 03:26:48 AM UTC 24 |
142059472095 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/225.uart_fifo_reset.1758923659 |
|
|
Sep 11 03:26:08 AM UTC 24 |
Sep 11 03:26:50 AM UTC 24 |
52076473363 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/204.uart_fifo_reset.419407701 |
|
|
Sep 11 03:25:35 AM UTC 24 |
Sep 11 03:26:52 AM UTC 24 |
200615479662 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.3975902797 |
|
|
Sep 11 03:13:01 AM UTC 24 |
Sep 11 03:26:52 AM UTC 24 |
114038626946 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/196.uart_fifo_reset.1535844234 |
|
|
Sep 11 03:25:25 AM UTC 24 |
Sep 11 03:26:52 AM UTC 24 |
98788849341 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/232.uart_fifo_reset.3939805200 |
|
|
Sep 11 03:26:24 AM UTC 24 |
Sep 11 03:26:53 AM UTC 24 |
18022979179 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/169.uart_fifo_reset.3639581814 |
|
|
Sep 11 03:24:49 AM UTC 24 |
Sep 11 03:26:56 AM UTC 24 |
83831220060 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/231.uart_fifo_reset.1937501733 |
|
|
Sep 11 03:26:24 AM UTC 24 |
Sep 11 03:26:56 AM UTC 24 |
62036552470 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_stress_all.2264173371 |
|
|
Sep 11 03:14:17 AM UTC 24 |
Sep 11 03:26:58 AM UTC 24 |
358912837601 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/237.uart_fifo_reset.269866137 |
|
|
Sep 11 03:26:34 AM UTC 24 |
Sep 11 03:26:58 AM UTC 24 |
24966726585 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/88.uart_fifo_reset.2177844434 |
|
|
Sep 11 03:22:34 AM UTC 24 |
Sep 11 03:26:59 AM UTC 24 |
121455521867 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/199.uart_fifo_reset.4128287016 |
|
|
Sep 11 03:25:28 AM UTC 24 |
Sep 11 03:26:59 AM UTC 24 |
56658424513 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/210.uart_fifo_reset.922364869 |
|
|
Sep 11 03:25:40 AM UTC 24 |
Sep 11 03:27:00 AM UTC 24 |
97937577389 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/234.uart_fifo_reset.1041719500 |
|
|
Sep 11 03:26:26 AM UTC 24 |
Sep 11 03:27:01 AM UTC 24 |
18748210593 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2778553675 |
|
|
Sep 11 03:25:32 AM UTC 24 |
Sep 11 03:27:02 AM UTC 24 |
124943497082 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/242.uart_fifo_reset.4223784887 |
|
|
Sep 11 03:26:41 AM UTC 24 |
Sep 11 03:27:03 AM UTC 24 |
75712134677 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.3790920322 |
|
|
Sep 11 03:18:57 AM UTC 24 |
Sep 11 03:27:03 AM UTC 24 |
214890849253 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3330432235 |
|
|
Sep 11 03:26:48 AM UTC 24 |
Sep 11 03:27:03 AM UTC 24 |
12357552041 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/241.uart_fifo_reset.637504170 |
|
|
Sep 11 03:26:40 AM UTC 24 |
Sep 11 03:27:03 AM UTC 24 |
72473264410 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_perf.3356879426 |
|
|
Sep 11 03:16:16 AM UTC 24 |
Sep 11 03:27:06 AM UTC 24 |
12352810514 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/200.uart_fifo_reset.3408732938 |
|
|
Sep 11 03:25:30 AM UTC 24 |
Sep 11 03:27:09 AM UTC 24 |
199678963922 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1371369679 |
|
|
Sep 11 03:25:15 AM UTC 24 |
Sep 11 03:27:12 AM UTC 24 |
35662314070 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3292829791 |
|
|
Sep 11 03:26:28 AM UTC 24 |
Sep 11 03:27:12 AM UTC 24 |
47499047829 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/228.uart_fifo_reset.233849544 |
|
|
Sep 11 03:26:16 AM UTC 24 |
Sep 11 03:27:16 AM UTC 24 |
61462205572 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/256.uart_fifo_reset.2944323759 |
|
|
Sep 11 03:26:59 AM UTC 24 |
Sep 11 03:27:17 AM UTC 24 |
19636297640 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/259.uart_fifo_reset.3050159022 |
|
|
Sep 11 03:27:00 AM UTC 24 |
Sep 11 03:27:18 AM UTC 24 |
28799131765 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/240.uart_fifo_reset.4006732823 |
|
|
Sep 11 03:26:39 AM UTC 24 |
Sep 11 03:27:19 AM UTC 24 |
92769220713 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/233.uart_fifo_reset.897201778 |
|
|
Sep 11 03:26:25 AM UTC 24 |
Sep 11 03:27:19 AM UTC 24 |
44018720055 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/211.uart_fifo_reset.4178226142 |
|
|
Sep 11 03:25:40 AM UTC 24 |
Sep 11 03:27:21 AM UTC 24 |
166923468804 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3687548801 |
|
|
Sep 11 03:27:04 AM UTC 24 |
Sep 11 03:27:23 AM UTC 24 |
10255572335 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/221.uart_fifo_reset.218086443 |
|
|
Sep 11 03:25:54 AM UTC 24 |
Sep 11 03:27:23 AM UTC 24 |
97829256105 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1130880533 |
|
|
Sep 11 03:25:46 AM UTC 24 |
Sep 11 03:27:24 AM UTC 24 |
371032876857 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/216.uart_fifo_reset.2898496776 |
|
|
Sep 11 03:25:47 AM UTC 24 |
Sep 11 03:27:24 AM UTC 24 |
118991544302 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_stress_all.664572605 |
|
|
Sep 11 03:11:29 AM UTC 24 |
Sep 11 03:27:25 AM UTC 24 |
211623286882 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/263.uart_fifo_reset.3202275099 |
|
|
Sep 11 03:27:04 AM UTC 24 |
Sep 11 03:27:26 AM UTC 24 |
56638838932 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/191.uart_fifo_reset.128870887 |
|
|
Sep 11 03:25:22 AM UTC 24 |
Sep 11 03:27:26 AM UTC 24 |
62455877135 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/246.uart_fifo_reset.3926649088 |
|
|
Sep 11 03:26:46 AM UTC 24 |
Sep 11 03:27:28 AM UTC 24 |
25015430827 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/249.uart_fifo_reset.1345249115 |
|
|
Sep 11 03:26:51 AM UTC 24 |
Sep 11 03:27:28 AM UTC 24 |
24389092088 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/135.uart_fifo_reset.2955460011 |
|
|
Sep 11 03:23:55 AM UTC 24 |
Sep 11 03:27:29 AM UTC 24 |
72926425798 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2421130572 |
|
|
Sep 11 03:26:59 AM UTC 24 |
Sep 11 03:27:29 AM UTC 24 |
56018945228 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3037361786 |
|
|
Sep 11 03:26:46 AM UTC 24 |
Sep 11 03:27:30 AM UTC 24 |
40547250836 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/186.uart_fifo_reset.765706092 |
|
|
Sep 11 03:25:16 AM UTC 24 |
Sep 11 03:27:31 AM UTC 24 |
302319035181 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1981351987 |
|
|
Sep 11 03:26:36 AM UTC 24 |
Sep 11 03:27:32 AM UTC 24 |
84502365575 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1822672971 |
|
|
Sep 11 03:27:17 AM UTC 24 |
Sep 11 03:27:35 AM UTC 24 |
19035535479 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/251.uart_fifo_reset.411514626 |
|
|
Sep 11 03:26:52 AM UTC 24 |
Sep 11 03:27:36 AM UTC 24 |
169386140112 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/270.uart_fifo_reset.1161706975 |
|
|
Sep 11 03:27:14 AM UTC 24 |
Sep 11 03:27:37 AM UTC 24 |
10966929375 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/190.uart_fifo_reset.2489622075 |
|
|
Sep 11 03:25:21 AM UTC 24 |
Sep 11 03:27:39 AM UTC 24 |
209007722263 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/252.uart_fifo_reset.2977772073 |
|
|
Sep 11 03:26:53 AM UTC 24 |
Sep 11 03:27:40 AM UTC 24 |
108824806623 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/276.uart_fifo_reset.3324946412 |
|
|
Sep 11 03:27:21 AM UTC 24 |
Sep 11 03:27:42 AM UTC 24 |
29808486133 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/293.uart_fifo_reset.1044828920 |
|
|
Sep 11 03:27:37 AM UTC 24 |
Sep 11 03:28:43 AM UTC 24 |
156809144666 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/253.uart_fifo_reset.923661994 |
|
|
Sep 11 03:26:55 AM UTC 24 |
Sep 11 03:27:42 AM UTC 24 |
131741449300 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/269.uart_fifo_reset.3046852852 |
|
|
Sep 11 03:27:13 AM UTC 24 |
Sep 11 03:27:44 AM UTC 24 |
36467238072 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/238.uart_fifo_reset.510111645 |
|
|
Sep 11 03:26:35 AM UTC 24 |
Sep 11 03:27:44 AM UTC 24 |
133031593181 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1011476863 |
|
|
Sep 11 03:26:52 AM UTC 24 |
Sep 11 03:27:45 AM UTC 24 |
22570548811 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/282.uart_fifo_reset.1295600972 |
|
|
Sep 11 03:27:27 AM UTC 24 |
Sep 11 03:27:47 AM UTC 24 |
67160325403 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/280.uart_fifo_reset.3687746379 |
|
|
Sep 11 03:27:24 AM UTC 24 |
Sep 11 03:27:47 AM UTC 24 |
181537286967 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/273.uart_fifo_reset.3804484985 |
|
|
Sep 11 03:27:19 AM UTC 24 |
Sep 11 03:27:52 AM UTC 24 |
71149904819 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/166.uart_fifo_reset.1571793107 |
|
|
Sep 11 03:24:48 AM UTC 24 |
Sep 11 03:27:53 AM UTC 24 |
179643437168 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/267.uart_fifo_reset.288119189 |
|
|
Sep 11 03:27:07 AM UTC 24 |
Sep 11 03:27:55 AM UTC 24 |
58038989773 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2628503699 |
|
|
Sep 11 03:27:24 AM UTC 24 |
Sep 11 03:27:57 AM UTC 24 |
16187390996 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/277.uart_fifo_reset.4130412499 |
|
|
Sep 11 03:27:23 AM UTC 24 |
Sep 11 03:27:58 AM UTC 24 |
22237724584 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/205.uart_fifo_reset.3342616150 |
|
|
Sep 11 03:25:35 AM UTC 24 |
Sep 11 03:28:00 AM UTC 24 |
141516586355 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/272.uart_fifo_reset.3689762002 |
|
|
Sep 11 03:27:18 AM UTC 24 |
Sep 11 03:28:04 AM UTC 24 |
66220837826 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1405076309 |
|
|
Sep 11 03:26:41 AM UTC 24 |
Sep 11 03:28:05 AM UTC 24 |
25311455849 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/260.uart_fifo_reset.2246120978 |
|
|
Sep 11 03:27:01 AM UTC 24 |
Sep 11 03:28:05 AM UTC 24 |
164848531710 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3912426505 |
|
|
Sep 11 03:15:49 AM UTC 24 |
Sep 11 03:28:10 AM UTC 24 |
145173483161 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/298.uart_fifo_reset.2595892503 |
|
|
Sep 11 03:27:45 AM UTC 24 |
Sep 11 03:28:12 AM UTC 24 |
85871839263 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2604761958 |
|
|
Sep 11 03:27:30 AM UTC 24 |
Sep 11 03:28:14 AM UTC 24 |
113988072890 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/294.uart_fifo_reset.2026216303 |
|
|
Sep 11 03:27:39 AM UTC 24 |
Sep 11 03:28:15 AM UTC 24 |
13329968438 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/297.uart_fifo_reset.2901105532 |
|
|
Sep 11 03:27:43 AM UTC 24 |
Sep 11 03:28:15 AM UTC 24 |
70012162796 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/244.uart_fifo_reset.3770027695 |
|
|
Sep 11 03:26:45 AM UTC 24 |
Sep 11 03:28:17 AM UTC 24 |
50872161911 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/292.uart_fifo_reset.803873210 |
|
|
Sep 11 03:27:37 AM UTC 24 |
Sep 11 03:28:18 AM UTC 24 |
44113997488 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/167.uart_fifo_reset.269071011 |
|
|
Sep 11 03:24:48 AM UTC 24 |
Sep 11 03:28:20 AM UTC 24 |
110077619894 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/290.uart_fifo_reset.814223260 |
|
|
Sep 11 03:27:33 AM UTC 24 |
Sep 11 03:28:22 AM UTC 24 |
123274138065 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/177.uart_fifo_reset.908492178 |
|
|
Sep 11 03:25:01 AM UTC 24 |
Sep 11 03:28:24 AM UTC 24 |
98367729578 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2569699495 |
|
|
Sep 11 03:27:20 AM UTC 24 |
Sep 11 03:28:25 AM UTC 24 |
148241777149 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2292310543 |
|
|
Sep 11 03:27:29 AM UTC 24 |
Sep 11 03:28:27 AM UTC 24 |
122957329814 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/165.uart_fifo_reset.311602957 |
|
|
Sep 11 03:24:47 AM UTC 24 |
Sep 11 03:28:34 AM UTC 24 |
120463380417 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_perf.1647165739 |
|
|
Sep 11 03:16:50 AM UTC 24 |
Sep 11 03:28:38 AM UTC 24 |
16166903299 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/281.uart_fifo_reset.1285805133 |
|
|
Sep 11 03:27:26 AM UTC 24 |
Sep 11 03:28:38 AM UTC 24 |
69930355147 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2933784894 |
|
|
Sep 11 03:27:20 AM UTC 24 |
Sep 11 03:28:39 AM UTC 24 |
95842153324 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/197.uart_fifo_reset.1900338446 |
|
|
Sep 11 03:25:26 AM UTC 24 |
Sep 11 03:28:39 AM UTC 24 |
63574038519 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_perf.491850885 |
|
|
Sep 11 03:17:13 AM UTC 24 |
Sep 11 03:28:39 AM UTC 24 |
8269964625 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/255.uart_fifo_reset.1356109226 |
|
|
Sep 11 03:26:57 AM UTC 24 |
Sep 11 03:28:41 AM UTC 24 |
62919802284 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/287.uart_fifo_reset.1447529756 |
|
|
Sep 11 03:27:30 AM UTC 24 |
Sep 11 03:28:42 AM UTC 24 |
111562537551 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/265.uart_fifo_reset.4012753880 |
|
|
Sep 11 03:27:04 AM UTC 24 |
Sep 11 03:28:44 AM UTC 24 |
43578948090 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/213.uart_fifo_reset.2412467835 |
|
|
Sep 11 03:25:43 AM UTC 24 |
Sep 11 03:28:46 AM UTC 24 |
49747645059 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/258.uart_fifo_reset.1057752258 |
|
|
Sep 11 03:27:00 AM UTC 24 |
Sep 11 03:28:46 AM UTC 24 |
252972469164 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/254.uart_fifo_reset.3896961464 |
|
|
Sep 11 03:26:57 AM UTC 24 |
Sep 11 03:28:48 AM UTC 24 |
142241098452 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/289.uart_fifo_reset.3689553212 |
|
|
Sep 11 03:27:32 AM UTC 24 |
Sep 11 03:28:53 AM UTC 24 |
37863075091 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/184.uart_fifo_reset.921718071 |
|
|
Sep 11 03:25:12 AM UTC 24 |
Sep 11 03:28:53 AM UTC 24 |
141203883441 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/278.uart_fifo_reset.3635000437 |
|
|
Sep 11 03:27:24 AM UTC 24 |
Sep 11 03:28:56 AM UTC 24 |
97631456527 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/262.uart_fifo_reset.3758106137 |
|
|
Sep 11 03:27:03 AM UTC 24 |
Sep 11 03:28:58 AM UTC 24 |
60205348366 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/120.uart_fifo_reset.2437140401 |
|
|
Sep 11 03:23:40 AM UTC 24 |
Sep 11 03:29:00 AM UTC 24 |
192025492667 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/268.uart_fifo_reset.3337562727 |
|
|
Sep 11 03:27:11 AM UTC 24 |
Sep 11 03:29:05 AM UTC 24 |
119494069572 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/288.uart_fifo_reset.2115145679 |
|
|
Sep 11 03:27:30 AM UTC 24 |
Sep 11 03:29:07 AM UTC 24 |
46322990868 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/247.uart_fifo_reset.1235540253 |
|
|
Sep 11 03:26:46 AM UTC 24 |
Sep 11 03:29:07 AM UTC 24 |
131611643108 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3949447333 |
|
|
Sep 11 03:27:41 AM UTC 24 |
Sep 11 03:29:10 AM UTC 24 |
326313350814 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/264.uart_fifo_reset.2854662603 |
|
|
Sep 11 03:27:04 AM UTC 24 |
Sep 11 03:29:27 AM UTC 24 |
132982079804 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3252602438 |
|
|
Sep 11 03:27:45 AM UTC 24 |
Sep 11 03:29:30 AM UTC 24 |
187460051360 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/283.uart_fifo_reset.1158835049 |
|
|
Sep 11 03:27:27 AM UTC 24 |
Sep 11 03:29:31 AM UTC 24 |
243155732369 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/230.uart_fifo_reset.551596577 |
|
|
Sep 11 03:26:17 AM UTC 24 |
Sep 11 03:29:33 AM UTC 24 |
312674137204 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/296.uart_fifo_reset.2755057647 |
|
|
Sep 11 03:27:43 AM UTC 24 |
Sep 11 03:29:34 AM UTC 24 |
98196276733 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_intr.1103511016 |
|
|
Sep 11 03:19:20 AM UTC 24 |
Sep 11 03:29:34 AM UTC 24 |
336356240048 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/236.uart_fifo_reset.1832633004 |
|
|
Sep 11 03:26:29 AM UTC 24 |
Sep 11 03:29:52 AM UTC 24 |
102552236687 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/261.uart_fifo_reset.2206462475 |
|
|
Sep 11 03:27:02 AM UTC 24 |
Sep 11 03:29:52 AM UTC 24 |
59511518777 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_fifo_reset.2700039226 |
|
|
Sep 11 03:19:39 AM UTC 24 |
Sep 11 03:30:05 AM UTC 24 |
191497536266 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/206.uart_fifo_reset.863615507 |
|
|
Sep 11 03:25:39 AM UTC 24 |
Sep 11 03:30:07 AM UTC 24 |
122619778378 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_stress_all.2231633097 |
|
|
Sep 11 03:05:31 AM UTC 24 |
Sep 11 03:30:15 AM UTC 24 |
755828675722 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/285.uart_fifo_reset.314318275 |
|
|
Sep 11 03:27:29 AM UTC 24 |
Sep 11 03:30:48 AM UTC 24 |
112507361287 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/68.uart_fifo_reset.1042765252 |
|
|
Sep 11 03:21:12 AM UTC 24 |
Sep 11 03:30:58 AM UTC 24 |
185702342177 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1317078598 |
|
|
Sep 11 03:27:36 AM UTC 24 |
Sep 11 03:32:38 AM UTC 24 |
169200857102 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_perf.2337212713 |
|
|
Sep 11 03:19:10 AM UTC 24 |
Sep 11 03:35:45 AM UTC 24 |
15332359460 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.3567265534 |
|
|
Sep 11 03:19:30 AM UTC 24 |
Sep 11 03:36:39 AM UTC 24 |
150177495835 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/139.uart_fifo_reset.652065832 |
|
|
Sep 11 03:24:07 AM UTC 24 |
Sep 11 03:37:01 AM UTC 24 |
145531907634 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.265606432 |
|
|
Sep 11 03:17:14 AM UTC 24 |
Sep 11 03:38:14 AM UTC 24 |
157260506470 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.4245097550 |
|
|
Sep 11 03:27:46 AM UTC 24 |
Sep 11 03:27:50 AM UTC 24 |
92496965 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.3658486529 |
|
|
Sep 11 03:27:48 AM UTC 24 |
Sep 11 03:27:50 AM UTC 24 |
12580721 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.928394440 |
|
|
Sep 11 03:27:48 AM UTC 24 |
Sep 11 03:27:50 AM UTC 24 |
50422769 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1734590085 |
|
|
Sep 11 03:27:51 AM UTC 24 |
Sep 11 03:27:53 AM UTC 24 |
50216200 ps |
| T49 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3788194458 |
|
|
Sep 11 03:27:51 AM UTC 24 |
Sep 11 03:27:53 AM UTC 24 |
16854103 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3670331861 |
|
|
Sep 11 03:27:53 AM UTC 24 |
Sep 11 03:27:55 AM UTC 24 |
75218287 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.169223878 |
|
|
Sep 11 03:27:53 AM UTC 24 |
Sep 11 03:27:55 AM UTC 24 |
38108982 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.2004830552 |
|
|
Sep 11 03:27:51 AM UTC 24 |
Sep 11 03:27:56 AM UTC 24 |
1463741829 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3994919328 |
|
|
Sep 11 03:27:54 AM UTC 24 |
Sep 11 03:27:57 AM UTC 24 |
21181577 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.4013664330 |
|
|
Sep 11 03:27:56 AM UTC 24 |
Sep 11 03:27:57 AM UTC 24 |
36857357 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3394540380 |
|
|
Sep 11 03:27:57 AM UTC 24 |
Sep 11 03:27:59 AM UTC 24 |
11634551 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3618226430 |
|
|
Sep 11 03:27:57 AM UTC 24 |
Sep 11 03:27:59 AM UTC 24 |
12413586 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.1907572767 |
|
|
Sep 11 03:27:56 AM UTC 24 |
Sep 11 03:27:59 AM UTC 24 |
96809228 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2843427886 |
|
|
Sep 11 03:27:55 AM UTC 24 |
Sep 11 03:27:59 AM UTC 24 |
795815855 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.1745434365 |
|
|
Sep 11 03:27:58 AM UTC 24 |
Sep 11 03:28:00 AM UTC 24 |
72044882 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.359398960 |
|
|
Sep 11 03:27:58 AM UTC 24 |
Sep 11 03:28:00 AM UTC 24 |
93855871 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.32969734 |
|
|
Sep 11 03:27:58 AM UTC 24 |
Sep 11 03:28:01 AM UTC 24 |
704239556 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3841951365 |
|
|
Sep 11 03:27:59 AM UTC 24 |
Sep 11 03:28:01 AM UTC 24 |
70414445 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.3394916312 |
|
|
Sep 11 03:27:59 AM UTC 24 |
Sep 11 03:28:01 AM UTC 24 |
15223387 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3265248111 |
|
|
Sep 11 03:27:59 AM UTC 24 |
Sep 11 03:28:02 AM UTC 24 |
96494250 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2028940423 |
|
|
Sep 11 03:28:01 AM UTC 24 |
Sep 11 03:28:03 AM UTC 24 |
25064730 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.988065321 |
|
|
Sep 11 03:28:01 AM UTC 24 |
Sep 11 03:28:03 AM UTC 24 |
39929566 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.3440899148 |
|
|
Sep 11 03:27:59 AM UTC 24 |
Sep 11 03:28:03 AM UTC 24 |
34261293 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3225598125 |
|
|
Sep 11 03:28:02 AM UTC 24 |
Sep 11 03:28:04 AM UTC 24 |
54622010 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3048523086 |
|
|
Sep 11 03:28:02 AM UTC 24 |
Sep 11 03:28:04 AM UTC 24 |
15319112 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4007774732 |
|
|
Sep 11 03:28:02 AM UTC 24 |
Sep 11 03:28:04 AM UTC 24 |
29232353 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3286935610 |
|
|
Sep 11 03:28:03 AM UTC 24 |
Sep 11 03:28:05 AM UTC 24 |
47835272 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.3090864110 |
|
|
Sep 11 03:28:03 AM UTC 24 |
Sep 11 03:28:05 AM UTC 24 |
15896368 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.1046978342 |
|
|
Sep 11 03:28:03 AM UTC 24 |
Sep 11 03:28:05 AM UTC 24 |
15209364 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.4114168962 |
|
|
Sep 11 03:28:01 AM UTC 24 |
Sep 11 03:28:05 AM UTC 24 |
217048679 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1053121896 |
|
|
Sep 11 03:28:02 AM UTC 24 |
Sep 11 03:28:06 AM UTC 24 |
37239350 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.2496747258 |
|
|
Sep 11 03:28:03 AM UTC 24 |
Sep 11 03:28:06 AM UTC 24 |
206564127 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1384545074 |
|
|
Sep 11 03:28:05 AM UTC 24 |
Sep 11 03:28:07 AM UTC 24 |
20903769 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.508107413 |
|
|
Sep 11 03:28:05 AM UTC 24 |
Sep 11 03:28:07 AM UTC 24 |
56992692 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3727068251 |
|
|
Sep 11 03:28:05 AM UTC 24 |
Sep 11 03:28:07 AM UTC 24 |
139265693 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.925938748 |
|
|
Sep 11 03:28:05 AM UTC 24 |
Sep 11 03:28:08 AM UTC 24 |
182516550 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2353243289 |
|
|
Sep 11 03:28:06 AM UTC 24 |
Sep 11 03:28:08 AM UTC 24 |
40477905 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.2630165427 |
|
|
Sep 11 03:28:06 AM UTC 24 |
Sep 11 03:28:08 AM UTC 24 |
14375437 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3529852537 |
|
|
Sep 11 03:28:06 AM UTC 24 |
Sep 11 03:28:08 AM UTC 24 |
25039787 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1083446932 |
|
|
Sep 11 03:28:06 AM UTC 24 |
Sep 11 03:28:09 AM UTC 24 |
170904913 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.2220753310 |
|
|
Sep 11 03:28:06 AM UTC 24 |
Sep 11 03:28:09 AM UTC 24 |
55070090 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.2371999136 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:21 AM UTC 24 |
40695832 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3942140781 |
|
|
Sep 11 03:28:06 AM UTC 24 |
Sep 11 03:28:09 AM UTC 24 |
33735702 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3464779309 |
|
|
Sep 11 03:28:08 AM UTC 24 |
Sep 11 03:28:10 AM UTC 24 |
18505169 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1884530525 |
|
|
Sep 11 03:28:08 AM UTC 24 |
Sep 11 03:28:10 AM UTC 24 |
21174436 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.1435116714 |
|
|
Sep 11 03:28:08 AM UTC 24 |
Sep 11 03:28:10 AM UTC 24 |
46061474 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2219605691 |
|
|
Sep 11 03:28:06 AM UTC 24 |
Sep 11 03:28:11 AM UTC 24 |
265532299 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2171210976 |
|
|
Sep 11 03:28:09 AM UTC 24 |
Sep 11 03:28:11 AM UTC 24 |
14779849 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.1793951853 |
|
|
Sep 11 03:28:15 AM UTC 24 |
Sep 11 03:28:17 AM UTC 24 |
186120547 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2828350785 |
|
|
Sep 11 03:28:09 AM UTC 24 |
Sep 11 03:28:11 AM UTC 24 |
16708410 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.405566773 |
|
|
Sep 11 03:28:08 AM UTC 24 |
Sep 11 03:28:12 AM UTC 24 |
182766921 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1123282096 |
|
|
Sep 11 03:28:09 AM UTC 24 |
Sep 11 03:28:12 AM UTC 24 |
210842630 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2179521386 |
|
|
Sep 11 03:28:10 AM UTC 24 |
Sep 11 03:28:12 AM UTC 24 |
121838179 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.1247631309 |
|
|
Sep 11 03:28:10 AM UTC 24 |
Sep 11 03:28:13 AM UTC 24 |
74125235 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2570863784 |
|
|
Sep 11 03:28:11 AM UTC 24 |
Sep 11 03:28:13 AM UTC 24 |
14718857 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.2945755653 |
|
|
Sep 11 03:28:11 AM UTC 24 |
Sep 11 03:28:13 AM UTC 24 |
18111957 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4133243738 |
|
|
Sep 11 03:28:11 AM UTC 24 |
Sep 11 03:28:13 AM UTC 24 |
236820921 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3681726543 |
|
|
Sep 11 03:28:11 AM UTC 24 |
Sep 11 03:28:13 AM UTC 24 |
17790096 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3848647139 |
|
|
Sep 11 03:28:10 AM UTC 24 |
Sep 11 03:28:13 AM UTC 24 |
316177167 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.608539728 |
|
|
Sep 11 03:28:11 AM UTC 24 |
Sep 11 03:28:14 AM UTC 24 |
32453221 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3934173077 |
|
|
Sep 11 03:28:13 AM UTC 24 |
Sep 11 03:28:14 AM UTC 24 |
21549380 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.3824203925 |
|
|
Sep 11 03:28:13 AM UTC 24 |
Sep 11 03:28:15 AM UTC 24 |
135183773 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1286636318 |
|
|
Sep 11 03:28:13 AM UTC 24 |
Sep 11 03:28:15 AM UTC 24 |
41132560 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3077044170 |
|
|
Sep 11 03:28:13 AM UTC 24 |
Sep 11 03:28:15 AM UTC 24 |
90491992 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1235025187 |
|
|
Sep 11 03:28:13 AM UTC 24 |
Sep 11 03:28:15 AM UTC 24 |
77265234 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.3641040797 |
|
|
Sep 11 03:28:13 AM UTC 24 |
Sep 11 03:28:16 AM UTC 24 |
403337010 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1136414050 |
|
|
Sep 11 03:28:15 AM UTC 24 |
Sep 11 03:28:17 AM UTC 24 |
17005741 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.1408190181 |
|
|
Sep 11 03:28:15 AM UTC 24 |
Sep 11 03:28:17 AM UTC 24 |
15167380 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.485487921 |
|
|
Sep 11 03:28:15 AM UTC 24 |
Sep 11 03:28:17 AM UTC 24 |
77255268 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1713113786 |
|
|
Sep 11 03:28:15 AM UTC 24 |
Sep 11 03:28:17 AM UTC 24 |
42086290 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2067539685 |
|
|
Sep 11 03:28:15 AM UTC 24 |
Sep 11 03:28:17 AM UTC 24 |
26752520 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.2904826440 |
|
|
Sep 11 03:28:15 AM UTC 24 |
Sep 11 03:28:17 AM UTC 24 |
70700548 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3215212188 |
|
|
Sep 11 03:28:15 AM UTC 24 |
Sep 11 03:28:17 AM UTC 24 |
84328172 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.4111149440 |
|
|
Sep 11 03:28:17 AM UTC 24 |
Sep 11 03:28:19 AM UTC 24 |
40172662 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.3523563305 |
|
|
Sep 11 03:28:17 AM UTC 24 |
Sep 11 03:28:19 AM UTC 24 |
19961341 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2700813152 |
|
|
Sep 11 03:28:17 AM UTC 24 |
Sep 11 03:28:19 AM UTC 24 |
96998189 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1683911065 |
|
|
Sep 11 03:28:17 AM UTC 24 |
Sep 11 03:28:19 AM UTC 24 |
43759620 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.267208044 |
|
|
Sep 11 03:28:17 AM UTC 24 |
Sep 11 03:28:19 AM UTC 24 |
56215081 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3007506085 |
|
|
Sep 11 03:28:17 AM UTC 24 |
Sep 11 03:28:19 AM UTC 24 |
28727319 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1452014707 |
|
|
Sep 11 03:28:17 AM UTC 24 |
Sep 11 03:28:19 AM UTC 24 |
45590434 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4034373497 |
|
|
Sep 11 03:28:17 AM UTC 24 |
Sep 11 03:28:19 AM UTC 24 |
103261678 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1021405953 |
|
|
Sep 11 03:28:17 AM UTC 24 |
Sep 11 03:28:20 AM UTC 24 |
67680119 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.1873135092 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:21 AM UTC 24 |
17694470 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.65378504 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:21 AM UTC 24 |
83472384 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.3945640713 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:21 AM UTC 24 |
17527301 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2094277287 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:22 AM UTC 24 |
672197997 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.2159142323 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:21 AM UTC 24 |
54016089 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3825044493 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:21 AM UTC 24 |
66689401 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1749478788 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:22 AM UTC 24 |
53004030 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.4107028244 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:22 AM UTC 24 |
401066316 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.289368939 |
|
|
Sep 11 03:28:19 AM UTC 24 |
Sep 11 03:28:22 AM UTC 24 |
71411906 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1997057840 |
|
|
Sep 11 03:28:21 AM UTC 24 |
Sep 11 03:28:23 AM UTC 24 |
37276632 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.4247806430 |
|
|
Sep 11 03:28:21 AM UTC 24 |
Sep 11 03:28:23 AM UTC 24 |
16276384 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1626247149 |
|
|
Sep 11 03:28:21 AM UTC 24 |
Sep 11 03:28:23 AM UTC 24 |
20882529 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1778115203 |
|
|
Sep 11 03:28:21 AM UTC 24 |
Sep 11 03:28:23 AM UTC 24 |
22983567 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2907626659 |
|
|
Sep 11 03:28:21 AM UTC 24 |
Sep 11 03:28:23 AM UTC 24 |
42375781 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.3753691287 |
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Sep 11 03:28:22 AM UTC 24 |
Sep 11 03:28:23 AM UTC 24 |
40163495 ps |