Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1318
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1255 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1070695430 Sep 11 03:28:22 AM UTC 24 Sep 11 03:28:24 AM UTC 24 38870317 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.4194043704 Sep 11 03:28:22 AM UTC 24 Sep 11 03:28:24 AM UTC 24 90904063 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3563942092 Sep 11 03:28:21 AM UTC 24 Sep 11 03:28:24 AM UTC 24 53702899 ps
T1256 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3563514162 Sep 11 03:28:21 AM UTC 24 Sep 11 03:28:24 AM UTC 24 69397224 ps
T1257 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3574021449 Sep 11 03:28:21 AM UTC 24 Sep 11 03:28:24 AM UTC 24 131117238 ps
T1258 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.287711433 Sep 11 03:28:21 AM UTC 24 Sep 11 03:28:25 AM UTC 24 526387048 ps
T1259 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.1260560907 Sep 11 03:28:24 AM UTC 24 Sep 11 03:28:26 AM UTC 24 99257528 ps
T1260 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2982191952 Sep 11 03:28:24 AM UTC 24 Sep 11 03:28:26 AM UTC 24 29559267 ps
T1261 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.115653047 Sep 11 03:28:24 AM UTC 24 Sep 11 03:28:26 AM UTC 24 84281430 ps
T1262 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.2225272892 Sep 11 03:28:24 AM UTC 24 Sep 11 03:28:26 AM UTC 24 15897282 ps
T1263 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.789661831 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:27 AM UTC 24 33679672 ps
T1264 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1869283452 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:27 AM UTC 24 17234268 ps
T1265 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1018284373 Sep 11 03:28:24 AM UTC 24 Sep 11 03:28:27 AM UTC 24 100942173 ps
T1266 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.909737136 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:27 AM UTC 24 24847530 ps
T1267 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.1201147960 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:27 AM UTC 24 12789595 ps
T1268 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2422746013 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:27 AM UTC 24 25483445 ps
T1269 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1780616888 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:27 AM UTC 24 20142625 ps
T1270 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.254401580 Sep 11 03:28:24 AM UTC 24 Sep 11 03:28:27 AM UTC 24 163952444 ps
T1271 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.1006216777 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:27 AM UTC 24 123840043 ps
T1272 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.89154338 Sep 11 03:28:24 AM UTC 24 Sep 11 03:28:28 AM UTC 24 33209300 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3780590753 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:28 AM UTC 24 69297182 ps
T1273 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3340040574 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:28 AM UTC 24 142929057 ps
T1274 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.144015405 Sep 11 03:28:25 AM UTC 24 Sep 11 03:28:28 AM UTC 24 33926768 ps
T1275 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2868853805 Sep 11 03:28:27 AM UTC 24 Sep 11 03:28:29 AM UTC 24 57974570 ps
T1276 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.1383691629 Sep 11 03:28:27 AM UTC 24 Sep 11 03:28:29 AM UTC 24 32679096 ps
T1277 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3085462250 Sep 11 03:28:27 AM UTC 24 Sep 11 03:28:29 AM UTC 24 327703762 ps
T1278 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.2406964243 Sep 11 03:28:27 AM UTC 24 Sep 11 03:28:29 AM UTC 24 48162487 ps
T1279 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.398281198 Sep 11 03:28:27 AM UTC 24 Sep 11 03:28:29 AM UTC 24 508696907 ps
T1280 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1658439943 Sep 11 03:28:27 AM UTC 24 Sep 11 03:28:29 AM UTC 24 232369816 ps
T1281 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1222705904 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:32 AM UTC 24 63040402 ps
T1282 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3125319027 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:32 AM UTC 24 56977810 ps
T1283 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.582690416 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 20570348 ps
T1284 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.155485567 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:40 AM UTC 24 15887398 ps
T1285 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.149756417 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 42491278 ps
T1286 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2151825882 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 139130067 ps
T1287 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1893817777 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 25101261 ps
T1288 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.3947312832 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 145494422 ps
T1289 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1111337075 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 16792580 ps
T1290 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2940931253 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 12304598 ps
T1291 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.127636376 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 13059613 ps
T1292 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2509074870 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 64875353 ps
T1293 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1475335888 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 127788033 ps
T1294 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.791812436 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 21328674 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3555574978 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:33 AM UTC 24 60669426 ps
T1295 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.494964349 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:34 AM UTC 24 17236584 ps
T1296 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2511588721 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:34 AM UTC 24 42896490 ps
T1297 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1706881171 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:34 AM UTC 24 41912642 ps
T1298 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.1041771276 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:34 AM UTC 24 59873944 ps
T1299 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.4198873281 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:34 AM UTC 24 15883078 ps
T1300 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.454251675 Sep 11 03:28:32 AM UTC 24 Sep 11 03:28:34 AM UTC 24 13866965 ps
T1301 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.579870351 Sep 11 03:28:32 AM UTC 24 Sep 11 03:28:34 AM UTC 24 45700234 ps
T1302 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.690779417 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:34 AM UTC 24 47466457 ps
T1303 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2974846531 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:34 AM UTC 24 48058611 ps
T1304 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2898031751 Sep 11 03:28:31 AM UTC 24 Sep 11 03:28:34 AM UTC 24 107987716 ps
T1305 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1560389638 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:39 AM UTC 24 23685031 ps
T1306 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.3312329362 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:39 AM UTC 24 42902638 ps
T1307 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.100816584 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:39 AM UTC 24 18467731 ps
T1308 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.677719603 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:39 AM UTC 24 14052532 ps
T1309 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.360667453 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:39 AM UTC 24 22939622 ps
T1310 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3092632957 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:39 AM UTC 24 17586880 ps
T1311 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.3157571715 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:39 AM UTC 24 11933731 ps
T1312 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.154591419 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:39 AM UTC 24 33090995 ps
T1313 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.2752593178 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:39 AM UTC 24 41921955 ps
T1314 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2834742755 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:40 AM UTC 24 33243999 ps
T1315 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2862357901 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:40 AM UTC 24 49336199 ps
T1316 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.920666441 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:40 AM UTC 24 14464455 ps
T1317 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.1539186255 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:40 AM UTC 24 13757170 ps
T1318 /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.2763759555 Sep 11 03:28:37 AM UTC 24 Sep 11 03:28:40 AM UTC 24 22301281 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_loopback.1067029679
Short name T7
Test name
Test status
Simulation time 6887435861 ps
CPU time 7.29 seconds
Started Sep 11 02:55:59 AM UTC 24
Finished Sep 11 02:56:07 AM UTC 24
Peak memory 208300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067029679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1067029679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.2911735312
Short name T19
Test name
Test status
Simulation time 1736612828 ps
CPU time 31.89 seconds
Started Sep 11 02:56:06 AM UTC 24
Finished Sep 11 02:56:39 AM UTC 24
Peak memory 223852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2911735312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_
with_rand_reset.2911735312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_stress_all.821746638
Short name T111
Test name
Test status
Simulation time 350474084257 ps
CPU time 269.99 seconds
Started Sep 11 02:56:00 AM UTC 24
Finished Sep 11 03:00:37 AM UTC 24
Peak memory 220488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821746638 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.821746638
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_stress_all.1162157750
Short name T268
Test name
Test status
Simulation time 291956516942 ps
CPU time 307.55 seconds
Started Sep 11 02:56:06 AM UTC 24
Finished Sep 11 03:01:17 AM UTC 24
Peak memory 217604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162157750 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1162157750
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_tx_rx.2816969887
Short name T17
Test name
Test status
Simulation time 112748136965 ps
CPU time 30.28 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 02:56:29 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816969887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2816969887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_stress_all.1368692866
Short name T120
Test name
Test status
Simulation time 153020075874 ps
CPU time 347.07 seconds
Started Sep 11 02:56:36 AM UTC 24
Finished Sep 11 03:02:27 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368692866 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.1368692866
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_intr.2804810282
Short name T13
Test name
Test status
Simulation time 17334779208 ps
CPU time 19.31 seconds
Started Sep 11 02:56:02 AM UTC 24
Finished Sep 11 02:56:23 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804810282 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2804810282
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_stress_all.2352246946
Short name T123
Test name
Test status
Simulation time 187969543959 ps
CPU time 182.06 seconds
Started Sep 11 02:57:22 AM UTC 24
Finished Sep 11 03:00:27 AM UTC 24
Peak memory 208708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352246946 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2352246946
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.296909277
Short name T30
Test name
Test status
Simulation time 2970004150 ps
CPU time 45.06 seconds
Started Sep 11 02:56:31 AM UTC 24
Finished Sep 11 02:57:17 AM UTC 24
Peak memory 217584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=296909277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_w
ith_rand_reset.296909277
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_fifo_full.3825874130
Short name T253
Test name
Test status
Simulation time 224354504092 ps
CPU time 209.66 seconds
Started Sep 11 02:56:01 AM UTC 24
Finished Sep 11 02:59:37 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825874130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3825874130
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_sec_cm.1169502644
Short name T6
Test name
Test status
Simulation time 88681829 ps
CPU time 1.03 seconds
Started Sep 11 02:56:00 AM UTC 24
Finished Sep 11 02:56:05 AM UTC 24
Peak memory 239508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169502644 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1169502644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_stress_all.813459436
Short name T290
Test name
Test status
Simulation time 1141884316650 ps
CPU time 161.58 seconds
Started Sep 11 03:02:05 AM UTC 24
Finished Sep 11 03:04:49 AM UTC 24
Peak memory 217588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813459436 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.813459436
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_tx_rx.3816913803
Short name T102
Test name
Test status
Simulation time 124397834057 ps
CPU time 62.69 seconds
Started Sep 11 02:56:07 AM UTC 24
Finished Sep 11 02:57:11 AM UTC 24
Peak memory 208500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816913803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3816913803
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.113871231
Short name T339
Test name
Test status
Simulation time 61502025765 ps
CPU time 289.5 seconds
Started Sep 11 02:57:20 AM UTC 24
Finished Sep 11 03:02:14 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113871231 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.113871231
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.1661127755
Short name T110
Test name
Test status
Simulation time 190411165852 ps
CPU time 96.96 seconds
Started Sep 11 02:56:44 AM UTC 24
Finished Sep 11 02:58:23 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661127755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1661127755
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.2028940423
Short name T52
Test name
Test status
Simulation time 25064730 ps
CPU time 0.9 seconds
Started Sep 11 03:28:01 AM UTC 24
Finished Sep 11 03:28:03 AM UTC 24
Peak memory 200576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028940423 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.2028940423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.1739937843
Short name T168
Test name
Test status
Simulation time 245071434855 ps
CPU time 68.18 seconds
Started Sep 11 02:56:24 AM UTC 24
Finished Sep 11 02:57:34 AM UTC 24
Peak memory 208784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739937843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.1739937843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.846510331
Short name T318
Test name
Test status
Simulation time 121085489883 ps
CPU time 286.12 seconds
Started Sep 11 02:56:55 AM UTC 24
Finished Sep 11 03:01:44 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846510331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.846510331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_tx_rx.3407993449
Short name T109
Test name
Test status
Simulation time 99439104071 ps
CPU time 64.68 seconds
Started Sep 11 02:57:09 AM UTC 24
Finished Sep 11 02:58:16 AM UTC 24
Peak memory 208784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407993449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3407993449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_intr.81533557
Short name T272
Test name
Test status
Simulation time 54883285870 ps
CPU time 42.85 seconds
Started Sep 11 02:56:41 AM UTC 24
Finished Sep 11 02:57:26 AM UTC 24
Peak memory 208516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81533557 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.81533557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.3313833939
Short name T91
Test name
Test status
Simulation time 215664925113 ps
CPU time 183.91 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 02:59:04 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313833939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3313833939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.76193385
Short name T259
Test name
Test status
Simulation time 12771656172 ps
CPU time 147.54 seconds
Started Sep 11 02:57:35 AM UTC 24
Finished Sep 11 03:00:06 AM UTC 24
Peak memory 217736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=76193385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_wi
th_rand_reset.76193385
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.2496747258
Short name T71
Test name
Test status
Simulation time 206564127 ps
CPU time 1.63 seconds
Started Sep 11 03:28:03 AM UTC 24
Finished Sep 11 03:28:06 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496747258 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2496747258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_stress_all.1394020518
Short name T327
Test name
Test status
Simulation time 360702409561 ps
CPU time 265.7 seconds
Started Sep 11 03:01:31 AM UTC 24
Finished Sep 11 03:06:01 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394020518 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1394020518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_fifo_full.4174579569
Short name T299
Test name
Test status
Simulation time 38542039157 ps
CPU time 45.94 seconds
Started Sep 11 03:04:34 AM UTC 24
Finished Sep 11 03:05:21 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174579569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4174579569
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.172325477
Short name T20
Test name
Test status
Simulation time 20362885557 ps
CPU time 58.34 seconds
Started Sep 11 02:56:00 AM UTC 24
Finished Sep 11 02:57:03 AM UTC 24
Peak memory 219820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=172325477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_w
ith_rand_reset.172325477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_fifo_reset.1037420152
Short name T94
Test name
Test status
Simulation time 60192562360 ps
CPU time 79.46 seconds
Started Sep 11 03:01:16 AM UTC 24
Finished Sep 11 03:02:37 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037420152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.1037420152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_alert_test.2315328042
Short name T9
Test name
Test status
Simulation time 13066454 ps
CPU time 0.84 seconds
Started Sep 11 02:56:06 AM UTC 24
Finished Sep 11 02:56:08 AM UTC 24
Peak memory 204372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315328042 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.2315328042
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1389694527
Short name T37
Test name
Test status
Simulation time 39573150679 ps
CPU time 30.52 seconds
Started Sep 11 02:56:08 AM UTC 24
Finished Sep 11 02:56:40 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389694527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1389694527
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_intr.2231841740
Short name T93
Test name
Test status
Simulation time 41280439685 ps
CPU time 14.3 seconds
Started Sep 11 02:59:11 AM UTC 24
Finished Sep 11 02:59:26 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231841740 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2231841740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_stress_all.199986610
Short name T193
Test name
Test status
Simulation time 418429092456 ps
CPU time 744.78 seconds
Started Sep 11 02:58:56 AM UTC 24
Finished Sep 11 03:11:30 AM UTC 24
Peak memory 212212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199986610 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.199986610
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.211426004
Short name T12
Test name
Test status
Simulation time 16945081012 ps
CPU time 16.81 seconds
Started Sep 11 02:56:01 AM UTC 24
Finished Sep 11 02:56:22 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211426004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.211426004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_stress_all.3861265763
Short name T283
Test name
Test status
Simulation time 127116306427 ps
CPU time 241.05 seconds
Started Sep 11 02:59:29 AM UTC 24
Finished Sep 11 03:03:34 AM UTC 24
Peak memory 217648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861265763 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3861265763
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_stress_all.1149655218
Short name T122
Test name
Test status
Simulation time 190538806298 ps
CPU time 326.99 seconds
Started Sep 11 02:56:23 AM UTC 24
Finished Sep 11 03:01:54 AM UTC 24
Peak memory 217656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149655218 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1149655218
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1734590085
Short name T48
Test name
Test status
Simulation time 50216200 ps
CPU time 0.93 seconds
Started Sep 11 03:27:51 AM UTC 24
Finished Sep 11 03:27:53 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734590085 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1734590085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_fifo_reset.1195666791
Short name T112
Test name
Test status
Simulation time 52553348470 ps
CPU time 121.55 seconds
Started Sep 11 02:58:32 AM UTC 24
Finished Sep 11 03:00:36 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195666791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1195666791
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_fifo_reset.2738733605
Short name T119
Test name
Test status
Simulation time 149150602145 ps
CPU time 189.5 seconds
Started Sep 11 02:59:07 AM UTC 24
Finished Sep 11 03:02:20 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738733605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2738733605
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_stress_all.2569710815
Short name T165
Test name
Test status
Simulation time 353907846514 ps
CPU time 500.73 seconds
Started Sep 11 03:06:08 AM UTC 24
Finished Sep 11 03:14:35 AM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569710815 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2569710815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.4276417168
Short name T141
Test name
Test status
Simulation time 33068181174 ps
CPU time 71.97 seconds
Started Sep 11 02:57:18 AM UTC 24
Finished Sep 11 02:58:32 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276417168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4276417168
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_fifo_full.5348442
Short name T354
Test name
Test status
Simulation time 219162438079 ps
CPU time 551.57 seconds
Started Sep 11 02:59:04 AM UTC 24
Finished Sep 11 03:08:22 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5348442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.5348442
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.1013087180
Short name T80
Test name
Test status
Simulation time 29404937456 ps
CPU time 47.34 seconds
Started Sep 11 03:02:03 AM UTC 24
Finished Sep 11 03:02:51 AM UTC 24
Peak memory 225328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1013087180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all
_with_rand_reset.1013087180
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_fifo_reset.2878635417
Short name T103
Test name
Test status
Simulation time 9039946646 ps
CPU time 23.59 seconds
Started Sep 11 02:56:40 AM UTC 24
Finished Sep 11 02:57:05 AM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878635417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.2878635417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_fifo_reset.4027615631
Short name T126
Test name
Test status
Simulation time 32321775936 ps
CPU time 83.87 seconds
Started Sep 11 03:04:04 AM UTC 24
Finished Sep 11 03:05:30 AM UTC 24
Peak memory 208784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027615631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.4027615631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.3172334036
Short name T310
Test name
Test status
Simulation time 128751257091 ps
CPU time 231.82 seconds
Started Sep 11 02:56:27 AM UTC 24
Finished Sep 11 03:00:22 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172334036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3172334036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.3780590753
Short name T74
Test name
Test status
Simulation time 69297182 ps
CPU time 1.42 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:28 AM UTC 24
Peak memory 201356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780590753 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3780590753
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_fifo_reset.2208711962
Short name T142
Test name
Test status
Simulation time 112169584779 ps
CPU time 47.33 seconds
Started Sep 11 03:05:17 AM UTC 24
Finished Sep 11 03:06:06 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208711962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2208711962
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_noise_filter.2148751649
Short name T296
Test name
Test status
Simulation time 72079938954 ps
CPU time 87.12 seconds
Started Sep 11 03:00:37 AM UTC 24
Finished Sep 11 03:02:06 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148751649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.2148751649
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_fifo_full.2901456542
Short name T131
Test name
Test status
Simulation time 74350071202 ps
CPU time 153.74 seconds
Started Sep 11 03:01:08 AM UTC 24
Finished Sep 11 03:03:45 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901456542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2901456542
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/168.uart_fifo_reset.714677080
Short name T1075
Test name
Test status
Simulation time 87145114199 ps
CPU time 104.57 seconds
Started Sep 11 03:24:49 AM UTC 24
Finished Sep 11 03:26:36 AM UTC 24
Peak memory 208600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714677080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.714677080
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/168.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_tx_rx.2212823699
Short name T104
Test name
Test status
Simulation time 34586999839 ps
CPU time 40.92 seconds
Started Sep 11 02:56:53 AM UTC 24
Finished Sep 11 02:57:35 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212823699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2212823699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2871121799
Short name T107
Test name
Test status
Simulation time 51584761515 ps
CPU time 145.23 seconds
Started Sep 11 02:56:01 AM UTC 24
Finished Sep 11 02:58:32 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871121799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2871121799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/115.uart_fifo_reset.3494883580
Short name T250
Test name
Test status
Simulation time 103923878903 ps
CPU time 103.52 seconds
Started Sep 11 03:23:26 AM UTC 24
Finished Sep 11 03:25:12 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494883580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3494883580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/115.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/207.uart_fifo_reset.2477975399
Short name T1072
Test name
Test status
Simulation time 168130304761 ps
CPU time 47.71 seconds
Started Sep 11 03:25:39 AM UTC 24
Finished Sep 11 03:26:28 AM UTC 24
Peak memory 208536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477975399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2477975399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/207.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/82.uart_fifo_reset.2961103070
Short name T179
Test name
Test status
Simulation time 118763958652 ps
CPU time 92.3 seconds
Started Sep 11 03:22:05 AM UTC 24
Finished Sep 11 03:23:39 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961103070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2961103070
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/82.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.2531132550
Short name T133
Test name
Test status
Simulation time 18185382921 ps
CPU time 41.21 seconds
Started Sep 11 03:00:17 AM UTC 24
Finished Sep 11 03:01:00 AM UTC 24
Peak memory 208704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531132550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.2531132550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/159.uart_fifo_reset.3404615830
Short name T195
Test name
Test status
Simulation time 64032079161 ps
CPU time 37.45 seconds
Started Sep 11 03:24:36 AM UTC 24
Finished Sep 11 03:25:15 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404615830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.3404615830
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/159.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/191.uart_fifo_reset.128870887
Short name T217
Test name
Test status
Simulation time 62455877135 ps
CPU time 121.83 seconds
Started Sep 11 03:25:22 AM UTC 24
Finished Sep 11 03:27:26 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128870887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.128870887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/191.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/262.uart_fifo_reset.3758106137
Short name T244
Test name
Test status
Simulation time 60205348366 ps
CPU time 113.05 seconds
Started Sep 11 03:27:03 AM UTC 24
Finished Sep 11 03:28:58 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758106137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3758106137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/262.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_stress_all.1819218265
Short name T164
Test name
Test status
Simulation time 222488432727 ps
CPU time 325.74 seconds
Started Sep 11 03:08:24 AM UTC 24
Finished Sep 11 03:13:54 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819218265 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.1819218265
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/90.uart_fifo_reset.3135038388
Short name T198
Test name
Test status
Simulation time 30415995132 ps
CPU time 28.18 seconds
Started Sep 11 03:22:39 AM UTC 24
Finished Sep 11 03:23:09 AM UTC 24
Peak memory 208784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135038388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.3135038388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/90.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_perf.1047738221
Short name T305
Test name
Test status
Simulation time 10798966862 ps
CPU time 125.37 seconds
Started Sep 11 02:59:25 AM UTC 24
Finished Sep 11 03:01:33 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047738221 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1047738221
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/142.uart_fifo_reset.2978880015
Short name T219
Test name
Test status
Simulation time 26887722879 ps
CPU time 47.1 seconds
Started Sep 11 03:24:09 AM UTC 24
Finished Sep 11 03:24:58 AM UTC 24
Peak memory 208804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978880015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2978880015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/142.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_tx_rx.3717713515
Short name T288
Test name
Test status
Simulation time 59164031179 ps
CPU time 56.13 seconds
Started Sep 11 03:01:08 AM UTC 24
Finished Sep 11 03:02:06 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717713515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3717713515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_fifo_reset.3300626836
Short name T121
Test name
Test status
Simulation time 23719260846 ps
CPU time 44.48 seconds
Started Sep 11 03:01:46 AM UTC 24
Finished Sep 11 03:02:32 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300626836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3300626836
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.126456118
Short name T157
Test name
Test status
Simulation time 95467376722 ps
CPU time 52.01 seconds
Started Sep 11 03:03:41 AM UTC 24
Finished Sep 11 03:04:35 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126456118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.126456118
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_stress_all.3335636815
Short name T388
Test name
Test status
Simulation time 218098412759 ps
CPU time 185.2 seconds
Started Sep 11 03:07:25 AM UTC 24
Finished Sep 11 03:10:33 AM UTC 24
Peak memory 217512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335636815 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.3335636815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/282.uart_fifo_reset.1295600972
Short name T1128
Test name
Test status
Simulation time 67160325403 ps
CPU time 19.14 seconds
Started Sep 11 03:27:27 AM UTC 24
Finished Sep 11 03:27:47 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295600972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.1295600972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/282.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_noise_filter.211268752
Short name T88
Test name
Test status
Simulation time 116422301856 ps
CPU time 85.66 seconds
Started Sep 11 02:57:00 AM UTC 24
Finished Sep 11 02:58:27 AM UTC 24
Peak memory 209084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211268752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.211268752
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.3825044493
Short name T100
Test name
Test status
Simulation time 66689401 ps
CPU time 1.41 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:21 AM UTC 24
Peak memory 201740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825044493 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3825044493
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.829793041
Short name T35
Test name
Test status
Simulation time 7650636515 ps
CPU time 36.34 seconds
Started Sep 11 02:58:51 AM UTC 24
Finished Sep 11 02:59:29 AM UTC 24
Peak memory 219956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=829793041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all_
with_rand_reset.829793041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/100.uart_fifo_reset.143931105
Short name T189
Test name
Test status
Simulation time 178181130841 ps
CPU time 68.4 seconds
Started Sep 11 03:23:06 AM UTC 24
Finished Sep 11 03:24:16 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143931105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.143931105
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/100.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/103.uart_fifo_reset.3308003215
Short name T992
Test name
Test status
Simulation time 162335362909 ps
CPU time 33.47 seconds
Started Sep 11 03:23:09 AM UTC 24
Finished Sep 11 03:23:44 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308003215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3308003215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/103.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/114.uart_fifo_reset.2715803682
Short name T202
Test name
Test status
Simulation time 16360135805 ps
CPU time 30.78 seconds
Started Sep 11 03:23:26 AM UTC 24
Finished Sep 11 03:23:58 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715803682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2715803682
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/114.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/122.uart_fifo_reset.1712430147
Short name T209
Test name
Test status
Simulation time 108493086287 ps
CPU time 98.27 seconds
Started Sep 11 03:23:43 AM UTC 24
Finished Sep 11 03:25:23 AM UTC 24
Peak memory 208412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712430147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.1712430147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/122.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_fifo_reset.3998343853
Short name T222
Test name
Test status
Simulation time 31801629931 ps
CPU time 25.44 seconds
Started Sep 11 03:00:07 AM UTC 24
Finished Sep 11 03:00:34 AM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998343853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.3998343853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.3684847364
Short name T78
Test name
Test status
Simulation time 12859363680 ps
CPU time 54.58 seconds
Started Sep 11 03:00:28 AM UTC 24
Finished Sep 11 03:01:24 AM UTC 24
Peak memory 221744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3684847364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all
_with_rand_reset.3684847364
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/140.uart_fifo_reset.953398808
Short name T241
Test name
Test status
Simulation time 21516013658 ps
CPU time 22.85 seconds
Started Sep 11 03:24:07 AM UTC 24
Finished Sep 11 03:24:31 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953398808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.953398808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/140.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/146.uart_fifo_reset.2943622176
Short name T236
Test name
Test status
Simulation time 6126661599 ps
CPU time 23.62 seconds
Started Sep 11 03:24:16 AM UTC 24
Finished Sep 11 03:24:41 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943622176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.2943622176
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/146.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_intr.409412343
Short name T95
Test name
Test status
Simulation time 35462009547 ps
CPU time 29.97 seconds
Started Sep 11 03:01:18 AM UTC 24
Finished Sep 11 03:01:49 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409412343 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.409412343
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/154.uart_fifo_reset.3910196324
Short name T239
Test name
Test status
Simulation time 24370821535 ps
CPU time 55.94 seconds
Started Sep 11 03:24:32 AM UTC 24
Finished Sep 11 03:25:30 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910196324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3910196324
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/154.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/155.uart_fifo_reset.864411741
Short name T245
Test name
Test status
Simulation time 34099580273 ps
CPU time 63.94 seconds
Started Sep 11 03:24:32 AM UTC 24
Finished Sep 11 03:25:38 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864411741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.864411741
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/155.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_fifo_reset.2578067712
Short name T148
Test name
Test status
Simulation time 109344601757 ps
CPU time 26.45 seconds
Started Sep 11 03:02:37 AM UTC 24
Finished Sep 11 03:03:05 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578067712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2578067712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/224.uart_fifo_reset.2910300246
Short name T206
Test name
Test status
Simulation time 109995051284 ps
CPU time 41.96 seconds
Started Sep 11 03:26:01 AM UTC 24
Finished Sep 11 03:26:45 AM UTC 24
Peak memory 208632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910300246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.2910300246
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/224.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/242.uart_fifo_reset.4223784887
Short name T211
Test name
Test status
Simulation time 75712134677 ps
CPU time 21.13 seconds
Started Sep 11 03:26:41 AM UTC 24
Finished Sep 11 03:27:03 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223784887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4223784887
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/242.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/264.uart_fifo_reset.2854662603
Short name T232
Test name
Test status
Simulation time 132982079804 ps
CPU time 139.9 seconds
Started Sep 11 03:27:04 AM UTC 24
Finished Sep 11 03:29:27 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854662603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2854662603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/264.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1822672971
Short name T227
Test name
Test status
Simulation time 19035535479 ps
CPU time 17.48 seconds
Started Sep 11 03:27:17 AM UTC 24
Finished Sep 11 03:27:35 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822672971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1822672971
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/271.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/287.uart_fifo_reset.1447529756
Short name T240
Test name
Test status
Simulation time 111562537551 ps
CPU time 69.95 seconds
Started Sep 11 03:27:30 AM UTC 24
Finished Sep 11 03:28:42 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447529756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1447529756
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/287.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/296.uart_fifo_reset.2755057647
Short name T230
Test name
Test status
Simulation time 98196276733 ps
CPU time 108.9 seconds
Started Sep 11 03:27:43 AM UTC 24
Finished Sep 11 03:29:34 AM UTC 24
Peak memory 208632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755057647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2755057647
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/296.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_fifo_reset.2116598453
Short name T132
Test name
Test status
Simulation time 14955674141 ps
CPU time 36.99 seconds
Started Sep 11 03:10:02 AM UTC 24
Finished Sep 11 03:10:40 AM UTC 24
Peak memory 208892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116598453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2116598453
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/52.uart_fifo_reset.2194945518
Short name T194
Test name
Test status
Simulation time 68609678398 ps
CPU time 25.06 seconds
Started Sep 11 03:19:55 AM UTC 24
Finished Sep 11 03:20:22 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194945518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2194945518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/52.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/75.uart_fifo_reset.1326736047
Short name T249
Test name
Test status
Simulation time 106983283438 ps
CPU time 216.79 seconds
Started Sep 11 03:21:43 AM UTC 24
Finished Sep 11 03:25:23 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326736047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1326736047
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/75.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/76.uart_fifo_reset.1099708740
Short name T228
Test name
Test status
Simulation time 54060233403 ps
CPU time 54.62 seconds
Started Sep 11 03:21:44 AM UTC 24
Finished Sep 11 03:22:40 AM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099708740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1099708740
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/76.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.169223878
Short name T50
Test name
Test status
Simulation time 38108982 ps
CPU time 1.16 seconds
Started Sep 11 03:27:53 AM UTC 24
Finished Sep 11 03:27:55 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169223878 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.169223878
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.2004830552
Short name T1184
Test name
Test status
Simulation time 1463741829 ps
CPU time 3.68 seconds
Started Sep 11 03:27:51 AM UTC 24
Finished Sep 11 03:27:56 AM UTC 24
Peak memory 202688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004830552 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.2004830552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3788194458
Short name T49
Test name
Test status
Simulation time 16854103 ps
CPU time 0.91 seconds
Started Sep 11 03:27:51 AM UTC 24
Finished Sep 11 03:27:53 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788194458 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3788194458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3994919328
Short name T1185
Test name
Test status
Simulation time 21181577 ps
CPU time 1.16 seconds
Started Sep 11 03:27:54 AM UTC 24
Finished Sep 11 03:27:57 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3994919328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_r
eset.3994919328
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.3658486529
Short name T1183
Test name
Test status
Simulation time 12580721 ps
CPU time 0.83 seconds
Started Sep 11 03:27:48 AM UTC 24
Finished Sep 11 03:27:50 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658486529 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3658486529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.3670331861
Short name T58
Test name
Test status
Simulation time 75218287 ps
CPU time 0.95 seconds
Started Sep 11 03:27:53 AM UTC 24
Finished Sep 11 03:27:55 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670331861 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.3670331861
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.4245097550
Short name T1182
Test name
Test status
Simulation time 92496965 ps
CPU time 2.73 seconds
Started Sep 11 03:27:46 AM UTC 24
Finished Sep 11 03:27:50 AM UTC 24
Peak memory 204776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245097550 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.4245097550
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.928394440
Short name T68
Test name
Test status
Simulation time 50422769 ps
CPU time 1.24 seconds
Started Sep 11 03:27:48 AM UTC 24
Finished Sep 11 03:27:50 AM UTC 24
Peak memory 201684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928394440 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.928394440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.1745434365
Short name T51
Test name
Test status
Simulation time 72044882 ps
CPU time 0.96 seconds
Started Sep 11 03:27:58 AM UTC 24
Finished Sep 11 03:28:00 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745434365 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1745434365
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.32969734
Short name T1189
Test name
Test status
Simulation time 704239556 ps
CPU time 1.69 seconds
Started Sep 11 03:27:58 AM UTC 24
Finished Sep 11 03:28:01 AM UTC 24
Peak memory 201876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32969734 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10
/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.32969734
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.3618226430
Short name T1187
Test name
Test status
Simulation time 12413586 ps
CPU time 0.86 seconds
Started Sep 11 03:27:57 AM UTC 24
Finished Sep 11 03:27:59 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618226430 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3618226430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3841951365
Short name T1190
Test name
Test status
Simulation time 70414445 ps
CPU time 1.06 seconds
Started Sep 11 03:27:59 AM UTC 24
Finished Sep 11 03:28:01 AM UTC 24
Peak memory 201196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3841951365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r
eset.3841951365
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3394540380
Short name T59
Test name
Test status
Simulation time 11634551 ps
CPU time 0.87 seconds
Started Sep 11 03:27:57 AM UTC 24
Finished Sep 11 03:27:59 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394540380 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3394540380
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.4013664330
Short name T1186
Test name
Test status
Simulation time 36857357 ps
CPU time 0.81 seconds
Started Sep 11 03:27:56 AM UTC 24
Finished Sep 11 03:27:57 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013664330 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4013664330
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.359398960
Short name T60
Test name
Test status
Simulation time 93855871 ps
CPU time 1.06 seconds
Started Sep 11 03:27:58 AM UTC 24
Finished Sep 11 03:28:00 AM UTC 24
Peak memory 205716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359398960 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.359398960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2843427886
Short name T1188
Test name
Test status
Simulation time 795815855 ps
CPU time 3.56 seconds
Started Sep 11 03:27:55 AM UTC 24
Finished Sep 11 03:27:59 AM UTC 24
Peak memory 202664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843427886 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2843427886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.1907572767
Short name T69
Test name
Test status
Simulation time 96809228 ps
CPU time 2.08 seconds
Started Sep 11 03:27:56 AM UTC 24
Finished Sep 11 03:27:59 AM UTC 24
Peak memory 202744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907572767 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1907572767
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4034373497
Short name T1239
Test name
Test status
Simulation time 103261678 ps
CPU time 1.24 seconds
Started Sep 11 03:28:17 AM UTC 24
Finished Sep 11 03:28:19 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4034373497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_
reset.4034373497
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1683911065
Short name T1235
Test name
Test status
Simulation time 43759620 ps
CPU time 0.82 seconds
Started Sep 11 03:28:17 AM UTC 24
Finished Sep 11 03:28:19 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683911065 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1683911065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.3523563305
Short name T1233
Test name
Test status
Simulation time 19961341 ps
CPU time 0.7 seconds
Started Sep 11 03:28:17 AM UTC 24
Finished Sep 11 03:28:19 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523563305 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3523563305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.3007506085
Short name T1237
Test name
Test status
Simulation time 28727319 ps
CPU time 1.1 seconds
Started Sep 11 03:28:17 AM UTC 24
Finished Sep 11 03:28:19 AM UTC 24
Peak memory 201812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007506085 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.3007506085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.1021405953
Short name T1240
Test name
Test status
Simulation time 67680119 ps
CPU time 1.88 seconds
Started Sep 11 03:28:17 AM UTC 24
Finished Sep 11 03:28:20 AM UTC 24
Peak memory 201112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021405953 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1021405953
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.1452014707
Short name T1238
Test name
Test status
Simulation time 45590434 ps
CPU time 1.39 seconds
Started Sep 11 03:28:17 AM UTC 24
Finished Sep 11 03:28:19 AM UTC 24
Peak memory 201744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452014707 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1452014707
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1749478788
Short name T1246
Test name
Test status
Simulation time 53004030 ps
CPU time 1.51 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:22 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1749478788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_
reset.1749478788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.65378504
Short name T1242
Test name
Test status
Simulation time 83472384 ps
CPU time 0.82 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:21 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65378504 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.65378504
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.1873135092
Short name T1241
Test name
Test status
Simulation time 17694470 ps
CPU time 0.79 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:21 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873135092 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1873135092
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.2159142323
Short name T1245
Test name
Test status
Simulation time 54016089 ps
CPU time 1.03 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:21 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159142323 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.2159142323
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.2094277287
Short name T1244
Test name
Test status
Simulation time 672197997 ps
CPU time 1.95 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:22 AM UTC 24
Peak memory 203620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094277287 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2094277287
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.4107028244
Short name T1247
Test name
Test status
Simulation time 401066316 ps
CPU time 1.85 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:22 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107028244 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4107028244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1626247149
Short name T1251
Test name
Test status
Simulation time 20882529 ps
CPU time 0.95 seconds
Started Sep 11 03:28:21 AM UTC 24
Finished Sep 11 03:28:23 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1626247149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_
reset.1626247149
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.2371999136
Short name T57
Test name
Test status
Simulation time 40695832 ps
CPU time 0.84 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:21 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371999136 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2371999136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.3945640713
Short name T1243
Test name
Test status
Simulation time 17527301 ps
CPU time 0.73 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:21 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945640713 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3945640713
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.4247806430
Short name T1250
Test name
Test status
Simulation time 16276384 ps
CPU time 0.9 seconds
Started Sep 11 03:28:21 AM UTC 24
Finished Sep 11 03:28:23 AM UTC 24
Peak memory 203732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247806430 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.4247806430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.289368939
Short name T1248
Test name
Test status
Simulation time 71411906 ps
CPU time 1.78 seconds
Started Sep 11 03:28:19 AM UTC 24
Finished Sep 11 03:28:22 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289368939 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.289368939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3574021449
Short name T1257
Test name
Test status
Simulation time 131117238 ps
CPU time 1.4 seconds
Started Sep 11 03:28:21 AM UTC 24
Finished Sep 11 03:28:24 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3574021449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_
reset.3574021449
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.2907626659
Short name T1253
Test name
Test status
Simulation time 42375781 ps
CPU time 0.81 seconds
Started Sep 11 03:28:21 AM UTC 24
Finished Sep 11 03:28:23 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907626659 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2907626659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1997057840
Short name T1249
Test name
Test status
Simulation time 37276632 ps
CPU time 0.72 seconds
Started Sep 11 03:28:21 AM UTC 24
Finished Sep 11 03:28:23 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997057840 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1997057840
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.1778115203
Short name T1252
Test name
Test status
Simulation time 22983567 ps
CPU time 0.86 seconds
Started Sep 11 03:28:21 AM UTC 24
Finished Sep 11 03:28:23 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778115203 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.1778115203
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3563514162
Short name T1256
Test name
Test status
Simulation time 69397224 ps
CPU time 1.64 seconds
Started Sep 11 03:28:21 AM UTC 24
Finished Sep 11 03:28:24 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563514162 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3563514162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.3563942092
Short name T73
Test name
Test status
Simulation time 53702899 ps
CPU time 1.37 seconds
Started Sep 11 03:28:21 AM UTC 24
Finished Sep 11 03:28:24 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563942092 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3563942092
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1018284373
Short name T1265
Test name
Test status
Simulation time 100942173 ps
CPU time 1.34 seconds
Started Sep 11 03:28:24 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1018284373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_
reset.1018284373
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1070695430
Short name T1255
Test name
Test status
Simulation time 38870317 ps
CPU time 0.75 seconds
Started Sep 11 03:28:22 AM UTC 24
Finished Sep 11 03:28:24 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070695430 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1070695430
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.3753691287
Short name T1254
Test name
Test status
Simulation time 40163495 ps
CPU time 0.77 seconds
Started Sep 11 03:28:22 AM UTC 24
Finished Sep 11 03:28:23 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753691287 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3753691287
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.115653047
Short name T1261
Test name
Test status
Simulation time 84281430 ps
CPU time 0.89 seconds
Started Sep 11 03:28:24 AM UTC 24
Finished Sep 11 03:28:26 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115653047 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.115653047
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.287711433
Short name T1258
Test name
Test status
Simulation time 526387048 ps
CPU time 2.38 seconds
Started Sep 11 03:28:21 AM UTC 24
Finished Sep 11 03:28:25 AM UTC 24
Peak memory 204732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287711433 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.287711433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.4194043704
Short name T72
Test name
Test status
Simulation time 90904063 ps
CPU time 0.94 seconds
Started Sep 11 03:28:22 AM UTC 24
Finished Sep 11 03:28:24 AM UTC 24
Peak memory 201744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194043704 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4194043704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.789661831
Short name T1263
Test name
Test status
Simulation time 33679672 ps
CPU time 0.95 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=789661831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_r
eset.789661831
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.1260560907
Short name T1259
Test name
Test status
Simulation time 99257528 ps
CPU time 0.61 seconds
Started Sep 11 03:28:24 AM UTC 24
Finished Sep 11 03:28:26 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260560907 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1260560907
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.2225272892
Short name T1262
Test name
Test status
Simulation time 15897282 ps
CPU time 0.77 seconds
Started Sep 11 03:28:24 AM UTC 24
Finished Sep 11 03:28:26 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225272892 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2225272892
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.2982191952
Short name T1260
Test name
Test status
Simulation time 29559267 ps
CPU time 0.68 seconds
Started Sep 11 03:28:24 AM UTC 24
Finished Sep 11 03:28:26 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982191952 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.2982191952
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.89154338
Short name T1272
Test name
Test status
Simulation time 33209300 ps
CPU time 1.98 seconds
Started Sep 11 03:28:24 AM UTC 24
Finished Sep 11 03:28:28 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89154338 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.89154338
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.254401580
Short name T1270
Test name
Test status
Simulation time 163952444 ps
CPU time 1.52 seconds
Started Sep 11 03:28:24 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254401580 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.254401580
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2422746013
Short name T1268
Test name
Test status
Simulation time 25483445 ps
CPU time 0.83 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2422746013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_
reset.2422746013
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.909737136
Short name T1266
Test name
Test status
Simulation time 24847530 ps
CPU time 0.73 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909737136 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.909737136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1869283452
Short name T1264
Test name
Test status
Simulation time 17234268 ps
CPU time 0.71 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869283452 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1869283452
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1780616888
Short name T1269
Test name
Test status
Simulation time 20142625 ps
CPU time 0.97 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780616888 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.1780616888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.1006216777
Short name T1271
Test name
Test status
Simulation time 123840043 ps
CPU time 1.23 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 201500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006216777 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1006216777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3340040574
Short name T1273
Test name
Test status
Simulation time 142929057 ps
CPU time 1.66 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:28 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340040574 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3340040574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3085462250
Short name T1277
Test name
Test status
Simulation time 327703762 ps
CPU time 0.79 seconds
Started Sep 11 03:28:27 AM UTC 24
Finished Sep 11 03:28:29 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3085462250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_
reset.3085462250
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.1383691629
Short name T1276
Test name
Test status
Simulation time 32679096 ps
CPU time 0.72 seconds
Started Sep 11 03:28:27 AM UTC 24
Finished Sep 11 03:28:29 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383691629 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1383691629
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.1201147960
Short name T1267
Test name
Test status
Simulation time 12789595 ps
CPU time 0.75 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201147960 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1201147960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.2868853805
Short name T1275
Test name
Test status
Simulation time 57974570 ps
CPU time 0.67 seconds
Started Sep 11 03:28:27 AM UTC 24
Finished Sep 11 03:28:29 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868853805 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.2868853805
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.144015405
Short name T1274
Test name
Test status
Simulation time 33926768 ps
CPU time 1.95 seconds
Started Sep 11 03:28:25 AM UTC 24
Finished Sep 11 03:28:28 AM UTC 24
Peak memory 201396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144015405 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.144015405
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1222705904
Short name T1281
Test name
Test status
Simulation time 63040402 ps
CPU time 0.65 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:32 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1222705904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_
reset.1222705904
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.3125319027
Short name T1282
Test name
Test status
Simulation time 56977810 ps
CPU time 0.67 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:32 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125319027 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3125319027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.2406964243
Short name T1278
Test name
Test status
Simulation time 48162487 ps
CPU time 0.71 seconds
Started Sep 11 03:28:27 AM UTC 24
Finished Sep 11 03:28:29 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406964243 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2406964243
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.582690416
Short name T1283
Test name
Test status
Simulation time 20570348 ps
CPU time 0.81 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582690416 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.582690416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.1658439943
Short name T1280
Test name
Test status
Simulation time 232369816 ps
CPU time 1.48 seconds
Started Sep 11 03:28:27 AM UTC 24
Finished Sep 11 03:28:29 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658439943 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1658439943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.398281198
Short name T1279
Test name
Test status
Simulation time 508696907 ps
CPU time 1.31 seconds
Started Sep 11 03:28:27 AM UTC 24
Finished Sep 11 03:28:29 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398281198 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.398281198
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2509074870
Short name T1292
Test name
Test status
Simulation time 64875353 ps
CPU time 0.91 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2509074870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_
reset.2509074870
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.149756417
Short name T1285
Test name
Test status
Simulation time 42491278 ps
CPU time 0.71 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149756417 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.149756417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.2151825882
Short name T1286
Test name
Test status
Simulation time 139130067 ps
CPU time 0.76 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151825882 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2151825882
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.1475335888
Short name T1293
Test name
Test status
Simulation time 127788033 ps
CPU time 0.91 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475335888 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.1475335888
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2898031751
Short name T1304
Test name
Test status
Simulation time 107987716 ps
CPU time 2.1 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 202624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898031751 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2898031751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.3555574978
Short name T98
Test name
Test status
Simulation time 60669426 ps
CPU time 1.18 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555574978 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3555574978
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.3048523086
Short name T1193
Test name
Test status
Simulation time 15319112 ps
CPU time 1 seconds
Started Sep 11 03:28:02 AM UTC 24
Finished Sep 11 03:28:04 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048523086 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3048523086
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.4114168962
Short name T1197
Test name
Test status
Simulation time 217048679 ps
CPU time 3.68 seconds
Started Sep 11 03:28:01 AM UTC 24
Finished Sep 11 03:28:05 AM UTC 24
Peak memory 201880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114168962 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.4114168962
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.4007774732
Short name T1194
Test name
Test status
Simulation time 29232353 ps
CPU time 1.02 seconds
Started Sep 11 03:28:02 AM UTC 24
Finished Sep 11 03:28:04 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4007774732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_r
eset.4007774732
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.988065321
Short name T61
Test name
Test status
Simulation time 39929566 ps
CPU time 0.89 seconds
Started Sep 11 03:28:01 AM UTC 24
Finished Sep 11 03:28:03 AM UTC 24
Peak memory 201672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988065321 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.988065321
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.3394916312
Short name T1191
Test name
Test status
Simulation time 15223387 ps
CPU time 0.9 seconds
Started Sep 11 03:27:59 AM UTC 24
Finished Sep 11 03:28:01 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394916312 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3394916312
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.3225598125
Short name T62
Test name
Test status
Simulation time 54622010 ps
CPU time 0.93 seconds
Started Sep 11 03:28:02 AM UTC 24
Finished Sep 11 03:28:04 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225598125 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.3225598125
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.3440899148
Short name T1192
Test name
Test status
Simulation time 34261293 ps
CPU time 2.4 seconds
Started Sep 11 03:27:59 AM UTC 24
Finished Sep 11 03:28:03 AM UTC 24
Peak memory 204732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440899148 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3440899148
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.3265248111
Short name T70
Test name
Test status
Simulation time 96494250 ps
CPU time 1.48 seconds
Started Sep 11 03:27:59 AM UTC 24
Finished Sep 11 03:28:02 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265248111 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3265248111
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1111337075
Short name T1289
Test name
Test status
Simulation time 16792580 ps
CPU time 0.67 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111337075 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1111337075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1893817777
Short name T1287
Test name
Test status
Simulation time 25101261 ps
CPU time 0.61 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893817777 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1893817777
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.3947312832
Short name T1288
Test name
Test status
Simulation time 145494422 ps
CPU time 0.66 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947312832 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.3947312832
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.127636376
Short name T1291
Test name
Test status
Simulation time 13059613 ps
CPU time 0.69 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127636376 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.127636376
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.2940931253
Short name T1290
Test name
Test status
Simulation time 12304598 ps
CPU time 0.58 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940931253 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2940931253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.1041771276
Short name T1298
Test name
Test status
Simulation time 59873944 ps
CPU time 0.76 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041771276 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1041771276
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.2511588721
Short name T1296
Test name
Test status
Simulation time 42896490 ps
CPU time 0.69 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511588721 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2511588721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.1706881171
Short name T1297
Test name
Test status
Simulation time 41912642 ps
CPU time 0.64 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706881171 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1706881171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.494964349
Short name T1295
Test name
Test status
Simulation time 17236584 ps
CPU time 0.79 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494964349 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.494964349
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.791812436
Short name T1294
Test name
Test status
Simulation time 21328674 ps
CPU time 0.64 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:33 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791812436 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.791812436
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.1384545074
Short name T53
Test name
Test status
Simulation time 20903769 ps
CPU time 1 seconds
Started Sep 11 03:28:05 AM UTC 24
Finished Sep 11 03:28:07 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384545074 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1384545074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.925938748
Short name T1200
Test name
Test status
Simulation time 182516550 ps
CPU time 2.16 seconds
Started Sep 11 03:28:05 AM UTC 24
Finished Sep 11 03:28:08 AM UTC 24
Peak memory 206976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925938748 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
0/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.925938748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.3090864110
Short name T1196
Test name
Test status
Simulation time 15896368 ps
CPU time 0.88 seconds
Started Sep 11 03:28:03 AM UTC 24
Finished Sep 11 03:28:05 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090864110 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3090864110
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3727068251
Short name T1199
Test name
Test status
Simulation time 139265693 ps
CPU time 1.2 seconds
Started Sep 11 03:28:05 AM UTC 24
Finished Sep 11 03:28:07 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3727068251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r
eset.3727068251
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.1046978342
Short name T63
Test name
Test status
Simulation time 15209364 ps
CPU time 0.89 seconds
Started Sep 11 03:28:03 AM UTC 24
Finished Sep 11 03:28:05 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046978342 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.1046978342
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.3286935610
Short name T1195
Test name
Test status
Simulation time 47835272 ps
CPU time 0.86 seconds
Started Sep 11 03:28:03 AM UTC 24
Finished Sep 11 03:28:05 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286935610 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3286935610
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.508107413
Short name T64
Test name
Test status
Simulation time 56992692 ps
CPU time 0.95 seconds
Started Sep 11 03:28:05 AM UTC 24
Finished Sep 11 03:28:07 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508107413 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.508107413
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.1053121896
Short name T1198
Test name
Test status
Simulation time 37239350 ps
CPU time 2.6 seconds
Started Sep 11 03:28:02 AM UTC 24
Finished Sep 11 03:28:06 AM UTC 24
Peak memory 202684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053121896 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1053121896
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.690779417
Short name T1302
Test name
Test status
Simulation time 47466457 ps
CPU time 0.77 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690779417 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.690779417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.2974846531
Short name T1303
Test name
Test status
Simulation time 48058611 ps
CPU time 0.75 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974846531 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2974846531
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.4198873281
Short name T1299
Test name
Test status
Simulation time 15883078 ps
CPU time 0.66 seconds
Started Sep 11 03:28:31 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198873281 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4198873281
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.454251675
Short name T1300
Test name
Test status
Simulation time 13866965 ps
CPU time 0.61 seconds
Started Sep 11 03:28:32 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454251675 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.454251675
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.579870351
Short name T1301
Test name
Test status
Simulation time 45700234 ps
CPU time 0.6 seconds
Started Sep 11 03:28:32 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579870351 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.579870351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.360667453
Short name T1309
Test name
Test status
Simulation time 22939622 ps
CPU time 0.66 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360667453 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.360667453
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.100816584
Short name T1307
Test name
Test status
Simulation time 18467731 ps
CPU time 0.61 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100816584 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.100816584
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.677719603
Short name T1308
Test name
Test status
Simulation time 14052532 ps
CPU time 0.62 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677719603 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.677719603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.1539186255
Short name T1317
Test name
Test status
Simulation time 13757170 ps
CPU time 0.76 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:40 AM UTC 24
Peak memory 201396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539186255 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1539186255
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.3092632957
Short name T1310
Test name
Test status
Simulation time 17586880 ps
CPU time 0.54 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092632957 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3092632957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1083446932
Short name T55
Test name
Test status
Simulation time 170904913 ps
CPU time 1.14 seconds
Started Sep 11 03:28:06 AM UTC 24
Finished Sep 11 03:28:09 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083446932 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1083446932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2219605691
Short name T1207
Test name
Test status
Simulation time 265532299 ps
CPU time 3.87 seconds
Started Sep 11 03:28:06 AM UTC 24
Finished Sep 11 03:28:11 AM UTC 24
Peak memory 202688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219605691 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2219605691
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3529852537
Short name T54
Test name
Test status
Simulation time 25039787 ps
CPU time 0.91 seconds
Started Sep 11 03:28:06 AM UTC 24
Finished Sep 11 03:28:08 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529852537 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3529852537
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1884530525
Short name T1205
Test name
Test status
Simulation time 21174436 ps
CPU time 1.45 seconds
Started Sep 11 03:28:08 AM UTC 24
Finished Sep 11 03:28:10 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1884530525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r
eset.1884530525
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.2630165427
Short name T65
Test name
Test status
Simulation time 14375437 ps
CPU time 0.91 seconds
Started Sep 11 03:28:06 AM UTC 24
Finished Sep 11 03:28:08 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630165427 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2630165427
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2353243289
Short name T1201
Test name
Test status
Simulation time 40477905 ps
CPU time 0.87 seconds
Started Sep 11 03:28:06 AM UTC 24
Finished Sep 11 03:28:08 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353243289 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2353243289
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3464779309
Short name T1204
Test name
Test status
Simulation time 18505169 ps
CPU time 0.96 seconds
Started Sep 11 03:28:08 AM UTC 24
Finished Sep 11 03:28:10 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464779309 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.3464779309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3942140781
Short name T1203
Test name
Test status
Simulation time 33735702 ps
CPU time 2.22 seconds
Started Sep 11 03:28:06 AM UTC 24
Finished Sep 11 03:28:09 AM UTC 24
Peak memory 204732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942140781 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3942140781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.2220753310
Short name T1202
Test name
Test status
Simulation time 55070090 ps
CPU time 1.39 seconds
Started Sep 11 03:28:06 AM UTC 24
Finished Sep 11 03:28:09 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220753310 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2220753310
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.3312329362
Short name T1306
Test name
Test status
Simulation time 42902638 ps
CPU time 0.54 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312329362 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3312329362
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.2752593178
Short name T1313
Test name
Test status
Simulation time 41921955 ps
CPU time 0.62 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 201236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752593178 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2752593178
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.3157571715
Short name T1311
Test name
Test status
Simulation time 11933731 ps
CPU time 0.7 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157571715 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3157571715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.1560389638
Short name T1305
Test name
Test status
Simulation time 23685031 ps
CPU time 0.58 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560389638 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1560389638
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.920666441
Short name T1316
Test name
Test status
Simulation time 14464455 ps
CPU time 0.76 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:40 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920666441 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.920666441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.2763759555
Short name T1318
Test name
Test status
Simulation time 22301281 ps
CPU time 0.68 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:40 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763759555 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2763759555
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2834742755
Short name T1314
Test name
Test status
Simulation time 33243999 ps
CPU time 0.62 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:40 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834742755 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2834742755
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.154591419
Short name T1312
Test name
Test status
Simulation time 33090995 ps
CPU time 0.68 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154591419 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.154591419
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.2862357901
Short name T1315
Test name
Test status
Simulation time 49336199 ps
CPU time 0.72 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:40 AM UTC 24
Peak memory 201644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862357901 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2862357901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.155485567
Short name T1284
Test name
Test status
Simulation time 15887398 ps
CPU time 0.85 seconds
Started Sep 11 03:28:37 AM UTC 24
Finished Sep 11 03:28:40 AM UTC 24
Peak memory 201616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155485567 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.155485567
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2179521386
Short name T1213
Test name
Test status
Simulation time 121838179 ps
CPU time 1.21 seconds
Started Sep 11 03:28:10 AM UTC 24
Finished Sep 11 03:28:12 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2179521386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r
eset.2179521386
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.2171210976
Short name T1208
Test name
Test status
Simulation time 14779849 ps
CPU time 0.89 seconds
Started Sep 11 03:28:09 AM UTC 24
Finished Sep 11 03:28:11 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171210976 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2171210976
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.2828350785
Short name T1210
Test name
Test status
Simulation time 16708410 ps
CPU time 0.89 seconds
Started Sep 11 03:28:09 AM UTC 24
Finished Sep 11 03:28:11 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828350785 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.2828350785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.1123282096
Short name T1212
Test name
Test status
Simulation time 210842630 ps
CPU time 1.17 seconds
Started Sep 11 03:28:09 AM UTC 24
Finished Sep 11 03:28:12 AM UTC 24
Peak memory 201684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123282096 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.1123282096
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.405566773
Short name T1211
Test name
Test status
Simulation time 182766921 ps
CPU time 2.69 seconds
Started Sep 11 03:28:08 AM UTC 24
Finished Sep 11 03:28:12 AM UTC 24
Peak memory 202676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405566773 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.405566773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.1435116714
Short name T1206
Test name
Test status
Simulation time 46061474 ps
CPU time 1.45 seconds
Started Sep 11 03:28:08 AM UTC 24
Finished Sep 11 03:28:10 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435116714 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1435116714
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3681726543
Short name T1217
Test name
Test status
Simulation time 17790096 ps
CPU time 0.99 seconds
Started Sep 11 03:28:11 AM UTC 24
Finished Sep 11 03:28:13 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3681726543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r
eset.3681726543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.2945755653
Short name T56
Test name
Test status
Simulation time 18111957 ps
CPU time 0.91 seconds
Started Sep 11 03:28:11 AM UTC 24
Finished Sep 11 03:28:13 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945755653 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2945755653
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.2570863784
Short name T1215
Test name
Test status
Simulation time 14718857 ps
CPU time 0.88 seconds
Started Sep 11 03:28:11 AM UTC 24
Finished Sep 11 03:28:13 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570863784 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2570863784
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.4133243738
Short name T1216
Test name
Test status
Simulation time 236820921 ps
CPU time 1.03 seconds
Started Sep 11 03:28:11 AM UTC 24
Finished Sep 11 03:28:13 AM UTC 24
Peak memory 201812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133243738 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.4133243738
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3848647139
Short name T1218
Test name
Test status
Simulation time 316177167 ps
CPU time 2.56 seconds
Started Sep 11 03:28:10 AM UTC 24
Finished Sep 11 03:28:13 AM UTC 24
Peak memory 202812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848647139 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3848647139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.1247631309
Short name T1214
Test name
Test status
Simulation time 74125235 ps
CPU time 1.94 seconds
Started Sep 11 03:28:10 AM UTC 24
Finished Sep 11 03:28:13 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247631309 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1247631309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3077044170
Short name T1223
Test name
Test status
Simulation time 90491992 ps
CPU time 1.1 seconds
Started Sep 11 03:28:13 AM UTC 24
Finished Sep 11 03:28:15 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3077044170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r
eset.3077044170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.1286636318
Short name T1222
Test name
Test status
Simulation time 41132560 ps
CPU time 0.92 seconds
Started Sep 11 03:28:13 AM UTC 24
Finished Sep 11 03:28:15 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286636318 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1286636318
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.3934173077
Short name T1220
Test name
Test status
Simulation time 21549380 ps
CPU time 0.84 seconds
Started Sep 11 03:28:13 AM UTC 24
Finished Sep 11 03:28:14 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934173077 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.3934173077
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.3824203925
Short name T1221
Test name
Test status
Simulation time 135183773 ps
CPU time 0.85 seconds
Started Sep 11 03:28:13 AM UTC 24
Finished Sep 11 03:28:15 AM UTC 24
Peak memory 203668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824203925 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.3824203925
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.608539728
Short name T1219
Test name
Test status
Simulation time 32453221 ps
CPU time 1.8 seconds
Started Sep 11 03:28:11 AM UTC 24
Finished Sep 11 03:28:14 AM UTC 24
Peak memory 201632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608539728 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.608539728
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.3641040797
Short name T1225
Test name
Test status
Simulation time 403337010 ps
CPU time 1.98 seconds
Started Sep 11 03:28:13 AM UTC 24
Finished Sep 11 03:28:16 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641040797 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3641040797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1713113786
Short name T1229
Test name
Test status
Simulation time 42086290 ps
CPU time 0.97 seconds
Started Sep 11 03:28:15 AM UTC 24
Finished Sep 11 03:28:17 AM UTC 24
Peak memory 201688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1713113786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r
eset.1713113786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.1408190181
Short name T1227
Test name
Test status
Simulation time 15167380 ps
CPU time 0.89 seconds
Started Sep 11 03:28:15 AM UTC 24
Finished Sep 11 03:28:17 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408190181 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1408190181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1136414050
Short name T1226
Test name
Test status
Simulation time 17005741 ps
CPU time 0.85 seconds
Started Sep 11 03:28:15 AM UTC 24
Finished Sep 11 03:28:17 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136414050 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1136414050
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.485487921
Short name T1228
Test name
Test status
Simulation time 77255268 ps
CPU time 1 seconds
Started Sep 11 03:28:15 AM UTC 24
Finished Sep 11 03:28:17 AM UTC 24
Peak memory 201684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485487921 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.485487921
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1235025187
Short name T1224
Test name
Test status
Simulation time 77265234 ps
CPU time 1.56 seconds
Started Sep 11 03:28:13 AM UTC 24
Finished Sep 11 03:28:15 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235025187 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1235025187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.3215212188
Short name T99
Test name
Test status
Simulation time 84328172 ps
CPU time 1.67 seconds
Started Sep 11 03:28:15 AM UTC 24
Finished Sep 11 03:28:17 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215212188 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3215212188
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.267208044
Short name T1236
Test name
Test status
Simulation time 56215081 ps
CPU time 1.11 seconds
Started Sep 11 03:28:17 AM UTC 24
Finished Sep 11 03:28:19 AM UTC 24
Peak memory 201624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=267208044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_re
set.267208044
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.4111149440
Short name T1232
Test name
Test status
Simulation time 40172662 ps
CPU time 0.9 seconds
Started Sep 11 03:28:17 AM UTC 24
Finished Sep 11 03:28:19 AM UTC 24
Peak memory 201748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111149440 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4111149440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.2067539685
Short name T1230
Test name
Test status
Simulation time 26752520 ps
CPU time 0.82 seconds
Started Sep 11 03:28:15 AM UTC 24
Finished Sep 11 03:28:17 AM UTC 24
Peak memory 201680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067539685 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.2067539685
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.2700813152
Short name T1234
Test name
Test status
Simulation time 96998189 ps
CPU time 0.86 seconds
Started Sep 11 03:28:17 AM UTC 24
Finished Sep 11 03:28:19 AM UTC 24
Peak memory 201620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700813152 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.2700813152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.1793951853
Short name T1209
Test name
Test status
Simulation time 186120547 ps
CPU time 1.62 seconds
Started Sep 11 03:28:15 AM UTC 24
Finished Sep 11 03:28:17 AM UTC 24
Peak memory 203724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793951853 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1793951853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.2904826440
Short name T1231
Test name
Test status
Simulation time 70700548 ps
CPU time 1.24 seconds
Started Sep 11 03:28:15 AM UTC 24
Finished Sep 11 03:28:17 AM UTC 24
Peak memory 201660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904826440 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2904826440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_alert_test.2419037248
Short name T4
Test name
Test status
Simulation time 16673385 ps
CPU time 0.7 seconds
Started Sep 11 02:56:00 AM UTC 24
Finished Sep 11 02:56:05 AM UTC 24
Peak memory 202388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419037248 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2419037248
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_fifo_full.2841862343
Short name T278
Test name
Test status
Simulation time 237494782211 ps
CPU time 110.03 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 02:57:51 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841862343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2841862343
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.1182719045
Short name T105
Test name
Test status
Simulation time 35842890289 ps
CPU time 62.67 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 02:57:02 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182719045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1182719045
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2580827199
Short name T314
Test name
Test status
Simulation time 46638075671 ps
CPU time 249.08 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 03:00:10 AM UTC 24
Peak memory 212220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580827199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2580827199
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_intr.424975029
Short name T89
Test name
Test status
Simulation time 75244665619 ps
CPU time 176.91 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 02:58:57 AM UTC 24
Peak memory 208624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424975029 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.424975029
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.3309698400
Short name T303
Test name
Test status
Simulation time 63191056555 ps
CPU time 397.91 seconds
Started Sep 11 02:55:59 AM UTC 24
Finished Sep 11 03:02:42 AM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309698400 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.3309698400
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_noise_filter.2013047515
Short name T279
Test name
Test status
Simulation time 52307871819 ps
CPU time 107.75 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 02:57:47 AM UTC 24
Peak memory 217576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013047515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2013047515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_perf.1661080796
Short name T42
Test name
Test status
Simulation time 2740262457 ps
CPU time 47.01 seconds
Started Sep 11 02:55:59 AM UTC 24
Finished Sep 11 02:56:47 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661080796 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1661080796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_rx_oversample.1559954236
Short name T3
Test name
Test status
Simulation time 2352461140 ps
CPU time 4.2 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 02:56:02 AM UTC 24
Peak memory 207404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559954236 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.1559954236
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.2015846310
Short name T1
Test name
Test status
Simulation time 2739869853 ps
CPU time 1.83 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 02:56:00 AM UTC 24
Peak memory 204504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015846310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2015846310
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_smoke.2334982187
Short name T5
Test name
Test status
Simulation time 103656962 ps
CPU time 1.35 seconds
Started Sep 11 02:55:56 AM UTC 24
Finished Sep 11 02:56:05 AM UTC 24
Peak memory 206480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334982187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2334982187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.4193545833
Short name T2
Test name
Test status
Simulation time 2522234564 ps
CPU time 2.16 seconds
Started Sep 11 02:55:57 AM UTC 24
Finished Sep 11 02:56:01 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193545833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.4193545833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.345250001
Short name T800
Test name
Test status
Simulation time 138092687414 ps
CPU time 1285.39 seconds
Started Sep 11 02:56:04 AM UTC 24
Finished Sep 11 03:17:44 AM UTC 24
Peak memory 212368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345250001 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.345250001
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_loopback.3490769322
Short name T24
Test name
Test status
Simulation time 5974170212 ps
CPU time 20.1 seconds
Started Sep 11 02:56:03 AM UTC 24
Finished Sep 11 02:56:25 AM UTC 24
Peak memory 208704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490769322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.3490769322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_noise_filter.1591849509
Short name T21
Test name
Test status
Simulation time 53691826064 ps
CPU time 22.67 seconds
Started Sep 11 02:56:02 AM UTC 24
Finished Sep 11 02:56:26 AM UTC 24
Peak memory 217520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591849509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1591849509
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_perf.3039523516
Short name T366
Test name
Test status
Simulation time 4218385768 ps
CPU time 314.98 seconds
Started Sep 11 02:56:03 AM UTC 24
Finished Sep 11 03:01:23 AM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039523516 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.3039523516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_rx_oversample.3901401240
Short name T22
Test name
Test status
Simulation time 3696120702 ps
CPU time 30.88 seconds
Started Sep 11 02:56:02 AM UTC 24
Finished Sep 11 02:56:35 AM UTC 24
Peak memory 207276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901401240 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3901401240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.2403240609
Short name T11
Test name
Test status
Simulation time 139888122179 ps
CPU time 17.98 seconds
Started Sep 11 02:56:02 AM UTC 24
Finished Sep 11 02:56:22 AM UTC 24
Peak memory 208656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403240609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2403240609
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.2316014675
Short name T15
Test name
Test status
Simulation time 3884002147 ps
CPU time 8.31 seconds
Started Sep 11 02:56:02 AM UTC 24
Finished Sep 11 02:56:12 AM UTC 24
Peak memory 207140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316014675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2316014675
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_sec_cm.720651374
Short name T10
Test name
Test status
Simulation time 60780337 ps
CPU time 1.05 seconds
Started Sep 11 02:56:06 AM UTC 24
Finished Sep 11 02:56:08 AM UTC 24
Peak memory 238464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720651374 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.720651374
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_smoke.3606197345
Short name T8
Test name
Test status
Simulation time 549851642 ps
CPU time 3.31 seconds
Started Sep 11 02:56:00 AM UTC 24
Finished Sep 11 02:56:08 AM UTC 24
Peak memory 207664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606197345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3606197345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.4018875206
Short name T39
Test name
Test status
Simulation time 12725595159 ps
CPU time 36.17 seconds
Started Sep 11 02:56:03 AM UTC 24
Finished Sep 11 02:56:41 AM UTC 24
Peak memory 208164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018875206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.4018875206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/1.uart_tx_rx.1219223793
Short name T47
Test name
Test status
Simulation time 50642109557 ps
CPU time 54.23 seconds
Started Sep 11 02:56:01 AM UTC 24
Finished Sep 11 02:57:00 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219223793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1219223793
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/1.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_alert_test.3233917420
Short name T423
Test name
Test status
Simulation time 32090590 ps
CPU time 0.85 seconds
Started Sep 11 02:58:58 AM UTC 24
Finished Sep 11 02:59:00 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233917420 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3233917420
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_fifo_full.2572856943
Short name T152
Test name
Test status
Simulation time 27784099066 ps
CPU time 73.65 seconds
Started Sep 11 02:58:30 AM UTC 24
Finished Sep 11 02:59:45 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572856943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2572856943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.356508274
Short name T520
Test name
Test status
Simulation time 125408067884 ps
CPU time 453.05 seconds
Started Sep 11 02:58:32 AM UTC 24
Finished Sep 11 03:06:11 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356508274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.356508274
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_intr.592795894
Short name T372
Test name
Test status
Simulation time 15703864216 ps
CPU time 7.47 seconds
Started Sep 11 02:58:33 AM UTC 24
Finished Sep 11 02:58:42 AM UTC 24
Peak memory 207132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592795894 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.592795894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.4070348345
Short name T721
Test name
Test status
Simulation time 148999863777 ps
CPU time 964.82 seconds
Started Sep 11 02:58:49 AM UTC 24
Finished Sep 11 03:15:05 AM UTC 24
Peak memory 212244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070348345 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.4070348345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_loopback.3614857944
Short name T422
Test name
Test status
Simulation time 1651285412 ps
CPU time 7.55 seconds
Started Sep 11 02:58:47 AM UTC 24
Finished Sep 11 02:58:55 AM UTC 24
Peak memory 207156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614857944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3614857944
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_noise_filter.2411960261
Short name T276
Test name
Test status
Simulation time 112856067693 ps
CPU time 70.76 seconds
Started Sep 11 02:58:33 AM UTC 24
Finished Sep 11 02:59:46 AM UTC 24
Peak memory 208816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411960261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2411960261
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_perf.4063849241
Short name T499
Test name
Test status
Simulation time 6752966477 ps
CPU time 376.32 seconds
Started Sep 11 02:58:49 AM UTC 24
Finished Sep 11 03:05:10 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063849241 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4063849241
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_rx_oversample.2364513479
Short name T424
Test name
Test status
Simulation time 6359489949 ps
CPU time 36.03 seconds
Started Sep 11 02:58:33 AM UTC 24
Finished Sep 11 02:59:11 AM UTC 24
Peak memory 208448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364513479 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2364513479
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.1589471779
Short name T124
Test name
Test status
Simulation time 95982169797 ps
CPU time 206.61 seconds
Started Sep 11 02:58:43 AM UTC 24
Finished Sep 11 03:02:12 AM UTC 24
Peak memory 208728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589471779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1589471779
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.3404365616
Short name T306
Test name
Test status
Simulation time 1584138042 ps
CPU time 5.32 seconds
Started Sep 11 02:58:35 AM UTC 24
Finished Sep 11 02:58:42 AM UTC 24
Peak memory 205216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404365616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3404365616
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_smoke.2872385690
Short name T302
Test name
Test status
Simulation time 427474029 ps
CPU time 3.48 seconds
Started Sep 11 02:58:28 AM UTC 24
Finished Sep 11 02:58:33 AM UTC 24
Peak memory 207288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872385690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2872385690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.1032248690
Short name T361
Test name
Test status
Simulation time 1824944831 ps
CPU time 1.88 seconds
Started Sep 11 02:58:43 AM UTC 24
Finished Sep 11 02:58:45 AM UTC 24
Peak memory 206372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032248690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1032248690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/10.uart_tx_rx.1882659120
Short name T293
Test name
Test status
Simulation time 38167226532 ps
CPU time 20.35 seconds
Started Sep 11 02:58:28 AM UTC 24
Finished Sep 11 02:58:50 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882659120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1882659120
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/10.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/101.uart_fifo_reset.685819475
Short name T199
Test name
Test status
Simulation time 69135294237 ps
CPU time 30.78 seconds
Started Sep 11 03:23:07 AM UTC 24
Finished Sep 11 03:23:39 AM UTC 24
Peak memory 208808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685819475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.685819475
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/101.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/102.uart_fifo_reset.1585026721
Short name T993
Test name
Test status
Simulation time 25275918583 ps
CPU time 35.11 seconds
Started Sep 11 03:23:08 AM UTC 24
Finished Sep 11 03:23:45 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585026721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1585026721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/102.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/104.uart_fifo_reset.1946105978
Short name T996
Test name
Test status
Simulation time 87694113953 ps
CPU time 37.95 seconds
Started Sep 11 03:23:10 AM UTC 24
Finished Sep 11 03:23:50 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946105978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1946105978
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/104.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/105.uart_fifo_reset.3517673175
Short name T218
Test name
Test status
Simulation time 185449403138 ps
CPU time 69.06 seconds
Started Sep 11 03:23:12 AM UTC 24
Finished Sep 11 03:24:23 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517673175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3517673175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/105.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/106.uart_fifo_reset.1160364151
Short name T987
Test name
Test status
Simulation time 27121701255 ps
CPU time 21.35 seconds
Started Sep 11 03:23:12 AM UTC 24
Finished Sep 11 03:23:35 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160364151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1160364151
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/106.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/107.uart_fifo_reset.1559873760
Short name T225
Test name
Test status
Simulation time 84739778570 ps
CPU time 95.95 seconds
Started Sep 11 03:23:13 AM UTC 24
Finished Sep 11 03:24:51 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559873760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.1559873760
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/107.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/108.uart_fifo_reset.2433168989
Short name T226
Test name
Test status
Simulation time 97750953245 ps
CPU time 98.63 seconds
Started Sep 11 03:23:13 AM UTC 24
Finished Sep 11 03:24:54 AM UTC 24
Peak memory 208816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433168989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2433168989
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/108.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/109.uart_fifo_reset.1864528085
Short name T1009
Test name
Test status
Simulation time 86752781941 ps
CPU time 55.22 seconds
Started Sep 11 03:23:17 AM UTC 24
Finished Sep 11 03:24:13 AM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864528085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1864528085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/109.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_alert_test.701415951
Short name T425
Test name
Test status
Simulation time 91575772 ps
CPU time 0.84 seconds
Started Sep 11 02:59:33 AM UTC 24
Finished Sep 11 02:59:35 AM UTC 24
Peak memory 202384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701415951 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.701415951
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.4294447924
Short name T155
Test name
Test status
Simulation time 144080055646 ps
CPU time 371.44 seconds
Started Sep 11 02:59:05 AM UTC 24
Finished Sep 11 03:05:21 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294447924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.4294447924
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.3923311864
Short name T341
Test name
Test status
Simulation time 102451835489 ps
CPU time 221.3 seconds
Started Sep 11 02:59:27 AM UTC 24
Finished Sep 11 03:03:12 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923311864 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3923311864
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_loopback.2495116369
Short name T427
Test name
Test status
Simulation time 6681776366 ps
CPU time 16.37 seconds
Started Sep 11 02:59:22 AM UTC 24
Finished Sep 11 02:59:40 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495116369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2495116369
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_noise_filter.3265282957
Short name T286
Test name
Test status
Simulation time 216822998874 ps
CPU time 122.28 seconds
Started Sep 11 02:59:12 AM UTC 24
Finished Sep 11 03:01:16 AM UTC 24
Peak memory 208964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265282957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3265282957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_rx_oversample.4139399770
Short name T426
Test name
Test status
Simulation time 4424969548 ps
CPU time 25.82 seconds
Started Sep 11 02:59:09 AM UTC 24
Finished Sep 11 02:59:36 AM UTC 24
Peak memory 207980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139399770 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.4139399770
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.3218060162
Short name T113
Test name
Test status
Simulation time 146946138306 ps
CPU time 98.52 seconds
Started Sep 11 02:59:16 AM UTC 24
Finished Sep 11 03:00:56 AM UTC 24
Peak memory 208976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218060162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3218060162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.622889523
Short name T336
Test name
Test status
Simulation time 39787783729 ps
CPU time 28.64 seconds
Started Sep 11 02:59:14 AM UTC 24
Finished Sep 11 02:59:44 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622889523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.622889523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_smoke.135992240
Short name T301
Test name
Test status
Simulation time 471202021 ps
CPU time 2.29 seconds
Started Sep 11 02:59:00 AM UTC 24
Finished Sep 11 02:59:04 AM UTC 24
Peak memory 207744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135992240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.uart_smoke.135992240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.1264321618
Short name T352
Test name
Test status
Simulation time 4597426860 ps
CPU time 73.64 seconds
Started Sep 11 02:59:29 AM UTC 24
Finished Sep 11 03:00:45 AM UTC 24
Peak memory 217584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1264321618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all
_with_rand_reset.1264321618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.46336157
Short name T346
Test name
Test status
Simulation time 6286280468 ps
CPU time 28.65 seconds
Started Sep 11 02:59:19 AM UTC 24
Finished Sep 11 02:59:49 AM UTC 24
Peak memory 208328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46336157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.46336157
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/11.uart_tx_rx.806893129
Short name T266
Test name
Test status
Simulation time 48822812321 ps
CPU time 74.61 seconds
Started Sep 11 02:59:00 AM UTC 24
Finished Sep 11 03:00:17 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806893129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.806893129
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/11.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/110.uart_fifo_reset.1166379802
Short name T998
Test name
Test status
Simulation time 51666425084 ps
CPU time 31.65 seconds
Started Sep 11 03:23:18 AM UTC 24
Finished Sep 11 03:23:51 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166379802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1166379802
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/110.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/111.uart_fifo_reset.1953668242
Short name T216
Test name
Test status
Simulation time 56194324229 ps
CPU time 101.7 seconds
Started Sep 11 03:23:20 AM UTC 24
Finished Sep 11 03:25:04 AM UTC 24
Peak memory 208948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953668242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1953668242
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/111.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/112.uart_fifo_reset.276627574
Short name T1055
Test name
Test status
Simulation time 29086011274 ps
CPU time 140.83 seconds
Started Sep 11 03:23:22 AM UTC 24
Finished Sep 11 03:25:45 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276627574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.276627574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/112.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/113.uart_fifo_reset.2110774720
Short name T1056
Test name
Test status
Simulation time 52795954473 ps
CPU time 138.86 seconds
Started Sep 11 03:23:24 AM UTC 24
Finished Sep 11 03:25:45 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110774720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.2110774720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/113.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/116.uart_fifo_reset.1744092016
Short name T1023
Test name
Test status
Simulation time 51353698958 ps
CPU time 72.49 seconds
Started Sep 11 03:23:33 AM UTC 24
Finished Sep 11 03:24:48 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744092016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1744092016
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/116.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/117.uart_fifo_reset.2953990523
Short name T1014
Test name
Test status
Simulation time 47358916451 ps
CPU time 51.69 seconds
Started Sep 11 03:23:35 AM UTC 24
Finished Sep 11 03:24:28 AM UTC 24
Peak memory 208624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953990523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2953990523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/117.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/118.uart_fifo_reset.85559031
Short name T916
Test name
Test status
Simulation time 99938364320 ps
CPU time 61.73 seconds
Started Sep 11 03:23:39 AM UTC 24
Finished Sep 11 03:24:43 AM UTC 24
Peak memory 208628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85559031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.85559031
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/118.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/119.uart_fifo_reset.387117325
Short name T146
Test name
Test status
Simulation time 178023243297 ps
CPU time 99.25 seconds
Started Sep 11 03:23:40 AM UTC 24
Finished Sep 11 03:25:22 AM UTC 24
Peak memory 208632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387117325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.387117325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/119.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_alert_test.4233880319
Short name T428
Test name
Test status
Simulation time 31577261 ps
CPU time 0.82 seconds
Started Sep 11 02:59:54 AM UTC 24
Finished Sep 11 02:59:55 AM UTC 24
Peak memory 204432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233880319 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4233880319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_fifo_full.2265540660
Short name T263
Test name
Test status
Simulation time 38736049568 ps
CPU time 30.31 seconds
Started Sep 11 02:59:37 AM UTC 24
Finished Sep 11 03:00:08 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265540660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2265540660
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.3250743930
Short name T92
Test name
Test status
Simulation time 34322761725 ps
CPU time 8.9 seconds
Started Sep 11 02:59:37 AM UTC 24
Finished Sep 11 02:59:47 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250743930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3250743930
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_fifo_reset.3314568567
Short name T184
Test name
Test status
Simulation time 112245438341 ps
CPU time 274.62 seconds
Started Sep 11 02:59:38 AM UTC 24
Finished Sep 11 03:04:16 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314568567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.3314568567
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_intr.1098035188
Short name T373
Test name
Test status
Simulation time 46784526260 ps
CPU time 116.53 seconds
Started Sep 11 02:59:41 AM UTC 24
Finished Sep 11 03:01:40 AM UTC 24
Peak memory 208508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098035188 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1098035188
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.344034562
Short name T516
Test name
Test status
Simulation time 213565996295 ps
CPU time 371.78 seconds
Started Sep 11 02:59:49 AM UTC 24
Finished Sep 11 03:06:06 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344034562 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.344034562
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_loopback.671198096
Short name T429
Test name
Test status
Simulation time 5370464802 ps
CPU time 8.1 seconds
Started Sep 11 02:59:47 AM UTC 24
Finished Sep 11 02:59:56 AM UTC 24
Peak memory 207356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671198096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.uart_loopback.671198096
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_noise_filter.981326138
Short name T294
Test name
Test status
Simulation time 162463523532 ps
CPU time 165.02 seconds
Started Sep 11 02:59:43 AM UTC 24
Finished Sep 11 03:02:30 AM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981326138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.981326138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_perf.1819863147
Short name T364
Test name
Test status
Simulation time 19617092411 ps
CPU time 268.04 seconds
Started Sep 11 02:59:48 AM UTC 24
Finished Sep 11 03:04:20 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819863147 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1819863147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_rx_oversample.1195318359
Short name T433
Test name
Test status
Simulation time 7202452960 ps
CPU time 43.76 seconds
Started Sep 11 02:59:39 AM UTC 24
Finished Sep 11 03:00:24 AM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195318359 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1195318359
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.1901531618
Short name T118
Test name
Test status
Simulation time 28388102223 ps
CPU time 98.59 seconds
Started Sep 11 02:59:46 AM UTC 24
Finished Sep 11 03:01:27 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901531618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1901531618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.2490223202
Short name T292
Test name
Test status
Simulation time 3026888392 ps
CPU time 6.99 seconds
Started Sep 11 02:59:45 AM UTC 24
Finished Sep 11 02:59:53 AM UTC 24
Peak memory 207264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490223202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2490223202
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_smoke.784669663
Short name T330
Test name
Test status
Simulation time 279598924 ps
CPU time 1.75 seconds
Started Sep 11 02:59:35 AM UTC 24
Finished Sep 11 02:59:38 AM UTC 24
Peak memory 207132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784669663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.uart_smoke.784669663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_stress_all.149377143
Short name T643
Test name
Test status
Simulation time 30379002630 ps
CPU time 691.48 seconds
Started Sep 11 02:59:51 AM UTC 24
Finished Sep 11 03:11:31 AM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149377143 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.149377143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.2513177679
Short name T362
Test name
Test status
Simulation time 2444482321 ps
CPU time 45.57 seconds
Started Sep 11 02:59:51 AM UTC 24
Finished Sep 11 03:00:38 AM UTC 24
Peak memory 217708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2513177679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all
_with_rand_reset.2513177679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.2466354615
Short name T358
Test name
Test status
Simulation time 962743051 ps
CPU time 2.34 seconds
Started Sep 11 02:59:47 AM UTC 24
Finished Sep 11 02:59:50 AM UTC 24
Peak memory 207876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466354615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.2466354615
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/12.uart_tx_rx.1835853089
Short name T317
Test name
Test status
Simulation time 4814111721 ps
CPU time 9.27 seconds
Started Sep 11 02:59:37 AM UTC 24
Finished Sep 11 02:59:47 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835853089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1835853089
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/12.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/120.uart_fifo_reset.2437140401
Short name T1162
Test name
Test status
Simulation time 192025492667 ps
CPU time 315.8 seconds
Started Sep 11 03:23:40 AM UTC 24
Finished Sep 11 03:29:00 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437140401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2437140401
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/120.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/121.uart_fifo_reset.3825690815
Short name T1028
Test name
Test status
Simulation time 104811214344 ps
CPU time 77.46 seconds
Started Sep 11 03:23:41 AM UTC 24
Finished Sep 11 03:25:00 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825690815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3825690815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/121.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/123.uart_fifo_reset.2313222643
Short name T1018
Test name
Test status
Simulation time 73788420169 ps
CPU time 51.29 seconds
Started Sep 11 03:23:43 AM UTC 24
Finished Sep 11 03:24:36 AM UTC 24
Peak memory 208164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313222643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2313222643
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/123.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/124.uart_fifo_reset.2179455381
Short name T1025
Test name
Test status
Simulation time 26212674218 ps
CPU time 69.19 seconds
Started Sep 11 03:23:44 AM UTC 24
Finished Sep 11 03:24:55 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179455381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2179455381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/124.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/125.uart_fifo_reset.1609985879
Short name T1003
Test name
Test status
Simulation time 43024389231 ps
CPU time 14.83 seconds
Started Sep 11 03:23:45 AM UTC 24
Finished Sep 11 03:24:01 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609985879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1609985879
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/125.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/126.uart_fifo_reset.2026466218
Short name T1013
Test name
Test status
Simulation time 15362327851 ps
CPU time 39.86 seconds
Started Sep 11 03:23:46 AM UTC 24
Finished Sep 11 03:24:27 AM UTC 24
Peak memory 208724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026466218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.2026466218
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/126.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/127.uart_fifo_reset.2849691788
Short name T1044
Test name
Test status
Simulation time 125145249697 ps
CPU time 99.74 seconds
Started Sep 11 03:23:48 AM UTC 24
Finished Sep 11 03:25:30 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849691788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2849691788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/127.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/128.uart_fifo_reset.3970494699
Short name T1016
Test name
Test status
Simulation time 78005469709 ps
CPU time 41.27 seconds
Started Sep 11 03:23:49 AM UTC 24
Finished Sep 11 03:24:32 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970494699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3970494699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/128.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/129.uart_fifo_reset.1678120022
Short name T1007
Test name
Test status
Simulation time 30881204364 ps
CPU time 17.1 seconds
Started Sep 11 03:23:50 AM UTC 24
Finished Sep 11 03:24:08 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678120022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1678120022
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/129.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_alert_test.970652873
Short name T435
Test name
Test status
Simulation time 76606320 ps
CPU time 0.86 seconds
Started Sep 11 03:00:29 AM UTC 24
Finished Sep 11 03:00:31 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970652873 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.970652873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_fifo_full.495023237
Short name T269
Test name
Test status
Simulation time 173687111418 ps
CPU time 118.76 seconds
Started Sep 11 03:00:00 AM UTC 24
Finished Sep 11 03:02:04 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495023237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.495023237
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.2710930375
Short name T351
Test name
Test status
Simulation time 9432601755 ps
CPU time 26.84 seconds
Started Sep 11 03:00:06 AM UTC 24
Finished Sep 11 03:00:34 AM UTC 24
Peak memory 207424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710930375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2710930375
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_intr.726333788
Short name T375
Test name
Test status
Simulation time 4198843202 ps
CPU time 14.14 seconds
Started Sep 11 03:00:10 AM UTC 24
Finished Sep 11 03:00:25 AM UTC 24
Peak memory 205084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726333788 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.726333788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.2740611768
Short name T333
Test name
Test status
Simulation time 20685754745 ps
CPU time 149.78 seconds
Started Sep 11 03:00:27 AM UTC 24
Finished Sep 11 03:02:59 AM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740611768 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2740611768
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_loopback.745262901
Short name T434
Test name
Test status
Simulation time 1036308122 ps
CPU time 4 seconds
Started Sep 11 03:00:23 AM UTC 24
Finished Sep 11 03:00:28 AM UTC 24
Peak memory 205024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745262901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_loopback.745262901
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_noise_filter.4125099443
Short name T304
Test name
Test status
Simulation time 17429238128 ps
CPU time 54.25 seconds
Started Sep 11 03:00:11 AM UTC 24
Finished Sep 11 03:01:07 AM UTC 24
Peak memory 207428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125099443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.4125099443
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_perf.4239056348
Short name T332
Test name
Test status
Simulation time 22396487863 ps
CPU time 86.22 seconds
Started Sep 11 03:00:25 AM UTC 24
Finished Sep 11 03:01:54 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239056348 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.4239056348
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_rx_oversample.3019616249
Short name T432
Test name
Test status
Simulation time 4477410069 ps
CPU time 12.36 seconds
Started Sep 11 03:00:09 AM UTC 24
Finished Sep 11 03:00:23 AM UTC 24
Peak memory 207712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019616249 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3019616249
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.538157886
Short name T367
Test name
Test status
Simulation time 30282197610 ps
CPU time 93.08 seconds
Started Sep 11 03:00:14 AM UTC 24
Finished Sep 11 03:01:49 AM UTC 24
Peak memory 205012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538157886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.538157886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_smoke.4277277996
Short name T430
Test name
Test status
Simulation time 308611130 ps
CPU time 1.57 seconds
Started Sep 11 02:59:57 AM UTC 24
Finished Sep 11 02:59:59 AM UTC 24
Peak memory 206368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277277996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4277277996
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_stress_all.2779820650
Short name T200
Test name
Test status
Simulation time 331388746361 ps
CPU time 608.77 seconds
Started Sep 11 03:00:29 AM UTC 24
Finished Sep 11 03:10:44 AM UTC 24
Peak memory 212408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779820650 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2779820650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.2248764142
Short name T322
Test name
Test status
Simulation time 967364782 ps
CPU time 2.12 seconds
Started Sep 11 03:00:23 AM UTC 24
Finished Sep 11 03:00:26 AM UTC 24
Peak memory 207148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248764142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2248764142
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/13.uart_tx_rx.3132313469
Short name T289
Test name
Test status
Simulation time 10539584248 ps
CPU time 31.1 seconds
Started Sep 11 02:59:58 AM UTC 24
Finished Sep 11 03:00:30 AM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132313469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3132313469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/13.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/130.uart_fifo_reset.3115678725
Short name T190
Test name
Test status
Simulation time 15088870506 ps
CPU time 27.41 seconds
Started Sep 11 03:23:51 AM UTC 24
Finished Sep 11 03:24:20 AM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115678725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3115678725
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/130.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/131.uart_fifo_reset.391435817
Short name T1005
Test name
Test status
Simulation time 56383440530 ps
CPU time 13.63 seconds
Started Sep 11 03:23:51 AM UTC 24
Finished Sep 11 03:24:06 AM UTC 24
Peak memory 208788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391435817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.391435817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/131.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/132.uart_fifo_reset.3713224504
Short name T251
Test name
Test status
Simulation time 57072362179 ps
CPU time 42.22 seconds
Started Sep 11 03:23:51 AM UTC 24
Finished Sep 11 03:24:35 AM UTC 24
Peak memory 208528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713224504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3713224504
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/132.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/133.uart_fifo_reset.2756370370
Short name T1022
Test name
Test status
Simulation time 86928032777 ps
CPU time 53.61 seconds
Started Sep 11 03:23:51 AM UTC 24
Finished Sep 11 03:24:46 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756370370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2756370370
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/133.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/134.uart_fifo_reset.1029094631
Short name T1046
Test name
Test status
Simulation time 122834225396 ps
CPU time 98.62 seconds
Started Sep 11 03:23:54 AM UTC 24
Finished Sep 11 03:25:34 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029094631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1029094631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/134.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/135.uart_fifo_reset.2955460011
Short name T1117
Test name
Test status
Simulation time 72926425798 ps
CPU time 210.85 seconds
Started Sep 11 03:23:55 AM UTC 24
Finished Sep 11 03:27:29 AM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955460011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2955460011
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/135.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/136.uart_fifo_reset.2663406157
Short name T1031
Test name
Test status
Simulation time 197953273176 ps
CPU time 70.85 seconds
Started Sep 11 03:23:56 AM UTC 24
Finished Sep 11 03:25:08 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663406157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2663406157
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/136.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/137.uart_fifo_reset.795606289
Short name T1012
Test name
Test status
Simulation time 20766640106 ps
CPU time 26.14 seconds
Started Sep 11 03:23:59 AM UTC 24
Finished Sep 11 03:24:26 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795606289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.795606289
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/137.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/138.uart_fifo_reset.615664471
Short name T1010
Test name
Test status
Simulation time 69202911210 ps
CPU time 10.32 seconds
Started Sep 11 03:24:02 AM UTC 24
Finished Sep 11 03:24:13 AM UTC 24
Peak memory 208712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615664471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.615664471
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/138.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/139.uart_fifo_reset.652065832
Short name T1180
Test name
Test status
Simulation time 145531907634 ps
CPU time 764.98 seconds
Started Sep 11 03:24:07 AM UTC 24
Finished Sep 11 03:37:01 AM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652065832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.652065832
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/139.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_alert_test.4007965386
Short name T438
Test name
Test status
Simulation time 31850189 ps
CPU time 0.82 seconds
Started Sep 11 03:01:04 AM UTC 24
Finished Sep 11 03:01:06 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007965386 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.4007965386
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_fifo_full.4161615019
Short name T160
Test name
Test status
Simulation time 61440127666 ps
CPU time 42.69 seconds
Started Sep 11 03:00:33 AM UTC 24
Finished Sep 11 03:01:17 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161615019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.4161615019
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.2914131613
Short name T334
Test name
Test status
Simulation time 43829535686 ps
CPU time 38.92 seconds
Started Sep 11 03:00:34 AM UTC 24
Finished Sep 11 03:01:14 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914131613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2914131613
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_fifo_reset.1147398014
Short name T395
Test name
Test status
Simulation time 49148255674 ps
CPU time 27.04 seconds
Started Sep 11 03:00:35 AM UTC 24
Finished Sep 11 03:01:04 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147398014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1147398014
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_intr.2196738674
Short name T702
Test name
Test status
Simulation time 432395140050 ps
CPU time 814.4 seconds
Started Sep 11 03:00:36 AM UTC 24
Finished Sep 11 03:14:20 AM UTC 24
Peak memory 212196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196738674 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2196738674
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.1917063601
Short name T609
Test name
Test status
Simulation time 298810254591 ps
CPU time 553.24 seconds
Started Sep 11 03:01:00 AM UTC 24
Finished Sep 11 03:10:22 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917063601 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1917063601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_loopback.2562024698
Short name T437
Test name
Test status
Simulation time 7651946691 ps
CPU time 2.55 seconds
Started Sep 11 03:00:56 AM UTC 24
Finished Sep 11 03:00:59 AM UTC 24
Peak memory 208568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562024698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2562024698
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_perf.3995940316
Short name T491
Test name
Test status
Simulation time 16947280058 ps
CPU time 220.76 seconds
Started Sep 11 03:00:57 AM UTC 24
Finished Sep 11 03:04:42 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995940316 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3995940316
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_rx_oversample.1429571072
Short name T436
Test name
Test status
Simulation time 2969425154 ps
CPU time 18.86 seconds
Started Sep 11 03:00:35 AM UTC 24
Finished Sep 11 03:00:55 AM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429571072 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1429571072
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.3915759341
Short name T144
Test name
Test status
Simulation time 41568115452 ps
CPU time 29.72 seconds
Started Sep 11 03:00:46 AM UTC 24
Finished Sep 11 03:01:17 AM UTC 24
Peak memory 208864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915759341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3915759341
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.2060954910
Short name T370
Test name
Test status
Simulation time 40692661674 ps
CPU time 38.12 seconds
Started Sep 11 03:00:39 AM UTC 24
Finished Sep 11 03:01:19 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060954910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2060954910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_smoke.3750628351
Short name T326
Test name
Test status
Simulation time 313218919 ps
CPU time 2.77 seconds
Started Sep 11 03:00:31 AM UTC 24
Finished Sep 11 03:00:35 AM UTC 24
Peak memory 208048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750628351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3750628351
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_stress_all.3372974048
Short name T368
Test name
Test status
Simulation time 138121440952 ps
CPU time 88.61 seconds
Started Sep 11 03:01:03 AM UTC 24
Finished Sep 11 03:02:34 AM UTC 24
Peak memory 217776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372974048 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3372974048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.1379335890
Short name T441
Test name
Test status
Simulation time 3091820927 ps
CPU time 26.21 seconds
Started Sep 11 03:01:01 AM UTC 24
Finished Sep 11 03:01:29 AM UTC 24
Peak memory 209024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1379335890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all
_with_rand_reset.1379335890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.923687048
Short name T308
Test name
Test status
Simulation time 6988785710 ps
CPU time 19.34 seconds
Started Sep 11 03:00:47 AM UTC 24
Finished Sep 11 03:01:07 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923687048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.923687048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/14.uart_tx_rx.3324563028
Short name T328
Test name
Test status
Simulation time 54802406259 ps
CPU time 81.37 seconds
Started Sep 11 03:00:32 AM UTC 24
Finished Sep 11 03:01:55 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324563028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3324563028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/14.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/141.uart_fifo_reset.940756938
Short name T220
Test name
Test status
Simulation time 247002449917 ps
CPU time 69.36 seconds
Started Sep 11 03:24:07 AM UTC 24
Finished Sep 11 03:25:18 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940756938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.940756938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/141.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/143.uart_fifo_reset.643913175
Short name T1038
Test name
Test status
Simulation time 99035562564 ps
CPU time 66.1 seconds
Started Sep 11 03:24:13 AM UTC 24
Finished Sep 11 03:25:21 AM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643913175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.643913175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/143.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/144.uart_fifo_reset.4081661837
Short name T212
Test name
Test status
Simulation time 21156416320 ps
CPU time 34.16 seconds
Started Sep 11 03:24:14 AM UTC 24
Finished Sep 11 03:24:50 AM UTC 24
Peak memory 208840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081661837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.4081661837
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/144.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/145.uart_fifo_reset.3998251843
Short name T1020
Test name
Test status
Simulation time 38374581523 ps
CPU time 26.72 seconds
Started Sep 11 03:24:14 AM UTC 24
Finished Sep 11 03:24:42 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998251843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.3998251843
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/145.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/147.uart_fifo_reset.129770138
Short name T1030
Test name
Test status
Simulation time 23693618583 ps
CPU time 44.16 seconds
Started Sep 11 03:24:21 AM UTC 24
Finished Sep 11 03:25:06 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129770138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.129770138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/147.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/148.uart_fifo_reset.702488307
Short name T1066
Test name
Test status
Simulation time 124066040947 ps
CPU time 104.76 seconds
Started Sep 11 03:24:22 AM UTC 24
Finished Sep 11 03:26:08 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702488307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.702488307
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/148.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/149.uart_fifo_reset.78004672
Short name T1062
Test name
Test status
Simulation time 52071521234 ps
CPU time 88.33 seconds
Started Sep 11 03:24:24 AM UTC 24
Finished Sep 11 03:25:54 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78004672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.78004672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/149.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_alert_test.2057611672
Short name T442
Test name
Test status
Simulation time 14140585 ps
CPU time 0.88 seconds
Started Sep 11 03:01:33 AM UTC 24
Finished Sep 11 03:01:35 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057611672 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2057611672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.1919845076
Short name T137
Test name
Test status
Simulation time 86654534925 ps
CPU time 147.96 seconds
Started Sep 11 03:01:11 AM UTC 24
Finished Sep 11 03:03:42 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919845076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.1919845076
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.3237090706
Short name T739
Test name
Test status
Simulation time 192344424753 ps
CPU time 845.1 seconds
Started Sep 11 03:01:28 AM UTC 24
Finished Sep 11 03:15:44 AM UTC 24
Peak memory 212216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237090706 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3237090706
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_loopback.2431769028
Short name T440
Test name
Test status
Simulation time 31523820 ps
CPU time 0.84 seconds
Started Sep 11 03:01:25 AM UTC 24
Finished Sep 11 03:01:27 AM UTC 24
Peak memory 204432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431769028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.2431769028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_noise_filter.2820880961
Short name T393
Test name
Test status
Simulation time 160626402680 ps
CPU time 25.85 seconds
Started Sep 11 03:01:18 AM UTC 24
Finished Sep 11 03:01:45 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820880961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2820880961
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_perf.2204130238
Short name T363
Test name
Test status
Simulation time 4466687530 ps
CPU time 61.07 seconds
Started Sep 11 03:01:28 AM UTC 24
Finished Sep 11 03:02:31 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204130238 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2204130238
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_rx_oversample.3027535564
Short name T450
Test name
Test status
Simulation time 6306447243 ps
CPU time 64.93 seconds
Started Sep 11 03:01:18 AM UTC 24
Finished Sep 11 03:02:24 AM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027535564 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3027535564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.2518508241
Short name T125
Test name
Test status
Simulation time 61637945520 ps
CPU time 25.76 seconds
Started Sep 11 03:01:20 AM UTC 24
Finished Sep 11 03:01:47 AM UTC 24
Peak memory 208864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518508241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.2518508241
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.1691696095
Short name T455
Test name
Test status
Simulation time 42235625794 ps
CPU time 76.38 seconds
Started Sep 11 03:01:18 AM UTC 24
Finished Sep 11 03:02:36 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691696095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.1691696095
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_smoke.981064552
Short name T439
Test name
Test status
Simulation time 447458611 ps
CPU time 2.21 seconds
Started Sep 11 03:01:07 AM UTC 24
Finished Sep 11 03:01:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981064552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 15.uart_smoke.981064552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.718296749
Short name T79
Test name
Test status
Simulation time 2129897051 ps
CPU time 20.89 seconds
Started Sep 11 03:01:29 AM UTC 24
Finished Sep 11 03:01:52 AM UTC 24
Peak memory 217580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=718296749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all_
with_rand_reset.718296749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.2973644833
Short name T280
Test name
Test status
Simulation time 13245888748 ps
CPU time 28.13 seconds
Started Sep 11 03:01:24 AM UTC 24
Finished Sep 11 03:01:53 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973644833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2973644833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/150.uart_fifo_reset.2857376161
Short name T1021
Test name
Test status
Simulation time 8036266843 ps
CPU time 18.23 seconds
Started Sep 11 03:24:27 AM UTC 24
Finished Sep 11 03:24:46 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857376161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2857376161
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/150.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/151.uart_fifo_reset.3288892645
Short name T197
Test name
Test status
Simulation time 9307441516 ps
CPU time 15.83 seconds
Started Sep 11 03:24:28 AM UTC 24
Finished Sep 11 03:24:45 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288892645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.3288892645
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/151.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/152.uart_fifo_reset.2441596981
Short name T1034
Test name
Test status
Simulation time 96613627063 ps
CPU time 43.73 seconds
Started Sep 11 03:24:29 AM UTC 24
Finished Sep 11 03:25:14 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441596981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2441596981
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/152.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1553644775
Short name T1061
Test name
Test status
Simulation time 134943850628 ps
CPU time 79.55 seconds
Started Sep 11 03:24:32 AM UTC 24
Finished Sep 11 03:25:53 AM UTC 24
Peak memory 208772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553644775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1553644775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/153.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/156.uart_fifo_reset.2275003612
Short name T1058
Test name
Test status
Simulation time 154551276206 ps
CPU time 74.32 seconds
Started Sep 11 03:24:32 AM UTC 24
Finished Sep 11 03:25:48 AM UTC 24
Peak memory 208632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275003612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2275003612
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/156.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/157.uart_fifo_reset.2789688048
Short name T1040
Test name
Test status
Simulation time 364125168724 ps
CPU time 48.99 seconds
Started Sep 11 03:24:33 AM UTC 24
Finished Sep 11 03:25:24 AM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789688048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2789688048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/157.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/158.uart_fifo_reset.1718512944
Short name T1027
Test name
Test status
Simulation time 22270555787 ps
CPU time 19.96 seconds
Started Sep 11 03:24:35 AM UTC 24
Finished Sep 11 03:24:57 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718512944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1718512944
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/158.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_alert_test.3026934783
Short name T445
Test name
Test status
Simulation time 30596130 ps
CPU time 0.85 seconds
Started Sep 11 03:02:07 AM UTC 24
Finished Sep 11 03:02:09 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026934783 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3026934783
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_fifo_full.2614750693
Short name T136
Test name
Test status
Simulation time 53130954257 ps
CPU time 55.67 seconds
Started Sep 11 03:01:44 AM UTC 24
Finished Sep 11 03:02:41 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614750693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2614750693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.2575749646
Short name T254
Test name
Test status
Simulation time 108278312307 ps
CPU time 80.89 seconds
Started Sep 11 03:01:46 AM UTC 24
Finished Sep 11 03:03:09 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575749646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2575749646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_intr.245073749
Short name T576
Test name
Test status
Simulation time 62260107532 ps
CPU time 405.26 seconds
Started Sep 11 03:01:50 AM UTC 24
Finished Sep 11 03:08:41 AM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245073749 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.245073749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.452088213
Short name T755
Test name
Test status
Simulation time 127480146530 ps
CPU time 849.65 seconds
Started Sep 11 03:01:56 AM UTC 24
Finished Sep 11 03:16:16 AM UTC 24
Peak memory 212164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452088213 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.452088213
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_loopback.1332380028
Short name T447
Test name
Test status
Simulation time 10330747311 ps
CPU time 14.28 seconds
Started Sep 11 03:01:54 AM UTC 24
Finished Sep 11 03:02:10 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332380028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1332380028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_noise_filter.3575831103
Short name T316
Test name
Test status
Simulation time 148090543201 ps
CPU time 83.85 seconds
Started Sep 11 03:01:50 AM UTC 24
Finished Sep 11 03:03:16 AM UTC 24
Peak memory 208812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575831103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3575831103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_perf.3171559014
Short name T357
Test name
Test status
Simulation time 7445765447 ps
CPU time 63.58 seconds
Started Sep 11 03:01:55 AM UTC 24
Finished Sep 11 03:03:01 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171559014 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3171559014
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_rx_oversample.3406616683
Short name T443
Test name
Test status
Simulation time 5904432232 ps
CPU time 5.63 seconds
Started Sep 11 03:01:48 AM UTC 24
Finished Sep 11 03:01:55 AM UTC 24
Peak memory 207204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406616683 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3406616683
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.1541517368
Short name T162
Test name
Test status
Simulation time 65656521024 ps
CPU time 64.05 seconds
Started Sep 11 03:01:54 AM UTC 24
Finished Sep 11 03:03:00 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541517368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1541517368
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.1651283840
Short name T444
Test name
Test status
Simulation time 4290032049 ps
CPU time 9.03 seconds
Started Sep 11 03:01:52 AM UTC 24
Finished Sep 11 03:02:02 AM UTC 24
Peak memory 205216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651283840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.1651283840
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_smoke.412032868
Short name T347
Test name
Test status
Simulation time 889232552 ps
CPU time 5.41 seconds
Started Sep 11 03:01:37 AM UTC 24
Finished Sep 11 03:01:43 AM UTC 24
Peak memory 207944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412032868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.uart_smoke.412032868
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.3428012972
Short name T449
Test name
Test status
Simulation time 6924998554 ps
CPU time 15.84 seconds
Started Sep 11 03:01:54 AM UTC 24
Finished Sep 11 03:02:11 AM UTC 24
Peak memory 208392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428012972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3428012972
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/16.uart_tx_rx.2906164532
Short name T446
Test name
Test status
Simulation time 64193341283 ps
CPU time 26.99 seconds
Started Sep 11 03:01:41 AM UTC 24
Finished Sep 11 03:02:09 AM UTC 24
Peak memory 207140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906164532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2906164532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/16.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/160.uart_fifo_reset.3329897440
Short name T1041
Test name
Test status
Simulation time 78489511010 ps
CPU time 43.03 seconds
Started Sep 11 03:24:41 AM UTC 24
Finished Sep 11 03:25:25 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329897440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3329897440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/160.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/161.uart_fifo_reset.1440612547
Short name T1035
Test name
Test status
Simulation time 40127403429 ps
CPU time 32 seconds
Started Sep 11 03:24:42 AM UTC 24
Finished Sep 11 03:25:15 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440612547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1440612547
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/161.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/162.uart_fifo_reset.788835434
Short name T1043
Test name
Test status
Simulation time 52684745137 ps
CPU time 43.07 seconds
Started Sep 11 03:24:44 AM UTC 24
Finished Sep 11 03:25:28 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788835434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.788835434
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/162.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/163.uart_fifo_reset.2175164090
Short name T1037
Test name
Test status
Simulation time 35891712525 ps
CPU time 34.85 seconds
Started Sep 11 03:24:44 AM UTC 24
Finished Sep 11 03:25:20 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175164090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2175164090
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/163.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/164.uart_fifo_reset.1609056603
Short name T1033
Test name
Test status
Simulation time 58896635447 ps
CPU time 23.07 seconds
Started Sep 11 03:24:46 AM UTC 24
Finished Sep 11 03:25:10 AM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609056603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1609056603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/164.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/165.uart_fifo_reset.311602957
Short name T1148
Test name
Test status
Simulation time 120463380417 ps
CPU time 223.54 seconds
Started Sep 11 03:24:47 AM UTC 24
Finished Sep 11 03:28:34 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311602957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.311602957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/165.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/166.uart_fifo_reset.1571793107
Short name T1130
Test name
Test status
Simulation time 179643437168 ps
CPU time 182.31 seconds
Started Sep 11 03:24:48 AM UTC 24
Finished Sep 11 03:27:53 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571793107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1571793107
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/166.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/167.uart_fifo_reset.269071011
Short name T1143
Test name
Test status
Simulation time 110077619894 ps
CPU time 209.09 seconds
Started Sep 11 03:24:48 AM UTC 24
Finished Sep 11 03:28:20 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269071011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.269071011
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/167.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/169.uart_fifo_reset.3639581814
Short name T1088
Test name
Test status
Simulation time 83831220060 ps
CPU time 124.55 seconds
Started Sep 11 03:24:49 AM UTC 24
Finished Sep 11 03:26:56 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639581814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3639581814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/169.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_alert_test.2268796562
Short name T453
Test name
Test status
Simulation time 11973397 ps
CPU time 0.82 seconds
Started Sep 11 03:02:33 AM UTC 24
Finished Sep 11 03:02:35 AM UTC 24
Peak memory 204432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268796562 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2268796562
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_fifo_full.959558012
Short name T350
Test name
Test status
Simulation time 148518364662 ps
CPU time 91.12 seconds
Started Sep 11 03:02:10 AM UTC 24
Finished Sep 11 03:03:43 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959558012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.959558012
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.4166977175
Short name T331
Test name
Test status
Simulation time 64824156362 ps
CPU time 73.69 seconds
Started Sep 11 03:02:11 AM UTC 24
Finished Sep 11 03:03:26 AM UTC 24
Peak memory 208656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166977175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.4166977175
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_fifo_reset.1914869027
Short name T129
Test name
Test status
Simulation time 64208383929 ps
CPU time 177.88 seconds
Started Sep 11 03:02:11 AM UTC 24
Finished Sep 11 03:05:12 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914869027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1914869027
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_intr.4032158210
Short name T451
Test name
Test status
Simulation time 17507400044 ps
CPU time 14.08 seconds
Started Sep 11 03:02:13 AM UTC 24
Finished Sep 11 03:02:28 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032158210 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.4032158210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.3409108196
Short name T642
Test name
Test status
Simulation time 136514197309 ps
CPU time 530.56 seconds
Started Sep 11 03:02:32 AM UTC 24
Finished Sep 11 03:11:29 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409108196 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3409108196
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_loopback.3731301325
Short name T454
Test name
Test status
Simulation time 1063021603 ps
CPU time 5.21 seconds
Started Sep 11 03:02:30 AM UTC 24
Finished Sep 11 03:02:36 AM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731301325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3731301325
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_noise_filter.2448278131
Short name T343
Test name
Test status
Simulation time 117379154636 ps
CPU time 75.7 seconds
Started Sep 11 03:02:15 AM UTC 24
Finished Sep 11 03:03:33 AM UTC 24
Peak memory 208956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448278131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2448278131
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_perf.3233956775
Short name T495
Test name
Test status
Simulation time 14137689422 ps
CPU time 140.56 seconds
Started Sep 11 03:02:31 AM UTC 24
Finished Sep 11 03:04:54 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233956775 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.3233956775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_rx_oversample.4027832744
Short name T462
Test name
Test status
Simulation time 5079266158 ps
CPU time 45.18 seconds
Started Sep 11 03:02:12 AM UTC 24
Finished Sep 11 03:02:59 AM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027832744 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.4027832744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.2201105846
Short name T601
Test name
Test status
Simulation time 167433231500 ps
CPU time 443.09 seconds
Started Sep 11 03:02:26 AM UTC 24
Finished Sep 11 03:09:54 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201105846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.2201105846
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.3479089244
Short name T458
Test name
Test status
Simulation time 33054589899 ps
CPU time 23.74 seconds
Started Sep 11 03:02:21 AM UTC 24
Finished Sep 11 03:02:46 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479089244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3479089244
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_smoke.135130065
Short name T448
Test name
Test status
Simulation time 448578962 ps
CPU time 2.31 seconds
Started Sep 11 03:02:07 AM UTC 24
Finished Sep 11 03:02:10 AM UTC 24
Peak memory 207336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135130065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.uart_smoke.135130065
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_stress_all.1921833621
Short name T512
Test name
Test status
Simulation time 230672887252 ps
CPU time 183.94 seconds
Started Sep 11 03:02:33 AM UTC 24
Finished Sep 11 03:05:40 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921833621 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.1921833621
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.353906225
Short name T81
Test name
Test status
Simulation time 5053109061 ps
CPU time 70.46 seconds
Started Sep 11 03:02:32 AM UTC 24
Finished Sep 11 03:03:44 AM UTC 24
Peak memory 217800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=353906225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all_
with_rand_reset.353906225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.2738403782
Short name T452
Test name
Test status
Simulation time 1188835603 ps
CPU time 2.55 seconds
Started Sep 11 03:02:28 AM UTC 24
Finished Sep 11 03:02:31 AM UTC 24
Peak memory 208024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738403782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.2738403782
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/17.uart_tx_rx.2072706516
Short name T457
Test name
Test status
Simulation time 25196237614 ps
CPU time 29.41 seconds
Started Sep 11 03:02:10 AM UTC 24
Finished Sep 11 03:02:41 AM UTC 24
Peak memory 208712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072706516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2072706516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/17.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/170.uart_fifo_reset.214811549
Short name T1053
Test name
Test status
Simulation time 46942545551 ps
CPU time 49.96 seconds
Started Sep 11 03:24:50 AM UTC 24
Finished Sep 11 03:25:42 AM UTC 24
Peak memory 208252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214811549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.214811549
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/170.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/171.uart_fifo_reset.3532821620
Short name T1036
Test name
Test status
Simulation time 59389714299 ps
CPU time 25.93 seconds
Started Sep 11 03:24:52 AM UTC 24
Finished Sep 11 03:25:20 AM UTC 24
Peak memory 208588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532821620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3532821620
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/171.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/172.uart_fifo_reset.3395184140
Short name T1049
Test name
Test status
Simulation time 71534903802 ps
CPU time 42.51 seconds
Started Sep 11 03:24:54 AM UTC 24
Finished Sep 11 03:25:38 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395184140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3395184140
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/172.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/173.uart_fifo_reset.2217900533
Short name T1052
Test name
Test status
Simulation time 20039782625 ps
CPU time 42.86 seconds
Started Sep 11 03:24:55 AM UTC 24
Finished Sep 11 03:25:40 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217900533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2217900533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/173.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/174.uart_fifo_reset.3675690234
Short name T1060
Test name
Test status
Simulation time 41294826353 ps
CPU time 54.16 seconds
Started Sep 11 03:24:57 AM UTC 24
Finished Sep 11 03:25:52 AM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675690234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3675690234
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/174.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/175.uart_fifo_reset.739939501
Short name T1051
Test name
Test status
Simulation time 21765158729 ps
CPU time 39.85 seconds
Started Sep 11 03:24:58 AM UTC 24
Finished Sep 11 03:25:39 AM UTC 24
Peak memory 208532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739939501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.739939501
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/175.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/176.uart_fifo_reset.2875677624
Short name T1048
Test name
Test status
Simulation time 28264376018 ps
CPU time 37.97 seconds
Started Sep 11 03:24:59 AM UTC 24
Finished Sep 11 03:25:38 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875677624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2875677624
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/176.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/177.uart_fifo_reset.908492178
Short name T1145
Test name
Test status
Simulation time 98367729578 ps
CPU time 199.88 seconds
Started Sep 11 03:25:01 AM UTC 24
Finished Sep 11 03:28:24 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908492178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.908492178
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/177.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/178.uart_fifo_reset.1052868649
Short name T1047
Test name
Test status
Simulation time 16938874741 ps
CPU time 29.07 seconds
Started Sep 11 03:25:04 AM UTC 24
Finished Sep 11 03:25:34 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052868649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1052868649
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/178.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/179.uart_fifo_reset.1355864426
Short name T224
Test name
Test status
Simulation time 39203836188 ps
CPU time 19.17 seconds
Started Sep 11 03:25:07 AM UTC 24
Finished Sep 11 03:25:27 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355864426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1355864426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/179.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_alert_test.2311694064
Short name T464
Test name
Test status
Simulation time 41783920 ps
CPU time 0.83 seconds
Started Sep 11 03:02:59 AM UTC 24
Finished Sep 11 03:03:01 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311694064 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2311694064
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_fifo_full.1591416245
Short name T471
Test name
Test status
Simulation time 37208786677 ps
CPU time 66.14 seconds
Started Sep 11 03:02:37 AM UTC 24
Finished Sep 11 03:03:45 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591416245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1591416245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.4146312815
Short name T134
Test name
Test status
Simulation time 115847172986 ps
CPU time 80.6 seconds
Started Sep 11 03:02:37 AM UTC 24
Finished Sep 11 03:04:00 AM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146312815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.4146312815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_intr.34568910
Short name T469
Test name
Test status
Simulation time 57731141776 ps
CPU time 54.14 seconds
Started Sep 11 03:02:42 AM UTC 24
Finished Sep 11 03:03:37 AM UTC 24
Peak memory 207144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34568910 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.34568910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.4013068220
Short name T928
Test name
Test status
Simulation time 190555728416 ps
CPU time 1111.3 seconds
Started Sep 11 03:02:52 AM UTC 24
Finished Sep 11 03:21:37 AM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013068220 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4013068220
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_loopback.2855646978
Short name T463
Test name
Test status
Simulation time 2549898199 ps
CPU time 11.5 seconds
Started Sep 11 03:02:47 AM UTC 24
Finished Sep 11 03:03:00 AM UTC 24
Peak memory 208060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855646978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2855646978
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_noise_filter.847107417
Short name T349
Test name
Test status
Simulation time 98454851096 ps
CPU time 53.24 seconds
Started Sep 11 03:02:42 AM UTC 24
Finished Sep 11 03:03:36 AM UTC 24
Peak memory 208284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847107417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.847107417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_perf.3681764751
Short name T482
Test name
Test status
Simulation time 5786272130 ps
CPU time 83.04 seconds
Started Sep 11 03:02:52 AM UTC 24
Finished Sep 11 03:04:17 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681764751 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3681764751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_rx_oversample.2020319533
Short name T461
Test name
Test status
Simulation time 5085986331 ps
CPU time 12.93 seconds
Started Sep 11 03:02:39 AM UTC 24
Finished Sep 11 03:02:53 AM UTC 24
Peak memory 207204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020319533 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2020319533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.3878980425
Short name T513
Test name
Test status
Simulation time 131100651275 ps
CPU time 189.63 seconds
Started Sep 11 03:02:46 AM UTC 24
Finished Sep 11 03:05:59 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878980425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.3878980425
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.655255920
Short name T459
Test name
Test status
Simulation time 1745828104 ps
CPU time 2.51 seconds
Started Sep 11 03:02:43 AM UTC 24
Finished Sep 11 03:02:46 AM UTC 24
Peak memory 205024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655255920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.655255920
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_smoke.2734436461
Short name T456
Test name
Test status
Simulation time 966031770 ps
CPU time 1.6 seconds
Started Sep 11 03:02:34 AM UTC 24
Finished Sep 11 03:02:37 AM UTC 24
Peak memory 206312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734436461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2734436461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_stress_all.3468873696
Short name T751
Test name
Test status
Simulation time 482546913268 ps
CPU time 770.66 seconds
Started Sep 11 03:02:59 AM UTC 24
Finished Sep 11 03:15:59 AM UTC 24
Peak memory 221324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468873696 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3468873696
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.4130344606
Short name T378
Test name
Test status
Simulation time 4726231585 ps
CPU time 34 seconds
Started Sep 11 03:02:53 AM UTC 24
Finished Sep 11 03:03:29 AM UTC 24
Peak memory 217776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4130344606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all
_with_rand_reset.4130344606
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.776754456
Short name T460
Test name
Test status
Simulation time 1580965968 ps
CPU time 3.66 seconds
Started Sep 11 03:02:46 AM UTC 24
Finished Sep 11 03:02:51 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776754456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.776754456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/18.uart_tx_rx.2042179482
Short name T281
Test name
Test status
Simulation time 89026010022 ps
CPU time 63.75 seconds
Started Sep 11 03:02:36 AM UTC 24
Finished Sep 11 03:03:42 AM UTC 24
Peak memory 208948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042179482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2042179482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/18.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2360938992
Short name T1069
Test name
Test status
Simulation time 164621152122 ps
CPU time 67.63 seconds
Started Sep 11 03:25:07 AM UTC 24
Finished Sep 11 03:26:16 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360938992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2360938992
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/180.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/181.uart_fifo_reset.880517393
Short name T1042
Test name
Test status
Simulation time 8055987842 ps
CPU time 17.16 seconds
Started Sep 11 03:25:09 AM UTC 24
Finished Sep 11 03:25:28 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880517393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.880517393
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/181.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/182.uart_fifo_reset.2956443387
Short name T1039
Test name
Test status
Simulation time 4565396478 ps
CPU time 11.64 seconds
Started Sep 11 03:25:10 AM UTC 24
Finished Sep 11 03:25:23 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956443387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2956443387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/182.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/183.uart_fifo_reset.2807829688
Short name T1045
Test name
Test status
Simulation time 32399102676 ps
CPU time 18.14 seconds
Started Sep 11 03:25:11 AM UTC 24
Finished Sep 11 03:25:31 AM UTC 24
Peak memory 208140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807829688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2807829688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/183.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/184.uart_fifo_reset.921718071
Short name T1160
Test name
Test status
Simulation time 141203883441 ps
CPU time 217.93 seconds
Started Sep 11 03:25:12 AM UTC 24
Finished Sep 11 03:28:53 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921718071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.921718071
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/184.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/185.uart_fifo_reset.1371369679
Short name T1102
Test name
Test status
Simulation time 35662314070 ps
CPU time 113.61 seconds
Started Sep 11 03:25:15 AM UTC 24
Finished Sep 11 03:27:12 AM UTC 24
Peak memory 208660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371369679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1371369679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/185.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/186.uart_fifo_reset.765706092
Short name T1119
Test name
Test status
Simulation time 302319035181 ps
CPU time 133.07 seconds
Started Sep 11 03:25:16 AM UTC 24
Finished Sep 11 03:27:31 AM UTC 24
Peak memory 208564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765706092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.765706092
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/186.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/187.uart_fifo_reset.1455167286
Short name T1064
Test name
Test status
Simulation time 18866790216 ps
CPU time 41.96 seconds
Started Sep 11 03:25:17 AM UTC 24
Finished Sep 11 03:26:00 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455167286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1455167286
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/187.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/188.uart_fifo_reset.2382032037
Short name T1059
Test name
Test status
Simulation time 53927981659 ps
CPU time 29.67 seconds
Started Sep 11 03:25:19 AM UTC 24
Finished Sep 11 03:25:50 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382032037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2382032037
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/188.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/189.uart_fifo_reset.126691072
Short name T1063
Test name
Test status
Simulation time 54928350077 ps
CPU time 33.02 seconds
Started Sep 11 03:25:21 AM UTC 24
Finished Sep 11 03:25:55 AM UTC 24
Peak memory 208796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126691072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.126691072
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/189.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_alert_test.56909973
Short name T470
Test name
Test status
Simulation time 28395104 ps
CPU time 0.8 seconds
Started Sep 11 03:03:37 AM UTC 24
Finished Sep 11 03:03:39 AM UTC 24
Peak memory 204360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56909973 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.56909973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_fifo_full.287352104
Short name T515
Test name
Test status
Simulation time 229278088461 ps
CPU time 175.22 seconds
Started Sep 11 03:03:02 AM UTC 24
Finished Sep 11 03:05:59 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287352104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.287352104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_fifo_overflow.614027011
Short name T154
Test name
Test status
Simulation time 23223575529 ps
CPU time 66.49 seconds
Started Sep 11 03:03:02 AM UTC 24
Finished Sep 11 03:04:11 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614027011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.614027011
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_fifo_reset.4085630786
Short name T221
Test name
Test status
Simulation time 217519264028 ps
CPU time 44.62 seconds
Started Sep 11 03:03:07 AM UTC 24
Finished Sep 11 03:03:53 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085630786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.4085630786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_intr.2684166931
Short name T488
Test name
Test status
Simulation time 49745345804 ps
CPU time 80.61 seconds
Started Sep 11 03:03:10 AM UTC 24
Finished Sep 11 03:04:32 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684166931 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2684166931
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.3405594135
Short name T562
Test name
Test status
Simulation time 183178084873 ps
CPU time 268.25 seconds
Started Sep 11 03:03:32 AM UTC 24
Finished Sep 11 03:08:03 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405594135 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3405594135
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_loopback.4115239267
Short name T468
Test name
Test status
Simulation time 9118417072 ps
CPU time 5.5 seconds
Started Sep 11 03:03:29 AM UTC 24
Finished Sep 11 03:03:36 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115239267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.4115239267
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_noise_filter.4057788960
Short name T478
Test name
Test status
Simulation time 376908779669 ps
CPU time 45.82 seconds
Started Sep 11 03:03:13 AM UTC 24
Finished Sep 11 03:04:00 AM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057788960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.4057788960
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_perf.1063659794
Short name T398
Test name
Test status
Simulation time 23883326136 ps
CPU time 730.97 seconds
Started Sep 11 03:03:30 AM UTC 24
Finished Sep 11 03:15:50 AM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063659794 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1063659794
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_rx_oversample.3725862041
Short name T484
Test name
Test status
Simulation time 6171092571 ps
CPU time 69.74 seconds
Started Sep 11 03:03:08 AM UTC 24
Finished Sep 11 03:04:19 AM UTC 24
Peak memory 208648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725862041 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.3725862041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.271932663
Short name T128
Test name
Test status
Simulation time 20565966066 ps
CPU time 53.53 seconds
Started Sep 11 03:03:16 AM UTC 24
Finished Sep 11 03:04:11 AM UTC 24
Peak memory 208260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271932663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.271932663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.3893349760
Short name T481
Test name
Test status
Simulation time 45716329711 ps
CPU time 51.28 seconds
Started Sep 11 03:03:14 AM UTC 24
Finished Sep 11 03:04:07 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893349760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3893349760
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_smoke.2614125388
Short name T465
Test name
Test status
Simulation time 841647335 ps
CPU time 5.86 seconds
Started Sep 11 03:03:00 AM UTC 24
Finished Sep 11 03:03:07 AM UTC 24
Peak memory 207544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614125388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2614125388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_stress_all.749242627
Short name T678
Test name
Test status
Simulation time 164905268913 ps
CPU time 579.08 seconds
Started Sep 11 03:03:35 AM UTC 24
Finished Sep 11 03:13:21 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749242627 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.749242627
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.3787205702
Short name T472
Test name
Test status
Simulation time 2616962717 ps
CPU time 16.15 seconds
Started Sep 11 03:03:34 AM UTC 24
Finished Sep 11 03:03:51 AM UTC 24
Peak memory 217644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3787205702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all
_with_rand_reset.3787205702
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.418388258
Short name T467
Test name
Test status
Simulation time 615126482 ps
CPU time 2.48 seconds
Started Sep 11 03:03:27 AM UTC 24
Finished Sep 11 03:03:31 AM UTC 24
Peak memory 207076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418388258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.418388258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/19.uart_tx_rx.3065316123
Short name T466
Test name
Test status
Simulation time 13517547783 ps
CPU time 11.17 seconds
Started Sep 11 03:03:01 AM UTC 24
Finished Sep 11 03:03:13 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065316123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3065316123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/19.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/190.uart_fifo_reset.2489622075
Short name T1122
Test name
Test status
Simulation time 209007722263 ps
CPU time 135.51 seconds
Started Sep 11 03:25:21 AM UTC 24
Finished Sep 11 03:27:39 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489622075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2489622075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/190.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/192.uart_fifo_reset.88679037
Short name T1065
Test name
Test status
Simulation time 172513629692 ps
CPU time 43.56 seconds
Started Sep 11 03:25:23 AM UTC 24
Finished Sep 11 03:26:08 AM UTC 24
Peak memory 208892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88679037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.88679037
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/192.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3809294513
Short name T1082
Test name
Test status
Simulation time 48655873695 ps
CPU time 78.8 seconds
Started Sep 11 03:25:24 AM UTC 24
Finished Sep 11 03:26:45 AM UTC 24
Peak memory 208664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809294513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3809294513
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/193.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3645718742
Short name T1054
Test name
Test status
Simulation time 20331324473 ps
CPU time 17.4 seconds
Started Sep 11 03:25:24 AM UTC 24
Finished Sep 11 03:25:43 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645718742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3645718742
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/194.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/195.uart_fifo_reset.3314327773
Short name T1057
Test name
Test status
Simulation time 34154470991 ps
CPU time 21.25 seconds
Started Sep 11 03:25:24 AM UTC 24
Finished Sep 11 03:25:47 AM UTC 24
Peak memory 208708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314327773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3314327773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/195.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/196.uart_fifo_reset.1535844234
Short name T1086
Test name
Test status
Simulation time 98788849341 ps
CPU time 84.94 seconds
Started Sep 11 03:25:25 AM UTC 24
Finished Sep 11 03:26:52 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535844234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1535844234
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/196.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/197.uart_fifo_reset.1900338446
Short name T1152
Test name
Test status
Simulation time 63574038519 ps
CPU time 189.43 seconds
Started Sep 11 03:25:26 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900338446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1900338446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/197.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/198.uart_fifo_reset.4246642044
Short name T1050
Test name
Test status
Simulation time 12087928477 ps
CPU time 8.85 seconds
Started Sep 11 03:25:28 AM UTC 24
Finished Sep 11 03:25:39 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246642044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4246642044
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/198.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/199.uart_fifo_reset.4128287016
Short name T1093
Test name
Test status
Simulation time 56658424513 ps
CPU time 88.74 seconds
Started Sep 11 03:25:28 AM UTC 24
Finished Sep 11 03:26:59 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128287016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4128287016
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/199.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_alert_test.208428886
Short name T29
Test name
Test status
Simulation time 12410475 ps
CPU time 0.82 seconds
Started Sep 11 02:56:23 AM UTC 24
Finished Sep 11 02:56:24 AM UTC 24
Peak memory 204364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208428886 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.208428886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_fifo_full.2233714817
Short name T90
Test name
Test status
Simulation time 83810871320 ps
CPU time 127.49 seconds
Started Sep 11 02:56:07 AM UTC 24
Finished Sep 11 02:58:17 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233714817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2233714817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.2936968646
Short name T44
Test name
Test status
Simulation time 38438119155 ps
CPU time 19.75 seconds
Started Sep 11 02:56:08 AM UTC 24
Finished Sep 11 02:56:29 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936968646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2936968646
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_intr.3140277748
Short name T83
Test name
Test status
Simulation time 6630848613 ps
CPU time 25.2 seconds
Started Sep 11 02:56:08 AM UTC 24
Finished Sep 11 02:56:35 AM UTC 24
Peak memory 208476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140277748 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3140277748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.2778282063
Short name T258
Test name
Test status
Simulation time 82360593925 ps
CPU time 177.31 seconds
Started Sep 11 02:56:18 AM UTC 24
Finished Sep 11 02:59:18 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778282063 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2778282063
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_loopback.1587208564
Short name T25
Test name
Test status
Simulation time 3421282467 ps
CPU time 9.26 seconds
Started Sep 11 02:56:17 AM UTC 24
Finished Sep 11 02:56:27 AM UTC 24
Peak memory 207380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587208564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.uart_loopback.1587208564
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_noise_filter.1209687860
Short name T101
Test name
Test status
Simulation time 41819509273 ps
CPU time 38.92 seconds
Started Sep 11 02:56:09 AM UTC 24
Finished Sep 11 02:56:50 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209687860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1209687860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_perf.66874519
Short name T628
Test name
Test status
Simulation time 13277912530 ps
CPU time 864.21 seconds
Started Sep 11 02:56:17 AM UTC 24
Finished Sep 11 03:10:51 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66874519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.66874519
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_rx_oversample.1842583602
Short name T26
Test name
Test status
Simulation time 4292783088 ps
CPU time 38.44 seconds
Started Sep 11 02:56:08 AM UTC 24
Finished Sep 11 02:56:48 AM UTC 24
Peak memory 207468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842583602 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1842583602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.1507805292
Short name T67
Test name
Test status
Simulation time 22368026005 ps
CPU time 47.83 seconds
Started Sep 11 02:56:09 AM UTC 24
Finished Sep 11 02:56:59 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507805292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1507805292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.3026216631
Short name T319
Test name
Test status
Simulation time 77934967114 ps
CPU time 70.72 seconds
Started Sep 11 02:56:09 AM UTC 24
Finished Sep 11 02:57:22 AM UTC 24
Peak memory 205092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026216631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3026216631
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_sec_cm.56665986
Short name T28
Test name
Test status
Simulation time 37814485 ps
CPU time 1.04 seconds
Started Sep 11 02:56:23 AM UTC 24
Finished Sep 11 02:56:25 AM UTC 24
Peak memory 238036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56665986 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.56665986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_smoke.3938491423
Short name T14
Test name
Test status
Simulation time 885330646 ps
CPU time 1.95 seconds
Started Sep 11 02:56:06 AM UTC 24
Finished Sep 11 02:56:09 AM UTC 24
Peak memory 206316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938491423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3938491423
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1188237552
Short name T27
Test name
Test status
Simulation time 3384852220 ps
CPU time 38.01 seconds
Started Sep 11 02:56:22 AM UTC 24
Finished Sep 11 02:57:02 AM UTC 24
Peak memory 223984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1188237552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_
with_rand_reset.1188237552
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.2470378977
Short name T16
Test name
Test status
Simulation time 1442020632 ps
CPU time 3.41 seconds
Started Sep 11 02:56:12 AM UTC 24
Finished Sep 11 02:56:17 AM UTC 24
Peak memory 208512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470378977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.2470378977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_alert_test.2291277973
Short name T477
Test name
Test status
Simulation time 21654345 ps
CPU time 0.84 seconds
Started Sep 11 03:03:58 AM UTC 24
Finished Sep 11 03:04:00 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291277973 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2291277973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_fifo_full.1281622438
Short name T149
Test name
Test status
Simulation time 17340539832 ps
CPU time 51.72 seconds
Started Sep 11 03:03:39 AM UTC 24
Finished Sep 11 03:04:32 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281622438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1281622438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_fifo_reset.2227325028
Short name T186
Test name
Test status
Simulation time 87822080369 ps
CPU time 140.58 seconds
Started Sep 11 03:03:43 AM UTC 24
Finished Sep 11 03:06:06 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227325028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2227325028
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_intr.1940731048
Short name T474
Test name
Test status
Simulation time 29542186085 ps
CPU time 8.32 seconds
Started Sep 11 03:03:43 AM UTC 24
Finished Sep 11 03:03:53 AM UTC 24
Peak memory 208660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940731048 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1940731048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.558060776
Short name T600
Test name
Test status
Simulation time 106161849777 ps
CPU time 350.27 seconds
Started Sep 11 03:03:54 AM UTC 24
Finished Sep 11 03:09:49 AM UTC 24
Peak memory 208800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558060776 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.558060776
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_loopback.869138183
Short name T480
Test name
Test status
Simulation time 10271315388 ps
CPU time 11.83 seconds
Started Sep 11 03:03:52 AM UTC 24
Finished Sep 11 03:04:05 AM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869138183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_loopback.869138183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_noise_filter.2009817104
Short name T492
Test name
Test status
Simulation time 35259522120 ps
CPU time 61.63 seconds
Started Sep 11 03:03:43 AM UTC 24
Finished Sep 11 03:04:46 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009817104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2009817104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_perf.3991555331
Short name T782
Test name
Test status
Simulation time 14237161905 ps
CPU time 783.84 seconds
Started Sep 11 03:03:53 AM UTC 24
Finished Sep 11 03:17:05 AM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991555331 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3991555331
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_rx_oversample.2373691749
Short name T475
Test name
Test status
Simulation time 3862676054 ps
CPU time 8.57 seconds
Started Sep 11 03:03:43 AM UTC 24
Finished Sep 11 03:03:53 AM UTC 24
Peak memory 208276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373691749 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2373691749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.408644389
Short name T282
Test name
Test status
Simulation time 141574119375 ps
CPU time 95.58 seconds
Started Sep 11 03:03:45 AM UTC 24
Finished Sep 11 03:05:23 AM UTC 24
Peak memory 208020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408644389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.408644389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.676557115
Short name T476
Test name
Test status
Simulation time 4909805321 ps
CPU time 10.36 seconds
Started Sep 11 03:03:45 AM UTC 24
Finished Sep 11 03:03:57 AM UTC 24
Peak memory 207328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676557115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.676557115
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_smoke.1025397716
Short name T329
Test name
Test status
Simulation time 269669609 ps
CPU time 2.11 seconds
Started Sep 11 03:03:37 AM UTC 24
Finished Sep 11 03:03:40 AM UTC 24
Peak memory 207220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025397716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1025397716
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_stress_all.3763170516
Short name T680
Test name
Test status
Simulation time 183475822052 ps
CPU time 563.61 seconds
Started Sep 11 03:03:54 AM UTC 24
Finished Sep 11 03:13:24 AM UTC 24
Peak memory 217672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763170516 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3763170516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.3915456822
Short name T493
Test name
Test status
Simulation time 17094149113 ps
CPU time 56.65 seconds
Started Sep 11 03:03:54 AM UTC 24
Finished Sep 11 03:04:52 AM UTC 24
Peak memory 224792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3915456822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all
_with_rand_reset.3915456822
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1701439300
Short name T473
Test name
Test status
Simulation time 1302860301 ps
CPU time 4.57 seconds
Started Sep 11 03:03:47 AM UTC 24
Finished Sep 11 03:03:52 AM UTC 24
Peak memory 207380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701439300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1701439300
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/20.uart_tx_rx.14688186
Short name T262
Test name
Test status
Simulation time 87546183675 ps
CPU time 24.48 seconds
Started Sep 11 03:03:38 AM UTC 24
Finished Sep 11 03:04:04 AM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14688186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.14688186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/20.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/200.uart_fifo_reset.3408732938
Short name T1101
Test name
Test status
Simulation time 199678963922 ps
CPU time 97.65 seconds
Started Sep 11 03:25:30 AM UTC 24
Finished Sep 11 03:27:09 AM UTC 24
Peak memory 208560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408732938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3408732938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/200.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/201.uart_fifo_reset.3981032279
Short name T188
Test name
Test status
Simulation time 29215722106 ps
CPU time 12.97 seconds
Started Sep 11 03:25:31 AM UTC 24
Finished Sep 11 03:25:45 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981032279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3981032279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/201.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3743089446
Short name T1067
Test name
Test status
Simulation time 35721375758 ps
CPU time 37.11 seconds
Started Sep 11 03:25:31 AM UTC 24
Finished Sep 11 03:26:10 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743089446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3743089446
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/202.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2778553675
Short name T1096
Test name
Test status
Simulation time 124943497082 ps
CPU time 88.42 seconds
Started Sep 11 03:25:32 AM UTC 24
Finished Sep 11 03:27:02 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778553675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2778553675
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/203.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/204.uart_fifo_reset.419407701
Short name T242
Test name
Test status
Simulation time 200615479662 ps
CPU time 74.81 seconds
Started Sep 11 03:25:35 AM UTC 24
Finished Sep 11 03:26:52 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419407701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.419407701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/204.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/205.uart_fifo_reset.3342616150
Short name T1134
Test name
Test status
Simulation time 141516586355 ps
CPU time 142.68 seconds
Started Sep 11 03:25:35 AM UTC 24
Finished Sep 11 03:28:00 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342616150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3342616150
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/205.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/206.uart_fifo_reset.863615507
Short name T1173
Test name
Test status
Simulation time 122619778378 ps
CPU time 264.08 seconds
Started Sep 11 03:25:39 AM UTC 24
Finished Sep 11 03:30:07 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863615507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.863615507
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/206.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/208.uart_fifo_reset.1893434916
Short name T1071
Test name
Test status
Simulation time 89434850267 ps
CPU time 45.17 seconds
Started Sep 11 03:25:39 AM UTC 24
Finished Sep 11 03:26:26 AM UTC 24
Peak memory 208636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893434916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1893434916
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/208.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/209.uart_fifo_reset.2961887526
Short name T1083
Test name
Test status
Simulation time 142059472095 ps
CPU time 66.05 seconds
Started Sep 11 03:25:40 AM UTC 24
Finished Sep 11 03:26:48 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961887526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2961887526
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/209.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_alert_test.1632277371
Short name T487
Test name
Test status
Simulation time 13590037 ps
CPU time 0.86 seconds
Started Sep 11 03:04:27 AM UTC 24
Finished Sep 11 03:04:30 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632277371 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1632277371
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_fifo_full.743899917
Short name T356
Test name
Test status
Simulation time 145049739267 ps
CPU time 127.05 seconds
Started Sep 11 03:04:01 AM UTC 24
Finished Sep 11 03:06:11 AM UTC 24
Peak memory 208784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743899917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.743899917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.57283218
Short name T172
Test name
Test status
Simulation time 23621736755 ps
CPU time 70.68 seconds
Started Sep 11 03:04:04 AM UTC 24
Finished Sep 11 03:05:17 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57283218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.57283218
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_intr.1873849510
Short name T490
Test name
Test status
Simulation time 17292554034 ps
CPU time 26.11 seconds
Started Sep 11 03:04:08 AM UTC 24
Finished Sep 11 03:04:35 AM UTC 24
Peak memory 207140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873849510 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1873849510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.997040254
Short name T591
Test name
Test status
Simulation time 135359585151 ps
CPU time 295.42 seconds
Started Sep 11 03:04:20 AM UTC 24
Finished Sep 11 03:09:20 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997040254 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.997040254
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_loopback.2167276735
Short name T486
Test name
Test status
Simulation time 6480348544 ps
CPU time 6.75 seconds
Started Sep 11 03:04:18 AM UTC 24
Finished Sep 11 03:04:26 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167276735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2167276735
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_noise_filter.1372465674
Short name T287
Test name
Test status
Simulation time 47196508544 ps
CPU time 85.22 seconds
Started Sep 11 03:04:12 AM UTC 24
Finished Sep 11 03:05:39 AM UTC 24
Peak memory 208768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372465674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1372465674
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_perf.907378322
Short name T734
Test name
Test status
Simulation time 11840148888 ps
CPU time 664.84 seconds
Started Sep 11 03:04:19 AM UTC 24
Finished Sep 11 03:15:31 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907378322 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.907378322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_rx_oversample.1977292684
Short name T483
Test name
Test status
Simulation time 2213784592 ps
CPU time 11.98 seconds
Started Sep 11 03:04:05 AM UTC 24
Finished Sep 11 03:04:19 AM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977292684 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1977292684
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.1805715428
Short name T504
Test name
Test status
Simulation time 37106532565 ps
CPU time 60.95 seconds
Started Sep 11 03:04:16 AM UTC 24
Finished Sep 11 03:05:18 AM UTC 24
Peak memory 208480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805715428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1805715428
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.4284080232
Short name T365
Test name
Test status
Simulation time 1962294335 ps
CPU time 2.65 seconds
Started Sep 11 03:04:12 AM UTC 24
Finished Sep 11 03:04:15 AM UTC 24
Peak memory 205024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284080232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.4284080232
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_smoke.2071139749
Short name T479
Test name
Test status
Simulation time 93589065 ps
CPU time 1.15 seconds
Started Sep 11 03:04:01 AM UTC 24
Finished Sep 11 03:04:03 AM UTC 24
Peak memory 206476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071139749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2071139749
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_stress_all.239819928
Short name T96
Test name
Test status
Simulation time 64225209698 ps
CPU time 57.7 seconds
Started Sep 11 03:04:24 AM UTC 24
Finished Sep 11 03:05:24 AM UTC 24
Peak memory 208904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239819928 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.239819928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.593473026
Short name T135
Test name
Test status
Simulation time 28972687980 ps
CPU time 65.77 seconds
Started Sep 11 03:04:21 AM UTC 24
Finished Sep 11 03:05:29 AM UTC 24
Peak memory 223728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=593473026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all_
with_rand_reset.593473026
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.3676266600
Short name T485
Test name
Test status
Simulation time 934940707 ps
CPU time 5.19 seconds
Started Sep 11 03:04:17 AM UTC 24
Finished Sep 11 03:04:23 AM UTC 24
Peak memory 208096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676266600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3676266600
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/21.uart_tx_rx.3923779775
Short name T503
Test name
Test status
Simulation time 106416244043 ps
CPU time 74.93 seconds
Started Sep 11 03:04:01 AM UTC 24
Finished Sep 11 03:05:18 AM UTC 24
Peak memory 208804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923779775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3923779775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/21.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/210.uart_fifo_reset.922364869
Short name T1094
Test name
Test status
Simulation time 97937577389 ps
CPU time 77.76 seconds
Started Sep 11 03:25:40 AM UTC 24
Finished Sep 11 03:27:00 AM UTC 24
Peak memory 208568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922364869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.922364869
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/210.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/211.uart_fifo_reset.4178226142
Short name T1108
Test name
Test status
Simulation time 166923468804 ps
CPU time 98.53 seconds
Started Sep 11 03:25:40 AM UTC 24
Finished Sep 11 03:27:21 AM UTC 24
Peak memory 208652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178226142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4178226142
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/211.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/212.uart_fifo_reset.493634058
Short name T1079
Test name
Test status
Simulation time 20171127989 ps
CPU time 56.27 seconds
Started Sep 11 03:25:42 AM UTC 24
Finished Sep 11 03:26:40 AM UTC 24
Peak memory 208632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493634058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.493634058
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/212.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/213.uart_fifo_reset.2412467835
Short name T1156
Test name
Test status
Simulation time 49747645059 ps
CPU time 179.82 seconds
Started Sep 11 03:25:43 AM UTC 24
Finished Sep 11 03:28:46 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412467835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2412467835
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/213.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/214.uart_fifo_reset.1130880533
Short name T1111
Test name
Test status
Simulation time 371032876857 ps
CPU time 96.02 seconds
Started Sep 11 03:25:46 AM UTC 24
Finished Sep 11 03:27:24 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130880533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.1130880533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/214.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/215.uart_fifo_reset.3810034970
Short name T180
Test name
Test status
Simulation time 18137419365 ps
CPU time 29.5 seconds
Started Sep 11 03:25:46 AM UTC 24
Finished Sep 11 03:26:16 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810034970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3810034970
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/215.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/216.uart_fifo_reset.2898496776
Short name T1112
Test name
Test status
Simulation time 118991544302 ps
CPU time 95.19 seconds
Started Sep 11 03:25:47 AM UTC 24
Finished Sep 11 03:27:24 AM UTC 24
Peak memory 208588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898496776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2898496776
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/216.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3926011036
Short name T243
Test name
Test status
Simulation time 30056258463 ps
CPU time 34.67 seconds
Started Sep 11 03:25:48 AM UTC 24
Finished Sep 11 03:26:24 AM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926011036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3926011036
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/217.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1576855477
Short name T246
Test name
Test status
Simulation time 61879342377 ps
CPU time 36.75 seconds
Started Sep 11 03:25:49 AM UTC 24
Finished Sep 11 03:26:27 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576855477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1576855477
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/218.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/219.uart_fifo_reset.3710015546
Short name T1068
Test name
Test status
Simulation time 25387790394 ps
CPU time 22.88 seconds
Started Sep 11 03:25:51 AM UTC 24
Finished Sep 11 03:26:15 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710015546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3710015546
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/219.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_alert_test.1867504785
Short name T501
Test name
Test status
Simulation time 31287094 ps
CPU time 0.86 seconds
Started Sep 11 03:05:11 AM UTC 24
Finished Sep 11 03:05:13 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867504785 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.1867504785
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.3324140270
Short name T369
Test name
Test status
Simulation time 104470363900 ps
CPU time 90.33 seconds
Started Sep 11 03:04:35 AM UTC 24
Finished Sep 11 03:06:07 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324140270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3324140270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_fifo_reset.4088035227
Short name T387
Test name
Test status
Simulation time 21848209567 ps
CPU time 18.88 seconds
Started Sep 11 03:04:36 AM UTC 24
Finished Sep 11 03:04:56 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088035227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4088035227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_intr.1731109171
Short name T496
Test name
Test status
Simulation time 12160059298 ps
CPU time 21.53 seconds
Started Sep 11 03:04:43 AM UTC 24
Finished Sep 11 03:05:06 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731109171 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1731109171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.3761969809
Short name T559
Test name
Test status
Simulation time 160758948875 ps
CPU time 166.92 seconds
Started Sep 11 03:05:06 AM UTC 24
Finished Sep 11 03:07:56 AM UTC 24
Peak memory 208704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761969809 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.3761969809
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_loopback.2982029929
Short name T498
Test name
Test status
Simulation time 5015552356 ps
CPU time 12.62 seconds
Started Sep 11 03:04:55 AM UTC 24
Finished Sep 11 03:05:09 AM UTC 24
Peak memory 208636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982029929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2982029929
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_noise_filter.1756289051
Short name T518
Test name
Test status
Simulation time 245878624760 ps
CPU time 81.66 seconds
Started Sep 11 03:04:47 AM UTC 24
Finished Sep 11 03:06:10 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756289051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.1756289051
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_perf.3421604655
Short name T560
Test name
Test status
Simulation time 15491312255 ps
CPU time 177.81 seconds
Started Sep 11 03:04:57 AM UTC 24
Finished Sep 11 03:07:58 AM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421604655 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3421604655
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_rx_oversample.1087425747
Short name T500
Test name
Test status
Simulation time 4182719751 ps
CPU time 33.35 seconds
Started Sep 11 03:04:36 AM UTC 24
Finished Sep 11 03:05:10 AM UTC 24
Peak memory 207204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087425747 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1087425747
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.4241707417
Short name T153
Test name
Test status
Simulation time 116963615870 ps
CPU time 43.16 seconds
Started Sep 11 03:04:53 AM UTC 24
Finished Sep 11 03:05:38 AM UTC 24
Peak memory 208376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241707417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4241707417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.923890437
Short name T494
Test name
Test status
Simulation time 4448331926 ps
CPU time 2.66 seconds
Started Sep 11 03:04:49 AM UTC 24
Finished Sep 11 03:04:53 AM UTC 24
Peak memory 205012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923890437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.923890437
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_smoke.3941507628
Short name T489
Test name
Test status
Simulation time 631868885 ps
CPU time 2.67 seconds
Started Sep 11 03:04:30 AM UTC 24
Finished Sep 11 03:04:34 AM UTC 24
Peak memory 207084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941507628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3941507628
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_stress_all.4093646966
Short name T505
Test name
Test status
Simulation time 25909236332 ps
CPU time 11.74 seconds
Started Sep 11 03:05:10 AM UTC 24
Finished Sep 11 03:05:22 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093646966 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.4093646966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.3112066891
Short name T192
Test name
Test status
Simulation time 20871878289 ps
CPU time 78.54 seconds
Started Sep 11 03:05:09 AM UTC 24
Finished Sep 11 03:06:29 AM UTC 24
Peak memory 225332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3112066891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all
_with_rand_reset.3112066891
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.18224787
Short name T497
Test name
Test status
Simulation time 8726708893 ps
CPU time 13.51 seconds
Started Sep 11 03:04:53 AM UTC 24
Finished Sep 11 03:05:08 AM UTC 24
Peak memory 208572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18224787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.18224787
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/22.uart_tx_rx.706166454
Short name T533
Test name
Test status
Simulation time 42650362705 ps
CPU time 129.42 seconds
Started Sep 11 03:04:34 AM UTC 24
Finished Sep 11 03:06:45 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706166454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.706166454
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/22.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/220.uart_fifo_reset.1568872701
Short name T1076
Test name
Test status
Simulation time 48378077442 ps
CPU time 43.05 seconds
Started Sep 11 03:25:53 AM UTC 24
Finished Sep 11 03:26:37 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568872701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1568872701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/220.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/221.uart_fifo_reset.218086443
Short name T1110
Test name
Test status
Simulation time 97829256105 ps
CPU time 87.61 seconds
Started Sep 11 03:25:54 AM UTC 24
Finished Sep 11 03:27:23 AM UTC 24
Peak memory 208876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218086443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.218086443
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/221.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/222.uart_fifo_reset.3130112348
Short name T238
Test name
Test status
Simulation time 39081836955 ps
CPU time 26.6 seconds
Started Sep 11 03:25:55 AM UTC 24
Finished Sep 11 03:26:23 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130112348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3130112348
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/222.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/223.uart_fifo_reset.3964152640
Short name T1078
Test name
Test status
Simulation time 85790208555 ps
CPU time 42.14 seconds
Started Sep 11 03:25:56 AM UTC 24
Finished Sep 11 03:26:40 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964152640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3964152640
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/223.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/225.uart_fifo_reset.1758923659
Short name T1084
Test name
Test status
Simulation time 52076473363 ps
CPU time 40.21 seconds
Started Sep 11 03:26:08 AM UTC 24
Finished Sep 11 03:26:50 AM UTC 24
Peak memory 208704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758923659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.1758923659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/225.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/226.uart_fifo_reset.1375685541
Short name T1070
Test name
Test status
Simulation time 36089441811 ps
CPU time 12.54 seconds
Started Sep 11 03:26:09 AM UTC 24
Finished Sep 11 03:26:23 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375685541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1375685541
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/226.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/227.uart_fifo_reset.213387152
Short name T1077
Test name
Test status
Simulation time 9111147369 ps
CPU time 27.26 seconds
Started Sep 11 03:26:11 AM UTC 24
Finished Sep 11 03:26:39 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213387152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.213387152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/227.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/228.uart_fifo_reset.233849544
Short name T1104
Test name
Test status
Simulation time 61462205572 ps
CPU time 58.49 seconds
Started Sep 11 03:26:16 AM UTC 24
Finished Sep 11 03:27:16 AM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233849544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.233849544
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/228.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/229.uart_fifo_reset.4129677214
Short name T1081
Test name
Test status
Simulation time 9016786311 ps
CPU time 26.76 seconds
Started Sep 11 03:26:17 AM UTC 24
Finished Sep 11 03:26:45 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129677214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.4129677214
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/229.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_alert_test.241405482
Short name T510
Test name
Test status
Simulation time 70880656 ps
CPU time 0.86 seconds
Started Sep 11 03:05:34 AM UTC 24
Finished Sep 11 03:05:36 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241405482 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.241405482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_fifo_full.956925950
Short name T138
Test name
Test status
Simulation time 143144347522 ps
CPU time 128.17 seconds
Started Sep 11 03:05:14 AM UTC 24
Finished Sep 11 03:07:24 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956925950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.956925950
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.2733612052
Short name T139
Test name
Test status
Simulation time 94639235136 ps
CPU time 256.94 seconds
Started Sep 11 03:05:17 AM UTC 24
Finished Sep 11 03:09:38 AM UTC 24
Peak memory 208808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733612052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2733612052
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_intr.3137672162
Short name T536
Test name
Test status
Simulation time 50790581473 ps
CPU time 96.29 seconds
Started Sep 11 03:05:19 AM UTC 24
Finished Sep 11 03:06:57 AM UTC 24
Peak memory 208704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137672162 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3137672162
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.3301386900
Short name T617
Test name
Test status
Simulation time 177581621329 ps
CPU time 298.47 seconds
Started Sep 11 03:05:29 AM UTC 24
Finished Sep 11 03:10:31 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301386900 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3301386900
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_loopback.4126398144
Short name T509
Test name
Test status
Simulation time 5206561600 ps
CPU time 8.94 seconds
Started Sep 11 03:05:25 AM UTC 24
Finished Sep 11 03:05:35 AM UTC 24
Peak memory 205284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126398144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.uart_loopback.4126398144
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_noise_filter.2227256067
Short name T391
Test name
Test status
Simulation time 143454943617 ps
CPU time 171 seconds
Started Sep 11 03:05:21 AM UTC 24
Finished Sep 11 03:08:15 AM UTC 24
Peak memory 207896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227256067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2227256067
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_perf.1904033321
Short name T620
Test name
Test status
Simulation time 4684555497 ps
CPU time 307.53 seconds
Started Sep 11 03:05:26 AM UTC 24
Finished Sep 11 03:10:37 AM UTC 24
Peak memory 208972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904033321 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1904033321
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_rx_oversample.2168599597
Short name T508
Test name
Test status
Simulation time 4636711696 ps
CPU time 13.85 seconds
Started Sep 11 03:05:18 AM UTC 24
Finished Sep 11 03:05:33 AM UTC 24
Peak memory 207848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168599597 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2168599597
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.85114488
Short name T344
Test name
Test status
Simulation time 21423582868 ps
CPU time 31.56 seconds
Started Sep 11 03:05:23 AM UTC 24
Finished Sep 11 03:05:56 AM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85114488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.85114488
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.3721633048
Short name T506
Test name
Test status
Simulation time 3146447235 ps
CPU time 1.89 seconds
Started Sep 11 03:05:22 AM UTC 24
Finished Sep 11 03:05:25 AM UTC 24
Peak memory 204492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721633048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.3721633048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_smoke.45357661
Short name T502
Test name
Test status
Simulation time 444118053 ps
CPU time 3.92 seconds
Started Sep 11 03:05:12 AM UTC 24
Finished Sep 11 03:05:17 AM UTC 24
Peak memory 208284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45357661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_smoke.45357661
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_stress_all.2231633097
Short name T1174
Test name
Test status
Simulation time 755828675722 ps
CPU time 1469.14 seconds
Started Sep 11 03:05:31 AM UTC 24
Finished Sep 11 03:30:15 AM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231633097 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.2231633097
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.2281394933
Short name T82
Test name
Test status
Simulation time 9809990621 ps
CPU time 54.94 seconds
Started Sep 11 03:05:30 AM UTC 24
Finished Sep 11 03:06:26 AM UTC 24
Peak memory 221800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2281394933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all
_with_rand_reset.2281394933
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.2062440925
Short name T507
Test name
Test status
Simulation time 2376916698 ps
CPU time 3.78 seconds
Started Sep 11 03:05:24 AM UTC 24
Finished Sep 11 03:05:28 AM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062440925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2062440925
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/23.uart_tx_rx.170441308
Short name T400
Test name
Test status
Simulation time 97121992061 ps
CPU time 50.81 seconds
Started Sep 11 03:05:13 AM UTC 24
Finished Sep 11 03:06:05 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170441308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.170441308
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/23.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/230.uart_fifo_reset.551596577
Short name T1168
Test name
Test status
Simulation time 312674137204 ps
CPU time 193.4 seconds
Started Sep 11 03:26:17 AM UTC 24
Finished Sep 11 03:29:33 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551596577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.551596577
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/230.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/231.uart_fifo_reset.1937501733
Short name T1089
Test name
Test status
Simulation time 62036552470 ps
CPU time 31.02 seconds
Started Sep 11 03:26:24 AM UTC 24
Finished Sep 11 03:26:56 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937501733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1937501733
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/231.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/232.uart_fifo_reset.3939805200
Short name T1087
Test name
Test status
Simulation time 18022979179 ps
CPU time 28.35 seconds
Started Sep 11 03:26:24 AM UTC 24
Finished Sep 11 03:26:53 AM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939805200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3939805200
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/232.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/233.uart_fifo_reset.897201778
Short name T1107
Test name
Test status
Simulation time 44018720055 ps
CPU time 52.45 seconds
Started Sep 11 03:26:25 AM UTC 24
Finished Sep 11 03:27:19 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897201778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.897201778
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/233.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/234.uart_fifo_reset.1041719500
Short name T1095
Test name
Test status
Simulation time 18748210593 ps
CPU time 33.95 seconds
Started Sep 11 03:26:26 AM UTC 24
Finished Sep 11 03:27:01 AM UTC 24
Peak memory 208708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041719500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1041719500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/234.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/235.uart_fifo_reset.3292829791
Short name T1103
Test name
Test status
Simulation time 47499047829 ps
CPU time 42.92 seconds
Started Sep 11 03:26:28 AM UTC 24
Finished Sep 11 03:27:12 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292829791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3292829791
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/235.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/236.uart_fifo_reset.1832633004
Short name T1170
Test name
Test status
Simulation time 102552236687 ps
CPU time 199.52 seconds
Started Sep 11 03:26:29 AM UTC 24
Finished Sep 11 03:29:52 AM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832633004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1832633004
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/236.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/237.uart_fifo_reset.269866137
Short name T1091
Test name
Test status
Simulation time 24966726585 ps
CPU time 22.7 seconds
Started Sep 11 03:26:34 AM UTC 24
Finished Sep 11 03:26:58 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269866137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.269866137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/237.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/238.uart_fifo_reset.510111645
Short name T1126
Test name
Test status
Simulation time 133031593181 ps
CPU time 66.88 seconds
Started Sep 11 03:26:35 AM UTC 24
Finished Sep 11 03:27:44 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510111645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.510111645
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/238.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1981351987
Short name T1120
Test name
Test status
Simulation time 84502365575 ps
CPU time 54.03 seconds
Started Sep 11 03:26:36 AM UTC 24
Finished Sep 11 03:27:32 AM UTC 24
Peak memory 208800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981351987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1981351987
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/239.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_alert_test.3057006228
Short name T521
Test name
Test status
Simulation time 20185092 ps
CPU time 0.85 seconds
Started Sep 11 03:06:10 AM UTC 24
Finished Sep 11 03:06:12 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057006228 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3057006228
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_fifo_full.2933869650
Short name T537
Test name
Test status
Simulation time 40755450517 ps
CPU time 86.2 seconds
Started Sep 11 03:05:38 AM UTC 24
Finished Sep 11 03:07:06 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933869650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2933869650
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.3730687147
Short name T547
Test name
Test status
Simulation time 102559769311 ps
CPU time 115.89 seconds
Started Sep 11 03:05:38 AM UTC 24
Finished Sep 11 03:07:36 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730687147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3730687147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_fifo_reset.4284256603
Short name T182
Test name
Test status
Simulation time 96585586925 ps
CPU time 111.33 seconds
Started Sep 11 03:05:39 AM UTC 24
Finished Sep 11 03:07:33 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284256603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.4284256603
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_intr.716165456
Short name T544
Test name
Test status
Simulation time 25081669028 ps
CPU time 89.53 seconds
Started Sep 11 03:05:58 AM UTC 24
Finished Sep 11 03:07:29 AM UTC 24
Peak memory 208872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716165456 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.716165456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.4154890368
Short name T541
Test name
Test status
Simulation time 182432641384 ps
CPU time 70.52 seconds
Started Sep 11 03:06:07 AM UTC 24
Finished Sep 11 03:07:19 AM UTC 24
Peak memory 208776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154890368 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.4154890368
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_loopback.2895729821
Short name T522
Test name
Test status
Simulation time 7241612740 ps
CPU time 5.85 seconds
Started Sep 11 03:06:06 AM UTC 24
Finished Sep 11 03:06:13 AM UTC 24
Peak memory 207500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895729821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2895729821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_noise_filter.1183774235
Short name T624
Test name
Test status
Simulation time 90729670495 ps
CPU time 278.52 seconds
Started Sep 11 03:06:00 AM UTC 24
Finished Sep 11 03:10:42 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183774235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1183774235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_perf.2463370966
Short name T857
Test name
Test status
Simulation time 10315330667 ps
CPU time 827.15 seconds
Started Sep 11 03:06:07 AM UTC 24
Finished Sep 11 03:20:04 AM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463370966 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2463370966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_rx_oversample.496002491
Short name T514
Test name
Test status
Simulation time 1983183110 ps
CPU time 17.35 seconds
Started Sep 11 03:05:40 AM UTC 24
Finished Sep 11 03:05:59 AM UTC 24
Peak memory 207216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496002491 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.496002491
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.3382195867
Short name T143
Test name
Test status
Simulation time 118032223572 ps
CPU time 237.14 seconds
Started Sep 11 03:06:00 AM UTC 24
Finished Sep 11 03:10:01 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382195867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3382195867
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.1860939068
Short name T523
Test name
Test status
Simulation time 5594563777 ps
CPU time 17.18 seconds
Started Sep 11 03:06:00 AM UTC 24
Finished Sep 11 03:06:19 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860939068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1860939068
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_smoke.3275703212
Short name T511
Test name
Test status
Simulation time 322403145 ps
CPU time 1.56 seconds
Started Sep 11 03:05:35 AM UTC 24
Finished Sep 11 03:05:38 AM UTC 24
Peak memory 206428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275703212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3275703212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.3264561797
Short name T534
Test name
Test status
Simulation time 2355066767 ps
CPU time 39.54 seconds
Started Sep 11 03:06:07 AM UTC 24
Finished Sep 11 03:06:48 AM UTC 24
Peak memory 217772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3264561797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all
_with_rand_reset.3264561797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.234228945
Short name T519
Test name
Test status
Simulation time 1210285926 ps
CPU time 7.27 seconds
Started Sep 11 03:06:02 AM UTC 24
Finished Sep 11 03:06:11 AM UTC 24
Peak memory 208656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234228945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.234228945
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/24.uart_tx_rx.2686301680
Short name T348
Test name
Test status
Simulation time 98382779479 ps
CPU time 60.68 seconds
Started Sep 11 03:05:37 AM UTC 24
Finished Sep 11 03:06:39 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686301680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2686301680
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/24.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/240.uart_fifo_reset.4006732823
Short name T1106
Test name
Test status
Simulation time 92769220713 ps
CPU time 38.89 seconds
Started Sep 11 03:26:39 AM UTC 24
Finished Sep 11 03:27:19 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006732823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4006732823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/240.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/241.uart_fifo_reset.637504170
Short name T1099
Test name
Test status
Simulation time 72473264410 ps
CPU time 22.39 seconds
Started Sep 11 03:26:40 AM UTC 24
Finished Sep 11 03:27:03 AM UTC 24
Peak memory 208632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637504170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.637504170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/241.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/243.uart_fifo_reset.1405076309
Short name T1135
Test name
Test status
Simulation time 25311455849 ps
CPU time 82.24 seconds
Started Sep 11 03:26:41 AM UTC 24
Finished Sep 11 03:28:05 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405076309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.1405076309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/243.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/244.uart_fifo_reset.3770027695
Short name T207
Test name
Test status
Simulation time 50872161911 ps
CPU time 89.94 seconds
Started Sep 11 03:26:45 AM UTC 24
Finished Sep 11 03:28:17 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770027695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3770027695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/244.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/245.uart_fifo_reset.3037361786
Short name T1118
Test name
Test status
Simulation time 40547250836 ps
CPU time 42.01 seconds
Started Sep 11 03:26:46 AM UTC 24
Finished Sep 11 03:27:30 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037361786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.3037361786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/245.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/246.uart_fifo_reset.3926649088
Short name T1115
Test name
Test status
Simulation time 25015430827 ps
CPU time 40.57 seconds
Started Sep 11 03:26:46 AM UTC 24
Finished Sep 11 03:27:28 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926649088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3926649088
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/246.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/247.uart_fifo_reset.1235540253
Short name T1165
Test name
Test status
Simulation time 131611643108 ps
CPU time 138.86 seconds
Started Sep 11 03:26:46 AM UTC 24
Finished Sep 11 03:29:07 AM UTC 24
Peak memory 208876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235540253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1235540253
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/247.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/248.uart_fifo_reset.3330432235
Short name T1098
Test name
Test status
Simulation time 12357552041 ps
CPU time 13.97 seconds
Started Sep 11 03:26:48 AM UTC 24
Finished Sep 11 03:27:03 AM UTC 24
Peak memory 208664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330432235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3330432235
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/248.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/249.uart_fifo_reset.1345249115
Short name T1116
Test name
Test status
Simulation time 24389092088 ps
CPU time 35.8 seconds
Started Sep 11 03:26:51 AM UTC 24
Finished Sep 11 03:27:28 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345249115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1345249115
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/249.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_alert_test.3290394187
Short name T531
Test name
Test status
Simulation time 35644255 ps
CPU time 0.83 seconds
Started Sep 11 03:06:38 AM UTC 24
Finished Sep 11 03:06:40 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290394187 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3290394187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_fifo_full.3444886445
Short name T546
Test name
Test status
Simulation time 34168291212 ps
CPU time 79.77 seconds
Started Sep 11 03:06:12 AM UTC 24
Finished Sep 11 03:07:33 AM UTC 24
Peak memory 208632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444886445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3444886445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.3558891854
Short name T524
Test name
Test status
Simulation time 20423811913 ps
CPU time 8.44 seconds
Started Sep 11 03:06:12 AM UTC 24
Finished Sep 11 03:06:21 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558891854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3558891854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_fifo_reset.1840932529
Short name T525
Test name
Test status
Simulation time 4152932292 ps
CPU time 12.61 seconds
Started Sep 11 03:06:13 AM UTC 24
Finished Sep 11 03:06:27 AM UTC 24
Peak memory 207428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840932529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1840932529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_intr.2550335458
Short name T564
Test name
Test status
Simulation time 27072060875 ps
CPU time 102.56 seconds
Started Sep 11 03:06:20 AM UTC 24
Finished Sep 11 03:08:05 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550335458 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2550335458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.426255445
Short name T816
Test name
Test status
Simulation time 106464486667 ps
CPU time 691.19 seconds
Started Sep 11 03:06:31 AM UTC 24
Finished Sep 11 03:18:11 AM UTC 24
Peak memory 210276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426255445 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.426255445
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_loopback.661364540
Short name T529
Test name
Test status
Simulation time 3146217807 ps
CPU time 3.6 seconds
Started Sep 11 03:06:29 AM UTC 24
Finished Sep 11 03:06:34 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661364540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_loopback.661364540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_noise_filter.3086693885
Short name T586
Test name
Test status
Simulation time 66847067835 ps
CPU time 166.8 seconds
Started Sep 11 03:06:22 AM UTC 24
Finished Sep 11 03:09:11 AM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086693885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3086693885
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_perf.1667612048
Short name T578
Test name
Test status
Simulation time 4352522548 ps
CPU time 130.18 seconds
Started Sep 11 03:06:30 AM UTC 24
Finished Sep 11 03:08:43 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667612048 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.1667612048
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_rx_oversample.1605972193
Short name T535
Test name
Test status
Simulation time 2982790503 ps
CPU time 37.76 seconds
Started Sep 11 03:06:14 AM UTC 24
Finished Sep 11 03:06:53 AM UTC 24
Peak memory 207204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605972193 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1605972193
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.3638515429
Short name T161
Test name
Test status
Simulation time 73785484472 ps
CPU time 64.94 seconds
Started Sep 11 03:06:27 AM UTC 24
Finished Sep 11 03:07:34 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638515429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3638515429
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.2481756865
Short name T540
Test name
Test status
Simulation time 35864757299 ps
CPU time 52.91 seconds
Started Sep 11 03:06:25 AM UTC 24
Finished Sep 11 03:07:19 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481756865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2481756865
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_smoke.2948374399
Short name T527
Test name
Test status
Simulation time 6033625682 ps
CPU time 18.17 seconds
Started Sep 11 03:06:11 AM UTC 24
Finished Sep 11 03:06:31 AM UTC 24
Peak memory 208592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948374399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2948374399
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_stress_all.2862288456
Short name T675
Test name
Test status
Simulation time 553814952618 ps
CPU time 394.09 seconds
Started Sep 11 03:06:35 AM UTC 24
Finished Sep 11 03:13:14 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862288456 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.2862288456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.704231403
Short name T376
Test name
Test status
Simulation time 4322022907 ps
CPU time 25.37 seconds
Started Sep 11 03:06:33 AM UTC 24
Finished Sep 11 03:06:59 AM UTC 24
Peak memory 217932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=704231403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all_
with_rand_reset.704231403
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.4254965799
Short name T528
Test name
Test status
Simulation time 1345486277 ps
CPU time 3.17 seconds
Started Sep 11 03:06:27 AM UTC 24
Finished Sep 11 03:06:31 AM UTC 24
Peak memory 207888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254965799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.4254965799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/25.uart_tx_rx.404843432
Short name T530
Test name
Test status
Simulation time 54649990513 ps
CPU time 23.95 seconds
Started Sep 11 03:06:12 AM UTC 24
Finished Sep 11 03:06:37 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404843432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.404843432
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/25.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/250.uart_fifo_reset.1011476863
Short name T1127
Test name
Test status
Simulation time 22570548811 ps
CPU time 50.43 seconds
Started Sep 11 03:26:52 AM UTC 24
Finished Sep 11 03:27:45 AM UTC 24
Peak memory 208712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011476863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1011476863
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/250.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/251.uart_fifo_reset.411514626
Short name T247
Test name
Test status
Simulation time 169386140112 ps
CPU time 42.12 seconds
Started Sep 11 03:26:52 AM UTC 24
Finished Sep 11 03:27:36 AM UTC 24
Peak memory 208792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411514626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.411514626
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/251.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/252.uart_fifo_reset.2977772073
Short name T1123
Test name
Test status
Simulation time 108824806623 ps
CPU time 45.13 seconds
Started Sep 11 03:26:53 AM UTC 24
Finished Sep 11 03:27:40 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977772073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2977772073
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/252.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/253.uart_fifo_reset.923661994
Short name T1125
Test name
Test status
Simulation time 131741449300 ps
CPU time 46.17 seconds
Started Sep 11 03:26:55 AM UTC 24
Finished Sep 11 03:27:42 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923661994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.923661994
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/253.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/254.uart_fifo_reset.3896961464
Short name T1158
Test name
Test status
Simulation time 142241098452 ps
CPU time 108.26 seconds
Started Sep 11 03:26:57 AM UTC 24
Finished Sep 11 03:28:48 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896961464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3896961464
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/254.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/255.uart_fifo_reset.1356109226
Short name T1154
Test name
Test status
Simulation time 62919802284 ps
CPU time 102.19 seconds
Started Sep 11 03:26:57 AM UTC 24
Finished Sep 11 03:28:41 AM UTC 24
Peak memory 208648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356109226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1356109226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/255.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/256.uart_fifo_reset.2944323759
Short name T237
Test name
Test status
Simulation time 19636297640 ps
CPU time 16.81 seconds
Started Sep 11 03:26:59 AM UTC 24
Finished Sep 11 03:27:17 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944323759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2944323759
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/256.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2421130572
Short name T204
Test name
Test status
Simulation time 56018945228 ps
CPU time 28.29 seconds
Started Sep 11 03:26:59 AM UTC 24
Finished Sep 11 03:27:29 AM UTC 24
Peak memory 208580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421130572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2421130572
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/257.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/258.uart_fifo_reset.1057752258
Short name T1157
Test name
Test status
Simulation time 252972469164 ps
CPU time 104.26 seconds
Started Sep 11 03:27:00 AM UTC 24
Finished Sep 11 03:28:46 AM UTC 24
Peak memory 208660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057752258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1057752258
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/258.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/259.uart_fifo_reset.3050159022
Short name T1105
Test name
Test status
Simulation time 28799131765 ps
CPU time 16.55 seconds
Started Sep 11 03:27:00 AM UTC 24
Finished Sep 11 03:27:18 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050159022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3050159022
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/259.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_alert_test.3065801415
Short name T543
Test name
Test status
Simulation time 35528569 ps
CPU time 0.83 seconds
Started Sep 11 03:07:26 AM UTC 24
Finished Sep 11 03:07:28 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065801415 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.3065801415
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_fifo_full.1585256070
Short name T603
Test name
Test status
Simulation time 94655669742 ps
CPU time 196.79 seconds
Started Sep 11 03:06:41 AM UTC 24
Finished Sep 11 03:10:01 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585256070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1585256070
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.2299242919
Short name T569
Test name
Test status
Simulation time 23780165365 ps
CPU time 97.44 seconds
Started Sep 11 03:06:42 AM UTC 24
Finished Sep 11 03:08:22 AM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299242919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.2299242919
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_fifo_reset.560985153
Short name T187
Test name
Test status
Simulation time 11081817118 ps
CPU time 25.54 seconds
Started Sep 11 03:06:46 AM UTC 24
Finished Sep 11 03:07:13 AM UTC 24
Peak memory 208912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560985153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.560985153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_intr.671154192
Short name T538
Test name
Test status
Simulation time 27891772869 ps
CPU time 13.11 seconds
Started Sep 11 03:06:54 AM UTC 24
Finished Sep 11 03:07:08 AM UTC 24
Peak memory 207216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671154192 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.671154192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.3040653400
Short name T623
Test name
Test status
Simulation time 41165784133 ps
CPU time 198.39 seconds
Started Sep 11 03:07:20 AM UTC 24
Finished Sep 11 03:10:41 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040653400 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3040653400
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_loopback.4027293965
Short name T551
Test name
Test status
Simulation time 11518530393 ps
CPU time 29.54 seconds
Started Sep 11 03:07:14 AM UTC 24
Finished Sep 11 03:07:45 AM UTC 24
Peak memory 208648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027293965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.4027293965
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_noise_filter.1416321132
Short name T542
Test name
Test status
Simulation time 14996750799 ps
CPU time 25.43 seconds
Started Sep 11 03:06:58 AM UTC 24
Finished Sep 11 03:07:25 AM UTC 24
Peak memory 207608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416321132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.1416321132
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_perf.2553809607
Short name T718
Test name
Test status
Simulation time 6876961902 ps
CPU time 457.02 seconds
Started Sep 11 03:07:16 AM UTC 24
Finished Sep 11 03:14:59 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553809607 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2553809607
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_rx_oversample.2488309613
Short name T552
Test name
Test status
Simulation time 5759862987 ps
CPU time 54.1 seconds
Started Sep 11 03:06:49 AM UTC 24
Finished Sep 11 03:07:45 AM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488309613 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2488309613
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.463119751
Short name T550
Test name
Test status
Simulation time 19540328020 ps
CPU time 32.95 seconds
Started Sep 11 03:07:08 AM UTC 24
Finished Sep 11 03:07:42 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463119751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.463119751
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.1982506710
Short name T548
Test name
Test status
Simulation time 42079756530 ps
CPU time 36.59 seconds
Started Sep 11 03:07:00 AM UTC 24
Finished Sep 11 03:07:38 AM UTC 24
Peak memory 207064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982506710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1982506710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_smoke.1350899154
Short name T532
Test name
Test status
Simulation time 308769672 ps
CPU time 1.46 seconds
Started Sep 11 03:06:39 AM UTC 24
Finished Sep 11 03:06:41 AM UTC 24
Peak memory 206500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350899154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1350899154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.1831916719
Short name T549
Test name
Test status
Simulation time 1777555410 ps
CPU time 19.94 seconds
Started Sep 11 03:07:20 AM UTC 24
Finished Sep 11 03:07:41 AM UTC 24
Peak memory 217844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1831916719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all
_with_rand_reset.1831916719
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.2052695732
Short name T539
Test name
Test status
Simulation time 2383293379 ps
CPU time 3.89 seconds
Started Sep 11 03:07:10 AM UTC 24
Finished Sep 11 03:07:15 AM UTC 24
Peak memory 207284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052695732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2052695732
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/26.uart_tx_rx.999207882
Short name T555
Test name
Test status
Simulation time 31847649900 ps
CPU time 64.73 seconds
Started Sep 11 03:06:40 AM UTC 24
Finished Sep 11 03:07:46 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999207882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.999207882
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/26.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/260.uart_fifo_reset.2246120978
Short name T1136
Test name
Test status
Simulation time 164848531710 ps
CPU time 62.45 seconds
Started Sep 11 03:27:01 AM UTC 24
Finished Sep 11 03:28:05 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246120978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2246120978
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/260.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/261.uart_fifo_reset.2206462475
Short name T1171
Test name
Test status
Simulation time 59511518777 ps
CPU time 167.44 seconds
Started Sep 11 03:27:02 AM UTC 24
Finished Sep 11 03:29:52 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206462475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2206462475
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/261.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/263.uart_fifo_reset.3202275099
Short name T1114
Test name
Test status
Simulation time 56638838932 ps
CPU time 20.12 seconds
Started Sep 11 03:27:04 AM UTC 24
Finished Sep 11 03:27:26 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202275099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3202275099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/263.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/265.uart_fifo_reset.4012753880
Short name T1155
Test name
Test status
Simulation time 43578948090 ps
CPU time 97.82 seconds
Started Sep 11 03:27:04 AM UTC 24
Finished Sep 11 03:28:44 AM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012753880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.4012753880
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/265.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/266.uart_fifo_reset.3687548801
Short name T1109
Test name
Test status
Simulation time 10255572335 ps
CPU time 16.92 seconds
Started Sep 11 03:27:04 AM UTC 24
Finished Sep 11 03:27:23 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687548801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3687548801
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/266.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/267.uart_fifo_reset.288119189
Short name T1131
Test name
Test status
Simulation time 58038989773 ps
CPU time 46.75 seconds
Started Sep 11 03:27:07 AM UTC 24
Finished Sep 11 03:27:55 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288119189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.288119189
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/267.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/268.uart_fifo_reset.3337562727
Short name T1163
Test name
Test status
Simulation time 119494069572 ps
CPU time 111.56 seconds
Started Sep 11 03:27:11 AM UTC 24
Finished Sep 11 03:29:05 AM UTC 24
Peak memory 208784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337562727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3337562727
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/268.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/269.uart_fifo_reset.3046852852
Short name T248
Test name
Test status
Simulation time 36467238072 ps
CPU time 29.4 seconds
Started Sep 11 03:27:13 AM UTC 24
Finished Sep 11 03:27:44 AM UTC 24
Peak memory 208596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046852852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3046852852
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/269.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_alert_test.3826121746
Short name T558
Test name
Test status
Simulation time 41652644 ps
CPU time 0.84 seconds
Started Sep 11 03:07:52 AM UTC 24
Finished Sep 11 03:07:54 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826121746 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3826121746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_fifo_full.585544710
Short name T565
Test name
Test status
Simulation time 20724460232 ps
CPU time 39.65 seconds
Started Sep 11 03:07:32 AM UTC 24
Finished Sep 11 03:08:14 AM UTC 24
Peak memory 208452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585544710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.585544710
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.3969614928
Short name T163
Test name
Test status
Simulation time 41181101667 ps
CPU time 35.01 seconds
Started Sep 11 03:07:33 AM UTC 24
Finished Sep 11 03:08:10 AM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969614928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3969614928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_fifo_reset.867837378
Short name T405
Test name
Test status
Simulation time 81100554574 ps
CPU time 47.7 seconds
Started Sep 11 03:07:34 AM UTC 24
Finished Sep 11 03:08:24 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867837378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.867837378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_intr.3081318386
Short name T583
Test name
Test status
Simulation time 44298907342 ps
CPU time 83.57 seconds
Started Sep 11 03:07:38 AM UTC 24
Finished Sep 11 03:09:03 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081318386 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.3081318386
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.2303786521
Short name T649
Test name
Test status
Simulation time 69961811173 ps
CPU time 233.49 seconds
Started Sep 11 03:07:47 AM UTC 24
Finished Sep 11 03:11:44 AM UTC 24
Peak memory 208904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303786521 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2303786521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_loopback.838530301
Short name T556
Test name
Test status
Simulation time 34339973 ps
CPU time 0.92 seconds
Started Sep 11 03:07:46 AM UTC 24
Finished Sep 11 03:07:48 AM UTC 24
Peak memory 204428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838530301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.uart_loopback.838530301
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_noise_filter.2080107529
Short name T568
Test name
Test status
Simulation time 19242180424 ps
CPU time 38.96 seconds
Started Sep 11 03:07:40 AM UTC 24
Finished Sep 11 03:08:20 AM UTC 24
Peak memory 208008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080107529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2080107529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_perf.3313510844
Short name T406
Test name
Test status
Simulation time 12494577304 ps
CPU time 264.66 seconds
Started Sep 11 03:07:47 AM UTC 24
Finished Sep 11 03:12:15 AM UTC 24
Peak memory 208732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313510844 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3313510844
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_rx_oversample.4134109034
Short name T553
Test name
Test status
Simulation time 3281400944 ps
CPU time 9.84 seconds
Started Sep 11 03:07:35 AM UTC 24
Finished Sep 11 03:07:46 AM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134109034 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4134109034
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.2085748942
Short name T575
Test name
Test status
Simulation time 121939969710 ps
CPU time 56.04 seconds
Started Sep 11 03:07:43 AM UTC 24
Finished Sep 11 03:08:41 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085748942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2085748942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.2086473154
Short name T554
Test name
Test status
Simulation time 5692093711 ps
CPU time 3.11 seconds
Started Sep 11 03:07:42 AM UTC 24
Finished Sep 11 03:07:46 AM UTC 24
Peak memory 205216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086473154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.2086473154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_smoke.1857469947
Short name T545
Test name
Test status
Simulation time 155568753 ps
CPU time 1.21 seconds
Started Sep 11 03:07:29 AM UTC 24
Finished Sep 11 03:07:31 AM UTC 24
Peak memory 206476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857469947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.1857469947
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_stress_all.4240059816
Short name T127
Test name
Test status
Simulation time 178183608743 ps
CPU time 96.49 seconds
Started Sep 11 03:07:49 AM UTC 24
Finished Sep 11 03:09:28 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240059816 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.4240059816
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.2649844279
Short name T377
Test name
Test status
Simulation time 4521402238 ps
CPU time 49.14 seconds
Started Sep 11 03:07:47 AM UTC 24
Finished Sep 11 03:08:38 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2649844279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all
_with_rand_reset.2649844279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.2399034876
Short name T557
Test name
Test status
Simulation time 971439188 ps
CPU time 4.89 seconds
Started Sep 11 03:07:46 AM UTC 24
Finished Sep 11 03:07:52 AM UTC 24
Peak memory 207220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399034876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2399034876
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/27.uart_tx_rx.1635053697
Short name T606
Test name
Test status
Simulation time 78063212060 ps
CPU time 154.55 seconds
Started Sep 11 03:07:30 AM UTC 24
Finished Sep 11 03:10:07 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635053697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1635053697
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/27.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/270.uart_fifo_reset.1161706975
Short name T1121
Test name
Test status
Simulation time 10966929375 ps
CPU time 21.47 seconds
Started Sep 11 03:27:14 AM UTC 24
Finished Sep 11 03:27:37 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161706975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.1161706975
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/270.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/272.uart_fifo_reset.3689762002
Short name T159
Test name
Test status
Simulation time 66220837826 ps
CPU time 44.31 seconds
Started Sep 11 03:27:18 AM UTC 24
Finished Sep 11 03:28:04 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689762002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.3689762002
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/272.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/273.uart_fifo_reset.3804484985
Short name T196
Test name
Test status
Simulation time 71149904819 ps
CPU time 31.75 seconds
Started Sep 11 03:27:19 AM UTC 24
Finished Sep 11 03:27:52 AM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804484985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3804484985
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/273.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/274.uart_fifo_reset.2569699495
Short name T1146
Test name
Test status
Simulation time 148241777149 ps
CPU time 63.53 seconds
Started Sep 11 03:27:20 AM UTC 24
Finished Sep 11 03:28:25 AM UTC 24
Peak memory 208420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569699495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.2569699495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/274.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2933784894
Short name T1151
Test name
Test status
Simulation time 95842153324 ps
CPU time 77.02 seconds
Started Sep 11 03:27:20 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933784894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2933784894
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/275.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/276.uart_fifo_reset.3324946412
Short name T1124
Test name
Test status
Simulation time 29808486133 ps
CPU time 19.43 seconds
Started Sep 11 03:27:21 AM UTC 24
Finished Sep 11 03:27:42 AM UTC 24
Peak memory 208672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324946412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3324946412
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/276.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/277.uart_fifo_reset.4130412499
Short name T1133
Test name
Test status
Simulation time 22237724584 ps
CPU time 33.19 seconds
Started Sep 11 03:27:23 AM UTC 24
Finished Sep 11 03:27:58 AM UTC 24
Peak memory 207596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130412499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.4130412499
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/277.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/278.uart_fifo_reset.3635000437
Short name T1161
Test name
Test status
Simulation time 97631456527 ps
CPU time 89.59 seconds
Started Sep 11 03:27:24 AM UTC 24
Finished Sep 11 03:28:56 AM UTC 24
Peak memory 208404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635000437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3635000437
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/278.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/279.uart_fifo_reset.2628503699
Short name T1132
Test name
Test status
Simulation time 16187390996 ps
CPU time 31.01 seconds
Started Sep 11 03:27:24 AM UTC 24
Finished Sep 11 03:27:57 AM UTC 24
Peak memory 208272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628503699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2628503699
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/279.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_alert_test.3709852372
Short name T571
Test name
Test status
Simulation time 30979095 ps
CPU time 0.82 seconds
Started Sep 11 03:08:25 AM UTC 24
Finished Sep 11 03:08:26 AM UTC 24
Peak memory 204432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709852372 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3709852372
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_fifo_full.2178887628
Short name T590
Test name
Test status
Simulation time 35854137590 ps
CPU time 77.85 seconds
Started Sep 11 03:07:59 AM UTC 24
Finished Sep 11 03:09:18 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178887628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2178887628
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.3677386601
Short name T615
Test name
Test status
Simulation time 149942397480 ps
CPU time 145.97 seconds
Started Sep 11 03:08:00 AM UTC 24
Finished Sep 11 03:10:28 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677386601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.3677386601
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_fifo_reset.2357529833
Short name T174
Test name
Test status
Simulation time 62845142016 ps
CPU time 43.37 seconds
Started Sep 11 03:08:05 AM UTC 24
Finished Sep 11 03:08:50 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357529833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.2357529833
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_intr.4258923124
Short name T566
Test name
Test status
Simulation time 4422330183 ps
CPU time 6.89 seconds
Started Sep 11 03:08:06 AM UTC 24
Finished Sep 11 03:08:14 AM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258923124 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4258923124
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.3650564588
Short name T1017
Test name
Test status
Simulation time 107262224373 ps
CPU time 959.09 seconds
Started Sep 11 03:08:22 AM UTC 24
Finished Sep 11 03:24:32 AM UTC 24
Peak memory 212144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650564588 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3650564588
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_loopback.2663521365
Short name T574
Test name
Test status
Simulation time 9527569737 ps
CPU time 14.64 seconds
Started Sep 11 03:08:20 AM UTC 24
Finished Sep 11 03:08:36 AM UTC 24
Peak memory 207548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663521365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2663521365
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_noise_filter.3412643132
Short name T632
Test name
Test status
Simulation time 222889827841 ps
CPU time 164.78 seconds
Started Sep 11 03:08:11 AM UTC 24
Finished Sep 11 03:10:58 AM UTC 24
Peak memory 208896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412643132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.3412643132
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_perf.341816518
Short name T584
Test name
Test status
Simulation time 4424844764 ps
CPU time 44.83 seconds
Started Sep 11 03:08:21 AM UTC 24
Finished Sep 11 03:09:08 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341816518 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.341816518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_rx_oversample.4220939241
Short name T579
Test name
Test status
Simulation time 4284828788 ps
CPU time 48.17 seconds
Started Sep 11 03:08:05 AM UTC 24
Finished Sep 11 03:08:54 AM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220939241 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.4220939241
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.1286924339
Short name T604
Test name
Test status
Simulation time 59511979986 ps
CPU time 105.56 seconds
Started Sep 11 03:08:15 AM UTC 24
Finished Sep 11 03:10:03 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286924339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1286924339
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.1385077615
Short name T570
Test name
Test status
Simulation time 1876785097 ps
CPU time 7.74 seconds
Started Sep 11 03:08:14 AM UTC 24
Finished Sep 11 03:08:23 AM UTC 24
Peak memory 205024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385077615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.1385077615
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_smoke.1115763506
Short name T561
Test name
Test status
Simulation time 626175137 ps
CPU time 2.42 seconds
Started Sep 11 03:07:55 AM UTC 24
Finished Sep 11 03:07:59 AM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115763506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1115763506
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_stress_all_with_rand_reset.1952472995
Short name T588
Test name
Test status
Simulation time 8412072264 ps
CPU time 50.2 seconds
Started Sep 11 03:08:24 AM UTC 24
Finished Sep 11 03:09:15 AM UTC 24
Peak memory 224208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1952472995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all
_with_rand_reset.1952472995
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.2638074695
Short name T567
Test name
Test status
Simulation time 1679969303 ps
CPU time 2.4 seconds
Started Sep 11 03:08:16 AM UTC 24
Finished Sep 11 03:08:20 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638074695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2638074695
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/28.uart_tx_rx.481400187
Short name T396
Test name
Test status
Simulation time 128324500839 ps
CPU time 131.25 seconds
Started Sep 11 03:07:57 AM UTC 24
Finished Sep 11 03:10:10 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481400187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.481400187
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/28.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/280.uart_fifo_reset.3687746379
Short name T1129
Test name
Test status
Simulation time 181537286967 ps
CPU time 21.57 seconds
Started Sep 11 03:27:24 AM UTC 24
Finished Sep 11 03:27:47 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687746379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3687746379
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/280.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/281.uart_fifo_reset.1285805133
Short name T1150
Test name
Test status
Simulation time 69930355147 ps
CPU time 71.12 seconds
Started Sep 11 03:27:26 AM UTC 24
Finished Sep 11 03:28:38 AM UTC 24
Peak memory 208592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285805133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.1285805133
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/281.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/283.uart_fifo_reset.1158835049
Short name T1167
Test name
Test status
Simulation time 243155732369 ps
CPU time 122.52 seconds
Started Sep 11 03:27:27 AM UTC 24
Finished Sep 11 03:29:31 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158835049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.1158835049
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/283.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/284.uart_fifo_reset.2292310543
Short name T1147
Test name
Test status
Simulation time 122957329814 ps
CPU time 56.16 seconds
Started Sep 11 03:27:29 AM UTC 24
Finished Sep 11 03:28:27 AM UTC 24
Peak memory 208640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292310543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2292310543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/284.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/285.uart_fifo_reset.314318275
Short name T1175
Test name
Test status
Simulation time 112507361287 ps
CPU time 196.47 seconds
Started Sep 11 03:27:29 AM UTC 24
Finished Sep 11 03:30:48 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314318275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.314318275
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/285.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/286.uart_fifo_reset.2604761958
Short name T1139
Test name
Test status
Simulation time 113988072890 ps
CPU time 43.12 seconds
Started Sep 11 03:27:30 AM UTC 24
Finished Sep 11 03:28:14 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604761958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2604761958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/286.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/288.uart_fifo_reset.2115145679
Short name T1164
Test name
Test status
Simulation time 46322990868 ps
CPU time 94.35 seconds
Started Sep 11 03:27:30 AM UTC 24
Finished Sep 11 03:29:07 AM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115145679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2115145679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/288.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/289.uart_fifo_reset.3689553212
Short name T1159
Test name
Test status
Simulation time 37863075091 ps
CPU time 78.89 seconds
Started Sep 11 03:27:32 AM UTC 24
Finished Sep 11 03:28:53 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689553212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3689553212
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/289.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_alert_test.316994521
Short name T585
Test name
Test status
Simulation time 15789495 ps
CPU time 0.85 seconds
Started Sep 11 03:09:08 AM UTC 24
Finished Sep 11 03:09:10 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316994521 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.316994521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_fifo_full.1597035902
Short name T315
Test name
Test status
Simulation time 40719085466 ps
CPU time 64.77 seconds
Started Sep 11 03:08:31 AM UTC 24
Finished Sep 11 03:09:37 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597035902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1597035902
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.372393693
Short name T622
Test name
Test status
Simulation time 32361080574 ps
CPU time 121.62 seconds
Started Sep 11 03:08:37 AM UTC 24
Finished Sep 11 03:10:41 AM UTC 24
Peak memory 208712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372393693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.372393693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_fifo_reset.3078827633
Short name T701
Test name
Test status
Simulation time 99899171671 ps
CPU time 335.19 seconds
Started Sep 11 03:08:39 AM UTC 24
Finished Sep 11 03:14:19 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078827633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.3078827633
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_intr.639319309
Short name T580
Test name
Test status
Simulation time 18062208376 ps
CPU time 14.42 seconds
Started Sep 11 03:08:41 AM UTC 24
Finished Sep 11 03:08:57 AM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639319309 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.639319309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.2847161369
Short name T850
Test name
Test status
Simulation time 179261534655 ps
CPU time 596.68 seconds
Started Sep 11 03:09:01 AM UTC 24
Finished Sep 11 03:19:05 AM UTC 24
Peak memory 208948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847161369 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2847161369
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_loopback.2047356977
Short name T592
Test name
Test status
Simulation time 9072696775 ps
CPU time 24.33 seconds
Started Sep 11 03:08:58 AM UTC 24
Finished Sep 11 03:09:23 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047356977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2047356977
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_noise_filter.1875451440
Short name T683
Test name
Test status
Simulation time 61930331597 ps
CPU time 286.66 seconds
Started Sep 11 03:08:43 AM UTC 24
Finished Sep 11 03:13:34 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875451440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.1875451440
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_perf.3530071029
Short name T812
Test name
Test status
Simulation time 14133163008 ps
CPU time 534.17 seconds
Started Sep 11 03:09:00 AM UTC 24
Finished Sep 11 03:18:01 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530071029 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3530071029
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_rx_oversample.660572507
Short name T577
Test name
Test status
Simulation time 3580726224 ps
CPU time 10.69 seconds
Started Sep 11 03:08:41 AM UTC 24
Finished Sep 11 03:08:53 AM UTC 24
Peak memory 207792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660572507 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.660572507
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.621542720
Short name T587
Test name
Test status
Simulation time 42551950951 ps
CPU time 16.9 seconds
Started Sep 11 03:08:53 AM UTC 24
Finished Sep 11 03:09:12 AM UTC 24
Peak memory 208236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621542720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.621542720
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.1571929663
Short name T582
Test name
Test status
Simulation time 38367663140 ps
CPU time 11.39 seconds
Started Sep 11 03:08:50 AM UTC 24
Finished Sep 11 03:09:03 AM UTC 24
Peak memory 205216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571929663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.1571929663
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_smoke.3030973200
Short name T573
Test name
Test status
Simulation time 990470651 ps
CPU time 2.44 seconds
Started Sep 11 03:08:27 AM UTC 24
Finished Sep 11 03:08:30 AM UTC 24
Peak memory 208112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030973200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3030973200
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_stress_all.1285914849
Short name T789
Test name
Test status
Simulation time 329807718519 ps
CPU time 486.08 seconds
Started Sep 11 03:09:04 AM UTC 24
Finished Sep 11 03:17:16 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285914849 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1285914849
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.203053731
Short name T619
Test name
Test status
Simulation time 4995072364 ps
CPU time 90.77 seconds
Started Sep 11 03:09:04 AM UTC 24
Finished Sep 11 03:10:37 AM UTC 24
Peak memory 219828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=203053731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all_
with_rand_reset.203053731
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.1927261567
Short name T359
Test name
Test status
Simulation time 1136548272 ps
CPU time 2.38 seconds
Started Sep 11 03:08:56 AM UTC 24
Finished Sep 11 03:08:59 AM UTC 24
Peak memory 207480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927261567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1927261567
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/29.uart_tx_rx.381068344
Short name T581
Test name
Test status
Simulation time 56739536805 ps
CPU time 31.2 seconds
Started Sep 11 03:08:28 AM UTC 24
Finished Sep 11 03:09:00 AM UTC 24
Peak memory 208560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381068344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.381068344
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/29.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/290.uart_fifo_reset.814223260
Short name T1144
Test name
Test status
Simulation time 123274138065 ps
CPU time 47.23 seconds
Started Sep 11 03:27:33 AM UTC 24
Finished Sep 11 03:28:22 AM UTC 24
Peak memory 208872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814223260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.814223260
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/290.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1317078598
Short name T1177
Test name
Test status
Simulation time 169200857102 ps
CPU time 297.16 seconds
Started Sep 11 03:27:36 AM UTC 24
Finished Sep 11 03:32:38 AM UTC 24
Peak memory 212432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317078598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1317078598
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/291.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/292.uart_fifo_reset.803873210
Short name T1142
Test name
Test status
Simulation time 44113997488 ps
CPU time 39.04 seconds
Started Sep 11 03:27:37 AM UTC 24
Finished Sep 11 03:28:18 AM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803873210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.803873210
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/292.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/293.uart_fifo_reset.1044828920
Short name T147
Test name
Test status
Simulation time 156809144666 ps
CPU time 64.48 seconds
Started Sep 11 03:27:37 AM UTC 24
Finished Sep 11 03:28:43 AM UTC 24
Peak memory 208624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044828920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1044828920
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/293.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/294.uart_fifo_reset.2026216303
Short name T1140
Test name
Test status
Simulation time 13329968438 ps
CPU time 34.66 seconds
Started Sep 11 03:27:39 AM UTC 24
Finished Sep 11 03:28:15 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026216303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2026216303
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/294.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/295.uart_fifo_reset.3949447333
Short name T234
Test name
Test status
Simulation time 326313350814 ps
CPU time 87.63 seconds
Started Sep 11 03:27:41 AM UTC 24
Finished Sep 11 03:29:10 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949447333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3949447333
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/295.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/297.uart_fifo_reset.2901105532
Short name T1141
Test name
Test status
Simulation time 70012162796 ps
CPU time 31.44 seconds
Started Sep 11 03:27:43 AM UTC 24
Finished Sep 11 03:28:15 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901105532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2901105532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/297.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/298.uart_fifo_reset.2595892503
Short name T1138
Test name
Test status
Simulation time 85871839263 ps
CPU time 26.41 seconds
Started Sep 11 03:27:45 AM UTC 24
Finished Sep 11 03:28:12 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595892503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2595892503
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/298.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3252602438
Short name T1166
Test name
Test status
Simulation time 187460051360 ps
CPU time 103.43 seconds
Started Sep 11 03:27:45 AM UTC 24
Finished Sep 11 03:29:30 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252602438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3252602438
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/299.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_alert_test.2757203456
Short name T407
Test name
Test status
Simulation time 45755972 ps
CPU time 0.83 seconds
Started Sep 11 02:56:36 AM UTC 24
Finished Sep 11 02:56:38 AM UTC 24
Peak memory 204372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757203456 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2757203456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_fifo_full.1423250387
Short name T307
Test name
Test status
Simulation time 129611025523 ps
CPU time 174.79 seconds
Started Sep 11 02:56:24 AM UTC 24
Finished Sep 11 02:59:21 AM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423250387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1423250387
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_fifo_reset.1489661707
Short name T86
Test name
Test status
Simulation time 53299416150 ps
CPU time 42.03 seconds
Started Sep 11 02:56:25 AM UTC 24
Finished Sep 11 02:57:08 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489661707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1489661707
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_intr.1793556800
Short name T18
Test name
Test status
Simulation time 48686805177 ps
CPU time 38.65 seconds
Started Sep 11 02:56:26 AM UTC 24
Finished Sep 11 02:57:06 AM UTC 24
Peak memory 208288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793556800 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1793556800
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.2294750181
Short name T337
Test name
Test status
Simulation time 189202237735 ps
CPU time 252.11 seconds
Started Sep 11 02:56:30 AM UTC 24
Finished Sep 11 03:00:45 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294750181 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2294750181
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_loopback.2915005502
Short name T40
Test name
Test status
Simulation time 11712209889 ps
CPU time 13.67 seconds
Started Sep 11 02:56:28 AM UTC 24
Finished Sep 11 02:56:43 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915005502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2915005502
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_noise_filter.2313523999
Short name T273
Test name
Test status
Simulation time 34909104680 ps
CPU time 80.85 seconds
Started Sep 11 02:56:26 AM UTC 24
Finished Sep 11 02:57:49 AM UTC 24
Peak memory 207932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313523999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.2313523999
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_perf.3772752781
Short name T285
Test name
Test status
Simulation time 4568226077 ps
CPU time 59.89 seconds
Started Sep 11 02:56:30 AM UTC 24
Finished Sep 11 02:57:31 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772752781 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3772752781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_rx_oversample.1574406859
Short name T411
Test name
Test status
Simulation time 6267099595 ps
CPU time 55.24 seconds
Started Sep 11 02:56:25 AM UTC 24
Finished Sep 11 02:57:22 AM UTC 24
Peak memory 207724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574406859 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1574406859
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.2715817063
Short name T320
Test name
Test status
Simulation time 35890829298 ps
CPU time 78.61 seconds
Started Sep 11 02:56:27 AM UTC 24
Finished Sep 11 02:57:48 AM UTC 24
Peak memory 205020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715817063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2715817063
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_sec_cm.339826329
Short name T76
Test name
Test status
Simulation time 240751262 ps
CPU time 1.38 seconds
Started Sep 11 02:56:36 AM UTC 24
Finished Sep 11 02:56:38 AM UTC 24
Peak memory 237440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339826329 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.339826329
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_smoke.1339652748
Short name T338
Test name
Test status
Simulation time 886074912 ps
CPU time 5.22 seconds
Started Sep 11 02:56:24 AM UTC 24
Finished Sep 11 02:56:30 AM UTC 24
Peak memory 208576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339652748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1339652748
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2674330076
Short name T23
Test name
Test status
Simulation time 7219933015 ps
CPU time 11.06 seconds
Started Sep 11 02:56:27 AM UTC 24
Finished Sep 11 02:56:39 AM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674330076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2674330076
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/3.uart_tx_rx.1765023115
Short name T267
Test name
Test status
Simulation time 280118348634 ps
CPU time 141.68 seconds
Started Sep 11 02:56:24 AM UTC 24
Finished Sep 11 02:58:48 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765023115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1765023115
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/3.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_alert_test.1954817976
Short name T599
Test name
Test status
Simulation time 12299330 ps
CPU time 0.86 seconds
Started Sep 11 03:09:46 AM UTC 24
Finished Sep 11 03:09:49 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954817976 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1954817976
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_fifo_full.2380508279
Short name T605
Test name
Test status
Simulation time 57819226210 ps
CPU time 51.14 seconds
Started Sep 11 03:09:12 AM UTC 24
Finished Sep 11 03:10:05 AM UTC 24
Peak memory 208848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380508279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2380508279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.4241289374
Short name T169
Test name
Test status
Simulation time 245540715911 ps
CPU time 152.61 seconds
Started Sep 11 03:09:16 AM UTC 24
Finished Sep 11 03:11:51 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241289374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4241289374
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_fifo_reset.297273560
Short name T613
Test name
Test status
Simulation time 23257527501 ps
CPU time 66.94 seconds
Started Sep 11 03:09:17 AM UTC 24
Finished Sep 11 03:10:26 AM UTC 24
Peak memory 208808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297273560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.297273560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_intr.3974722533
Short name T594
Test name
Test status
Simulation time 12409246246 ps
CPU time 10.24 seconds
Started Sep 11 03:09:21 AM UTC 24
Finished Sep 11 03:09:32 AM UTC 24
Peak memory 208728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974722533 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3974722533
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.588901724
Short name T948
Test name
Test status
Simulation time 87152068857 ps
CPU time 751.02 seconds
Started Sep 11 03:09:38 AM UTC 24
Finished Sep 11 03:22:18 AM UTC 24
Peak memory 212268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588901724 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.588901724
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_loopback.3361108635
Short name T598
Test name
Test status
Simulation time 2778292308 ps
CPU time 11.53 seconds
Started Sep 11 03:09:33 AM UTC 24
Finished Sep 11 03:09:46 AM UTC 24
Peak memory 207480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361108635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3361108635
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_noise_filter.3457333245
Short name T607
Test name
Test status
Simulation time 76142079202 ps
CPU time 42.64 seconds
Started Sep 11 03:09:24 AM UTC 24
Finished Sep 11 03:10:08 AM UTC 24
Peak memory 208228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457333245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.3457333245
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_perf.897793517
Short name T767
Test name
Test status
Simulation time 7014938843 ps
CPU time 420.4 seconds
Started Sep 11 03:09:38 AM UTC 24
Finished Sep 11 03:16:44 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897793517 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.897793517
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_rx_oversample.4257515519
Short name T593
Test name
Test status
Simulation time 7116875641 ps
CPU time 7.24 seconds
Started Sep 11 03:09:19 AM UTC 24
Finished Sep 11 03:09:28 AM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257515519 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4257515519
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.427114239
Short name T602
Test name
Test status
Simulation time 67034287842 ps
CPU time 29.11 seconds
Started Sep 11 03:09:29 AM UTC 24
Finished Sep 11 03:09:59 AM UTC 24
Peak memory 208596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427114239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.427114239
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.736187494
Short name T595
Test name
Test status
Simulation time 1657584823 ps
CPU time 2.23 seconds
Started Sep 11 03:09:29 AM UTC 24
Finished Sep 11 03:09:32 AM UTC 24
Peak memory 205024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736187494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.736187494
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_smoke.769293518
Short name T589
Test name
Test status
Simulation time 535301294 ps
CPU time 4.37 seconds
Started Sep 11 03:09:11 AM UTC 24
Finished Sep 11 03:09:17 AM UTC 24
Peak memory 207156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769293518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.uart_smoke.769293518
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_stress_all.2356307320
Short name T921
Test name
Test status
Simulation time 655796019538 ps
CPU time 684.23 seconds
Started Sep 11 03:09:45 AM UTC 24
Finished Sep 11 03:21:19 AM UTC 24
Peak memory 222780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356307320 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2356307320
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.1516494099
Short name T597
Test name
Test status
Simulation time 871242099 ps
CPU time 4.78 seconds
Started Sep 11 03:09:38 AM UTC 24
Finished Sep 11 03:09:44 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1516494099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all
_with_rand_reset.1516494099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.3127151890
Short name T596
Test name
Test status
Simulation time 814626689 ps
CPU time 2.56 seconds
Started Sep 11 03:09:33 AM UTC 24
Finished Sep 11 03:09:37 AM UTC 24
Peak memory 207224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127151890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3127151890
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/30.uart_tx_rx.3843666363
Short name T663
Test name
Test status
Simulation time 48842658741 ps
CPU time 207.65 seconds
Started Sep 11 03:09:12 AM UTC 24
Finished Sep 11 03:12:43 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843666363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3843666363
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/30.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_alert_test.3360894581
Short name T616
Test name
Test status
Simulation time 39109634 ps
CPU time 0.72 seconds
Started Sep 11 03:10:27 AM UTC 24
Finished Sep 11 03:10:29 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360894581 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.3360894581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_fifo_full.3896007279
Short name T145
Test name
Test status
Simulation time 139983585317 ps
CPU time 124.61 seconds
Started Sep 11 03:09:55 AM UTC 24
Finished Sep 11 03:12:01 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896007279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3896007279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.3908255123
Short name T659
Test name
Test status
Simulation time 123623823423 ps
CPU time 148.47 seconds
Started Sep 11 03:10:01 AM UTC 24
Finished Sep 11 03:12:32 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908255123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3908255123
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_intr.17160690
Short name T634
Test name
Test status
Simulation time 27897674011 ps
CPU time 54.71 seconds
Started Sep 11 03:10:03 AM UTC 24
Finished Sep 11 03:10:59 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17160690 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.17160690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.2903516225
Short name T873
Test name
Test status
Simulation time 141451720675 ps
CPU time 543.45 seconds
Started Sep 11 03:10:26 AM UTC 24
Finished Sep 11 03:19:36 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903516225 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2903516225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_loopback.4273873510
Short name T621
Test name
Test status
Simulation time 7664360117 ps
CPU time 24.93 seconds
Started Sep 11 03:10:12 AM UTC 24
Finished Sep 11 03:10:39 AM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273873510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.4273873510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_noise_filter.2103674305
Short name T698
Test name
Test status
Simulation time 71993029926 ps
CPU time 242.53 seconds
Started Sep 11 03:10:06 AM UTC 24
Finished Sep 11 03:14:12 AM UTC 24
Peak memory 207680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103674305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2103674305
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_perf.1621190689
Short name T399
Test name
Test status
Simulation time 4468654446 ps
CPU time 64.83 seconds
Started Sep 11 03:10:23 AM UTC 24
Finished Sep 11 03:11:29 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621190689 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1621190689
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_rx_oversample.2395299013
Short name T611
Test name
Test status
Simulation time 4000452574 ps
CPU time 21.63 seconds
Started Sep 11 03:10:02 AM UTC 24
Finished Sep 11 03:10:25 AM UTC 24
Peak memory 207304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395299013 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2395299013
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.2327713298
Short name T660
Test name
Test status
Simulation time 61024925043 ps
CPU time 146.88 seconds
Started Sep 11 03:10:09 AM UTC 24
Finished Sep 11 03:12:39 AM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327713298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.2327713298
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.275780407
Short name T610
Test name
Test status
Simulation time 34024846029 ps
CPU time 15.12 seconds
Started Sep 11 03:10:08 AM UTC 24
Finished Sep 11 03:10:24 AM UTC 24
Peak memory 205280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275780407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.275780407
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_smoke.1172217083
Short name T608
Test name
Test status
Simulation time 5428352432 ps
CPU time 21.34 seconds
Started Sep 11 03:09:49 AM UTC 24
Finished Sep 11 03:10:12 AM UTC 24
Peak memory 208592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172217083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1172217083
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_stress_all.1075398532
Short name T397
Test name
Test status
Simulation time 671405360580 ps
CPU time 593.25 seconds
Started Sep 11 03:10:27 AM UTC 24
Finished Sep 11 03:20:27 AM UTC 24
Peak memory 217780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075398532 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1075398532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.681681768
Short name T673
Test name
Test status
Simulation time 5645701562 ps
CPU time 162.55 seconds
Started Sep 11 03:10:26 AM UTC 24
Finished Sep 11 03:13:11 AM UTC 24
Peak memory 219884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=681681768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all_
with_rand_reset.681681768
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.3419697206
Short name T614
Test name
Test status
Simulation time 8690765400 ps
CPU time 14.71 seconds
Started Sep 11 03:10:11 AM UTC 24
Finished Sep 11 03:10:27 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419697206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3419697206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/31.uart_tx_rx.1296531447
Short name T612
Test name
Test status
Simulation time 33874333932 ps
CPU time 35.1 seconds
Started Sep 11 03:09:50 AM UTC 24
Finished Sep 11 03:10:26 AM UTC 24
Peak memory 207180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296531447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1296531447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/31.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_alert_test.2798688290
Short name T629
Test name
Test status
Simulation time 19447215 ps
CPU time 0.84 seconds
Started Sep 11 03:10:51 AM UTC 24
Finished Sep 11 03:10:53 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798688290 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2798688290
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_fifo_full.634753624
Short name T630
Test name
Test status
Simulation time 81004632391 ps
CPU time 27.02 seconds
Started Sep 11 03:10:29 AM UTC 24
Finished Sep 11 03:10:57 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634753624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.634753624
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.1374026489
Short name T693
Test name
Test status
Simulation time 169216367885 ps
CPU time 208.64 seconds
Started Sep 11 03:10:32 AM UTC 24
Finished Sep 11 03:14:04 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374026489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1374026489
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_fifo_reset.2603390557
Short name T183
Test name
Test status
Simulation time 136757618055 ps
CPU time 23.87 seconds
Started Sep 11 03:10:32 AM UTC 24
Finished Sep 11 03:10:57 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603390557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2603390557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_intr.803020421
Short name T637
Test name
Test status
Simulation time 9057093338 ps
CPU time 31.85 seconds
Started Sep 11 03:10:37 AM UTC 24
Finished Sep 11 03:11:11 AM UTC 24
Peak memory 208868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803020421 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.803020421
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.154376906
Short name T791
Test name
Test status
Simulation time 80969657323 ps
CPU time 387.91 seconds
Started Sep 11 03:10:45 AM UTC 24
Finished Sep 11 03:17:18 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154376906 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.154376906
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_loopback.3372194106
Short name T626
Test name
Test status
Simulation time 2619365106 ps
CPU time 6.6 seconds
Started Sep 11 03:10:42 AM UTC 24
Finished Sep 11 03:10:49 AM UTC 24
Peak memory 207872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372194106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3372194106
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_noise_filter.2232783404
Short name T648
Test name
Test status
Simulation time 52907534088 ps
CPU time 64.24 seconds
Started Sep 11 03:10:38 AM UTC 24
Finished Sep 11 03:11:44 AM UTC 24
Peak memory 208892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232783404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2232783404
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_perf.387264893
Short name T651
Test name
Test status
Simulation time 26611533614 ps
CPU time 69.5 seconds
Started Sep 11 03:10:43 AM UTC 24
Finished Sep 11 03:11:54 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387264893 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.387264893
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_rx_oversample.1831237343
Short name T631
Test name
Test status
Simulation time 6051381974 ps
CPU time 23.02 seconds
Started Sep 11 03:10:33 AM UTC 24
Finished Sep 11 03:10:58 AM UTC 24
Peak memory 208196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831237343 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.1831237343
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.1336236644
Short name T641
Test name
Test status
Simulation time 46986304039 ps
CPU time 45.82 seconds
Started Sep 11 03:10:41 AM UTC 24
Finished Sep 11 03:11:28 AM UTC 24
Peak memory 208892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336236644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1336236644
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.2427325435
Short name T633
Test name
Test status
Simulation time 31121967116 ps
CPU time 17.96 seconds
Started Sep 11 03:10:40 AM UTC 24
Finished Sep 11 03:10:59 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427325435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2427325435
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_smoke.3964897608
Short name T618
Test name
Test status
Simulation time 291372405 ps
CPU time 2.42 seconds
Started Sep 11 03:10:28 AM UTC 24
Finished Sep 11 03:10:31 AM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964897608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3964897608
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_stress_all.982449160
Short name T845
Test name
Test status
Simulation time 223247888536 ps
CPU time 483.63 seconds
Started Sep 11 03:10:50 AM UTC 24
Finished Sep 11 03:19:00 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982449160 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.982449160
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2868859127
Short name T640
Test name
Test status
Simulation time 13113507692 ps
CPU time 25.53 seconds
Started Sep 11 03:10:48 AM UTC 24
Finished Sep 11 03:11:15 AM UTC 24
Peak memory 223904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2868859127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all
_with_rand_reset.2868859127
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.2920388509
Short name T625
Test name
Test status
Simulation time 4885815676 ps
CPU time 4.04 seconds
Started Sep 11 03:10:42 AM UTC 24
Finished Sep 11 03:10:47 AM UTC 24
Peak memory 208380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920388509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2920388509
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/32.uart_tx_rx.1573620498
Short name T627
Test name
Test status
Simulation time 19453393238 ps
CPU time 20.45 seconds
Started Sep 11 03:10:29 AM UTC 24
Finished Sep 11 03:10:51 AM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573620498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1573620498
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/32.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_alert_test.784295389
Short name T644
Test name
Test status
Simulation time 45445014 ps
CPU time 0.83 seconds
Started Sep 11 03:11:29 AM UTC 24
Finished Sep 11 03:11:32 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784295389 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.784295389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_fifo_full.4111546450
Short name T166
Test name
Test status
Simulation time 174861318930 ps
CPU time 259.96 seconds
Started Sep 11 03:10:58 AM UTC 24
Finished Sep 11 03:15:22 AM UTC 24
Peak memory 208868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111546450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4111546450
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.966512747
Short name T670
Test name
Test status
Simulation time 66475192121 ps
CPU time 125.09 seconds
Started Sep 11 03:10:58 AM UTC 24
Finished Sep 11 03:13:06 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966512747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.966512747
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_fifo_reset.1476199716
Short name T201
Test name
Test status
Simulation time 198327539469 ps
CPU time 310.48 seconds
Started Sep 11 03:10:59 AM UTC 24
Finished Sep 11 03:16:13 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476199716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.1476199716
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_intr.3009793114
Short name T647
Test name
Test status
Simulation time 50246285470 ps
CPU time 42.32 seconds
Started Sep 11 03:11:00 AM UTC 24
Finished Sep 11 03:11:43 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009793114 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.3009793114
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.3544118462
Short name T709
Test name
Test status
Simulation time 55078422709 ps
CPU time 197.85 seconds
Started Sep 11 03:11:16 AM UTC 24
Finished Sep 11 03:14:37 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544118462 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.3544118462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_loopback.1881959853
Short name T650
Test name
Test status
Simulation time 8942299315 ps
CPU time 36.17 seconds
Started Sep 11 03:11:14 AM UTC 24
Finished Sep 11 03:11:52 AM UTC 24
Peak memory 208280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881959853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1881959853
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_noise_filter.2741073099
Short name T646
Test name
Test status
Simulation time 87056106985 ps
CPU time 38.54 seconds
Started Sep 11 03:11:00 AM UTC 24
Finished Sep 11 03:11:39 AM UTC 24
Peak memory 217608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741073099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2741073099
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_perf.1740262712
Short name T720
Test name
Test status
Simulation time 2948006722 ps
CPU time 224.35 seconds
Started Sep 11 03:11:15 AM UTC 24
Finished Sep 11 03:15:03 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740262712 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1740262712
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_rx_oversample.3926283775
Short name T638
Test name
Test status
Simulation time 1971594550 ps
CPU time 12.24 seconds
Started Sep 11 03:11:00 AM UTC 24
Finished Sep 11 03:11:13 AM UTC 24
Peak memory 207216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926283775 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3926283775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.2263954269
Short name T672
Test name
Test status
Simulation time 124976063496 ps
CPU time 117.15 seconds
Started Sep 11 03:11:09 AM UTC 24
Finished Sep 11 03:13:09 AM UTC 24
Peak memory 208848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263954269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2263954269
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.283490838
Short name T658
Test name
Test status
Simulation time 35301022152 ps
CPU time 81.58 seconds
Started Sep 11 03:11:06 AM UTC 24
Finished Sep 11 03:12:29 AM UTC 24
Peak memory 205216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283490838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.283490838
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_smoke.2901480535
Short name T635
Test name
Test status
Simulation time 6337362977 ps
CPU time 13.13 seconds
Started Sep 11 03:10:51 AM UTC 24
Finished Sep 11 03:11:05 AM UTC 24
Peak memory 208640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901480535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2901480535
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_stress_all.664572605
Short name T1113
Test name
Test status
Simulation time 211623286882 ps
CPU time 944.82 seconds
Started Sep 11 03:11:29 AM UTC 24
Finished Sep 11 03:27:25 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664572605 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.664572605
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.2195970576
Short name T652
Test name
Test status
Simulation time 7547125710 ps
CPU time 29.39 seconds
Started Sep 11 03:11:28 AM UTC 24
Finished Sep 11 03:11:59 AM UTC 24
Peak memory 224784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2195970576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all
_with_rand_reset.2195970576
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.4094941299
Short name T639
Test name
Test status
Simulation time 996736435 ps
CPU time 2.65 seconds
Started Sep 11 03:11:11 AM UTC 24
Finished Sep 11 03:11:15 AM UTC 24
Peak memory 207888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094941299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.4094941299
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/33.uart_tx_rx.1662265761
Short name T636
Test name
Test status
Simulation time 11168272882 ps
CPU time 12.74 seconds
Started Sep 11 03:10:54 AM UTC 24
Finished Sep 11 03:11:08 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662265761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1662265761
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/33.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_alert_test.4078013814
Short name T656
Test name
Test status
Simulation time 27420855 ps
CPU time 0.83 seconds
Started Sep 11 03:12:06 AM UTC 24
Finished Sep 11 03:12:08 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078013814 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.4078013814
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_fifo_full.418414598
Short name T749
Test name
Test status
Simulation time 119887388708 ps
CPU time 260.4 seconds
Started Sep 11 03:11:33 AM UTC 24
Finished Sep 11 03:15:57 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418414598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.418414598
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.16478694
Short name T666
Test name
Test status
Simulation time 25358829098 ps
CPU time 82.13 seconds
Started Sep 11 03:11:35 AM UTC 24
Finished Sep 11 03:12:59 AM UTC 24
Peak memory 208492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16478694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.16478694
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_fifo_reset.2526888459
Short name T386
Test name
Test status
Simulation time 10301081071 ps
CPU time 21.18 seconds
Started Sep 11 03:11:40 AM UTC 24
Finished Sep 11 03:12:02 AM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526888459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2526888459
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_intr.2172832417
Short name T655
Test name
Test status
Simulation time 23417962901 ps
CPU time 18.9 seconds
Started Sep 11 03:11:45 AM UTC 24
Finished Sep 11 03:12:05 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172832417 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2172832417
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.2683703986
Short name T814
Test name
Test status
Simulation time 65684772832 ps
CPU time 358.18 seconds
Started Sep 11 03:12:03 AM UTC 24
Finished Sep 11 03:18:05 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683703986 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2683703986
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_loopback.670385107
Short name T662
Test name
Test status
Simulation time 12005389251 ps
CPU time 40.46 seconds
Started Sep 11 03:12:00 AM UTC 24
Finished Sep 11 03:12:42 AM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670385107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.uart_loopback.670385107
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_noise_filter.1945538416
Short name T695
Test name
Test status
Simulation time 58690325471 ps
CPU time 140.97 seconds
Started Sep 11 03:11:45 AM UTC 24
Finished Sep 11 03:14:08 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945538416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1945538416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_perf.2797619581
Short name T846
Test name
Test status
Simulation time 7580278118 ps
CPU time 415.37 seconds
Started Sep 11 03:12:01 AM UTC 24
Finished Sep 11 03:19:02 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797619581 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2797619581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_rx_oversample.1476369962
Short name T653
Test name
Test status
Simulation time 5818372627 ps
CPU time 15.24 seconds
Started Sep 11 03:11:44 AM UTC 24
Finished Sep 11 03:12:00 AM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476369962 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1476369962
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.2210507808
Short name T728
Test name
Test status
Simulation time 72784616701 ps
CPU time 205.65 seconds
Started Sep 11 03:11:53 AM UTC 24
Finished Sep 11 03:15:22 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210507808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2210507808
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1204336154
Short name T657
Test name
Test status
Simulation time 41872966668 ps
CPU time 15.09 seconds
Started Sep 11 03:11:52 AM UTC 24
Finished Sep 11 03:12:08 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204336154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1204336154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_smoke.72555515
Short name T645
Test name
Test status
Simulation time 778094900 ps
CPU time 1.91 seconds
Started Sep 11 03:11:31 AM UTC 24
Finished Sep 11 03:11:34 AM UTC 24
Peak memory 207720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72555515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_smoke.72555515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_stress_all.3926917173
Short name T688
Test name
Test status
Simulation time 113226908166 ps
CPU time 104.35 seconds
Started Sep 11 03:12:03 AM UTC 24
Finished Sep 11 03:13:49 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926917173 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3926917173
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.4005872433
Short name T669
Test name
Test status
Simulation time 3395863347 ps
CPU time 58.98 seconds
Started Sep 11 03:12:03 AM UTC 24
Finished Sep 11 03:13:03 AM UTC 24
Peak memory 217784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4005872433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all
_with_rand_reset.4005872433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.698322015
Short name T654
Test name
Test status
Simulation time 673762200 ps
CPU time 5.32 seconds
Started Sep 11 03:11:55 AM UTC 24
Finished Sep 11 03:12:02 AM UTC 24
Peak memory 207560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698322015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.698322015
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/34.uart_tx_rx.1102203954
Short name T676
Test name
Test status
Simulation time 37107433900 ps
CPU time 102.91 seconds
Started Sep 11 03:11:32 AM UTC 24
Finished Sep 11 03:13:17 AM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102203954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1102203954
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/34.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_alert_test.879655694
Short name T671
Test name
Test status
Simulation time 22866031 ps
CPU time 0.85 seconds
Started Sep 11 03:13:06 AM UTC 24
Finished Sep 11 03:13:08 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879655694 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.879655694
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_fifo_full.931287821
Short name T170
Test name
Test status
Simulation time 37025615569 ps
CPU time 29.8 seconds
Started Sep 11 03:12:16 AM UTC 24
Finished Sep 11 03:12:47 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931287821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.931287821
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.2713236137
Short name T686
Test name
Test status
Simulation time 54944812247 ps
CPU time 73.92 seconds
Started Sep 11 03:12:30 AM UTC 24
Finished Sep 11 03:13:46 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713236137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2713236137
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_fifo_reset.28025769
Short name T178
Test name
Test status
Simulation time 25841002821 ps
CPU time 52.68 seconds
Started Sep 11 03:12:32 AM UTC 24
Finished Sep 11 03:13:26 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28025769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.28025769
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_intr.679855354
Short name T664
Test name
Test status
Simulation time 8995749400 ps
CPU time 4.23 seconds
Started Sep 11 03:12:42 AM UTC 24
Finished Sep 11 03:12:48 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679855354 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.679855354
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.3975902797
Short name T1085
Test name
Test status
Simulation time 114038626946 ps
CPU time 821.3 seconds
Started Sep 11 03:13:01 AM UTC 24
Finished Sep 11 03:26:52 AM UTC 24
Peak memory 212204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975902797 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3975902797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_loopback.2665187581
Short name T667
Test name
Test status
Simulation time 3659803698 ps
CPU time 7.58 seconds
Started Sep 11 03:12:51 AM UTC 24
Finished Sep 11 03:13:00 AM UTC 24
Peak memory 207800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665187581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2665187581
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_noise_filter.3336092832
Short name T707
Test name
Test status
Simulation time 95623972124 ps
CPU time 104.21 seconds
Started Sep 11 03:12:43 AM UTC 24
Finished Sep 11 03:14:30 AM UTC 24
Peak memory 207492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336092832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3336092832
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_perf.257653352
Short name T884
Test name
Test status
Simulation time 13817735332 ps
CPU time 403.74 seconds
Started Sep 11 03:13:00 AM UTC 24
Finished Sep 11 03:19:49 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257653352 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.257653352
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_rx_oversample.3794326797
Short name T691
Test name
Test status
Simulation time 5832809149 ps
CPU time 70.95 seconds
Started Sep 11 03:12:39 AM UTC 24
Finished Sep 11 03:13:52 AM UTC 24
Peak memory 207468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794326797 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3794326797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.244908711
Short name T735
Test name
Test status
Simulation time 76214246399 ps
CPU time 171.41 seconds
Started Sep 11 03:12:48 AM UTC 24
Finished Sep 11 03:15:42 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244908711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.244908711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.1935361715
Short name T665
Test name
Test status
Simulation time 3133520611 ps
CPU time 4.05 seconds
Started Sep 11 03:12:45 AM UTC 24
Finished Sep 11 03:12:50 AM UTC 24
Peak memory 205216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935361715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1935361715
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_smoke.3366072426
Short name T661
Test name
Test status
Simulation time 5471329994 ps
CPU time 32.3 seconds
Started Sep 11 03:12:08 AM UTC 24
Finished Sep 11 03:12:41 AM UTC 24
Peak memory 208464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366072426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3366072426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_stress_all.371451540
Short name T881
Test name
Test status
Simulation time 328259215983 ps
CPU time 397.41 seconds
Started Sep 11 03:13:04 AM UTC 24
Finished Sep 11 03:19:46 AM UTC 24
Peak memory 217652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371451540 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.371451540
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.638315143
Short name T679
Test name
Test status
Simulation time 2471030642 ps
CPU time 18.76 seconds
Started Sep 11 03:13:02 AM UTC 24
Finished Sep 11 03:13:22 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=638315143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all_
with_rand_reset.638315143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.3175430811
Short name T668
Test name
Test status
Simulation time 7769673710 ps
CPU time 11.87 seconds
Started Sep 11 03:12:49 AM UTC 24
Finished Sep 11 03:13:02 AM UTC 24
Peak memory 208560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175430811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3175430811
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/35.uart_tx_rx.2910458847
Short name T674
Test name
Test status
Simulation time 77926763500 ps
CPU time 61.11 seconds
Started Sep 11 03:12:09 AM UTC 24
Finished Sep 11 03:13:12 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910458847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2910458847
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/35.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_alert_test.3422128889
Short name T687
Test name
Test status
Simulation time 23850891 ps
CPU time 0.83 seconds
Started Sep 11 03:13:46 AM UTC 24
Finished Sep 11 03:13:48 AM UTC 24
Peak memory 202384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422128889 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3422128889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_fifo_full.3788619610
Short name T158
Test name
Test status
Simulation time 72238899330 ps
CPU time 94.33 seconds
Started Sep 11 03:13:12 AM UTC 24
Finished Sep 11 03:14:49 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788619610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3788619610
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.953847509
Short name T699
Test name
Test status
Simulation time 46828071434 ps
CPU time 59.57 seconds
Started Sep 11 03:13:12 AM UTC 24
Finished Sep 11 03:14:14 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953847509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.953847509
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_fifo_reset.2992786197
Short name T205
Test name
Test status
Simulation time 41164096800 ps
CPU time 85.13 seconds
Started Sep 11 03:13:14 AM UTC 24
Finished Sep 11 03:14:42 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992786197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2992786197
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_intr.1982111768
Short name T697
Test name
Test status
Simulation time 55237461833 ps
CPU time 48.07 seconds
Started Sep 11 03:13:21 AM UTC 24
Finished Sep 11 03:14:10 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982111768 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.1982111768
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.2198276062
Short name T740
Test name
Test status
Simulation time 79072132079 ps
CPU time 129.44 seconds
Started Sep 11 03:13:34 AM UTC 24
Finished Sep 11 03:15:46 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198276062 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2198276062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_loopback.3239510402
Short name T689
Test name
Test status
Simulation time 5217017545 ps
CPU time 17.04 seconds
Started Sep 11 03:13:31 AM UTC 24
Finished Sep 11 03:13:49 AM UTC 24
Peak memory 207876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239510402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3239510402
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_noise_filter.4026369025
Short name T742
Test name
Test status
Simulation time 87077037492 ps
CPU time 143.29 seconds
Started Sep 11 03:13:22 AM UTC 24
Finished Sep 11 03:15:48 AM UTC 24
Peak memory 208456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026369025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.4026369025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_perf.2635234942
Short name T879
Test name
Test status
Simulation time 14550604521 ps
CPU time 363.94 seconds
Started Sep 11 03:13:33 AM UTC 24
Finished Sep 11 03:19:42 AM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635234942 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2635234942
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_rx_oversample.1112006272
Short name T694
Test name
Test status
Simulation time 5453315971 ps
CPU time 48.58 seconds
Started Sep 11 03:13:18 AM UTC 24
Finished Sep 11 03:14:08 AM UTC 24
Peak memory 207596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112006272 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1112006272
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.3560101273
Short name T685
Test name
Test status
Simulation time 42593387713 ps
CPU time 15.85 seconds
Started Sep 11 03:13:25 AM UTC 24
Finished Sep 11 03:13:42 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560101273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3560101273
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.877431775
Short name T684
Test name
Test status
Simulation time 5403382733 ps
CPU time 11.04 seconds
Started Sep 11 03:13:23 AM UTC 24
Finished Sep 11 03:13:35 AM UTC 24
Peak memory 205012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877431775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.877431775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_smoke.96036178
Short name T682
Test name
Test status
Simulation time 6068393251 ps
CPU time 21.87 seconds
Started Sep 11 03:13:09 AM UTC 24
Finished Sep 11 03:13:33 AM UTC 24
Peak memory 207872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96036178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_smoke.96036178
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_stress_all.267722240
Short name T901
Test name
Test status
Simulation time 312908792081 ps
CPU time 408.19 seconds
Started Sep 11 03:13:42 AM UTC 24
Finished Sep 11 03:20:36 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267722240 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.267722240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.1247119171
Short name T708
Test name
Test status
Simulation time 7279596880 ps
CPU time 52.64 seconds
Started Sep 11 03:13:36 AM UTC 24
Finished Sep 11 03:14:30 AM UTC 24
Peak memory 221872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1247119171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all
_with_rand_reset.1247119171
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.3731916510
Short name T681
Test name
Test status
Simulation time 4148877536 ps
CPU time 2.66 seconds
Started Sep 11 03:13:27 AM UTC 24
Finished Sep 11 03:13:31 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731916510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3731916510
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/36.uart_tx_rx.342686507
Short name T780
Test name
Test status
Simulation time 109013857426 ps
CPU time 229.26 seconds
Started Sep 11 03:13:09 AM UTC 24
Finished Sep 11 03:17:02 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342686507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.342686507
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/36.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_alert_test.198397588
Short name T704
Test name
Test status
Simulation time 21767329 ps
CPU time 0.82 seconds
Started Sep 11 03:14:20 AM UTC 24
Finished Sep 11 03:14:21 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198397588 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.198397588
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_fifo_full.751292615
Short name T722
Test name
Test status
Simulation time 43936667196 ps
CPU time 74.42 seconds
Started Sep 11 03:13:51 AM UTC 24
Finished Sep 11 03:15:07 AM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751292615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.751292615
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.1725376898
Short name T719
Test name
Test status
Simulation time 40913246647 ps
CPU time 65.51 seconds
Started Sep 11 03:13:53 AM UTC 24
Finished Sep 11 03:15:00 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725376898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1725376898
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_fifo_reset.3445971546
Short name T394
Test name
Test status
Simulation time 94754195376 ps
CPU time 109.95 seconds
Started Sep 11 03:13:53 AM UTC 24
Finished Sep 11 03:15:45 AM UTC 24
Peak memory 208648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445971546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3445971546
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_intr.1177630760
Short name T715
Test name
Test status
Simulation time 71851984735 ps
CPU time 53.56 seconds
Started Sep 11 03:13:59 AM UTC 24
Finished Sep 11 03:14:54 AM UTC 24
Peak memory 208708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177630760 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1177630760
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.3655208469
Short name T1011
Test name
Test status
Simulation time 127915444822 ps
CPU time 600.64 seconds
Started Sep 11 03:14:14 AM UTC 24
Finished Sep 11 03:24:21 AM UTC 24
Peak memory 212276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655208469 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3655208469
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_loopback.3505991823
Short name T703
Test name
Test status
Simulation time 3835713255 ps
CPU time 8.64 seconds
Started Sep 11 03:14:11 AM UTC 24
Finished Sep 11 03:14:21 AM UTC 24
Peak memory 207284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505991823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3505991823
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_noise_filter.2411024436
Short name T745
Test name
Test status
Simulation time 35415191156 ps
CPU time 102.57 seconds
Started Sep 11 03:14:05 AM UTC 24
Finished Sep 11 03:15:50 AM UTC 24
Peak memory 208428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411024436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2411024436
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_perf.887348515
Short name T795
Test name
Test status
Simulation time 6457908167 ps
CPU time 187.93 seconds
Started Sep 11 03:14:13 AM UTC 24
Finished Sep 11 03:17:24 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887348515 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.887348515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_rx_oversample.2034245997
Short name T692
Test name
Test status
Simulation time 1502353662 ps
CPU time 2.43 seconds
Started Sep 11 03:13:55 AM UTC 24
Finished Sep 11 03:13:58 AM UTC 24
Peak memory 207280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034245997 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2034245997
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.1855543426
Short name T778
Test name
Test status
Simulation time 85656503779 ps
CPU time 167.68 seconds
Started Sep 11 03:14:09 AM UTC 24
Finished Sep 11 03:17:00 AM UTC 24
Peak memory 208724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855543426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1855543426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.569004727
Short name T700
Test name
Test status
Simulation time 5682576929 ps
CPU time 6.46 seconds
Started Sep 11 03:14:08 AM UTC 24
Finished Sep 11 03:14:16 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569004727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.569004727
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_smoke.3649521120
Short name T690
Test name
Test status
Simulation time 436155285 ps
CPU time 2.29 seconds
Started Sep 11 03:13:49 AM UTC 24
Finished Sep 11 03:13:52 AM UTC 24
Peak memory 207160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649521120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3649521120
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_stress_all.2264173371
Short name T1090
Test name
Test status
Simulation time 358912837601 ps
CPU time 752.61 seconds
Started Sep 11 03:14:17 AM UTC 24
Finished Sep 11 03:26:58 AM UTC 24
Peak memory 221112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264173371 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2264173371
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.1431102033
Short name T711
Test name
Test status
Simulation time 2520262765 ps
CPU time 28.66 seconds
Started Sep 11 03:14:15 AM UTC 24
Finished Sep 11 03:14:45 AM UTC 24
Peak memory 217784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1431102033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all
_with_rand_reset.1431102033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.3307509532
Short name T705
Test name
Test status
Simulation time 11307982434 ps
CPU time 10.93 seconds
Started Sep 11 03:14:10 AM UTC 24
Finished Sep 11 03:14:22 AM UTC 24
Peak memory 208776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307509532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3307509532
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/37.uart_tx_rx.1797577241
Short name T696
Test name
Test status
Simulation time 9275963638 ps
CPU time 18.71 seconds
Started Sep 11 03:13:50 AM UTC 24
Finished Sep 11 03:14:09 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797577241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.1797577241
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/37.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_alert_test.4134974841
Short name T716
Test name
Test status
Simulation time 32421541 ps
CPU time 0.82 seconds
Started Sep 11 03:14:53 AM UTC 24
Finished Sep 11 03:14:55 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134974841 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4134974841
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_fifo_full.987665282
Short name T731
Test name
Test status
Simulation time 86620815156 ps
CPU time 65.78 seconds
Started Sep 11 03:14:22 AM UTC 24
Finished Sep 11 03:15:29 AM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987665282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.987665282
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.4055597494
Short name T714
Test name
Test status
Simulation time 36369839163 ps
CPU time 27.86 seconds
Started Sep 11 03:14:23 AM UTC 24
Finished Sep 11 03:14:52 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055597494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.4055597494
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_fifo_reset.1591404799
Short name T173
Test name
Test status
Simulation time 31653410052 ps
CPU time 29.73 seconds
Started Sep 11 03:14:24 AM UTC 24
Finished Sep 11 03:14:55 AM UTC 24
Peak memory 208784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591404799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1591404799
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_intr.3301833599
Short name T736
Test name
Test status
Simulation time 32480873441 ps
CPU time 69.57 seconds
Started Sep 11 03:14:32 AM UTC 24
Finished Sep 11 03:15:43 AM UTC 24
Peak memory 208776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301833599 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3301833599
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.2257885855
Short name T855
Test name
Test status
Simulation time 50567465419 ps
CPU time 261.75 seconds
Started Sep 11 03:14:46 AM UTC 24
Finished Sep 11 03:19:12 AM UTC 24
Peak memory 208776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257885855 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.2257885855
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_loopback.3475304457
Short name T727
Test name
Test status
Simulation time 7371831719 ps
CPU time 36.28 seconds
Started Sep 11 03:14:44 AM UTC 24
Finished Sep 11 03:15:22 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475304457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.3475304457
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_noise_filter.3227420056
Short name T730
Test name
Test status
Simulation time 108784381505 ps
CPU time 51.08 seconds
Started Sep 11 03:14:36 AM UTC 24
Finished Sep 11 03:15:29 AM UTC 24
Peak memory 208732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227420056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3227420056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_perf.264467638
Short name T796
Test name
Test status
Simulation time 7777226931 ps
CPU time 156.68 seconds
Started Sep 11 03:14:45 AM UTC 24
Finished Sep 11 03:17:25 AM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264467638 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.264467638
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1089805523
Short name T712
Test name
Test status
Simulation time 2013431503 ps
CPU time 12.27 seconds
Started Sep 11 03:14:32 AM UTC 24
Finished Sep 11 03:14:45 AM UTC 24
Peak memory 207216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089805523 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1089805523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.1287910283
Short name T768
Test name
Test status
Simulation time 101314497000 ps
CPU time 122.37 seconds
Started Sep 11 03:14:43 AM UTC 24
Finished Sep 11 03:16:47 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287910283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1287910283
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.1183108135
Short name T710
Test name
Test status
Simulation time 5776327244 ps
CPU time 3.2 seconds
Started Sep 11 03:14:38 AM UTC 24
Finished Sep 11 03:14:42 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183108135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1183108135
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_smoke.3582265408
Short name T706
Test name
Test status
Simulation time 750458252 ps
CPU time 1.33 seconds
Started Sep 11 03:14:21 AM UTC 24
Finished Sep 11 03:14:23 AM UTC 24
Peak memory 206312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582265408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3582265408
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_stress_all.4087270521
Short name T810
Test name
Test status
Simulation time 334499461197 ps
CPU time 182.3 seconds
Started Sep 11 03:14:50 AM UTC 24
Finished Sep 11 03:17:56 AM UTC 24
Peak memory 217780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087270521 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.4087270521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.3508540803
Short name T747
Test name
Test status
Simulation time 3038118357 ps
CPU time 60.69 seconds
Started Sep 11 03:14:49 AM UTC 24
Finished Sep 11 03:15:52 AM UTC 24
Peak memory 217932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3508540803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all
_with_rand_reset.3508540803
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.2631720765
Short name T713
Test name
Test status
Simulation time 1060779248 ps
CPU time 5.36 seconds
Started Sep 11 03:14:43 AM UTC 24
Finished Sep 11 03:14:49 AM UTC 24
Peak memory 207716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631720765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2631720765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/38.uart_tx_rx.2589310857
Short name T738
Test name
Test status
Simulation time 34357596972 ps
CPU time 79.53 seconds
Started Sep 11 03:14:22 AM UTC 24
Finished Sep 11 03:15:43 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589310857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2589310857
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/38.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_alert_test.1099755956
Short name T732
Test name
Test status
Simulation time 12944894 ps
CPU time 0.84 seconds
Started Sep 11 03:15:28 AM UTC 24
Finished Sep 11 03:15:30 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099755956 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1099755956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_fifo_full.1069106346
Short name T404
Test name
Test status
Simulation time 129517535059 ps
CPU time 109.2 seconds
Started Sep 11 03:14:57 AM UTC 24
Finished Sep 11 03:16:48 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069106346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1069106346
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.1026013309
Short name T383
Test name
Test status
Simulation time 35704746026 ps
CPU time 74.27 seconds
Started Sep 11 03:14:59 AM UTC 24
Finished Sep 11 03:16:15 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026013309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.1026013309
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_fifo_reset.3313587943
Short name T723
Test name
Test status
Simulation time 15728667683 ps
CPU time 11.93 seconds
Started Sep 11 03:15:00 AM UTC 24
Finished Sep 11 03:15:13 AM UTC 24
Peak memory 208904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313587943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3313587943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_intr.283601381
Short name T737
Test name
Test status
Simulation time 18262322917 ps
CPU time 37.81 seconds
Started Sep 11 03:15:04 AM UTC 24
Finished Sep 11 03:15:43 AM UTC 24
Peak memory 207132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283601381 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.283601381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.4188606388
Short name T851
Test name
Test status
Simulation time 95275438165 ps
CPU time 223.12 seconds
Started Sep 11 03:15:23 AM UTC 24
Finished Sep 11 03:19:09 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188606388 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.4188606388
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_loopback.206258227
Short name T729
Test name
Test status
Simulation time 8897523266 ps
CPU time 6.62 seconds
Started Sep 11 03:15:19 AM UTC 24
Finished Sep 11 03:15:27 AM UTC 24
Peak memory 207908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206258227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_loopback.206258227
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_noise_filter.1352805932
Short name T831
Test name
Test status
Simulation time 126779771037 ps
CPU time 204.83 seconds
Started Sep 11 03:15:06 AM UTC 24
Finished Sep 11 03:18:34 AM UTC 24
Peak memory 217652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352805932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1352805932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_perf.1312076113
Short name T839
Test name
Test status
Simulation time 6468748085 ps
CPU time 204.33 seconds
Started Sep 11 03:15:21 AM UTC 24
Finished Sep 11 03:18:49 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312076113 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1312076113
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_rx_oversample.1516977744
Short name T724
Test name
Test status
Simulation time 5635268694 ps
CPU time 13.36 seconds
Started Sep 11 03:15:01 AM UTC 24
Finished Sep 11 03:15:15 AM UTC 24
Peak memory 207204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516977744 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1516977744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.3976032507
Short name T887
Test name
Test status
Simulation time 334746500674 ps
CPU time 274.2 seconds
Started Sep 11 03:15:13 AM UTC 24
Finished Sep 11 03:19:51 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976032507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3976032507
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.4261825765
Short name T725
Test name
Test status
Simulation time 3696401582 ps
CPU time 10.8 seconds
Started Sep 11 03:15:07 AM UTC 24
Finished Sep 11 03:15:19 AM UTC 24
Peak memory 205216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261825765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.4261825765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_smoke.1894055389
Short name T717
Test name
Test status
Simulation time 445203925 ps
CPU time 2.67 seconds
Started Sep 11 03:14:54 AM UTC 24
Finished Sep 11 03:14:58 AM UTC 24
Peak memory 207452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894055389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1894055389
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_stress_all.1206130941
Short name T813
Test name
Test status
Simulation time 237149015432 ps
CPU time 159.5 seconds
Started Sep 11 03:15:23 AM UTC 24
Finished Sep 11 03:18:05 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206130941 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1206130941
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.3494561120
Short name T171
Test name
Test status
Simulation time 21539514998 ps
CPU time 89.18 seconds
Started Sep 11 03:15:23 AM UTC 24
Finished Sep 11 03:16:54 AM UTC 24
Peak memory 217784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3494561120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all
_with_rand_reset.3494561120
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.3538396156
Short name T726
Test name
Test status
Simulation time 3372323760 ps
CPU time 3.2 seconds
Started Sep 11 03:15:16 AM UTC 24
Finished Sep 11 03:15:21 AM UTC 24
Peak memory 208444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538396156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.3538396156
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/39.uart_tx_rx.158206738
Short name T392
Test name
Test status
Simulation time 186050824002 ps
CPU time 44.57 seconds
Started Sep 11 03:14:56 AM UTC 24
Finished Sep 11 03:15:42 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158206738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.158206738
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/39.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_alert_test.3419490040
Short name T75
Test name
Test status
Simulation time 11972745 ps
CPU time 0.8 seconds
Started Sep 11 02:56:51 AM UTC 24
Finished Sep 11 02:56:53 AM UTC 24
Peak memory 203880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419490040 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3419490040
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_fifo_full.4180747574
Short name T117
Test name
Test status
Simulation time 106937902942 ps
CPU time 207.25 seconds
Started Sep 11 02:56:39 AM UTC 24
Finished Sep 11 03:00:10 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180747574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.4180747574
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.3409806714
Short name T43
Test name
Test status
Simulation time 7523334521 ps
CPU time 7.28 seconds
Started Sep 11 02:56:40 AM UTC 24
Finished Sep 11 02:56:49 AM UTC 24
Peak memory 207636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409806714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3409806714
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.30665158
Short name T371
Test name
Test status
Simulation time 20903487224 ps
CPU time 28.68 seconds
Started Sep 11 02:56:49 AM UTC 24
Finished Sep 11 02:57:19 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30665158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.30665158
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_loopback.3520923416
Short name T409
Test name
Test status
Simulation time 14382035235 ps
CPU time 23.67 seconds
Started Sep 11 02:56:48 AM UTC 24
Finished Sep 11 02:57:13 AM UTC 24
Peak memory 208836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520923416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3520923416
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_noise_filter.2012552447
Short name T298
Test name
Test status
Simulation time 14028112152 ps
CPU time 33.7 seconds
Started Sep 11 02:56:41 AM UTC 24
Finished Sep 11 02:57:16 AM UTC 24
Peak memory 207420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012552447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.2012552447
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_perf.2143411172
Short name T284
Test name
Test status
Simulation time 13421109611 ps
CPU time 201.63 seconds
Started Sep 11 02:56:48 AM UTC 24
Finished Sep 11 03:00:13 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143411172 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2143411172
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_rx_oversample.3587690860
Short name T46
Test name
Test status
Simulation time 6655553099 ps
CPU time 16.04 seconds
Started Sep 11 02:56:41 AM UTC 24
Finished Sep 11 02:56:59 AM UTC 24
Peak memory 207276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587690860 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3587690860
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.1228289958
Short name T41
Test name
Test status
Simulation time 673817613 ps
CPU time 3.02 seconds
Started Sep 11 02:56:43 AM UTC 24
Finished Sep 11 02:56:47 AM UTC 24
Peak memory 205156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228289958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1228289958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_sec_cm.2480930889
Short name T77
Test name
Test status
Simulation time 58275470 ps
CPU time 1.24 seconds
Started Sep 11 02:56:51 AM UTC 24
Finished Sep 11 02:56:54 AM UTC 24
Peak memory 239708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480930889 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2480930889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_smoke.3301848147
Short name T38
Test name
Test status
Simulation time 782510503 ps
CPU time 1.74 seconds
Started Sep 11 02:56:38 AM UTC 24
Finished Sep 11 02:56:41 AM UTC 24
Peak memory 207924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301848147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3301848147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_stress_all.2545513345
Short name T97
Test name
Test status
Simulation time 88736219087 ps
CPU time 162.62 seconds
Started Sep 11 02:56:50 AM UTC 24
Finished Sep 11 02:59:35 AM UTC 24
Peak memory 208812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545513345 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2545513345
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.3443739775
Short name T32
Test name
Test status
Simulation time 3683029196 ps
CPU time 50.96 seconds
Started Sep 11 02:56:49 AM UTC 24
Finished Sep 11 02:57:41 AM UTC 24
Peak memory 219612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3443739775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_
with_rand_reset.3443739775
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.2595788963
Short name T45
Test name
Test status
Simulation time 874219465 ps
CPU time 3.01 seconds
Started Sep 11 02:56:47 AM UTC 24
Finished Sep 11 02:56:51 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595788963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2595788963
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/4.uart_tx_rx.3527168929
Short name T255
Test name
Test status
Simulation time 83833412612 ps
CPU time 162.26 seconds
Started Sep 11 02:56:39 AM UTC 24
Finished Sep 11 02:59:24 AM UTC 24
Peak memory 208712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527168929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3527168929
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/4.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_alert_test.3939452051
Short name T746
Test name
Test status
Simulation time 52042324 ps
CPU time 0.85 seconds
Started Sep 11 03:15:50 AM UTC 24
Finished Sep 11 03:15:52 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939452051 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3939452051
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_fifo_full.3452775058
Short name T758
Test name
Test status
Simulation time 39061032365 ps
CPU time 54.8 seconds
Started Sep 11 03:15:31 AM UTC 24
Finished Sep 11 03:16:27 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452775058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3452775058
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.3345399378
Short name T752
Test name
Test status
Simulation time 74071983319 ps
CPU time 34.74 seconds
Started Sep 11 03:15:32 AM UTC 24
Finished Sep 11 03:16:08 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345399378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3345399378
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_fifo_reset.2797943411
Short name T827
Test name
Test status
Simulation time 62725983692 ps
CPU time 167.14 seconds
Started Sep 11 03:15:32 AM UTC 24
Finished Sep 11 03:18:22 AM UTC 24
Peak memory 208860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797943411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2797943411
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_intr.1079643125
Short name T765
Test name
Test status
Simulation time 69058559495 ps
CPU time 55.9 seconds
Started Sep 11 03:15:42 AM UTC 24
Finished Sep 11 03:16:40 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079643125 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1079643125
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3912426505
Short name T1137
Test name
Test status
Simulation time 145173483161 ps
CPU time 732.97 seconds
Started Sep 11 03:15:49 AM UTC 24
Finished Sep 11 03:28:10 AM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912426505 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3912426505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_loopback.1108559353
Short name T756
Test name
Test status
Simulation time 9868156794 ps
CPU time 37.89 seconds
Started Sep 11 03:15:46 AM UTC 24
Finished Sep 11 03:16:25 AM UTC 24
Peak memory 208636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108559353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1108559353
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_noise_filter.1749989516
Short name T781
Test name
Test status
Simulation time 66703981806 ps
CPU time 79.39 seconds
Started Sep 11 03:15:43 AM UTC 24
Finished Sep 11 03:17:05 AM UTC 24
Peak memory 208816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749989516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1749989516
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_perf.3805170928
Short name T833
Test name
Test status
Simulation time 14944570341 ps
CPU time 170.2 seconds
Started Sep 11 03:15:47 AM UTC 24
Finished Sep 11 03:18:40 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805170928 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3805170928
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_rx_oversample.3484162602
Short name T750
Test name
Test status
Simulation time 4892772024 ps
CPU time 13.75 seconds
Started Sep 11 03:15:42 AM UTC 24
Finished Sep 11 03:15:57 AM UTC 24
Peak memory 207972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484162602 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3484162602
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.980692063
Short name T793
Test name
Test status
Simulation time 92167613363 ps
CPU time 95.12 seconds
Started Sep 11 03:15:44 AM UTC 24
Finished Sep 11 03:17:22 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980692063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.980692063
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.293198979
Short name T741
Test name
Test status
Simulation time 474858609 ps
CPU time 2.07 seconds
Started Sep 11 03:15:44 AM UTC 24
Finished Sep 11 03:15:48 AM UTC 24
Peak memory 205152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293198979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.293198979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_smoke.2370668721
Short name T744
Test name
Test status
Simulation time 5983156501 ps
CPU time 17.76 seconds
Started Sep 11 03:15:30 AM UTC 24
Finished Sep 11 03:15:49 AM UTC 24
Peak memory 208684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370668721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2370668721
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_stress_all.818962708
Short name T843
Test name
Test status
Simulation time 272901521538 ps
CPU time 186.29 seconds
Started Sep 11 03:15:49 AM UTC 24
Finished Sep 11 03:18:58 AM UTC 24
Peak memory 221832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818962708 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.818962708
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.3904266873
Short name T760
Test name
Test status
Simulation time 13413949882 ps
CPU time 37.36 seconds
Started Sep 11 03:15:49 AM UTC 24
Finished Sep 11 03:16:28 AM UTC 24
Peak memory 225476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3904266873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all
_with_rand_reset.3904266873
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.1888267926
Short name T743
Test name
Test status
Simulation time 3807671701 ps
CPU time 2.6 seconds
Started Sep 11 03:15:45 AM UTC 24
Finished Sep 11 03:15:48 AM UTC 24
Peak memory 207592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888267926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1888267926
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/40.uart_tx_rx.3812122922
Short name T783
Test name
Test status
Simulation time 44799128842 ps
CPU time 95.36 seconds
Started Sep 11 03:15:30 AM UTC 24
Finished Sep 11 03:17:07 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812122922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.3812122922
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/40.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_alert_test.901923441
Short name T763
Test name
Test status
Simulation time 11135299 ps
CPU time 0.86 seconds
Started Sep 11 03:16:28 AM UTC 24
Finished Sep 11 03:16:30 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901923441 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.901923441
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_fifo_full.1269081734
Short name T797
Test name
Test status
Simulation time 99191648036 ps
CPU time 100.04 seconds
Started Sep 11 03:15:52 AM UTC 24
Finished Sep 11 03:17:34 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269081734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.1269081734
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.4144577521
Short name T838
Test name
Test status
Simulation time 64759708980 ps
CPU time 172.28 seconds
Started Sep 11 03:15:52 AM UTC 24
Finished Sep 11 03:18:47 AM UTC 24
Peak memory 208892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144577521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.4144577521
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_fifo_reset.680013642
Short name T762
Test name
Test status
Simulation time 15261699442 ps
CPU time 31.37 seconds
Started Sep 11 03:15:55 AM UTC 24
Finished Sep 11 03:16:28 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680013642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.680013642
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_intr.2811933458
Short name T754
Test name
Test status
Simulation time 9915444649 ps
CPU time 15.92 seconds
Started Sep 11 03:15:58 AM UTC 24
Finished Sep 11 03:16:16 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811933458 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2811933458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.1207174054
Short name T859
Test name
Test status
Simulation time 73979699294 ps
CPU time 173.78 seconds
Started Sep 11 03:16:17 AM UTC 24
Finished Sep 11 03:19:14 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207174054 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1207174054
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_loopback.4058539098
Short name T757
Test name
Test status
Simulation time 3759239778 ps
CPU time 8.58 seconds
Started Sep 11 03:16:16 AM UTC 24
Finished Sep 11 03:16:26 AM UTC 24
Peak memory 207448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058539098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.4058539098
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_noise_filter.328622940
Short name T769
Test name
Test status
Simulation time 27994844900 ps
CPU time 47.14 seconds
Started Sep 11 03:16:00 AM UTC 24
Finished Sep 11 03:16:48 AM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328622940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.328622940
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_perf.3356879426
Short name T1100
Test name
Test status
Simulation time 12352810514 ps
CPU time 642.37 seconds
Started Sep 11 03:16:16 AM UTC 24
Finished Sep 11 03:27:06 AM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356879426 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3356879426
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_rx_oversample.1893469889
Short name T753
Test name
Test status
Simulation time 4654051087 ps
CPU time 10.58 seconds
Started Sep 11 03:15:57 AM UTC 24
Finished Sep 11 03:16:09 AM UTC 24
Peak memory 207920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893469889 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1893469889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.296757265
Short name T167
Test name
Test status
Simulation time 93525755667 ps
CPU time 297.89 seconds
Started Sep 11 03:16:10 AM UTC 24
Finished Sep 11 03:21:12 AM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296757265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.296757265
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.939714495
Short name T761
Test name
Test status
Simulation time 5519067823 ps
CPU time 18.16 seconds
Started Sep 11 03:16:09 AM UTC 24
Finished Sep 11 03:16:28 AM UTC 24
Peak memory 207264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939714495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.939714495
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_smoke.2435439943
Short name T748
Test name
Test status
Simulation time 766706884 ps
CPU time 2.18 seconds
Started Sep 11 03:15:51 AM UTC 24
Finished Sep 11 03:15:54 AM UTC 24
Peak memory 207764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435439943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2435439943
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_stress_all.3414849835
Short name T777
Test name
Test status
Simulation time 17270026568 ps
CPU time 30.5 seconds
Started Sep 11 03:16:26 AM UTC 24
Finished Sep 11 03:16:58 AM UTC 24
Peak memory 208844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414849835 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3414849835
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.3320579744
Short name T802
Test name
Test status
Simulation time 6049037265 ps
CPU time 77.87 seconds
Started Sep 11 03:16:26 AM UTC 24
Finished Sep 11 03:17:46 AM UTC 24
Peak memory 217868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3320579744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all
_with_rand_reset.3320579744
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.1502438148
Short name T774
Test name
Test status
Simulation time 6541929940 ps
CPU time 36.73 seconds
Started Sep 11 03:16:14 AM UTC 24
Finished Sep 11 03:16:52 AM UTC 24
Peak memory 208816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502438148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1502438148
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/41.uart_tx_rx.3054133045
Short name T759
Test name
Test status
Simulation time 92990470092 ps
CPU time 35.02 seconds
Started Sep 11 03:15:51 AM UTC 24
Finished Sep 11 03:16:27 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054133045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3054133045
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/41.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_alert_test.884780472
Short name T775
Test name
Test status
Simulation time 45107092 ps
CPU time 0.84 seconds
Started Sep 11 03:16:53 AM UTC 24
Finished Sep 11 03:16:54 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884780472 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.884780472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_fifo_full.2386808788
Short name T766
Test name
Test status
Simulation time 12149141593 ps
CPU time 11.87 seconds
Started Sep 11 03:16:29 AM UTC 24
Finished Sep 11 03:16:42 AM UTC 24
Peak memory 208416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386808788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2386808788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.910662170
Short name T806
Test name
Test status
Simulation time 44997273984 ps
CPU time 80.35 seconds
Started Sep 11 03:16:30 AM UTC 24
Finished Sep 11 03:17:52 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910662170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.910662170
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_fifo_reset.1662834704
Short name T784
Test name
Test status
Simulation time 63630102866 ps
CPU time 37.17 seconds
Started Sep 11 03:16:31 AM UTC 24
Finished Sep 11 03:17:09 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662834704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1662834704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_intr.2534566957
Short name T832
Test name
Test status
Simulation time 58181618600 ps
CPU time 112.17 seconds
Started Sep 11 03:16:41 AM UTC 24
Finished Sep 11 03:18:35 AM UTC 24
Peak memory 208816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534566957 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2534566957
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.3652742033
Short name T906
Test name
Test status
Simulation time 55471078995 ps
CPU time 229.74 seconds
Started Sep 11 03:16:50 AM UTC 24
Finished Sep 11 03:20:43 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652742033 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.3652742033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_loopback.515791625
Short name T772
Test name
Test status
Simulation time 249266402 ps
CPU time 0.97 seconds
Started Sep 11 03:16:49 AM UTC 24
Finished Sep 11 03:16:51 AM UTC 24
Peak memory 204428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515791625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.uart_loopback.515791625
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_noise_filter.2262281149
Short name T799
Test name
Test status
Simulation time 485459144769 ps
CPU time 57.27 seconds
Started Sep 11 03:16:42 AM UTC 24
Finished Sep 11 03:17:41 AM UTC 24
Peak memory 217676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262281149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2262281149
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_perf.1647165739
Short name T1149
Test name
Test status
Simulation time 16166903299 ps
CPU time 699.14 seconds
Started Sep 11 03:16:50 AM UTC 24
Finished Sep 11 03:28:38 AM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647165739 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1647165739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_rx_oversample.2010684578
Short name T771
Test name
Test status
Simulation time 2006342880 ps
CPU time 14.72 seconds
Started Sep 11 03:16:34 AM UTC 24
Finished Sep 11 03:16:50 AM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010684578 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2010684578
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.3378774146
Short name T805
Test name
Test status
Simulation time 61660619984 ps
CPU time 61.23 seconds
Started Sep 11 03:16:48 AM UTC 24
Finished Sep 11 03:17:51 AM UTC 24
Peak memory 208496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378774146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.3378774146
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.3539756515
Short name T770
Test name
Test status
Simulation time 1683856775 ps
CPU time 3.49 seconds
Started Sep 11 03:16:45 AM UTC 24
Finished Sep 11 03:16:50 AM UTC 24
Peak memory 205152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539756515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3539756515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_smoke.2259267112
Short name T764
Test name
Test status
Simulation time 462531232 ps
CPU time 3.23 seconds
Started Sep 11 03:16:28 AM UTC 24
Finished Sep 11 03:16:33 AM UTC 24
Peak memory 207516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259267112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2259267112
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_stress_all.1119890246
Short name T181
Test name
Test status
Simulation time 217595965643 ps
CPU time 142.94 seconds
Started Sep 11 03:16:53 AM UTC 24
Finished Sep 11 03:19:18 AM UTC 24
Peak memory 208672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119890246 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1119890246
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.1281042765
Short name T790
Test name
Test status
Simulation time 2382274958 ps
CPU time 24.12 seconds
Started Sep 11 03:16:53 AM UTC 24
Finished Sep 11 03:17:18 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1281042765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all
_with_rand_reset.1281042765
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.569685641
Short name T773
Test name
Test status
Simulation time 1134338658 ps
CPU time 2.03 seconds
Started Sep 11 03:16:48 AM UTC 24
Finished Sep 11 03:16:51 AM UTC 24
Peak memory 207208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569685641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.569685641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/42.uart_tx_rx.3836234138
Short name T776
Test name
Test status
Simulation time 100694968960 ps
CPU time 28.38 seconds
Started Sep 11 03:16:28 AM UTC 24
Finished Sep 11 03:16:58 AM UTC 24
Peak memory 208584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836234138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3836234138
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/42.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_alert_test.1396598619
Short name T792
Test name
Test status
Simulation time 14272776 ps
CPU time 0.87 seconds
Started Sep 11 03:17:19 AM UTC 24
Finished Sep 11 03:17:21 AM UTC 24
Peak memory 204236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396598619 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1396598619
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_fifo_full.1945855457
Short name T785
Test name
Test status
Simulation time 20648570352 ps
CPU time 11 seconds
Started Sep 11 03:16:59 AM UTC 24
Finished Sep 11 03:17:11 AM UTC 24
Peak memory 208624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945855457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1945855457
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1506577489
Short name T818
Test name
Test status
Simulation time 161654243202 ps
CPU time 72.23 seconds
Started Sep 11 03:16:59 AM UTC 24
Finished Sep 11 03:18:13 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506577489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1506577489
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_fifo_reset.507921032
Short name T176
Test name
Test status
Simulation time 22286065549 ps
CPU time 21.38 seconds
Started Sep 11 03:17:00 AM UTC 24
Finished Sep 11 03:17:22 AM UTC 24
Peak memory 208596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507921032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.507921032
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_intr.437753948
Short name T922
Test name
Test status
Simulation time 95529358725 ps
CPU time 251.99 seconds
Started Sep 11 03:17:03 AM UTC 24
Finished Sep 11 03:21:19 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437753948 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.437753948
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.265606432
Short name T1181
Test name
Test status
Simulation time 157260506470 ps
CPU time 1245.19 seconds
Started Sep 11 03:17:14 AM UTC 24
Finished Sep 11 03:38:14 AM UTC 24
Peak memory 212200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265606432 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.265606432
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_loopback.4238609371
Short name T788
Test name
Test status
Simulation time 1075745999 ps
CPU time 2.02 seconds
Started Sep 11 03:17:12 AM UTC 24
Finished Sep 11 03:17:14 AM UTC 24
Peak memory 207672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238609371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.uart_loopback.4238609371
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_noise_filter.1410131223
Short name T848
Test name
Test status
Simulation time 199536636376 ps
CPU time 115.21 seconds
Started Sep 11 03:17:05 AM UTC 24
Finished Sep 11 03:19:03 AM UTC 24
Peak memory 208832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410131223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1410131223
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_perf.491850885
Short name T1153
Test name
Test status
Simulation time 8269964625 ps
CPU time 678.38 seconds
Started Sep 11 03:17:13 AM UTC 24
Finished Sep 11 03:28:39 AM UTC 24
Peak memory 212336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491850885 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.491850885
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_rx_oversample.294015815
Short name T786
Test name
Test status
Simulation time 3701260980 ps
CPU time 10.08 seconds
Started Sep 11 03:17:01 AM UTC 24
Finished Sep 11 03:17:12 AM UTC 24
Peak memory 207204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294015815 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.294015815
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.3174352320
Short name T828
Test name
Test status
Simulation time 40737960000 ps
CPU time 81.7 seconds
Started Sep 11 03:17:08 AM UTC 24
Finished Sep 11 03:18:32 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174352320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3174352320
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.4289507011
Short name T787
Test name
Test status
Simulation time 5983377220 ps
CPU time 5.4 seconds
Started Sep 11 03:17:06 AM UTC 24
Finished Sep 11 03:17:13 AM UTC 24
Peak memory 205152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289507011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4289507011
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_smoke.791122920
Short name T779
Test name
Test status
Simulation time 669402461 ps
CPU time 4.73 seconds
Started Sep 11 03:16:55 AM UTC 24
Finished Sep 11 03:17:00 AM UTC 24
Peak memory 207748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791122920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.uart_smoke.791122920
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_stress_all.3786910917
Short name T980
Test name
Test status
Simulation time 161005033179 ps
CPU time 355.64 seconds
Started Sep 11 03:17:17 AM UTC 24
Finished Sep 11 03:23:17 AM UTC 24
Peak memory 217636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786910917 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3786910917
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.2255158058
Short name T829
Test name
Test status
Simulation time 4254726707 ps
CPU time 75.3 seconds
Started Sep 11 03:17:16 AM UTC 24
Finished Sep 11 03:18:33 AM UTC 24
Peak memory 219960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2255158058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all
_with_rand_reset.2255158058
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.946808071
Short name T801
Test name
Test status
Simulation time 12099789622 ps
CPU time 32.93 seconds
Started Sep 11 03:17:10 AM UTC 24
Finished Sep 11 03:17:45 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946808071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.946808071
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/43.uart_tx_rx.2633084307
Short name T807
Test name
Test status
Simulation time 97140812221 ps
CPU time 57.7 seconds
Started Sep 11 03:16:55 AM UTC 24
Finished Sep 11 03:17:54 AM UTC 24
Peak memory 208656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633084307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2633084307
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/43.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_alert_test.2223164224
Short name T808
Test name
Test status
Simulation time 14233127 ps
CPU time 0.82 seconds
Started Sep 11 03:17:52 AM UTC 24
Finished Sep 11 03:17:54 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223164224 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2223164224
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_fifo_full.913538074
Short name T883
Test name
Test status
Simulation time 70706855008 ps
CPU time 143.8 seconds
Started Sep 11 03:17:22 AM UTC 24
Finished Sep 11 03:19:48 AM UTC 24
Peak memory 208588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913538074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.913538074
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.3828180294
Short name T803
Test name
Test status
Simulation time 18442939132 ps
CPU time 23.46 seconds
Started Sep 11 03:17:23 AM UTC 24
Finished Sep 11 03:17:48 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828180294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3828180294
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_fifo_reset.364766367
Short name T231
Test name
Test status
Simulation time 9339617990 ps
CPU time 23.72 seconds
Started Sep 11 03:17:24 AM UTC 24
Finished Sep 11 03:17:49 AM UTC 24
Peak memory 208784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364766367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.364766367
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_intr.3334186398
Short name T817
Test name
Test status
Simulation time 38645355238 ps
CPU time 45.5 seconds
Started Sep 11 03:17:25 AM UTC 24
Finished Sep 11 03:18:12 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334186398 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3334186398
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.2765855139
Short name T999
Test name
Test status
Simulation time 114178165815 ps
CPU time 356.97 seconds
Started Sep 11 03:17:49 AM UTC 24
Finished Sep 11 03:23:51 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765855139 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2765855139
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_loopback.1300893796
Short name T804
Test name
Test status
Simulation time 2369715342 ps
CPU time 3.04 seconds
Started Sep 11 03:17:46 AM UTC 24
Finished Sep 11 03:17:50 AM UTC 24
Peak memory 207920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300893796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1300893796
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_noise_filter.557650781
Short name T819
Test name
Test status
Simulation time 53814112080 ps
CPU time 36.1 seconds
Started Sep 11 03:17:36 AM UTC 24
Finished Sep 11 03:18:13 AM UTC 24
Peak memory 208920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557650781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.557650781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_perf.98660075
Short name T994
Test name
Test status
Simulation time 29381016118 ps
CPU time 355.11 seconds
Started Sep 11 03:17:47 AM UTC 24
Finished Sep 11 03:23:47 AM UTC 24
Peak memory 208628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98660075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.98660075
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_rx_oversample.1277080648
Short name T820
Test name
Test status
Simulation time 4438870679 ps
CPU time 47.68 seconds
Started Sep 11 03:17:25 AM UTC 24
Finished Sep 11 03:18:15 AM UTC 24
Peak memory 207204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277080648 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.1277080648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.3533991886
Short name T870
Test name
Test status
Simulation time 95156537304 ps
CPU time 106.73 seconds
Started Sep 11 03:17:42 AM UTC 24
Finished Sep 11 03:19:30 AM UTC 24
Peak memory 208812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533991886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3533991886
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.2098668590
Short name T811
Test name
Test status
Simulation time 5310134592 ps
CPU time 20.97 seconds
Started Sep 11 03:17:37 AM UTC 24
Finished Sep 11 03:17:59 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098668590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2098668590
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_smoke.4165212000
Short name T794
Test name
Test status
Simulation time 490187775 ps
CPU time 3.53 seconds
Started Sep 11 03:17:19 AM UTC 24
Finished Sep 11 03:17:23 AM UTC 24
Peak memory 207480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165212000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_smoke.4165212000
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_stress_all.2887021557
Short name T882
Test name
Test status
Simulation time 347579399383 ps
CPU time 113.61 seconds
Started Sep 11 03:17:51 AM UTC 24
Finished Sep 11 03:19:47 AM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887021557 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2887021557
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.3579867119
Short name T864
Test name
Test status
Simulation time 20808296756 ps
CPU time 87.86 seconds
Started Sep 11 03:17:50 AM UTC 24
Finished Sep 11 03:19:20 AM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3579867119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all
_with_rand_reset.3579867119
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.2403156654
Short name T815
Test name
Test status
Simulation time 7346246220 ps
CPU time 23.72 seconds
Started Sep 11 03:17:45 AM UTC 24
Finished Sep 11 03:18:10 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403156654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2403156654
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/44.uart_tx_rx.1124327675
Short name T798
Test name
Test status
Simulation time 5888234281 ps
CPU time 13.11 seconds
Started Sep 11 03:17:22 AM UTC 24
Finished Sep 11 03:17:36 AM UTC 24
Peak memory 208388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124327675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1124327675
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/44.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_alert_test.1135129711
Short name T825
Test name
Test status
Simulation time 32635667 ps
CPU time 0.84 seconds
Started Sep 11 03:18:18 AM UTC 24
Finished Sep 11 03:18:19 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135129711 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1135129711
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_fifo_full.423896788
Short name T835
Test name
Test status
Simulation time 59587269786 ps
CPU time 47.99 seconds
Started Sep 11 03:17:54 AM UTC 24
Finished Sep 11 03:18:44 AM UTC 24
Peak memory 208636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423896788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.423896788
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.198513043
Short name T947
Test name
Test status
Simulation time 115748882821 ps
CPU time 256.91 seconds
Started Sep 11 03:17:57 AM UTC 24
Finished Sep 11 03:22:17 AM UTC 24
Peak memory 208636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198513043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.198513043
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_fifo_reset.3183974618
Short name T208
Test name
Test status
Simulation time 85744815238 ps
CPU time 40.64 seconds
Started Sep 11 03:17:57 AM UTC 24
Finished Sep 11 03:18:39 AM UTC 24
Peak memory 208624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183974618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3183974618
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_intr.2284968688
Short name T823
Test name
Test status
Simulation time 14859640374 ps
CPU time 15.45 seconds
Started Sep 11 03:18:02 AM UTC 24
Finished Sep 11 03:18:18 AM UTC 24
Peak memory 207136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284968688 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2284968688
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.3868049257
Short name T897
Test name
Test status
Simulation time 116800660599 ps
CPU time 131.16 seconds
Started Sep 11 03:18:13 AM UTC 24
Finished Sep 11 03:20:27 AM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868049257 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.3868049257
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_loopback.3433294292
Short name T824
Test name
Test status
Simulation time 5189614523 ps
CPU time 4.4 seconds
Started Sep 11 03:18:13 AM UTC 24
Finished Sep 11 03:18:19 AM UTC 24
Peak memory 207828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433294292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3433294292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_noise_filter.2520024773
Short name T856
Test name
Test status
Simulation time 238418050198 ps
CPU time 66.28 seconds
Started Sep 11 03:18:06 AM UTC 24
Finished Sep 11 03:19:14 AM UTC 24
Peak memory 217416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520024773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2520024773
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_perf.3279630956
Short name T930
Test name
Test status
Simulation time 3723370054 ps
CPU time 206.08 seconds
Started Sep 11 03:18:13 AM UTC 24
Finished Sep 11 03:21:42 AM UTC 24
Peak memory 208596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279630956 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3279630956
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_rx_oversample.3791989523
Short name T830
Test name
Test status
Simulation time 6321724260 ps
CPU time 31.87 seconds
Started Sep 11 03:18:00 AM UTC 24
Finished Sep 11 03:18:33 AM UTC 24
Peak memory 207472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791989523 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3791989523
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.2080360946
Short name T866
Test name
Test status
Simulation time 31633756311 ps
CPU time 69.82 seconds
Started Sep 11 03:18:11 AM UTC 24
Finished Sep 11 03:19:23 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080360946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2080360946
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2752714125
Short name T821
Test name
Test status
Simulation time 2735761419 ps
CPU time 9.35 seconds
Started Sep 11 03:18:06 AM UTC 24
Finished Sep 11 03:18:16 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752714125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2752714125
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_smoke.1143369106
Short name T809
Test name
Test status
Simulation time 735064802 ps
CPU time 2.02 seconds
Started Sep 11 03:17:52 AM UTC 24
Finished Sep 11 03:17:55 AM UTC 24
Peak memory 207508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143369106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1143369106
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_stress_all.3996852648
Short name T1029
Test name
Test status
Simulation time 77851902791 ps
CPU time 403.12 seconds
Started Sep 11 03:18:18 AM UTC 24
Finished Sep 11 03:25:06 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996852648 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3996852648
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.86278292
Short name T836
Test name
Test status
Simulation time 4602729360 ps
CPU time 29.44 seconds
Started Sep 11 03:18:15 AM UTC 24
Finished Sep 11 03:18:46 AM UTC 24
Peak memory 217708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=86278292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all_w
ith_rand_reset.86278292
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.214226279
Short name T822
Test name
Test status
Simulation time 818491795 ps
CPU time 3.36 seconds
Started Sep 11 03:18:12 AM UTC 24
Finished Sep 11 03:18:17 AM UTC 24
Peak memory 207164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214226279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.214226279
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/45.uart_tx_rx.714427716
Short name T849
Test name
Test status
Simulation time 40935469408 ps
CPU time 68.42 seconds
Started Sep 11 03:17:54 AM UTC 24
Finished Sep 11 03:19:05 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714427716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.714427716
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/45.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_alert_test.1692737183
Short name T840
Test name
Test status
Simulation time 81986588 ps
CPU time 0.81 seconds
Started Sep 11 03:18:48 AM UTC 24
Finished Sep 11 03:18:50 AM UTC 24
Peak memory 204432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692737183 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1692737183
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_fifo_full.1218092481
Short name T889
Test name
Test status
Simulation time 24782327013 ps
CPU time 90.63 seconds
Started Sep 11 03:18:20 AM UTC 24
Finished Sep 11 03:19:53 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218092481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1218092481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.1453581528
Short name T837
Test name
Test status
Simulation time 12644266963 ps
CPU time 23.01 seconds
Started Sep 11 03:18:22 AM UTC 24
Finished Sep 11 03:18:46 AM UTC 24
Peak memory 207580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453581528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1453581528
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_fifo_reset.345134361
Short name T233
Test name
Test status
Simulation time 212740167953 ps
CPU time 82.58 seconds
Started Sep 11 03:18:23 AM UTC 24
Finished Sep 11 03:19:48 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345134361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.345134361
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_intr.456755176
Short name T914
Test name
Test status
Simulation time 80026336442 ps
CPU time 142.9 seconds
Started Sep 11 03:18:34 AM UTC 24
Finished Sep 11 03:21:00 AM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456755176 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.456755176
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.3371135772
Short name T936
Test name
Test status
Simulation time 82821801635 ps
CPU time 188.91 seconds
Started Sep 11 03:18:45 AM UTC 24
Finished Sep 11 03:21:56 AM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371135772 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3371135772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_loopback.2513753462
Short name T841
Test name
Test status
Simulation time 7516357886 ps
CPU time 13.99 seconds
Started Sep 11 03:18:41 AM UTC 24
Finished Sep 11 03:18:56 AM UTC 24
Peak memory 208528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513753462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2513753462
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_noise_filter.2120873538
Short name T842
Test name
Test status
Simulation time 6973155042 ps
CPU time 20.97 seconds
Started Sep 11 03:18:34 AM UTC 24
Finished Sep 11 03:18:57 AM UTC 24
Peak memory 208428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120873538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2120873538
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_perf.529314967
Short name T974
Test name
Test status
Simulation time 16943395759 ps
CPU time 259.89 seconds
Started Sep 11 03:18:43 AM UTC 24
Finished Sep 11 03:23:06 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529314967 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.529314967
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_rx_oversample.4234770811
Short name T875
Test name
Test status
Simulation time 6819841261 ps
CPU time 61.49 seconds
Started Sep 11 03:18:33 AM UTC 24
Finished Sep 11 03:19:36 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234770811 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.4234770811
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.1975160143
Short name T852
Test name
Test status
Simulation time 16303761023 ps
CPU time 31.62 seconds
Started Sep 11 03:18:36 AM UTC 24
Finished Sep 11 03:19:09 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975160143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1975160143
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.2661410713
Short name T834
Test name
Test status
Simulation time 3487898004 ps
CPU time 6.29 seconds
Started Sep 11 03:18:34 AM UTC 24
Finished Sep 11 03:18:42 AM UTC 24
Peak memory 207064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661410713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2661410713
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_smoke.2292400701
Short name T826
Test name
Test status
Simulation time 477518112 ps
CPU time 1.66 seconds
Started Sep 11 03:18:19 AM UTC 24
Finished Sep 11 03:18:21 AM UTC 24
Peak memory 207028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292400701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2292400701
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_stress_all.1026101203
Short name T1019
Test name
Test status
Simulation time 246152854820 ps
CPU time 348.41 seconds
Started Sep 11 03:18:47 AM UTC 24
Finished Sep 11 03:24:40 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026101203 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1026101203
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.2363794797
Short name T854
Test name
Test status
Simulation time 5518561439 ps
CPU time 22.87 seconds
Started Sep 11 03:18:47 AM UTC 24
Finished Sep 11 03:19:11 AM UTC 24
Peak memory 217648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2363794797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all
_with_rand_reset.2363794797
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.3747813057
Short name T847
Test name
Test status
Simulation time 6805256617 ps
CPU time 21.59 seconds
Started Sep 11 03:18:39 AM UTC 24
Finished Sep 11 03:19:02 AM UTC 24
Peak memory 208500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747813057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3747813057
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/46.uart_tx_rx.2774405825
Short name T885
Test name
Test status
Simulation time 152171743887 ps
CPU time 88.63 seconds
Started Sep 11 03:18:20 AM UTC 24
Finished Sep 11 03:19:51 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774405825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2774405825
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/46.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_alert_test.2564095816
Short name T860
Test name
Test status
Simulation time 57496979 ps
CPU time 0.84 seconds
Started Sep 11 03:19:12 AM UTC 24
Finished Sep 11 03:19:14 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564095816 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2564095816
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_fifo_full.4174806981
Short name T896
Test name
Test status
Simulation time 53252455495 ps
CPU time 85.2 seconds
Started Sep 11 03:18:57 AM UTC 24
Finished Sep 11 03:20:24 AM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174806981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4174806981
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.3790920322
Short name T1097
Test name
Test status
Simulation time 214890849253 ps
CPU time 480.29 seconds
Started Sep 11 03:18:57 AM UTC 24
Finished Sep 11 03:27:03 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790920322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3790920322
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_fifo_reset.1886423914
Short name T973
Test name
Test status
Simulation time 112099975417 ps
CPU time 242.44 seconds
Started Sep 11 03:18:59 AM UTC 24
Finished Sep 11 03:23:05 AM UTC 24
Peak memory 208808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886423914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1886423914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_intr.2823059085
Short name T867
Test name
Test status
Simulation time 26775100003 ps
CPU time 20.95 seconds
Started Sep 11 03:19:00 AM UTC 24
Finished Sep 11 03:19:23 AM UTC 24
Peak memory 208564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823059085 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2823059085
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.961091110
Short name T956
Test name
Test status
Simulation time 119209180786 ps
CPU time 201.39 seconds
Started Sep 11 03:19:10 AM UTC 24
Finished Sep 11 03:22:34 AM UTC 24
Peak memory 208968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961091110 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.961091110
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_loopback.577757543
Short name T862
Test name
Test status
Simulation time 4376279074 ps
CPU time 11.53 seconds
Started Sep 11 03:19:06 AM UTC 24
Finished Sep 11 03:19:18 AM UTC 24
Peak memory 208076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577757543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.uart_loopback.577757543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_noise_filter.2268627450
Short name T903
Test name
Test status
Simulation time 121860773215 ps
CPU time 94.31 seconds
Started Sep 11 03:19:03 AM UTC 24
Finished Sep 11 03:20:39 AM UTC 24
Peak memory 217580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268627450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2268627450
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_perf.2337212713
Short name T1178
Test name
Test status
Simulation time 15332359460 ps
CPU time 983.25 seconds
Started Sep 11 03:19:10 AM UTC 24
Finished Sep 11 03:35:45 AM UTC 24
Peak memory 212208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337212713 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2337212713
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_rx_oversample.2644632215
Short name T858
Test name
Test status
Simulation time 6872835875 ps
CPU time 12.29 seconds
Started Sep 11 03:19:00 AM UTC 24
Finished Sep 11 03:19:14 AM UTC 24
Peak memory 207208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644632215 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2644632215
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.4159834375
Short name T872
Test name
Test status
Simulation time 71866775744 ps
CPU time 30.53 seconds
Started Sep 11 03:19:04 AM UTC 24
Finished Sep 11 03:19:35 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159834375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.4159834375
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.2734855219
Short name T865
Test name
Test status
Simulation time 5267699503 ps
CPU time 16.41 seconds
Started Sep 11 03:19:04 AM UTC 24
Finished Sep 11 03:19:21 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734855219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2734855219
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_smoke.2941535543
Short name T844
Test name
Test status
Simulation time 5591424487 ps
CPU time 8 seconds
Started Sep 11 03:18:50 AM UTC 24
Finished Sep 11 03:18:59 AM UTC 24
Peak memory 208372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941535543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2941535543
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_stress_all.1237146505
Short name T904
Test name
Test status
Simulation time 42968892569 ps
CPU time 86.22 seconds
Started Sep 11 03:19:12 AM UTC 24
Finished Sep 11 03:20:40 AM UTC 24
Peak memory 209016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237146505 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1237146505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.332665134
Short name T877
Test name
Test status
Simulation time 1778230190 ps
CPU time 26.67 seconds
Started Sep 11 03:19:11 AM UTC 24
Finished Sep 11 03:19:39 AM UTC 24
Peak memory 217740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=332665134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all_
with_rand_reset.332665134
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.4189868062
Short name T853
Test name
Test status
Simulation time 860387690 ps
CPU time 3.14 seconds
Started Sep 11 03:19:06 AM UTC 24
Finished Sep 11 03:19:10 AM UTC 24
Peak memory 207692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189868062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.4189868062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/47.uart_tx_rx.1138197481
Short name T863
Test name
Test status
Simulation time 38568816156 ps
CPU time 28.14 seconds
Started Sep 11 03:18:50 AM UTC 24
Finished Sep 11 03:19:19 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138197481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1138197481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/47.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_alert_test.1650652883
Short name T876
Test name
Test status
Simulation time 14637727 ps
CPU time 0.82 seconds
Started Sep 11 03:19:37 AM UTC 24
Finished Sep 11 03:19:38 AM UTC 24
Peak memory 204428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650652883 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1650652883
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_fifo_full.1993478590
Short name T905
Test name
Test status
Simulation time 59185447703 ps
CPU time 86.51 seconds
Started Sep 11 03:19:14 AM UTC 24
Finished Sep 11 03:20:43 AM UTC 24
Peak memory 208868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993478590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1993478590
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.3298756907
Short name T895
Test name
Test status
Simulation time 67404487879 ps
CPU time 56.93 seconds
Started Sep 11 03:19:16 AM UTC 24
Finished Sep 11 03:20:14 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298756907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.3298756907
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_fifo_reset.4246552910
Short name T177
Test name
Test status
Simulation time 5195357126 ps
CPU time 15.5 seconds
Started Sep 11 03:19:18 AM UTC 24
Finished Sep 11 03:19:34 AM UTC 24
Peak memory 208624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246552910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.4246552910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_intr.1103511016
Short name T1169
Test name
Test status
Simulation time 336356240048 ps
CPU time 607.84 seconds
Started Sep 11 03:19:20 AM UTC 24
Finished Sep 11 03:29:34 AM UTC 24
Peak memory 211980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103511016 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1103511016
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.3567265534
Short name T1179
Test name
Test status
Simulation time 150177495835 ps
CPU time 1017 seconds
Started Sep 11 03:19:30 AM UTC 24
Finished Sep 11 03:36:39 AM UTC 24
Peak memory 212144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567265534 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3567265534
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_loopback.2143603508
Short name T871
Test name
Test status
Simulation time 10251350101 ps
CPU time 11.1 seconds
Started Sep 11 03:19:23 AM UTC 24
Finished Sep 11 03:19:35 AM UTC 24
Peak memory 208620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143603508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2143603508
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_noise_filter.2880295482
Short name T902
Test name
Test status
Simulation time 41927685194 ps
CPU time 76.76 seconds
Started Sep 11 03:19:20 AM UTC 24
Finished Sep 11 03:20:38 AM UTC 24
Peak memory 208960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880295482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.2880295482
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_perf.1468417693
Short name T1073
Test name
Test status
Simulation time 6581807203 ps
CPU time 418.14 seconds
Started Sep 11 03:19:30 AM UTC 24
Finished Sep 11 03:26:34 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468417693 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.1468417693
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_rx_oversample.2452949746
Short name T886
Test name
Test status
Simulation time 3960481818 ps
CPU time 30.98 seconds
Started Sep 11 03:19:19 AM UTC 24
Finished Sep 11 03:19:51 AM UTC 24
Peak memory 207736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452949746 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2452949746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.966149362
Short name T986
Test name
Test status
Simulation time 218787805659 ps
CPU time 247.34 seconds
Started Sep 11 03:19:22 AM UTC 24
Finished Sep 11 03:23:33 AM UTC 24
Peak memory 208660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966149362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.966149362
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.2182434739
Short name T874
Test name
Test status
Simulation time 4789908489 ps
CPU time 14 seconds
Started Sep 11 03:19:21 AM UTC 24
Finished Sep 11 03:19:36 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182434739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2182434739
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_smoke.2565777512
Short name T861
Test name
Test status
Simulation time 304406470 ps
CPU time 1.57 seconds
Started Sep 11 03:19:14 AM UTC 24
Finished Sep 11 03:19:17 AM UTC 24
Peak memory 206312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565777512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2565777512
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_stress_all.3418899007
Short name T1074
Test name
Test status
Simulation time 195094751262 ps
CPU time 413.67 seconds
Started Sep 11 03:19:35 AM UTC 24
Finished Sep 11 03:26:34 AM UTC 24
Peak memory 208904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418899007 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3418899007
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.3802708842
Short name T898
Test name
Test status
Simulation time 12578791615 ps
CPU time 55.99 seconds
Started Sep 11 03:19:31 AM UTC 24
Finished Sep 11 03:20:29 AM UTC 24
Peak memory 219768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3802708842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all
_with_rand_reset.3802708842
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.1470520967
Short name T869
Test name
Test status
Simulation time 1465546501 ps
CPU time 5.67 seconds
Started Sep 11 03:19:23 AM UTC 24
Finished Sep 11 03:19:30 AM UTC 24
Peak memory 207628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470520967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1470520967
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/48.uart_tx_rx.1692225458
Short name T880
Test name
Test status
Simulation time 46446940397 ps
CPU time 29.31 seconds
Started Sep 11 03:19:14 AM UTC 24
Finished Sep 11 03:19:45 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692225458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.1692225458
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/48.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_alert_test.572381931
Short name T891
Test name
Test status
Simulation time 21143837 ps
CPU time 0.84 seconds
Started Sep 11 03:19:52 AM UTC 24
Finished Sep 11 03:19:54 AM UTC 24
Peak memory 204368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572381931 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.572381931
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_fifo_full.1515320846
Short name T957
Test name
Test status
Simulation time 94135897336 ps
CPU time 179.41 seconds
Started Sep 11 03:19:37 AM UTC 24
Finished Sep 11 03:22:39 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515320846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1515320846
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.4228579348
Short name T894
Test name
Test status
Simulation time 47516254478 ps
CPU time 27.86 seconds
Started Sep 11 03:19:37 AM UTC 24
Finished Sep 11 03:20:06 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228579348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4228579348
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_fifo_reset.2700039226
Short name T1172
Test name
Test status
Simulation time 191497536266 ps
CPU time 617.84 seconds
Started Sep 11 03:19:39 AM UTC 24
Finished Sep 11 03:30:05 AM UTC 24
Peak memory 210168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700039226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2700039226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_intr.2044550061
Short name T913
Test name
Test status
Simulation time 46978880828 ps
CPU time 71.88 seconds
Started Sep 11 03:19:41 AM UTC 24
Finished Sep 11 03:20:55 AM UTC 24
Peak memory 207544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044550061 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2044550061
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.3552426641
Short name T950
Test name
Test status
Simulation time 46851045647 ps
CPU time 151.52 seconds
Started Sep 11 03:19:50 AM UTC 24
Finished Sep 11 03:22:24 AM UTC 24
Peak memory 208944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552426641 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3552426641
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_loopback.3062745203
Short name T888
Test name
Test status
Simulation time 1853303335 ps
CPU time 2.62 seconds
Started Sep 11 03:19:49 AM UTC 24
Finished Sep 11 03:19:52 AM UTC 24
Peak memory 205156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062745203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3062745203
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_noise_filter.1379515310
Short name T389
Test name
Test status
Simulation time 34842320943 ps
CPU time 11.44 seconds
Started Sep 11 03:19:42 AM UTC 24
Finished Sep 11 03:19:55 AM UTC 24
Peak memory 207408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379515310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1379515310
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_perf.1984193818
Short name T964
Test name
Test status
Simulation time 39451073805 ps
CPU time 178.35 seconds
Started Sep 11 03:19:49 AM UTC 24
Finished Sep 11 03:22:50 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984193818 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1984193818
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_rx_oversample.456811165
Short name T890
Test name
Test status
Simulation time 4634503062 ps
CPU time 12.01 seconds
Started Sep 11 03:19:40 AM UTC 24
Finished Sep 11 03:19:53 AM UTC 24
Peak memory 208076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456811165 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.456811165
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.2982909772
Short name T929
Test name
Test status
Simulation time 60116553854 ps
CPU time 112.79 seconds
Started Sep 11 03:19:47 AM UTC 24
Finished Sep 11 03:21:42 AM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982909772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2982909772
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.1591026910
Short name T893
Test name
Test status
Simulation time 3232659803 ps
CPU time 10.27 seconds
Started Sep 11 03:19:46 AM UTC 24
Finished Sep 11 03:19:58 AM UTC 24
Peak memory 205216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591026910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1591026910
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_smoke.3375932989
Short name T878
Test name
Test status
Simulation time 439017306 ps
CPU time 2.35 seconds
Started Sep 11 03:19:37 AM UTC 24
Finished Sep 11 03:19:40 AM UTC 24
Peak memory 208444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375932989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3375932989
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_stress_all.3400627192
Short name T908
Test name
Test status
Simulation time 53685693255 ps
CPU time 53.41 seconds
Started Sep 11 03:19:52 AM UTC 24
Finished Sep 11 03:20:47 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400627192 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3400627192
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.2395783774
Short name T912
Test name
Test status
Simulation time 8426102463 ps
CPU time 58.11 seconds
Started Sep 11 03:19:52 AM UTC 24
Finished Sep 11 03:20:52 AM UTC 24
Peak memory 217796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2395783774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all
_with_rand_reset.2395783774
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.2995586338
Short name T892
Test name
Test status
Simulation time 980194153 ps
CPU time 5.38 seconds
Started Sep 11 03:19:47 AM UTC 24
Finished Sep 11 03:19:54 AM UTC 24
Peak memory 208140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995586338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2995586338
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/49.uart_tx_rx.309537766
Short name T923
Test name
Test status
Simulation time 105636706210 ps
CPU time 104.01 seconds
Started Sep 11 03:19:37 AM UTC 24
Finished Sep 11 03:21:23 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309537766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.309537766
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/49.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_alert_test.3686897056
Short name T408
Test name
Test status
Simulation time 17287304 ps
CPU time 0.85 seconds
Started Sep 11 02:57:07 AM UTC 24
Finished Sep 11 02:57:09 AM UTC 24
Peak memory 204372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686897056 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3686897056
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_fifo_full.1544161151
Short name T84
Test name
Test status
Simulation time 70260625646 ps
CPU time 61.31 seconds
Started Sep 11 02:56:54 AM UTC 24
Finished Sep 11 02:57:57 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544161151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1544161151
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_fifo_reset.531887492
Short name T175
Test name
Test status
Simulation time 20361669947 ps
CPU time 19.84 seconds
Started Sep 11 02:56:55 AM UTC 24
Finished Sep 11 02:57:16 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531887492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.531887492
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_intr.996296121
Short name T85
Test name
Test status
Simulation time 33380679949 ps
CPU time 27.11 seconds
Started Sep 11 02:56:57 AM UTC 24
Finished Sep 11 02:57:25 AM UTC 24
Peak memory 208712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996296121 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.996296121
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.3639883690
Short name T563
Test name
Test status
Simulation time 109142920261 ps
CPU time 653.27 seconds
Started Sep 11 02:57:03 AM UTC 24
Finished Sep 11 03:08:04 AM UTC 24
Peak memory 212280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639883690 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3639883690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_loopback.2541002576
Short name T380
Test name
Test status
Simulation time 6301237210 ps
CPU time 7.46 seconds
Started Sep 11 02:57:01 AM UTC 24
Finished Sep 11 02:57:09 AM UTC 24
Peak memory 207140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541002576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2541002576
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_perf.2931831588
Short name T868
Test name
Test status
Simulation time 26293626121 ps
CPU time 1331.26 seconds
Started Sep 11 02:57:03 AM UTC 24
Finished Sep 11 03:19:29 AM UTC 24
Peak memory 212224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931831588 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2931831588
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_rx_oversample.3317167638
Short name T410
Test name
Test status
Simulation time 4298305713 ps
CPU time 20.71 seconds
Started Sep 11 02:56:56 AM UTC 24
Finished Sep 11 02:57:18 AM UTC 24
Peak memory 207276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317167638 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3317167638
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.2935664684
Short name T116
Test name
Test status
Simulation time 29914987775 ps
CPU time 51.73 seconds
Started Sep 11 02:57:01 AM UTC 24
Finished Sep 11 02:57:54 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935664684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2935664684
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.4087702515
Short name T313
Test name
Test status
Simulation time 42120016447 ps
CPU time 16.06 seconds
Started Sep 11 02:57:00 AM UTC 24
Finished Sep 11 02:57:17 AM UTC 24
Peak memory 205092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087702515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.4087702515
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_smoke.72320154
Short name T264
Test name
Test status
Simulation time 512569253 ps
CPU time 2.36 seconds
Started Sep 11 02:56:51 AM UTC 24
Finished Sep 11 02:56:55 AM UTC 24
Peak memory 207676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72320154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_smoke.72320154
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_stress_all.2769504240
Short name T677
Test name
Test status
Simulation time 141228341966 ps
CPU time 961.07 seconds
Started Sep 11 02:57:07 AM UTC 24
Finished Sep 11 03:13:20 AM UTC 24
Peak memory 212148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769504240 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2769504240
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.1913172242
Short name T31
Test name
Test status
Simulation time 2102514894 ps
CPU time 12.43 seconds
Started Sep 11 02:57:05 AM UTC 24
Finished Sep 11 02:57:19 AM UTC 24
Peak memory 217720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1913172242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_
with_rand_reset.1913172242
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.609168208
Short name T342
Test name
Test status
Simulation time 6231322875 ps
CPU time 22.93 seconds
Started Sep 11 02:57:01 AM UTC 24
Finished Sep 11 02:57:25 AM UTC 24
Peak memory 208504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609168208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.609168208
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/50.uart_fifo_reset.3326995270
Short name T385
Test name
Test status
Simulation time 157075704555 ps
CPU time 235.97 seconds
Started Sep 11 03:19:53 AM UTC 24
Finished Sep 11 03:23:52 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326995270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3326995270
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/50.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.1268025998
Short name T899
Test name
Test status
Simulation time 4611410333 ps
CPU time 35.17 seconds
Started Sep 11 03:19:54 AM UTC 24
Finished Sep 11 03:20:31 AM UTC 24
Peak memory 217804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1268025998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all
_with_rand_reset.1268025998
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/51.uart_fifo_reset.2018494165
Short name T140
Test name
Test status
Simulation time 128571178519 ps
CPU time 158.47 seconds
Started Sep 11 03:19:54 AM UTC 24
Finished Sep 11 03:22:35 AM UTC 24
Peak memory 208736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018494165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2018494165
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/51.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.3666643671
Short name T900
Test name
Test status
Simulation time 9716638982 ps
CPU time 39.1 seconds
Started Sep 11 03:19:54 AM UTC 24
Finished Sep 11 03:20:35 AM UTC 24
Peak memory 217668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3666643671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all
_with_rand_reset.3666643671
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.3629083817
Short name T909
Test name
Test status
Simulation time 2790363120 ps
CPU time 52.67 seconds
Started Sep 11 03:19:55 AM UTC 24
Finished Sep 11 03:20:50 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3629083817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all
_with_rand_reset.3629083817
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/53.uart_fifo_reset.4051344747
Short name T1015
Test name
Test status
Simulation time 118384849270 ps
CPU time 268.91 seconds
Started Sep 11 03:19:58 AM UTC 24
Finished Sep 11 03:24:31 AM UTC 24
Peak memory 208848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051344747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.4051344747
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/53.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.1458829930
Short name T907
Test name
Test status
Simulation time 2957022467 ps
CPU time 37.7 seconds
Started Sep 11 03:20:05 AM UTC 24
Finished Sep 11 03:20:45 AM UTC 24
Peak memory 219820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1458829930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all
_with_rand_reset.1458829930
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/54.uart_fifo_reset.2390262617
Short name T235
Test name
Test status
Simulation time 164210936039 ps
CPU time 23.49 seconds
Started Sep 11 03:20:07 AM UTC 24
Finished Sep 11 03:20:32 AM UTC 24
Peak memory 208564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390262617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2390262617
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/54.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.895912568
Short name T915
Test name
Test status
Simulation time 9755252760 ps
CPU time 45.9 seconds
Started Sep 11 03:20:15 AM UTC 24
Finished Sep 11 03:21:02 AM UTC 24
Peak memory 217572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=895912568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all_
with_rand_reset.895912568
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/55.uart_fifo_reset.2155406190
Short name T1024
Test name
Test status
Simulation time 134361451491 ps
CPU time 262 seconds
Started Sep 11 03:20:23 AM UTC 24
Finished Sep 11 03:24:48 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155406190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2155406190
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/55.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.1566791932
Short name T910
Test name
Test status
Simulation time 7031466216 ps
CPU time 23.62 seconds
Started Sep 11 03:20:25 AM UTC 24
Finished Sep 11 03:20:50 AM UTC 24
Peak memory 219956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1566791932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all
_with_rand_reset.1566791932
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/56.uart_fifo_reset.1622898826
Short name T213
Test name
Test status
Simulation time 64677890749 ps
CPU time 158.74 seconds
Started Sep 11 03:20:28 AM UTC 24
Finished Sep 11 03:23:09 AM UTC 24
Peak memory 208912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622898826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1622898826
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/56.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.3396509318
Short name T920
Test name
Test status
Simulation time 3100142515 ps
CPU time 47.82 seconds
Started Sep 11 03:20:28 AM UTC 24
Finished Sep 11 03:21:17 AM UTC 24
Peak memory 217724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3396509318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all
_with_rand_reset.3396509318
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/57.uart_fifo_reset.1139783605
Short name T918
Test name
Test status
Simulation time 11532285896 ps
CPU time 35.54 seconds
Started Sep 11 03:20:30 AM UTC 24
Finished Sep 11 03:21:07 AM UTC 24
Peak memory 208708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139783605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1139783605
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/57.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/58.uart_fifo_reset.3626533752
Short name T401
Test name
Test status
Simulation time 96509901916 ps
CPU time 148.53 seconds
Started Sep 11 03:20:32 AM UTC 24
Finished Sep 11 03:23:03 AM UTC 24
Peak memory 208676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626533752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3626533752
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/58.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.2462712511
Short name T924
Test name
Test status
Simulation time 1169912360 ps
CPU time 52.74 seconds
Started Sep 11 03:20:35 AM UTC 24
Finished Sep 11 03:21:30 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2462712511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all
_with_rand_reset.2462712511
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/59.uart_fifo_reset.1577895333
Short name T934
Test name
Test status
Simulation time 91195608947 ps
CPU time 74.08 seconds
Started Sep 11 03:20:36 AM UTC 24
Finished Sep 11 03:21:52 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577895333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1577895333
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/59.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.1009234472
Short name T911
Test name
Test status
Simulation time 1167402610 ps
CPU time 10.83 seconds
Started Sep 11 03:20:39 AM UTC 24
Finished Sep 11 03:20:51 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1009234472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all
_with_rand_reset.1009234472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_alert_test.115585412
Short name T412
Test name
Test status
Simulation time 10458515 ps
CPU time 0.82 seconds
Started Sep 11 02:57:22 AM UTC 24
Finished Sep 11 02:57:24 AM UTC 24
Peak memory 204412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115585412 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.115585412
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_fifo_full.2002289045
Short name T108
Test name
Test status
Simulation time 54000249251 ps
CPU time 38.91 seconds
Started Sep 11 02:57:12 AM UTC 24
Finished Sep 11 02:57:52 AM UTC 24
Peak memory 208264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002289045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2002289045
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.4124765424
Short name T87
Test name
Test status
Simulation time 39168985650 ps
CPU time 37.44 seconds
Started Sep 11 02:57:12 AM UTC 24
Finished Sep 11 02:57:50 AM UTC 24
Peak memory 208480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124765424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4124765424
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_fifo_reset.4205754136
Short name T115
Test name
Test status
Simulation time 50444776921 ps
CPU time 16.29 seconds
Started Sep 11 02:57:12 AM UTC 24
Finished Sep 11 02:57:29 AM UTC 24
Peak memory 208816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205754136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4205754136
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_intr.4223973226
Short name T374
Test name
Test status
Simulation time 7230258711 ps
CPU time 4.84 seconds
Started Sep 11 02:57:16 AM UTC 24
Finished Sep 11 02:57:22 AM UTC 24
Peak memory 205088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223973226 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.4223973226
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_loopback.1576909082
Short name T381
Test name
Test status
Simulation time 3537447161 ps
CPU time 3.6 seconds
Started Sep 11 02:57:20 AM UTC 24
Finished Sep 11 02:57:25 AM UTC 24
Peak memory 207140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576909082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.uart_loopback.1576909082
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_noise_filter.3592404969
Short name T271
Test name
Test status
Simulation time 91985623465 ps
CPU time 48.66 seconds
Started Sep 11 02:57:18 AM UTC 24
Finished Sep 11 02:58:08 AM UTC 24
Peak memory 208912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592404969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3592404969
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_perf.2429072589
Short name T733
Test name
Test status
Simulation time 21183626532 ps
CPU time 1077.99 seconds
Started Sep 11 02:57:20 AM UTC 24
Finished Sep 11 03:15:31 AM UTC 24
Peak memory 212164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429072589 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2429072589
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_rx_oversample.1286648104
Short name T379
Test name
Test status
Simulation time 4207951558 ps
CPU time 15.26 seconds
Started Sep 11 02:57:14 AM UTC 24
Finished Sep 11 02:57:30 AM UTC 24
Peak memory 207212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286648104 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1286648104
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.574903667
Short name T252
Test name
Test status
Simulation time 49233655256 ps
CPU time 67.17 seconds
Started Sep 11 02:57:18 AM UTC 24
Finished Sep 11 02:58:27 AM UTC 24
Peak memory 207332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574903667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.574903667
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_smoke.1162789938
Short name T325
Test name
Test status
Simulation time 645570605 ps
CPU time 2.64 seconds
Started Sep 11 02:57:09 AM UTC 24
Finished Sep 11 02:57:13 AM UTC 24
Peak memory 207528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162789938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.1162789938
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.1835297230
Short name T33
Test name
Test status
Simulation time 1534814024 ps
CPU time 19.05 seconds
Started Sep 11 02:57:20 AM UTC 24
Finished Sep 11 02:57:41 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1835297230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_
with_rand_reset.1835297230
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.129587611
Short name T270
Test name
Test status
Simulation time 790807167 ps
CPU time 3.65 seconds
Started Sep 11 02:57:18 AM UTC 24
Finished Sep 11 02:57:23 AM UTC 24
Peak memory 207352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129587611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.129587611
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/60.uart_fifo_reset.338266481
Short name T156
Test name
Test status
Simulation time 15999302957 ps
CPU time 30.58 seconds
Started Sep 11 03:20:40 AM UTC 24
Finished Sep 11 03:21:11 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338266481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.338266481
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/60.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.2220029098
Short name T946
Test name
Test status
Simulation time 4144852032 ps
CPU time 89.53 seconds
Started Sep 11 03:20:41 AM UTC 24
Finished Sep 11 03:22:12 AM UTC 24
Peak memory 217644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2220029098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all
_with_rand_reset.2220029098
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/61.uart_fifo_reset.2373428101
Short name T966
Test name
Test status
Simulation time 75439453385 ps
CPU time 129.25 seconds
Started Sep 11 03:20:44 AM UTC 24
Finished Sep 11 03:22:55 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373428101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2373428101
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/61.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.1872558881
Short name T917
Test name
Test status
Simulation time 921705214 ps
CPU time 17.93 seconds
Started Sep 11 03:20:45 AM UTC 24
Finished Sep 11 03:21:04 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1872558881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all
_with_rand_reset.1872558881
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/62.uart_fifo_reset.3373692018
Short name T185
Test name
Test status
Simulation time 169804606607 ps
CPU time 52.91 seconds
Started Sep 11 03:20:46 AM UTC 24
Finished Sep 11 03:21:41 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373692018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3373692018
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/62.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.3995465672
Short name T933
Test name
Test status
Simulation time 2739782079 ps
CPU time 56.91 seconds
Started Sep 11 03:20:48 AM UTC 24
Finished Sep 11 03:21:46 AM UTC 24
Peak memory 217772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3995465672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all
_with_rand_reset.3995465672
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/63.uart_fifo_reset.894864704
Short name T951
Test name
Test status
Simulation time 51330264469 ps
CPU time 95.75 seconds
Started Sep 11 03:20:50 AM UTC 24
Finished Sep 11 03:22:28 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894864704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.894864704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/63.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.1201591877
Short name T919
Test name
Test status
Simulation time 1087293917 ps
CPU time 18.53 seconds
Started Sep 11 03:20:51 AM UTC 24
Finished Sep 11 03:21:11 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1201591877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all
_with_rand_reset.1201591877
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/64.uart_fifo_reset.3370698845
Short name T977
Test name
Test status
Simulation time 102552982956 ps
CPU time 137.63 seconds
Started Sep 11 03:20:52 AM UTC 24
Finished Sep 11 03:23:12 AM UTC 24
Peak memory 208808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370698845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3370698845
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/64.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/64.uart_stress_all_with_rand_reset.3781367839
Short name T931
Test name
Test status
Simulation time 41085820449 ps
CPU time 49.43 seconds
Started Sep 11 03:20:52 AM UTC 24
Finished Sep 11 03:21:43 AM UTC 24
Peak memory 224952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3781367839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_stress_all
_with_rand_reset.3781367839
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/64.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/65.uart_fifo_reset.3072738500
Short name T390
Test name
Test status
Simulation time 95329702830 ps
CPU time 35.06 seconds
Started Sep 11 03:20:55 AM UTC 24
Finished Sep 11 03:21:32 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072738500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3072738500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/65.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.2248640551
Short name T925
Test name
Test status
Simulation time 2696984340 ps
CPU time 30.06 seconds
Started Sep 11 03:21:00 AM UTC 24
Finished Sep 11 03:21:32 AM UTC 24
Peak memory 217644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2248640551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all
_with_rand_reset.2248640551
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/66.uart_fifo_reset.4291490038
Short name T938
Test name
Test status
Simulation time 14132888141 ps
CPU time 53.55 seconds
Started Sep 11 03:21:02 AM UTC 24
Finished Sep 11 03:21:58 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291490038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.4291490038
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/66.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.4022311147
Short name T937
Test name
Test status
Simulation time 8720136714 ps
CPU time 51.36 seconds
Started Sep 11 03:21:05 AM UTC 24
Finished Sep 11 03:21:57 AM UTC 24
Peak memory 223924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4022311147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all
_with_rand_reset.4022311147
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/67.uart_fifo_reset.496406983
Short name T935
Test name
Test status
Simulation time 59814797939 ps
CPU time 48.3 seconds
Started Sep 11 03:21:05 AM UTC 24
Finished Sep 11 03:21:54 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496406983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.496406983
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/67.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.3003706666
Short name T926
Test name
Test status
Simulation time 2949842756 ps
CPU time 26.35 seconds
Started Sep 11 03:21:08 AM UTC 24
Finished Sep 11 03:21:35 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3003706666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all
_with_rand_reset.3003706666
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/68.uart_fifo_reset.1042765252
Short name T1176
Test name
Test status
Simulation time 185702342177 ps
CPU time 579.7 seconds
Started Sep 11 03:21:12 AM UTC 24
Finished Sep 11 03:30:58 AM UTC 24
Peak memory 212224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042765252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1042765252
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/68.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.304028668
Short name T932
Test name
Test status
Simulation time 1674687830 ps
CPU time 31.47 seconds
Started Sep 11 03:21:12 AM UTC 24
Finished Sep 11 03:21:45 AM UTC 24
Peak memory 217736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=304028668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all_
with_rand_reset.304028668
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/69.uart_fifo_reset.1065434913
Short name T1004
Test name
Test status
Simulation time 135306655577 ps
CPU time 169.8 seconds
Started Sep 11 03:21:13 AM UTC 24
Finished Sep 11 03:24:06 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065434913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1065434913
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/69.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.143902781
Short name T927
Test name
Test status
Simulation time 2174930193 ps
CPU time 16.72 seconds
Started Sep 11 03:21:18 AM UTC 24
Finished Sep 11 03:21:36 AM UTC 24
Peak memory 217908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=143902781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all_
with_rand_reset.143902781
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_alert_test.1743890700
Short name T414
Test name
Test status
Simulation time 43212437 ps
CPU time 0.76 seconds
Started Sep 11 02:57:42 AM UTC 24
Finished Sep 11 02:57:43 AM UTC 24
Peak memory 204372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743890700 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1743890700
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_fifo_full.1125654372
Short name T114
Test name
Test status
Simulation time 18122478081 ps
CPU time 28.15 seconds
Started Sep 11 02:57:25 AM UTC 24
Finished Sep 11 02:57:55 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125654372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1125654372
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.3307139412
Short name T340
Test name
Test status
Simulation time 103228548238 ps
CPU time 91.82 seconds
Started Sep 11 02:57:25 AM UTC 24
Finished Sep 11 02:58:59 AM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307139412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3307139412
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_fifo_reset.2752595746
Short name T130
Test name
Test status
Simulation time 11745437707 ps
CPU time 37.85 seconds
Started Sep 11 02:57:27 AM UTC 24
Finished Sep 11 02:58:06 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752595746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2752595746
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_intr.578228614
Short name T345
Test name
Test status
Simulation time 140215962635 ps
CPU time 133.13 seconds
Started Sep 11 02:57:27 AM UTC 24
Finished Sep 11 02:59:42 AM UTC 24
Peak memory 208836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578228614 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.578228614
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.3259555939
Short name T517
Test name
Test status
Simulation time 171037974172 ps
CPU time 507.35 seconds
Started Sep 11 02:57:35 AM UTC 24
Finished Sep 11 03:06:10 AM UTC 24
Peak memory 210004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259555939 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3259555939
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_loopback.917949659
Short name T413
Test name
Test status
Simulation time 7048051432 ps
CPU time 7.36 seconds
Started Sep 11 02:57:33 AM UTC 24
Finished Sep 11 02:57:42 AM UTC 24
Peak memory 208144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917949659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.uart_loopback.917949659
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_noise_filter.912215811
Short name T360
Test name
Test status
Simulation time 108654614297 ps
CPU time 300.27 seconds
Started Sep 11 02:57:27 AM UTC 24
Finished Sep 11 03:02:32 AM UTC 24
Peak memory 207816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912215811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.912215811
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_perf.3910994679
Short name T353
Test name
Test status
Simulation time 24333238236 ps
CPU time 364.37 seconds
Started Sep 11 02:57:33 AM UTC 24
Finished Sep 11 03:03:42 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910994679 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.3910994679
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_rx_oversample.3452623973
Short name T415
Test name
Test status
Simulation time 4008955260 ps
CPU time 17.57 seconds
Started Sep 11 02:57:27 AM UTC 24
Finished Sep 11 02:57:46 AM UTC 24
Peak memory 207200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452623973 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3452623973
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.875683812
Short name T106
Test name
Test status
Simulation time 196489105984 ps
CPU time 40.01 seconds
Started Sep 11 02:57:31 AM UTC 24
Finished Sep 11 02:58:13 AM UTC 24
Peak memory 208264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875683812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.875683812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.4101580035
Short name T277
Test name
Test status
Simulation time 7323339856 ps
CPU time 1.89 seconds
Started Sep 11 02:57:29 AM UTC 24
Finished Sep 11 02:57:32 AM UTC 24
Peak memory 204432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101580035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.4101580035
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_smoke.4235266500
Short name T324
Test name
Test status
Simulation time 6152902026 ps
CPU time 5.2 seconds
Started Sep 11 02:57:23 AM UTC 24
Finished Sep 11 02:57:29 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235266500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.4235266500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_stress_all.3048046658
Short name T215
Test name
Test status
Simulation time 141253709515 ps
CPU time 984.19 seconds
Started Sep 11 02:57:37 AM UTC 24
Finished Sep 11 03:14:13 AM UTC 24
Peak memory 212284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048046658 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3048046658
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.2193709738
Short name T300
Test name
Test status
Simulation time 1987496172 ps
CPU time 3.15 seconds
Started Sep 11 02:57:31 AM UTC 24
Finished Sep 11 02:57:35 AM UTC 24
Peak memory 207468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193709738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.2193709738
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/7.uart_tx_rx.641790122
Short name T275
Test name
Test status
Simulation time 51710586257 ps
CPU time 145.54 seconds
Started Sep 11 02:57:23 AM UTC 24
Finished Sep 11 02:59:51 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641790122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.641790122
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/7.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/70.uart_fifo_reset.1877245217
Short name T384
Test name
Test status
Simulation time 75995624584 ps
CPU time 84.79 seconds
Started Sep 11 03:21:19 AM UTC 24
Finished Sep 11 03:22:46 AM UTC 24
Peak memory 208460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877245217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.1877245217
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/70.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.1584904789
Short name T942
Test name
Test status
Simulation time 2676371637 ps
CPU time 42.78 seconds
Started Sep 11 03:21:20 AM UTC 24
Finished Sep 11 03:22:04 AM UTC 24
Peak memory 219852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1584904789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all
_with_rand_reset.1584904789
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/71.uart_fifo_reset.291384224
Short name T939
Test name
Test status
Simulation time 68727134898 ps
CPU time 35.23 seconds
Started Sep 11 03:21:23 AM UTC 24
Finished Sep 11 03:22:00 AM UTC 24
Peak memory 208912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291384224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.291384224
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/71.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.2646574216
Short name T943
Test name
Test status
Simulation time 3331849991 ps
CPU time 32.83 seconds
Started Sep 11 03:21:30 AM UTC 24
Finished Sep 11 03:22:05 AM UTC 24
Peak memory 217776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2646574216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all
_with_rand_reset.2646574216
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/72.uart_fifo_reset.871713613
Short name T958
Test name
Test status
Simulation time 92539183728 ps
CPU time 68.42 seconds
Started Sep 11 03:21:32 AM UTC 24
Finished Sep 11 03:22:43 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871713613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.871713613
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/72.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.1752625019
Short name T952
Test name
Test status
Simulation time 17593175041 ps
CPU time 57.45 seconds
Started Sep 11 03:21:32 AM UTC 24
Finished Sep 11 03:22:32 AM UTC 24
Peak memory 221764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1752625019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all
_with_rand_reset.1752625019
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/73.uart_fifo_reset.246647889
Short name T940
Test name
Test status
Simulation time 18230808917 ps
CPU time 23.05 seconds
Started Sep 11 03:21:37 AM UTC 24
Finished Sep 11 03:22:01 AM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246647889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.246647889
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/73.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.1703574018
Short name T962
Test name
Test status
Simulation time 19192189368 ps
CPU time 68.88 seconds
Started Sep 11 03:21:37 AM UTC 24
Finished Sep 11 03:22:47 AM UTC 24
Peak memory 225244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1703574018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all
_with_rand_reset.1703574018
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/74.uart_fifo_reset.310226206
Short name T223
Test name
Test status
Simulation time 135642094878 ps
CPU time 24.88 seconds
Started Sep 11 03:21:38 AM UTC 24
Finished Sep 11 03:22:04 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310226206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.310226206
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/74.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.1638699812
Short name T941
Test name
Test status
Simulation time 7213297279 ps
CPU time 20.49 seconds
Started Sep 11 03:21:41 AM UTC 24
Finished Sep 11 03:22:03 AM UTC 24
Peak memory 217772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1638699812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all
_with_rand_reset.1638699812
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.2947096456
Short name T944
Test name
Test status
Simulation time 10145924282 ps
CPU time 20.78 seconds
Started Sep 11 03:21:43 AM UTC 24
Finished Sep 11 03:22:05 AM UTC 24
Peak memory 217736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2947096456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all
_with_rand_reset.2947096456
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.805200825
Short name T949
Test name
Test status
Simulation time 2324546712 ps
CPU time 33.96 seconds
Started Sep 11 03:21:45 AM UTC 24
Finished Sep 11 03:22:21 AM UTC 24
Peak memory 217924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=805200825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all_
with_rand_reset.805200825
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/77.uart_fifo_reset.3680365872
Short name T960
Test name
Test status
Simulation time 283983742623 ps
CPU time 56.57 seconds
Started Sep 11 03:21:47 AM UTC 24
Finished Sep 11 03:22:46 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680365872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3680365872
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/77.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.3023850909
Short name T961
Test name
Test status
Simulation time 2426931460 ps
CPU time 51.06 seconds
Started Sep 11 03:21:53 AM UTC 24
Finished Sep 11 03:22:46 AM UTC 24
Peak memory 217644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3023850909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all
_with_rand_reset.3023850909
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/78.uart_fifo_reset.283802560
Short name T945
Test name
Test status
Simulation time 5769676515 ps
CPU time 12.48 seconds
Started Sep 11 03:21:55 AM UTC 24
Finished Sep 11 03:22:09 AM UTC 24
Peak memory 208588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283802560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.283802560
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/78.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.3702152
Short name T971
Test name
Test status
Simulation time 8130540340 ps
CPU time 62.17 seconds
Started Sep 11 03:21:57 AM UTC 24
Finished Sep 11 03:23:01 AM UTC 24
Peak memory 224868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3702152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all_wi
th_rand_reset.3702152
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/79.uart_fifo_reset.94736062
Short name T1006
Test name
Test status
Simulation time 297372318000 ps
CPU time 125.56 seconds
Started Sep 11 03:21:59 AM UTC 24
Finished Sep 11 03:24:06 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94736062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.94736062
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/79.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.685504958
Short name T963
Test name
Test status
Simulation time 15040423810 ps
CPU time 47.49 seconds
Started Sep 11 03:21:59 AM UTC 24
Finished Sep 11 03:22:48 AM UTC 24
Peak memory 219772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=685504958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all_
with_rand_reset.685504958
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_alert_test.3195399472
Short name T417
Test name
Test status
Simulation time 56581313 ps
CPU time 0.75 seconds
Started Sep 11 02:58:08 AM UTC 24
Finished Sep 11 02:58:10 AM UTC 24
Peak memory 204372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195399472 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3195399472
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_fifo_full.4159744033
Short name T151
Test name
Test status
Simulation time 269619007423 ps
CPU time 340.97 seconds
Started Sep 11 02:57:44 AM UTC 24
Finished Sep 11 03:03:30 AM UTC 24
Peak memory 208892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159744033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.4159744033
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.1168159221
Short name T323
Test name
Test status
Simulation time 106709699445 ps
CPU time 293.33 seconds
Started Sep 11 02:57:48 AM UTC 24
Finished Sep 11 03:02:45 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168159221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.1168159221
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_fifo_reset.4173113923
Short name T214
Test name
Test status
Simulation time 13849487725 ps
CPU time 26.36 seconds
Started Sep 11 02:57:48 AM UTC 24
Finished Sep 11 02:58:15 AM UTC 24
Peak memory 208748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173113923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.4173113923
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.3538872846
Short name T355
Test name
Test status
Simulation time 57268449320 ps
CPU time 211.03 seconds
Started Sep 11 02:57:57 AM UTC 24
Finished Sep 11 03:01:31 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538872846 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3538872846
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_loopback.3208903126
Short name T416
Test name
Test status
Simulation time 9969578225 ps
CPU time 12.16 seconds
Started Sep 11 02:57:54 AM UTC 24
Finished Sep 11 02:58:08 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208903126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3208903126
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_noise_filter.3739741474
Short name T335
Test name
Test status
Simulation time 145939737224 ps
CPU time 187.94 seconds
Started Sep 11 02:57:52 AM UTC 24
Finished Sep 11 03:01:03 AM UTC 24
Peak memory 208744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739741474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3739741474
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_perf.2197312319
Short name T431
Test name
Test status
Simulation time 12283765224 ps
CPU time 124.42 seconds
Started Sep 11 02:57:56 AM UTC 24
Finished Sep 11 03:00:03 AM UTC 24
Peak memory 208752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197312319 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2197312319
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_rx_oversample.1270569153
Short name T418
Test name
Test status
Simulation time 3287458863 ps
CPU time 18.57 seconds
Started Sep 11 02:57:50 AM UTC 24
Finished Sep 11 02:58:10 AM UTC 24
Peak memory 207772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270569153 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1270569153
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.2394128117
Short name T265
Test name
Test status
Simulation time 36425661776 ps
CPU time 30.91 seconds
Started Sep 11 02:57:54 AM UTC 24
Finished Sep 11 02:58:26 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394128117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2394128117
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.3184914103
Short name T260
Test name
Test status
Simulation time 35348937202 ps
CPU time 12.32 seconds
Started Sep 11 02:57:52 AM UTC 24
Finished Sep 11 02:58:06 AM UTC 24
Peak memory 207076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184914103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.3184914103
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_smoke.1095616041
Short name T295
Test name
Test status
Simulation time 5519966586 ps
CPU time 10.64 seconds
Started Sep 11 02:57:42 AM UTC 24
Finished Sep 11 02:57:53 AM UTC 24
Peak memory 208348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095616041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1095616041
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_stress_all.4075383529
Short name T66
Test name
Test status
Simulation time 66816212264 ps
CPU time 83.51 seconds
Started Sep 11 02:58:04 AM UTC 24
Finished Sep 11 02:59:29 AM UTC 24
Peak memory 208964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075383529 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4075383529
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.4015964450
Short name T34
Test name
Test status
Simulation time 2616223594 ps
CPU time 11.63 seconds
Started Sep 11 02:57:58 AM UTC 24
Finished Sep 11 02:58:10 AM UTC 24
Peak memory 209028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4015964450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_
with_rand_reset.4015964450
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.2678158443
Short name T311
Test name
Test status
Simulation time 868096795 ps
CPU time 6.22 seconds
Started Sep 11 02:57:54 AM UTC 24
Finished Sep 11 02:58:02 AM UTC 24
Peak memory 208448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678158443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2678158443
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/8.uart_tx_rx.889024225
Short name T309
Test name
Test status
Simulation time 108267798249 ps
CPU time 527.71 seconds
Started Sep 11 02:57:44 AM UTC 24
Finished Sep 11 03:06:38 AM UTC 24
Peak memory 208648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889024225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.889024225
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/8.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/80.uart_fifo_reset.2403581569
Short name T210
Test name
Test status
Simulation time 53427242826 ps
CPU time 39 seconds
Started Sep 11 03:22:01 AM UTC 24
Finished Sep 11 03:22:41 AM UTC 24
Peak memory 208488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403581569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2403581569
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/80.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.867476625
Short name T953
Test name
Test status
Simulation time 2251276168 ps
CPU time 29.22 seconds
Started Sep 11 03:22:02 AM UTC 24
Finished Sep 11 03:22:33 AM UTC 24
Peak memory 223860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=867476625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all_
with_rand_reset.867476625
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/81.uart_fifo_reset.819774437
Short name T969
Test name
Test status
Simulation time 27896727380 ps
CPU time 52.97 seconds
Started Sep 11 03:22:04 AM UTC 24
Finished Sep 11 03:22:59 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819774437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.819774437
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/81.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.280341381
Short name T972
Test name
Test status
Simulation time 3518380086 ps
CPU time 54.77 seconds
Started Sep 11 03:22:05 AM UTC 24
Finished Sep 11 03:23:01 AM UTC 24
Peak memory 217796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=280341381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all_
with_rand_reset.280341381
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.3005578596
Short name T955
Test name
Test status
Simulation time 9393311427 ps
CPU time 26.86 seconds
Started Sep 11 03:22:05 AM UTC 24
Finished Sep 11 03:22:33 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3005578596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all
_with_rand_reset.3005578596
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1658733294
Short name T954
Test name
Test status
Simulation time 14159827722 ps
CPU time 25.34 seconds
Started Sep 11 03:22:06 AM UTC 24
Finished Sep 11 03:22:33 AM UTC 24
Peak memory 207800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658733294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1658733294
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/83.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.2197931169
Short name T1000
Test name
Test status
Simulation time 9424146181 ps
CPU time 98.47 seconds
Started Sep 11 03:22:10 AM UTC 24
Finished Sep 11 03:23:51 AM UTC 24
Peak memory 225140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2197931169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all
_with_rand_reset.2197931169
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/84.uart_fifo_reset.323834189
Short name T191
Test name
Test status
Simulation time 218495357624 ps
CPU time 152.28 seconds
Started Sep 11 03:22:13 AM UTC 24
Finished Sep 11 03:24:48 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323834189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.323834189
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/84.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.406945369
Short name T991
Test name
Test status
Simulation time 16584099334 ps
CPU time 82.07 seconds
Started Sep 11 03:22:17 AM UTC 24
Finished Sep 11 03:23:41 AM UTC 24
Peak memory 219828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=406945369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all_
with_rand_reset.406945369
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/85.uart_fifo_reset.420200519
Short name T203
Test name
Test status
Simulation time 45630210386 ps
CPU time 130.65 seconds
Started Sep 11 03:22:19 AM UTC 24
Finished Sep 11 03:24:31 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420200519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.420200519
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/85.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.2266177737
Short name T959
Test name
Test status
Simulation time 3345765656 ps
CPU time 21.94 seconds
Started Sep 11 03:22:22 AM UTC 24
Finished Sep 11 03:22:45 AM UTC 24
Peak memory 208908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2266177737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all
_with_rand_reset.2266177737
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/86.uart_fifo_reset.2230503271
Short name T968
Test name
Test status
Simulation time 31083818884 ps
CPU time 31.33 seconds
Started Sep 11 03:22:25 AM UTC 24
Finished Sep 11 03:22:58 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230503271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2230503271
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/86.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.1216051433
Short name T970
Test name
Test status
Simulation time 2163597603 ps
CPU time 30.89 seconds
Started Sep 11 03:22:29 AM UTC 24
Finished Sep 11 03:23:01 AM UTC 24
Peak memory 217708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1216051433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all
_with_rand_reset.1216051433
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/87.uart_fifo_reset.1618441966
Short name T967
Test name
Test status
Simulation time 20388132878 ps
CPU time 22.88 seconds
Started Sep 11 03:22:33 AM UTC 24
Finished Sep 11 03:22:57 AM UTC 24
Peak memory 208976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618441966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1618441966
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/87.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.3511090356
Short name T976
Test name
Test status
Simulation time 2843879665 ps
CPU time 35.92 seconds
Started Sep 11 03:22:34 AM UTC 24
Finished Sep 11 03:23:11 AM UTC 24
Peak memory 217644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3511090356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all
_with_rand_reset.3511090356
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/88.uart_fifo_reset.2177844434
Short name T1092
Test name
Test status
Simulation time 121455521867 ps
CPU time 261.4 seconds
Started Sep 11 03:22:34 AM UTC 24
Finished Sep 11 03:26:59 AM UTC 24
Peak memory 208952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177844434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2177844434
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/88.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.1063077301
Short name T965
Test name
Test status
Simulation time 8882405409 ps
CPU time 18.77 seconds
Started Sep 11 03:22:34 AM UTC 24
Finished Sep 11 03:22:54 AM UTC 24
Peak memory 225396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1063077301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all
_with_rand_reset.1063077301
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/89.uart_fifo_reset.3280047979
Short name T402
Test name
Test status
Simulation time 17486804777 ps
CPU time 34.88 seconds
Started Sep 11 03:22:35 AM UTC 24
Finished Sep 11 03:23:11 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280047979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3280047979
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/89.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.1786356117
Short name T982
Test name
Test status
Simulation time 13520725639 ps
CPU time 43.25 seconds
Started Sep 11 03:22:36 AM UTC 24
Finished Sep 11 03:23:21 AM UTC 24
Peak memory 221876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1786356117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all
_with_rand_reset.1786356117
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_alert_test.800901347
Short name T420
Test name
Test status
Simulation time 12319441 ps
CPU time 0.82 seconds
Started Sep 11 02:58:27 AM UTC 24
Finished Sep 11 02:58:29 AM UTC 24
Peak memory 204364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800901347 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.800901347
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_fifo_full.3677457179
Short name T291
Test name
Test status
Simulation time 77458936401 ps
CPU time 58.32 seconds
Started Sep 11 02:58:10 AM UTC 24
Finished Sep 11 02:59:10 AM UTC 24
Peak memory 208756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677457179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3677457179
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.2584311840
Short name T256
Test name
Test status
Simulation time 100796508524 ps
CPU time 54.77 seconds
Started Sep 11 02:58:10 AM UTC 24
Finished Sep 11 02:59:06 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584311840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.2584311840
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_fifo_reset.3396715704
Short name T274
Test name
Test status
Simulation time 91081964186 ps
CPU time 53.22 seconds
Started Sep 11 02:58:12 AM UTC 24
Finished Sep 11 02:59:07 AM UTC 24
Peak memory 208680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396715704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3396715704
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_intr.1847580793
Short name T419
Test name
Test status
Simulation time 470644737 ps
CPU time 1.31 seconds
Started Sep 11 02:58:12 AM UTC 24
Finished Sep 11 02:58:14 AM UTC 24
Peak memory 206356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847580793 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1847580793
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.3981394186
Short name T526
Test name
Test status
Simulation time 76308808572 ps
CPU time 480.36 seconds
Started Sep 11 02:58:23 AM UTC 24
Finished Sep 11 03:06:30 AM UTC 24
Peak memory 208732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981394186 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3981394186
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_loopback.2652545487
Short name T382
Test name
Test status
Simulation time 1543503292 ps
CPU time 4.57 seconds
Started Sep 11 02:58:17 AM UTC 24
Finished Sep 11 02:58:22 AM UTC 24
Peak memory 207480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652545487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2652545487
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_noise_filter.2483837590
Short name T257
Test name
Test status
Simulation time 27842551334 ps
CPU time 59 seconds
Started Sep 11 02:58:14 AM UTC 24
Finished Sep 11 02:59:15 AM UTC 24
Peak memory 207740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483837590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2483837590
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_perf.2862584025
Short name T572
Test name
Test status
Simulation time 8500226868 ps
CPU time 601.86 seconds
Started Sep 11 02:58:18 AM UTC 24
Finished Sep 11 03:08:27 AM UTC 24
Peak memory 212240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862584025 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2862584025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_rx_oversample.1202592042
Short name T421
Test name
Test status
Simulation time 4192770145 ps
CPU time 34.68 seconds
Started Sep 11 02:58:12 AM UTC 24
Finished Sep 11 02:58:48 AM UTC 24
Peak memory 207276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202592042 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1202592042
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3250923698
Short name T150
Test name
Test status
Simulation time 103004486704 ps
CPU time 56.4 seconds
Started Sep 11 02:58:15 AM UTC 24
Finished Sep 11 02:59:13 AM UTC 24
Peak memory 208828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250923698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3250923698
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.475023965
Short name T321
Test name
Test status
Simulation time 1658411087 ps
CPU time 6.24 seconds
Started Sep 11 02:58:15 AM UTC 24
Finished Sep 11 02:58:23 AM UTC 24
Peak memory 205028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475023965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.475023965
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_smoke.3297035505
Short name T297
Test name
Test status
Simulation time 277660468 ps
CPU time 1.4 seconds
Started Sep 11 02:58:08 AM UTC 24
Finished Sep 11 02:58:10 AM UTC 24
Peak memory 206432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297035505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3297035505
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_stress_all.966217554
Short name T403
Test name
Test status
Simulation time 233123122874 ps
CPU time 474.73 seconds
Started Sep 11 02:58:24 AM UTC 24
Finished Sep 11 03:06:24 AM UTC 24
Peak memory 208628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966217554 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.966217554
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.1810577690
Short name T36
Test name
Test status
Simulation time 8247177003 ps
CPU time 67.18 seconds
Started Sep 11 02:58:24 AM UTC 24
Finished Sep 11 02:59:33 AM UTC 24
Peak memory 217696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1810577690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_
with_rand_reset.1810577690
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.4125654854
Short name T312
Test name
Test status
Simulation time 7523676891 ps
CPU time 14.19 seconds
Started Sep 11 02:58:16 AM UTC 24
Finished Sep 11 02:58:32 AM UTC 24
Peak memory 208536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125654854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4125654854
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/9.uart_tx_rx.3657594424
Short name T261
Test name
Test status
Simulation time 75704588885 ps
CPU time 84.39 seconds
Started Sep 11 02:58:10 AM UTC 24
Finished Sep 11 02:59:36 AM UTC 24
Peak memory 208688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657594424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3657594424
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/9.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.1407194722
Short name T997
Test name
Test status
Simulation time 60244544984 ps
CPU time 66.7 seconds
Started Sep 11 03:22:41 AM UTC 24
Finished Sep 11 03:23:50 AM UTC 24
Peak memory 223924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1407194722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all
_with_rand_reset.1407194722
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/91.uart_fifo_reset.2310198375
Short name T1080
Test name
Test status
Simulation time 194970797896 ps
CPU time 238.55 seconds
Started Sep 11 03:22:42 AM UTC 24
Finished Sep 11 03:26:44 AM UTC 24
Peak memory 208692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310198375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2310198375
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/91.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.1799516461
Short name T988
Test name
Test status
Simulation time 5145851957 ps
CPU time 53.92 seconds
Started Sep 11 03:22:44 AM UTC 24
Finished Sep 11 03:23:39 AM UTC 24
Peak memory 221740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1799516461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all
_with_rand_reset.1799516461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3057181461
Short name T1002
Test name
Test status
Simulation time 137238027564 ps
CPU time 67.85 seconds
Started Sep 11 03:22:46 AM UTC 24
Finished Sep 11 03:23:55 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057181461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3057181461
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/92.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.1614254119
Short name T990
Test name
Test status
Simulation time 4730837037 ps
CPU time 53 seconds
Started Sep 11 03:22:47 AM UTC 24
Finished Sep 11 03:23:41 AM UTC 24
Peak memory 217712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1614254119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all
_with_rand_reset.1614254119
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/93.uart_fifo_reset.3660016733
Short name T1026
Test name
Test status
Simulation time 63653529525 ps
CPU time 126.4 seconds
Started Sep 11 03:22:47 AM UTC 24
Finished Sep 11 03:24:55 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660016733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3660016733
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/93.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.3691911512
Short name T229
Test name
Test status
Simulation time 26046063542 ps
CPU time 54.24 seconds
Started Sep 11 03:22:47 AM UTC 24
Finished Sep 11 03:23:43 AM UTC 24
Peak memory 217648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3691911512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_stress_all
_with_rand_reset.3691911512
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/94.uart_fifo_reset.921164622
Short name T975
Test name
Test status
Simulation time 29244416994 ps
CPU time 18.23 seconds
Started Sep 11 03:22:48 AM UTC 24
Finished Sep 11 03:23:07 AM UTC 24
Peak memory 208632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921164622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.921164622
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/94.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.932707862
Short name T995
Test name
Test status
Simulation time 20976554144 ps
CPU time 57.28 seconds
Started Sep 11 03:22:49 AM UTC 24
Finished Sep 11 03:23:48 AM UTC 24
Peak memory 217724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=932707862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all_
with_rand_reset.932707862
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/95.uart_fifo_reset.2305794665
Short name T978
Test name
Test status
Simulation time 32447554645 ps
CPU time 21.53 seconds
Started Sep 11 03:22:50 AM UTC 24
Finished Sep 11 03:23:13 AM UTC 24
Peak memory 208632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305794665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2305794665
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/95.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.4030530723
Short name T983
Test name
Test status
Simulation time 1760677794 ps
CPU time 26.85 seconds
Started Sep 11 03:22:55 AM UTC 24
Finished Sep 11 03:23:23 AM UTC 24
Peak memory 217712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4030530723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all
_with_rand_reset.4030530723
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/96.uart_fifo_reset.3476706025
Short name T989
Test name
Test status
Simulation time 16214096674 ps
CPU time 42.29 seconds
Started Sep 11 03:22:56 AM UTC 24
Finished Sep 11 03:23:40 AM UTC 24
Peak memory 208760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476706025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3476706025
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/96.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.1884969811
Short name T984
Test name
Test status
Simulation time 4106206542 ps
CPU time 26.33 seconds
Started Sep 11 03:22:57 AM UTC 24
Finished Sep 11 03:23:25 AM UTC 24
Peak memory 217772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1884969811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all
_with_rand_reset.1884969811
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/97.uart_fifo_reset.3907021500
Short name T1008
Test name
Test status
Simulation time 122192962739 ps
CPU time 72.4 seconds
Started Sep 11 03:22:58 AM UTC 24
Finished Sep 11 03:24:13 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907021500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3907021500
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/97.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.761863488
Short name T979
Test name
Test status
Simulation time 5412690628 ps
CPU time 15.53 seconds
Started Sep 11 03:22:59 AM UTC 24
Finished Sep 11 03:23:16 AM UTC 24
Peak memory 217912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=761863488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all_
with_rand_reset.761863488
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2971489314
Short name T1032
Test name
Test status
Simulation time 62763686461 ps
CPU time 125.76 seconds
Started Sep 11 03:23:02 AM UTC 24
Finished Sep 11 03:25:09 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971489314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2971489314
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/98.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.552262251
Short name T985
Test name
Test status
Simulation time 17136102336 ps
CPU time 21.53 seconds
Started Sep 11 03:23:03 AM UTC 24
Finished Sep 11 03:23:25 AM UTC 24
Peak memory 217836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=552262251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all_
with_rand_reset.552262251
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/99.uart_fifo_reset.2214758914
Short name T1001
Test name
Test status
Simulation time 35287779545 ps
CPU time 49.62 seconds
Started Sep 11 03:23:03 AM UTC 24
Finished Sep 11 03:23:54 AM UTC 24
Peak memory 208700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214758914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2214758914
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/99.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.2768896786
Short name T981
Test name
Test status
Simulation time 667666477 ps
CPU time 13.68 seconds
Started Sep 11 03:23:04 AM UTC 24
Finished Sep 11 03:23:19 AM UTC 24
Peak memory 208820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2768896786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all
_with_rand_reset.2768896786
Directory /workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%