| T1063 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/160.uart_fifo_reset.590248108 |
|
|
Sep 24 06:35:43 AM UTC 24 |
Sep 24 06:37:10 AM UTC 24 |
157517968551 ps |
| T1064 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3253732413 |
|
|
Sep 24 06:36:28 AM UTC 24 |
Sep 24 06:37:15 AM UTC 24 |
166791145014 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/176.uart_fifo_reset.4120471657 |
|
|
Sep 24 06:36:04 AM UTC 24 |
Sep 24 06:37:15 AM UTC 24 |
15919922213 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1745397235 |
|
|
Sep 24 06:36:15 AM UTC 24 |
Sep 24 06:37:19 AM UTC 24 |
32857545440 ps |
| T1065 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2445925498 |
|
|
Sep 24 06:36:53 AM UTC 24 |
Sep 24 06:37:20 AM UTC 24 |
20026460926 ps |
| T1066 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/155.uart_fifo_reset.393164939 |
|
|
Sep 24 06:35:38 AM UTC 24 |
Sep 24 06:37:26 AM UTC 24 |
112988295948 ps |
| T1067 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/190.uart_fifo_reset.1244746738 |
|
|
Sep 24 06:36:22 AM UTC 24 |
Sep 24 06:37:27 AM UTC 24 |
134703362556 ps |
| T1068 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/209.uart_fifo_reset.4044781501 |
|
|
Sep 24 06:37:03 AM UTC 24 |
Sep 24 06:37:28 AM UTC 24 |
42098408813 ps |
| T1069 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1286201172 |
|
|
Sep 24 06:35:53 AM UTC 24 |
Sep 24 06:37:31 AM UTC 24 |
93220088418 ps |
| T1070 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/171.uart_fifo_reset.2214984830 |
|
|
Sep 24 06:35:59 AM UTC 24 |
Sep 24 06:37:31 AM UTC 24 |
135365641422 ps |
| T1071 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_perf.3179099330 |
|
|
Sep 24 06:29:09 AM UTC 24 |
Sep 24 06:37:33 AM UTC 24 |
21954883544 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1900613266 |
|
|
Sep 24 06:36:41 AM UTC 24 |
Sep 24 06:37:33 AM UTC 24 |
43220261392 ps |
| T1072 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3048190599 |
|
|
Sep 24 06:25:51 AM UTC 24 |
Sep 24 06:37:34 AM UTC 24 |
107614427037 ps |
| T1073 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1140914912 |
|
|
Sep 24 06:37:20 AM UTC 24 |
Sep 24 06:37:37 AM UTC 24 |
20775640639 ps |
| T1074 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/173.uart_fifo_reset.920123703 |
|
|
Sep 24 06:36:03 AM UTC 24 |
Sep 24 06:37:37 AM UTC 24 |
98236032210 ps |
| T1075 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/181.uart_fifo_reset.571773942 |
|
|
Sep 24 06:36:15 AM UTC 24 |
Sep 24 06:37:37 AM UTC 24 |
58648920917 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/94.uart_fifo_reset.189080842 |
|
|
Sep 24 06:33:45 AM UTC 24 |
Sep 24 06:37:38 AM UTC 24 |
273336490119 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/213.uart_fifo_reset.1523051468 |
|
|
Sep 24 06:37:10 AM UTC 24 |
Sep 24 06:37:39 AM UTC 24 |
78608348354 ps |
| T1076 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/128.uart_fifo_reset.2262808873 |
|
|
Sep 24 06:34:57 AM UTC 24 |
Sep 24 06:37:39 AM UTC 24 |
65294264614 ps |
| T1077 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/202.uart_fifo_reset.2039765462 |
|
|
Sep 24 06:36:47 AM UTC 24 |
Sep 24 06:37:39 AM UTC 24 |
39448642895 ps |
| T1078 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/211.uart_fifo_reset.632540670 |
|
|
Sep 24 06:37:07 AM UTC 24 |
Sep 24 06:37:44 AM UTC 24 |
26067527008 ps |
| T1079 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/215.uart_fifo_reset.753104676 |
|
|
Sep 24 06:37:11 AM UTC 24 |
Sep 24 06:37:45 AM UTC 24 |
11817900075 ps |
| T1080 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/225.uart_fifo_reset.3056170858 |
|
|
Sep 24 06:37:33 AM UTC 24 |
Sep 24 06:37:46 AM UTC 24 |
79848263348 ps |
| T1081 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/212.uart_fifo_reset.2242953135 |
|
|
Sep 24 06:37:08 AM UTC 24 |
Sep 24 06:37:46 AM UTC 24 |
61093535525 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3525173902 |
|
|
Sep 24 06:36:32 AM UTC 24 |
Sep 24 06:37:47 AM UTC 24 |
153664135714 ps |
| T1082 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/201.uart_fifo_reset.2054843619 |
|
|
Sep 24 06:36:45 AM UTC 24 |
Sep 24 06:37:48 AM UTC 24 |
38007589157 ps |
| T1083 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2980356701 |
|
|
Sep 24 06:37:38 AM UTC 24 |
Sep 24 06:37:49 AM UTC 24 |
41186890794 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/51.uart_fifo_reset.3488177119 |
|
|
Sep 24 06:30:54 AM UTC 24 |
Sep 24 06:37:53 AM UTC 24 |
115943756121 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/223.uart_fifo_reset.1020849993 |
|
|
Sep 24 06:37:31 AM UTC 24 |
Sep 24 06:37:55 AM UTC 24 |
45112832904 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1001803148 |
|
|
Sep 24 06:37:05 AM UTC 24 |
Sep 24 06:37:55 AM UTC 24 |
33599825648 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/235.uart_fifo_reset.1182938555 |
|
|
Sep 24 06:37:44 AM UTC 24 |
Sep 24 06:37:55 AM UTC 24 |
10243301932 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/224.uart_fifo_reset.3533909511 |
|
|
Sep 24 06:37:31 AM UTC 24 |
Sep 24 06:37:56 AM UTC 24 |
95666857041 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/207.uart_fifo_reset.1538777881 |
|
|
Sep 24 06:37:02 AM UTC 24 |
Sep 24 06:37:58 AM UTC 24 |
19517945231 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/200.uart_fifo_reset.668664789 |
|
|
Sep 24 06:36:43 AM UTC 24 |
Sep 24 06:37:58 AM UTC 24 |
38259433146 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3620859925 |
|
|
Sep 24 06:37:38 AM UTC 24 |
Sep 24 06:38:02 AM UTC 24 |
9294451250 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/204.uart_fifo_reset.765455389 |
|
|
Sep 24 06:36:52 AM UTC 24 |
Sep 24 06:38:02 AM UTC 24 |
171230541327 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/205.uart_fifo_reset.3938023626 |
|
|
Sep 24 06:36:52 AM UTC 24 |
Sep 24 06:38:05 AM UTC 24 |
165776924402 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/216.uart_fifo_reset.3635098458 |
|
|
Sep 24 06:37:16 AM UTC 24 |
Sep 24 06:38:05 AM UTC 24 |
257413031765 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/220.uart_fifo_reset.56771200 |
|
|
Sep 24 06:37:27 AM UTC 24 |
Sep 24 06:38:06 AM UTC 24 |
88671496027 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/231.uart_fifo_reset.1276124458 |
|
|
Sep 24 06:37:39 AM UTC 24 |
Sep 24 06:38:08 AM UTC 24 |
30769962264 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/242.uart_fifo_reset.162276764 |
|
|
Sep 24 06:37:54 AM UTC 24 |
Sep 24 06:38:09 AM UTC 24 |
51660081828 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/241.uart_fifo_reset.2810493296 |
|
|
Sep 24 06:37:50 AM UTC 24 |
Sep 24 06:38:10 AM UTC 24 |
42378113634 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3750594082 |
|
|
Sep 24 06:36:26 AM UTC 24 |
Sep 24 06:38:11 AM UTC 24 |
78536289253 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2762284096 |
|
|
Sep 24 06:37:35 AM UTC 24 |
Sep 24 06:38:12 AM UTC 24 |
17510917150 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/184.uart_fifo_reset.4025253093 |
|
|
Sep 24 06:36:18 AM UTC 24 |
Sep 24 06:38:13 AM UTC 24 |
145972193234 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/177.uart_fifo_reset.1361732386 |
|
|
Sep 24 06:36:06 AM UTC 24 |
Sep 24 06:38:13 AM UTC 24 |
124850573884 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/219.uart_fifo_reset.1154226391 |
|
|
Sep 24 06:37:21 AM UTC 24 |
Sep 24 06:38:14 AM UTC 24 |
113689620297 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/178.uart_fifo_reset.3586076440 |
|
|
Sep 24 06:36:07 AM UTC 24 |
Sep 24 06:38:16 AM UTC 24 |
43808448633 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3340017845 |
|
|
Sep 24 06:36:21 AM UTC 24 |
Sep 24 06:38:17 AM UTC 24 |
127635291069 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3133195162 |
|
|
Sep 24 06:37:16 AM UTC 24 |
Sep 24 06:38:19 AM UTC 24 |
19492499242 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/280.uart_fifo_reset.2091643966 |
|
|
Sep 24 06:38:42 AM UTC 24 |
Sep 24 06:40:50 AM UTC 24 |
63853278403 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_noise_filter.1538821384 |
|
|
Sep 24 06:29:41 AM UTC 24 |
Sep 24 06:38:21 AM UTC 24 |
89851728806 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/150.uart_fifo_reset.2265654426 |
|
|
Sep 24 06:35:29 AM UTC 24 |
Sep 24 06:38:24 AM UTC 24 |
77915628844 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/246.uart_fifo_reset.3648985498 |
|
|
Sep 24 06:37:57 AM UTC 24 |
Sep 24 06:38:25 AM UTC 24 |
12943178128 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/97.uart_fifo_reset.796452211 |
|
|
Sep 24 06:33:50 AM UTC 24 |
Sep 24 06:38:26 AM UTC 24 |
111707078451 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/238.uart_fifo_reset.3330114140 |
|
|
Sep 24 06:37:47 AM UTC 24 |
Sep 24 06:38:28 AM UTC 24 |
30274471726 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/222.uart_fifo_reset.3380199659 |
|
|
Sep 24 06:37:28 AM UTC 24 |
Sep 24 06:38:29 AM UTC 24 |
34207855402 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2333178804 |
|
|
Sep 24 06:37:10 AM UTC 24 |
Sep 24 06:38:29 AM UTC 24 |
74766599130 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/228.uart_fifo_reset.3325537989 |
|
|
Sep 24 06:37:38 AM UTC 24 |
Sep 24 06:38:30 AM UTC 24 |
153264487209 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/185.uart_fifo_reset.2242970851 |
|
|
Sep 24 06:36:19 AM UTC 24 |
Sep 24 06:38:30 AM UTC 24 |
271275025048 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1173501667 |
|
|
Sep 24 06:38:09 AM UTC 24 |
Sep 24 06:38:30 AM UTC 24 |
117597712409 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/247.uart_fifo_reset.2655737740 |
|
|
Sep 24 06:37:58 AM UTC 24 |
Sep 24 06:38:31 AM UTC 24 |
58514137350 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/251.uart_fifo_reset.2538532470 |
|
|
Sep 24 06:38:06 AM UTC 24 |
Sep 24 06:38:36 AM UTC 24 |
60990317268 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/197.uart_fifo_reset.531806194 |
|
|
Sep 24 06:36:35 AM UTC 24 |
Sep 24 06:38:37 AM UTC 24 |
254417054431 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/259.uart_fifo_reset.1723659616 |
|
|
Sep 24 06:38:14 AM UTC 24 |
Sep 24 06:38:38 AM UTC 24 |
83260974698 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/243.uart_fifo_reset.598927277 |
|
|
Sep 24 06:37:56 AM UTC 24 |
Sep 24 06:38:40 AM UTC 24 |
33474151981 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/269.uart_fifo_reset.4050244325 |
|
|
Sep 24 06:38:29 AM UTC 24 |
Sep 24 06:38:41 AM UTC 24 |
15092934470 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/264.uart_fifo_reset.922207051 |
|
|
Sep 24 06:38:20 AM UTC 24 |
Sep 24 06:38:45 AM UTC 24 |
10240972544 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/252.uart_fifo_reset.2091970854 |
|
|
Sep 24 06:38:06 AM UTC 24 |
Sep 24 06:38:46 AM UTC 24 |
44309870145 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/112.uart_fifo_reset.1880390044 |
|
|
Sep 24 06:34:31 AM UTC 24 |
Sep 24 06:38:46 AM UTC 24 |
129891918709 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/157.uart_fifo_reset.970861918 |
|
|
Sep 24 06:35:40 AM UTC 24 |
Sep 24 06:38:46 AM UTC 24 |
86443639669 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/249.uart_fifo_reset.4128161413 |
|
|
Sep 24 06:38:02 AM UTC 24 |
Sep 24 06:38:49 AM UTC 24 |
89467320445 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/268.uart_fifo_reset.1991214119 |
|
|
Sep 24 06:38:27 AM UTC 24 |
Sep 24 06:38:50 AM UTC 24 |
6825761059 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/272.uart_fifo_reset.1865050316 |
|
|
Sep 24 06:38:31 AM UTC 24 |
Sep 24 06:38:52 AM UTC 24 |
32889407545 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3735247407 |
|
|
Sep 24 06:36:22 AM UTC 24 |
Sep 24 06:38:53 AM UTC 24 |
149377703218 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/267.uart_fifo_reset.439336382 |
|
|
Sep 24 06:38:26 AM UTC 24 |
Sep 24 06:38:55 AM UTC 24 |
43312769914 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/237.uart_fifo_reset.1805113597 |
|
|
Sep 24 06:37:46 AM UTC 24 |
Sep 24 06:38:56 AM UTC 24 |
50830115368 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/276.uart_fifo_reset.1781213782 |
|
|
Sep 24 06:38:37 AM UTC 24 |
Sep 24 06:39:00 AM UTC 24 |
48535634995 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1776448987 |
|
|
Sep 24 06:37:49 AM UTC 24 |
Sep 24 06:39:00 AM UTC 24 |
102407627893 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/275.uart_fifo_reset.1228873969 |
|
|
Sep 24 06:38:32 AM UTC 24 |
Sep 24 06:39:03 AM UTC 24 |
14870345346 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/253.uart_fifo_reset.521970071 |
|
|
Sep 24 06:38:07 AM UTC 24 |
Sep 24 06:39:08 AM UTC 24 |
50622687245 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3362234482 |
|
|
Sep 24 06:38:51 AM UTC 24 |
Sep 24 06:39:10 AM UTC 24 |
35206920943 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/248.uart_fifo_reset.61318662 |
|
|
Sep 24 06:37:59 AM UTC 24 |
Sep 24 06:39:11 AM UTC 24 |
89819627755 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/273.uart_fifo_reset.983084432 |
|
|
Sep 24 06:38:31 AM UTC 24 |
Sep 24 06:39:11 AM UTC 24 |
127777693659 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/256.uart_fifo_reset.3091010417 |
|
|
Sep 24 06:38:11 AM UTC 24 |
Sep 24 06:39:13 AM UTC 24 |
137666009682 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2120513011 |
|
|
Sep 24 06:38:58 AM UTC 24 |
Sep 24 06:39:18 AM UTC 24 |
128060459258 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_stress_all.1208027132 |
|
|
Sep 24 06:26:19 AM UTC 24 |
Sep 24 06:39:19 AM UTC 24 |
168376981261 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/271.uart_fifo_reset.3435384228 |
|
|
Sep 24 06:38:30 AM UTC 24 |
Sep 24 06:39:25 AM UTC 24 |
22623055387 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3286411449 |
|
|
Sep 24 06:38:46 AM UTC 24 |
Sep 24 06:39:26 AM UTC 24 |
20675119437 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3505388759 |
|
|
Sep 24 06:38:14 AM UTC 24 |
Sep 24 06:39:28 AM UTC 24 |
29677066540 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/263.uart_fifo_reset.4279384757 |
|
|
Sep 24 06:38:18 AM UTC 24 |
Sep 24 06:39:29 AM UTC 24 |
45235682583 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2959324505 |
|
|
Sep 24 06:38:47 AM UTC 24 |
Sep 24 06:39:29 AM UTC 24 |
21750770319 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2577145760 |
|
|
Sep 24 06:37:03 AM UTC 24 |
Sep 24 06:39:32 AM UTC 24 |
113549801771 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/293.uart_fifo_reset.207775901 |
|
|
Sep 24 06:39:04 AM UTC 24 |
Sep 24 06:39:34 AM UTC 24 |
45590308131 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/278.uart_fifo_reset.1065218535 |
|
|
Sep 24 06:38:39 AM UTC 24 |
Sep 24 06:39:35 AM UTC 24 |
93482480192 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/198.uart_fifo_reset.3405420549 |
|
|
Sep 24 06:36:39 AM UTC 24 |
Sep 24 06:39:35 AM UTC 24 |
147182244341 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/265.uart_fifo_reset.2468861989 |
|
|
Sep 24 06:38:22 AM UTC 24 |
Sep 24 06:39:38 AM UTC 24 |
40959188221 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/262.uart_fifo_reset.3828175947 |
|
|
Sep 24 06:38:16 AM UTC 24 |
Sep 24 06:39:39 AM UTC 24 |
73263140320 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/149.uart_fifo_reset.3162436541 |
|
|
Sep 24 06:35:28 AM UTC 24 |
Sep 24 06:39:41 AM UTC 24 |
147311048690 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_stress_all.1056935583 |
|
|
Sep 24 06:28:48 AM UTC 24 |
Sep 24 06:39:41 AM UTC 24 |
323630384351 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/285.uart_fifo_reset.4276641149 |
|
|
Sep 24 06:38:50 AM UTC 24 |
Sep 24 06:39:43 AM UTC 24 |
22517243764 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/266.uart_fifo_reset.2870661549 |
|
|
Sep 24 06:38:25 AM UTC 24 |
Sep 24 06:39:45 AM UTC 24 |
302693254952 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/234.uart_fifo_reset.3801617557 |
|
|
Sep 24 06:37:40 AM UTC 24 |
Sep 24 06:39:48 AM UTC 24 |
48977303939 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/236.uart_fifo_reset.3215137530 |
|
|
Sep 24 06:37:45 AM UTC 24 |
Sep 24 06:39:48 AM UTC 24 |
155019539318 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1845159897 |
|
|
Sep 24 06:39:01 AM UTC 24 |
Sep 24 06:39:49 AM UTC 24 |
16474953175 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/170.uart_fifo_reset.3557703523 |
|
|
Sep 24 06:35:58 AM UTC 24 |
Sep 24 06:39:50 AM UTC 24 |
97323401544 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/274.uart_fifo_reset.1056751247 |
|
|
Sep 24 06:38:31 AM UTC 24 |
Sep 24 06:39:50 AM UTC 24 |
43208774609 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2187207853 |
|
|
Sep 24 06:38:12 AM UTC 24 |
Sep 24 06:39:51 AM UTC 24 |
45435221284 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/240.uart_fifo_reset.2849142642 |
|
|
Sep 24 06:37:49 AM UTC 24 |
Sep 24 06:39:53 AM UTC 24 |
82127477836 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/255.uart_fifo_reset.360583144 |
|
|
Sep 24 06:38:10 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
51172511654 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3405975188 |
|
|
Sep 24 06:38:47 AM UTC 24 |
Sep 24 06:39:58 AM UTC 24 |
20006319843 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/221.uart_fifo_reset.2124435901 |
|
|
Sep 24 06:37:27 AM UTC 24 |
Sep 24 06:39:59 AM UTC 24 |
99648723411 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/294.uart_fifo_reset.821457948 |
|
|
Sep 24 06:39:09 AM UTC 24 |
Sep 24 06:39:59 AM UTC 24 |
40729002807 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/261.uart_fifo_reset.934924358 |
|
|
Sep 24 06:38:15 AM UTC 24 |
Sep 24 06:40:00 AM UTC 24 |
61869993312 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/245.uart_fifo_reset.160963112 |
|
|
Sep 24 06:37:56 AM UTC 24 |
Sep 24 06:40:04 AM UTC 24 |
141655641740 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/297.uart_fifo_reset.1231865115 |
|
|
Sep 24 06:39:12 AM UTC 24 |
Sep 24 06:40:05 AM UTC 24 |
18613436009 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2463980778 |
|
|
Sep 24 06:38:13 AM UTC 24 |
Sep 24 06:40:08 AM UTC 24 |
40164720743 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/250.uart_fifo_reset.2674338839 |
|
|
Sep 24 06:38:03 AM UTC 24 |
Sep 24 06:40:10 AM UTC 24 |
159910238381 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/227.uart_fifo_reset.858104660 |
|
|
Sep 24 06:37:36 AM UTC 24 |
Sep 24 06:40:11 AM UTC 24 |
325807726975 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/232.uart_fifo_reset.287257255 |
|
|
Sep 24 06:37:40 AM UTC 24 |
Sep 24 06:40:21 AM UTC 24 |
89429345712 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/284.uart_fifo_reset.987169517 |
|
|
Sep 24 06:38:47 AM UTC 24 |
Sep 24 06:40:25 AM UTC 24 |
44243203409 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/270.uart_fifo_reset.713962909 |
|
|
Sep 24 06:38:30 AM UTC 24 |
Sep 24 06:40:29 AM UTC 24 |
65704833548 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/288.uart_fifo_reset.3642284855 |
|
|
Sep 24 06:38:54 AM UTC 24 |
Sep 24 06:40:32 AM UTC 24 |
79442665388 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1624601532 |
|
|
Sep 24 06:39:12 AM UTC 24 |
Sep 24 06:40:48 AM UTC 24 |
39873185238 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/298.uart_fifo_reset.217706263 |
|
|
Sep 24 06:39:14 AM UTC 24 |
Sep 24 06:40:53 AM UTC 24 |
50255527532 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2104755453 |
|
|
Sep 24 06:36:47 AM UTC 24 |
Sep 24 06:40:56 AM UTC 24 |
135916786225 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/277.uart_fifo_reset.2023724610 |
|
|
Sep 24 06:38:38 AM UTC 24 |
Sep 24 06:41:02 AM UTC 24 |
93003693719 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/295.uart_fifo_reset.1642264831 |
|
|
Sep 24 06:39:11 AM UTC 24 |
Sep 24 06:41:04 AM UTC 24 |
178784716508 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/279.uart_fifo_reset.409867328 |
|
|
Sep 24 06:38:41 AM UTC 24 |
Sep 24 06:41:17 AM UTC 24 |
89488663845 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3125981500 |
|
|
Sep 24 06:39:01 AM UTC 24 |
Sep 24 06:41:24 AM UTC 24 |
133672425015 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.2841516834 |
|
|
Sep 24 06:09:39 AM UTC 24 |
Sep 24 06:41:26 AM UTC 24 |
175941750154 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3391949022 |
|
|
Sep 24 06:39:18 AM UTC 24 |
Sep 24 06:41:28 AM UTC 24 |
76945859314 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/287.uart_fifo_reset.4061810335 |
|
|
Sep 24 06:38:53 AM UTC 24 |
Sep 24 06:41:34 AM UTC 24 |
191705869720 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/146.uart_fifo_reset.1519160984 |
|
|
Sep 24 06:35:22 AM UTC 24 |
Sep 24 06:41:45 AM UTC 24 |
216878338018 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.3753000610 |
|
|
Sep 24 06:27:43 AM UTC 24 |
Sep 24 06:41:50 AM UTC 24 |
141168339098 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/289.uart_fifo_reset.2067354204 |
|
|
Sep 24 06:38:57 AM UTC 24 |
Sep 24 06:41:52 AM UTC 24 |
139615810789 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2107229341 |
|
|
Sep 24 06:37:40 AM UTC 24 |
Sep 24 06:41:59 AM UTC 24 |
132023578942 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/192.uart_fifo_reset.903679811 |
|
|
Sep 24 06:36:26 AM UTC 24 |
Sep 24 06:42:31 AM UTC 24 |
54225431011 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.1067423267 |
|
|
Sep 24 06:30:37 AM UTC 24 |
Sep 24 06:42:57 AM UTC 24 |
239968366560 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/195.uart_fifo_reset.1480697213 |
|
|
Sep 24 06:36:31 AM UTC 24 |
Sep 24 06:43:57 AM UTC 24 |
118043507476 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_stress_all.2526888775 |
|
|
Sep 24 06:19:02 AM UTC 24 |
Sep 24 06:45:20 AM UTC 24 |
213027955752 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_perf.3889255846 |
|
|
Sep 24 06:26:17 AM UTC 24 |
Sep 24 06:45:22 AM UTC 24 |
20821783414 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/244.uart_fifo_reset.642432102 |
|
|
Sep 24 06:37:56 AM UTC 24 |
Sep 24 06:45:49 AM UTC 24 |
61107134909 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.1297794963 |
|
|
Sep 24 06:28:11 AM UTC 24 |
Sep 24 06:46:01 AM UTC 24 |
128496222368 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2393238985 |
|
|
Sep 24 06:36:20 AM UTC 24 |
Sep 24 06:47:38 AM UTC 24 |
312354146877 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_stress_all.1429942292 |
|
|
Sep 24 06:25:17 AM UTC 24 |
Sep 24 06:49:18 AM UTC 24 |
111253131624 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.390793796 |
|
|
Sep 24 06:30:42 AM UTC 24 |
Sep 24 06:53:59 AM UTC 24 |
152892254330 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2313101123 |
|
|
Sep 24 06:39:19 AM UTC 24 |
Sep 24 06:39:23 AM UTC 24 |
189644478 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3239258036 |
|
|
Sep 24 06:39:23 AM UTC 24 |
Sep 24 06:39:26 AM UTC 24 |
90442848 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2196849685 |
|
|
Sep 24 06:39:26 AM UTC 24 |
Sep 24 06:39:27 AM UTC 24 |
11165341 ps |
| T50 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1420939728 |
|
|
Sep 24 06:39:27 AM UTC 24 |
Sep 24 06:39:29 AM UTC 24 |
27583760 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.243326322 |
|
|
Sep 24 06:39:28 AM UTC 24 |
Sep 24 06:39:30 AM UTC 24 |
28404425 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1816376719 |
|
|
Sep 24 06:39:28 AM UTC 24 |
Sep 24 06:39:31 AM UTC 24 |
130872529 ps |
| T51 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.3950906729 |
|
|
Sep 24 06:39:29 AM UTC 24 |
Sep 24 06:39:31 AM UTC 24 |
79959018 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.568704401 |
|
|
Sep 24 06:39:30 AM UTC 24 |
Sep 24 06:39:32 AM UTC 24 |
38843664 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.194954084 |
|
|
Sep 24 06:39:30 AM UTC 24 |
Sep 24 06:39:32 AM UTC 24 |
75067952 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3949587887 |
|
|
Sep 24 06:39:31 AM UTC 24 |
Sep 24 06:39:33 AM UTC 24 |
41068019 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2556323366 |
|
|
Sep 24 06:39:30 AM UTC 24 |
Sep 24 06:39:34 AM UTC 24 |
100628005 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.318124703 |
|
|
Sep 24 06:39:32 AM UTC 24 |
Sep 24 06:39:34 AM UTC 24 |
48376465 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.580253642 |
|
|
Sep 24 06:39:32 AM UTC 24 |
Sep 24 06:39:34 AM UTC 24 |
13069624 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3162746167 |
|
|
Sep 24 06:39:33 AM UTC 24 |
Sep 24 06:39:35 AM UTC 24 |
42219408 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.376107052 |
|
|
Sep 24 06:39:34 AM UTC 24 |
Sep 24 06:39:35 AM UTC 24 |
18569226 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.1053117775 |
|
|
Sep 24 06:39:35 AM UTC 24 |
Sep 24 06:39:37 AM UTC 24 |
19784631 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.167201830 |
|
|
Sep 24 06:39:35 AM UTC 24 |
Sep 24 06:39:37 AM UTC 24 |
23604902 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1132073961 |
|
|
Sep 24 06:39:35 AM UTC 24 |
Sep 24 06:39:37 AM UTC 24 |
19132988 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.57727152 |
|
|
Sep 24 06:39:33 AM UTC 24 |
Sep 24 06:39:38 AM UTC 24 |
214030801 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.1003159655 |
|
|
Sep 24 06:39:35 AM UTC 24 |
Sep 24 06:39:38 AM UTC 24 |
160775165 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.3042174616 |
|
|
Sep 24 06:39:36 AM UTC 24 |
Sep 24 06:39:38 AM UTC 24 |
127766936 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.4042302892 |
|
|
Sep 24 06:39:36 AM UTC 24 |
Sep 24 06:39:38 AM UTC 24 |
49354853 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2721036630 |
|
|
Sep 24 06:39:36 AM UTC 24 |
Sep 24 06:39:38 AM UTC 24 |
49592491 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.1266204115 |
|
|
Sep 24 06:39:35 AM UTC 24 |
Sep 24 06:39:39 AM UTC 24 |
162613626 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.455736530 |
|
|
Sep 24 06:39:37 AM UTC 24 |
Sep 24 06:39:40 AM UTC 24 |
580499699 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.995414485 |
|
|
Sep 24 06:39:37 AM UTC 24 |
Sep 24 06:39:40 AM UTC 24 |
29010077 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.2435569374 |
|
|
Sep 24 06:39:36 AM UTC 24 |
Sep 24 06:39:40 AM UTC 24 |
694405231 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.74957675 |
|
|
Sep 24 06:39:39 AM UTC 24 |
Sep 24 06:39:41 AM UTC 24 |
59558976 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2330087009 |
|
|
Sep 24 06:39:39 AM UTC 24 |
Sep 24 06:39:41 AM UTC 24 |
33238646 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.95642299 |
|
|
Sep 24 06:39:39 AM UTC 24 |
Sep 24 06:39:41 AM UTC 24 |
17466225 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.2814869251 |
|
|
Sep 24 06:39:38 AM UTC 24 |
Sep 24 06:39:41 AM UTC 24 |
99046487 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.44973509 |
|
|
Sep 24 06:39:39 AM UTC 24 |
Sep 24 06:39:41 AM UTC 24 |
92950386 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.404126971 |
|
|
Sep 24 06:39:39 AM UTC 24 |
Sep 24 06:39:42 AM UTC 24 |
525950298 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.252966406 |
|
|
Sep 24 06:39:40 AM UTC 24 |
Sep 24 06:39:42 AM UTC 24 |
43904968 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2066685717 |
|
|
Sep 24 06:39:40 AM UTC 24 |
Sep 24 06:39:42 AM UTC 24 |
27987214 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4145063268 |
|
|
Sep 24 06:39:40 AM UTC 24 |
Sep 24 06:39:43 AM UTC 24 |
23758824 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.1493303823 |
|
|
Sep 24 06:39:49 AM UTC 24 |
Sep 24 06:39:51 AM UTC 24 |
102286013 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.680301770 |
|
|
Sep 24 06:39:40 AM UTC 24 |
Sep 24 06:39:43 AM UTC 24 |
119846884 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.3738596668 |
|
|
Sep 24 06:39:42 AM UTC 24 |
Sep 24 06:39:44 AM UTC 24 |
24141413 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.231458257 |
|
|
Sep 24 06:39:42 AM UTC 24 |
Sep 24 06:39:44 AM UTC 24 |
19720220 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.388010309 |
|
|
Sep 24 06:39:42 AM UTC 24 |
Sep 24 06:39:44 AM UTC 24 |
51550090 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3012223106 |
|
|
Sep 24 06:39:42 AM UTC 24 |
Sep 24 06:39:44 AM UTC 24 |
19670309 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2634109889 |
|
|
Sep 24 06:39:42 AM UTC 24 |
Sep 24 06:39:44 AM UTC 24 |
31113793 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1435470213 |
|
|
Sep 24 06:39:42 AM UTC 24 |
Sep 24 06:39:44 AM UTC 24 |
2045521110 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3937478356 |
|
|
Sep 24 06:39:43 AM UTC 24 |
Sep 24 06:39:45 AM UTC 24 |
39423980 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2399751700 |
|
|
Sep 24 06:39:42 AM UTC 24 |
Sep 24 06:39:45 AM UTC 24 |
1615779338 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.3159503530 |
|
|
Sep 24 06:39:43 AM UTC 24 |
Sep 24 06:39:45 AM UTC 24 |
55492948 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.2743565864 |
|
|
Sep 24 06:39:43 AM UTC 24 |
Sep 24 06:39:46 AM UTC 24 |
28311821 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3612049821 |
|
|
Sep 24 06:39:42 AM UTC 24 |
Sep 24 06:39:46 AM UTC 24 |
1030062214 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3215107600 |
|
|
Sep 24 06:39:43 AM UTC 24 |
Sep 24 06:39:46 AM UTC 24 |
133486135 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.3459816352 |
|
|
Sep 24 06:39:45 AM UTC 24 |
Sep 24 06:39:47 AM UTC 24 |
22617792 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.833798593 |
|
|
Sep 24 06:39:45 AM UTC 24 |
Sep 24 06:39:47 AM UTC 24 |
41442498 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.15671996 |
|
|
Sep 24 06:39:45 AM UTC 24 |
Sep 24 06:39:47 AM UTC 24 |
54982048 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3266466517 |
|
|
Sep 24 06:39:45 AM UTC 24 |
Sep 24 06:39:47 AM UTC 24 |
49131111 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.2011938212 |
|
|
Sep 24 06:39:45 AM UTC 24 |
Sep 24 06:39:47 AM UTC 24 |
94321077 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3157850092 |
|
|
Sep 24 06:39:45 AM UTC 24 |
Sep 24 06:39:47 AM UTC 24 |
100285323 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3298332964 |
|
|
Sep 24 06:39:45 AM UTC 24 |
Sep 24 06:39:47 AM UTC 24 |
21789985 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.422120161 |
|
|
Sep 24 06:39:45 AM UTC 24 |
Sep 24 06:39:48 AM UTC 24 |
203812821 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2989623109 |
|
|
Sep 24 06:39:49 AM UTC 24 |
Sep 24 06:39:51 AM UTC 24 |
36490048 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.3719505875 |
|
|
Sep 24 06:39:47 AM UTC 24 |
Sep 24 06:39:48 AM UTC 24 |
50700113 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.2120458034 |
|
|
Sep 24 06:39:47 AM UTC 24 |
Sep 24 06:39:48 AM UTC 24 |
19251346 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2178150947 |
|
|
Sep 24 06:39:47 AM UTC 24 |
Sep 24 06:39:49 AM UTC 24 |
62018571 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.56095544 |
|
|
Sep 24 06:39:46 AM UTC 24 |
Sep 24 06:39:49 AM UTC 24 |
142928445 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3076281866 |
|
|
Sep 24 06:39:45 AM UTC 24 |
Sep 24 06:39:49 AM UTC 24 |
128173530 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3384061861 |
|
|
Sep 24 06:39:47 AM UTC 24 |
Sep 24 06:39:49 AM UTC 24 |
196303102 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.1102908444 |
|
|
Sep 24 06:39:47 AM UTC 24 |
Sep 24 06:39:49 AM UTC 24 |
43454646 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.1062233605 |
|
|
Sep 24 06:39:49 AM UTC 24 |
Sep 24 06:39:50 AM UTC 24 |
44460793 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1244608226 |
|
|
Sep 24 06:39:48 AM UTC 24 |
Sep 24 06:39:50 AM UTC 24 |
29003473 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1015913068 |
|
|
Sep 24 06:39:49 AM UTC 24 |
Sep 24 06:39:50 AM UTC 24 |
39992648 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3238937089 |
|
|
Sep 24 06:39:49 AM UTC 24 |
Sep 24 06:39:51 AM UTC 24 |
53473959 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1832676205 |
|
|
Sep 24 06:39:47 AM UTC 24 |
Sep 24 06:39:51 AM UTC 24 |
110167967 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.1996493160 |
|
|
Sep 24 06:39:49 AM UTC 24 |
Sep 24 06:39:51 AM UTC 24 |
15231206 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.752612600 |
|
|
Sep 24 06:39:49 AM UTC 24 |
Sep 24 06:39:51 AM UTC 24 |
226690234 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1786678859 |
|
|
Sep 24 06:39:51 AM UTC 24 |
Sep 24 06:39:52 AM UTC 24 |
26557122 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2611381636 |
|
|
Sep 24 06:39:50 AM UTC 24 |
Sep 24 06:39:52 AM UTC 24 |
21055013 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.3069919827 |
|
|
Sep 24 06:39:51 AM UTC 24 |
Sep 24 06:39:52 AM UTC 24 |
15219638 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1478556245 |
|
|
Sep 24 06:39:50 AM UTC 24 |
Sep 24 06:39:52 AM UTC 24 |
45443506 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1210958650 |
|
|
Sep 24 06:39:51 AM UTC 24 |
Sep 24 06:39:53 AM UTC 24 |
106677961 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.1197059451 |
|
|
Sep 24 06:39:51 AM UTC 24 |
Sep 24 06:39:53 AM UTC 24 |
18031870 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2473311553 |
|
|
Sep 24 06:39:51 AM UTC 24 |
Sep 24 06:39:53 AM UTC 24 |
84747363 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.556814732 |
|
|
Sep 24 06:39:51 AM UTC 24 |
Sep 24 06:39:53 AM UTC 24 |
93701664 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.2174071902 |
|
|
Sep 24 06:39:50 AM UTC 24 |
Sep 24 06:39:54 AM UTC 24 |
61571047 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.461131875 |
|
|
Sep 24 06:39:51 AM UTC 24 |
Sep 24 06:39:54 AM UTC 24 |
261694439 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1670151336 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
49982952 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3558126800 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
72211276 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3955657484 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
50515572 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2620710449 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
15724186 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.37325874 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
54601409 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.2874486454 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
28054421 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1888218255 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
23298143 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1603862216 |
|
|
Sep 24 06:39:54 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
83202224 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.3745314466 |
|
|
Sep 24 06:39:54 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
107283480 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1631020227 |
|
|
Sep 24 06:39:54 AM UTC 24 |
Sep 24 06:39:55 AM UTC 24 |
34855462 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.3035077537 |
|
|
Sep 24 06:39:54 AM UTC 24 |
Sep 24 06:39:56 AM UTC 24 |
12025894 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1430956697 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:56 AM UTC 24 |
315611319 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.785100154 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:56 AM UTC 24 |
45221757 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.2702855559 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:56 AM UTC 24 |
91845070 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.4051058557 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:56 AM UTC 24 |
237207435 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1758345727 |
|
|
Sep 24 06:39:53 AM UTC 24 |
Sep 24 06:39:57 AM UTC 24 |
186893915 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.156512549 |
|
|
Sep 24 06:39:54 AM UTC 24 |
Sep 24 06:39:57 AM UTC 24 |
192413228 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3768113603 |
|
|
Sep 24 06:39:56 AM UTC 24 |
Sep 24 06:39:58 AM UTC 24 |
48015207 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.683499838 |
|
|
Sep 24 06:40:10 AM UTC 24 |
Sep 24 06:40:12 AM UTC 24 |
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| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.3604106210 |
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Sep 24 06:39:56 AM UTC 24 |
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100262625 ps |