Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.08 97.65 100.00 98.35 100.00 99.57


Total test records in report: 1312
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
T1253 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.3989640021 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:58 AM UTC 24 24173998 ps
T1254 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3074909690 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:58 AM UTC 24 11113109 ps
T1255 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1234171223 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:58 AM UTC 24 82069515 ps
T1256 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.1240157409 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:58 AM UTC 24 36311270 ps
T1257 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.726327984 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:58 AM UTC 24 13704053 ps
T1258 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.537624337 Sep 24 06:39:57 AM UTC 24 Sep 24 06:39:58 AM UTC 24 27156130 ps
T1259 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4254162349 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:58 AM UTC 24 27661668 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.596940158 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:58 AM UTC 24 161211250 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.1476107922 Sep 24 06:39:57 AM UTC 24 Sep 24 06:39:58 AM UTC 24 13337503 ps
T1260 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3115200093 Sep 24 06:39:57 AM UTC 24 Sep 24 06:39:59 AM UTC 24 46093608 ps
T1261 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2249323419 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:59 AM UTC 24 24054321 ps
T1262 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.2687550463 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:59 AM UTC 24 40432568 ps
T1263 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1810553779 Sep 24 06:39:56 AM UTC 24 Sep 24 06:39:59 AM UTC 24 112219496 ps
T1264 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2683725466 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:01 AM UTC 24 24752265 ps
T1265 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3647017936 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 47512251 ps
T1266 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1256693322 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 18310491 ps
T1267 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.1963727967 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 116313353 ps
T1268 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2661903032 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 22511307 ps
T1269 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.1689880239 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 21763197 ps
T1270 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1720649638 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 83887639 ps
T1271 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3288732031 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 31459341 ps
T1272 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2660345477 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 14124403 ps
T1273 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.457360810 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 17114502 ps
T1274 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.2740303951 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 48338638 ps
T1275 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1680831265 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 13997836 ps
T1276 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2934844037 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 48891217 ps
T1277 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1933885011 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 31153536 ps
T1278 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.1647169796 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 17044391 ps
T1279 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.585283804 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 28657460 ps
T1280 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2800804707 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 172482422 ps
T1281 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.2588809933 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:02 AM UTC 24 210664443 ps
T1282 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.918246998 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:03 AM UTC 24 240208536 ps
T1283 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.2647007718 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:03 AM UTC 24 93490515 ps
T1284 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2887392842 Sep 24 06:40:00 AM UTC 24 Sep 24 06:40:03 AM UTC 24 176455469 ps
T1285 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.12232738 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:06 AM UTC 24 64330782 ps
T1286 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1919228217 Sep 24 06:40:04 AM UTC 24 Sep 24 06:40:06 AM UTC 24 14427171 ps
T1287 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1398442675 Sep 24 06:40:04 AM UTC 24 Sep 24 06:40:06 AM UTC 24 13766095 ps
T1288 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.13034325 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:06 AM UTC 24 11181400 ps
T1289 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3597805020 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:06 AM UTC 24 13417470 ps
T1290 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2758183937 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:06 AM UTC 24 47504363 ps
T1291 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2493779943 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 23506192 ps
T1292 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.3132465778 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 54724709 ps
T1293 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.660549728 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 12320836 ps
T1294 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.3572087919 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 48255440 ps
T1295 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.1251621921 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 15282958 ps
T1296 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.402857402 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 11618951 ps
T1297 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.196966467 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 46350698 ps
T1298 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.299897096 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 26440370 ps
T1299 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.3229140141 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 12374411 ps
T1300 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2498788541 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 15486535 ps
T1301 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.4231418874 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 24619684 ps
T1302 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.3814427461 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 18137776 ps
T1303 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2314620614 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 13714124 ps
T1304 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1517549736 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 33863044 ps
T1305 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.2004473862 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 42446069 ps
T1306 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3659492809 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 23280455 ps
T1307 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.521421594 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 42693397 ps
T1308 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1270885219 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 11141770 ps
T1309 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1431387181 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 157915171 ps
T1310 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2406138283 Sep 24 06:40:05 AM UTC 24 Sep 24 06:40:07 AM UTC 24 21467010 ps
T1311 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.3442297049 Sep 24 06:40:10 AM UTC 24 Sep 24 06:40:12 AM UTC 24 36123131 ps
T1312 /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.302668846 Sep 24 06:40:10 AM UTC 24 Sep 24 06:40:12 AM UTC 24 17320770 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.2203303805
Short name T10
Test name
Test status
Simulation time 369049145 ps
CPU time 7.94 seconds
Started Sep 24 05:58:49 AM UTC 24
Finished Sep 24 05:59:02 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2203303805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all_
with_rand_reset.2203303805
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.631831918
Short name T5
Test name
Test status
Simulation time 22107200925 ps
CPU time 9.98 seconds
Started Sep 24 05:58:42 AM UTC 24
Finished Sep 24 05:58:53 AM UTC 24
Peak memory 203780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631831918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.631831918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_long_xfer_wo_dly.1697495907
Short name T278
Test name
Test status
Simulation time 53117402159 ps
CPU time 157.03 seconds
Started Sep 24 06:00:35 AM UTC 24
Finished Sep 24 06:03:15 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697495907 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1697495907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_stress_all.3062146275
Short name T16
Test name
Test status
Simulation time 277135739151 ps
CPU time 144.11 seconds
Started Sep 24 06:00:40 AM UTC 24
Finished Sep 24 06:03:06 AM UTC 24
Peak memory 207876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062146275 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3062146275
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_stress_all.704055608
Short name T155
Test name
Test status
Simulation time 450788128296 ps
CPU time 465.6 seconds
Started Sep 24 06:01:32 AM UTC 24
Finished Sep 24 06:09:24 AM UTC 24
Peak memory 205840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704055608 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.704055608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.3152115176
Short name T275
Test name
Test status
Simulation time 202037759318 ps
CPU time 233.99 seconds
Started Sep 24 06:04:16 AM UTC 24
Finished Sep 24 06:08:14 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152115176 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3152115176
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_stress_all.2803253098
Short name T24
Test name
Test status
Simulation time 97627138512 ps
CPU time 47.85 seconds
Started Sep 24 06:03:51 AM UTC 24
Finished Sep 24 06:04:41 AM UTC 24
Peak memory 204044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803253098 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2803253098
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_stress_all.4149623783
Short name T274
Test name
Test status
Simulation time 426658174666 ps
CPU time 117.13 seconds
Started Sep 24 06:04:58 AM UTC 24
Finished Sep 24 06:06:57 AM UTC 24
Peak memory 207888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149623783 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.4149623783
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_stress_all.1018211642
Short name T106
Test name
Test status
Simulation time 128911565767 ps
CPU time 339.7 seconds
Started Sep 24 05:58:50 AM UTC 24
Finished Sep 24 06:04:38 AM UTC 24
Peak memory 207880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018211642 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1018211642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_fifo_reset.2287026256
Short name T94
Test name
Test status
Simulation time 35681211895 ps
CPU time 85.7 seconds
Started Sep 24 05:59:03 AM UTC 24
Finished Sep 24 06:00:31 AM UTC 24
Peak memory 209196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287026256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2287026256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_sec_cm.1569972052
Short name T8
Test name
Test status
Simulation time 254921830 ps
CPU time 1.23 seconds
Started Sep 24 05:58:55 AM UTC 24
Finished Sep 24 05:58:57 AM UTC 24
Peak memory 236392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569972052 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1569972052
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.254334469
Short name T22
Test name
Test status
Simulation time 531873917 ps
CPU time 3.83 seconds
Started Sep 24 05:59:39 AM UTC 24
Finished Sep 24 05:59:43 AM UTC 24
Peak memory 203916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254334469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.254334469
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.3814871844
Short name T14
Test name
Test status
Simulation time 342830178157 ps
CPU time 60.98 seconds
Started Sep 24 06:01:19 AM UTC 24
Finished Sep 24 06:02:21 AM UTC 24
Peak memory 209280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814871844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3814871844
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_stress_all.2199216390
Short name T96
Test name
Test status
Simulation time 298886124022 ps
CPU time 155.6 seconds
Started Sep 24 06:12:29 AM UTC 24
Finished Sep 24 06:15:07 AM UTC 24
Peak memory 214996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199216390 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2199216390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_long_xfer_wo_dly.54241898
Short name T47
Test name
Test status
Simulation time 91157355869 ps
CPU time 110.23 seconds
Started Sep 24 05:59:46 AM UTC 24
Finished Sep 24 06:01:38 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54241898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.54241898
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.2868499
Short name T118
Test name
Test status
Simulation time 115985173477 ps
CPU time 195.12 seconds
Started Sep 24 06:00:09 AM UTC 24
Finished Sep 24 06:03:27 AM UTC 24
Peak memory 209284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2868499
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.3950906729
Short name T51
Test name
Test status
Simulation time 79959018 ps
CPU time 1.16 seconds
Started Sep 24 06:39:29 AM UTC 24
Finished Sep 24 06:39:31 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950906729 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3950906729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.3773408315
Short name T31
Test name
Test status
Simulation time 3742565737 ps
CPU time 19.25 seconds
Started Sep 24 05:59:47 AM UTC 24
Finished Sep 24 06:00:07 AM UTC 24
Peak memory 217256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3773408315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all_
with_rand_reset.3773408315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_noise_filter.643561843
Short name T360
Test name
Test status
Simulation time 240366123363 ps
CPU time 224.52 seconds
Started Sep 24 06:06:50 AM UTC 24
Finished Sep 24 06:10:38 AM UTC 24
Peak memory 220492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643561843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.643561843
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_fifo_full.3127788593
Short name T121
Test name
Test status
Simulation time 62280221723 ps
CPU time 73.7 seconds
Started Sep 24 06:03:16 AM UTC 24
Finished Sep 24 06:04:32 AM UTC 24
Peak memory 209524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127788593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3127788593
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_stress_all.3311745874
Short name T366
Test name
Test status
Simulation time 303826684961 ps
CPU time 475.57 seconds
Started Sep 24 06:06:17 AM UTC 24
Finished Sep 24 06:14:19 AM UTC 24
Peak memory 217044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311745874 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.3311745874
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_perf.3209726526
Short name T376
Test name
Test status
Simulation time 32582225879 ps
CPU time 432.62 seconds
Started Sep 24 06:05:20 AM UTC 24
Finished Sep 24 06:12:38 AM UTC 24
Peak memory 209620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209726526 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.3209726526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_intg_err.752612600
Short name T81
Test name
Test status
Simulation time 226690234 ps
CPU time 1.39 seconds
Started Sep 24 06:39:49 AM UTC 24
Finished Sep 24 06:39:51 AM UTC 24
Peak memory 201764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752612600 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.752612600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_stress_all.2375562277
Short name T107
Test name
Test status
Simulation time 158396873591 ps
CPU time 452.35 seconds
Started Sep 24 06:02:15 AM UTC 24
Finished Sep 24 06:09:53 AM UTC 24
Peak memory 205832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375562277 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2375562277
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.790976037
Short name T126
Test name
Test status
Simulation time 183417184487 ps
CPU time 244 seconds
Started Sep 24 05:59:35 AM UTC 24
Finished Sep 24 06:03:43 AM UTC 24
Peak memory 203796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790976037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.790976037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.3941630751
Short name T98
Test name
Test status
Simulation time 62810625099 ps
CPU time 35.8 seconds
Started Sep 24 06:03:17 AM UTC 24
Finished Sep 24 06:03:55 AM UTC 24
Peak memory 203980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941630751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3941630751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_alert_test.2072806245
Short name T6
Test name
Test status
Simulation time 14838683 ps
CPU time 0.87 seconds
Started Sep 24 05:58:55 AM UTC 24
Finished Sep 24 05:58:57 AM UTC 24
Peak memory 203256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072806245 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2072806245
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.4235143389
Short name T111
Test name
Test status
Simulation time 2395477205 ps
CPU time 45.89 seconds
Started Sep 24 06:09:10 AM UTC 24
Finished Sep 24 06:09:57 AM UTC 24
Peak memory 218872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4235143389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all
_with_rand_reset.4235143389
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_perf.576579564
Short name T350
Test name
Test status
Simulation time 22574119440 ps
CPU time 222.44 seconds
Started Sep 24 06:06:10 AM UTC 24
Finished Sep 24 06:09:56 AM UTC 24
Peak memory 203968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576579564 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.576579564
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.3907310820
Short name T143
Test name
Test status
Simulation time 87532636454 ps
CPU time 125.23 seconds
Started Sep 24 06:04:47 AM UTC 24
Finished Sep 24 06:06:55 AM UTC 24
Peak memory 226372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3907310820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all_
with_rand_reset.3907310820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_fifo_reset.4187445106
Short name T172
Test name
Test status
Simulation time 223250080912 ps
CPU time 579.39 seconds
Started Sep 24 05:58:42 AM UTC 24
Finished Sep 24 06:08:29 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187445106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.4187445106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_stress_all.1359931675
Short name T358
Test name
Test status
Simulation time 234058095288 ps
CPU time 204.57 seconds
Started Sep 24 06:14:42 AM UTC 24
Finished Sep 24 06:18:10 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359931675 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1359931675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_fifo_full.2156440819
Short name T102
Test name
Test status
Simulation time 127592611442 ps
CPU time 39.01 seconds
Started Sep 24 06:05:02 AM UTC 24
Finished Sep 24 06:05:43 AM UTC 24
Peak memory 209260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156440819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2156440819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.243326322
Short name T65
Test name
Test status
Simulation time 28404425 ps
CPU time 0.89 seconds
Started Sep 24 06:39:28 AM UTC 24
Finished Sep 24 06:39:30 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243326322 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.243326322
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_fifo_reset.539384338
Short name T134
Test name
Test status
Simulation time 97084898023 ps
CPU time 76.44 seconds
Started Sep 24 06:07:13 AM UTC 24
Finished Sep 24 06:08:31 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539384338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.539384338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_fifo_overflow.3216785868
Short name T140
Test name
Test status
Simulation time 155283470575 ps
CPU time 76.28 seconds
Started Sep 24 06:10:30 AM UTC 24
Finished Sep 24 06:11:49 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216785868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3216785868
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_fifo_reset.1004096515
Short name T135
Test name
Test status
Simulation time 89301207224 ps
CPU time 84.94 seconds
Started Sep 24 06:00:09 AM UTC 24
Finished Sep 24 06:01:35 AM UTC 24
Peak memory 208848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004096515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.1004096515
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_stress_all.2357798785
Short name T160
Test name
Test status
Simulation time 136361678026 ps
CPU time 99.35 seconds
Started Sep 24 06:20:35 AM UTC 24
Finished Sep 24 06:22:16 AM UTC 24
Peak memory 220876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357798785 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2357798785
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_noise_filter.2722944881
Short name T297
Test name
Test status
Simulation time 232599615625 ps
CPU time 71.27 seconds
Started Sep 24 06:02:38 AM UTC 24
Finished Sep 24 06:03:51 AM UTC 24
Peak memory 209664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722944881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2722944881
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.1818182450
Short name T43
Test name
Test status
Simulation time 17481130050 ps
CPU time 35.15 seconds
Started Sep 24 06:03:46 AM UTC 24
Finished Sep 24 06:04:23 AM UTC 24
Peak memory 225748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1818182450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all_
with_rand_reset.1818182450
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_long_xfer_wo_dly.3470980441
Short name T351
Test name
Test status
Simulation time 102983970938 ps
CPU time 161.28 seconds
Started Sep 24 06:08:20 AM UTC 24
Finished Sep 24 06:11:05 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470980441 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3470980441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/50.uart_fifo_reset.1368568367
Short name T153
Test name
Test status
Simulation time 55346491737 ps
CPU time 47.71 seconds
Started Sep 24 06:30:50 AM UTC 24
Finished Sep 24 06:31:39 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368568367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1368568367
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/50.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.2802508049
Short name T103
Test name
Test status
Simulation time 57757953352 ps
CPU time 97.25 seconds
Started Sep 24 06:07:47 AM UTC 24
Finished Sep 24 06:09:27 AM UTC 24
Peak memory 209576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802508049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2802508049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_fifo_full.1896740636
Short name T137
Test name
Test status
Simulation time 147410998831 ps
CPU time 204.11 seconds
Started Sep 24 06:11:50 AM UTC 24
Finished Sep 24 06:15:17 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896740636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1896740636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_stress_all_with_rand_reset.452152927
Short name T92
Test name
Test status
Simulation time 27566233848 ps
CPU time 89.06 seconds
Started Sep 24 06:14:33 AM UTC 24
Finished Sep 24 06:16:05 AM UTC 24
Peak memory 226164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=452152927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all_
with_rand_reset.452152927
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/84.uart_fifo_reset.3261628495
Short name T223
Test name
Test status
Simulation time 105668754650 ps
CPU time 121.64 seconds
Started Sep 24 06:33:08 AM UTC 24
Finished Sep 24 06:35:12 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261628495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3261628495
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/84.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.3239258036
Short name T77
Test name
Test status
Simulation time 90442848 ps
CPU time 1.98 seconds
Started Sep 24 06:39:23 AM UTC 24
Finished Sep 24 06:39:26 AM UTC 24
Peak memory 201720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239258036 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3239258036
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.1965429996
Short name T139
Test name
Test status
Simulation time 36112752261 ps
CPU time 96.09 seconds
Started Sep 24 06:08:40 AM UTC 24
Finished Sep 24 06:10:18 AM UTC 24
Peak memory 209064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965429996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1965429996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_fifo_overflow.146431424
Short name T132
Test name
Test status
Simulation time 63475918342 ps
CPU time 96.52 seconds
Started Sep 24 06:17:04 AM UTC 24
Finished Sep 24 06:18:43 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146431424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.146431424
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_stress_all.3754893383
Short name T75
Test name
Test status
Simulation time 123092724380 ps
CPU time 209.73 seconds
Started Sep 24 06:04:20 AM UTC 24
Finished Sep 24 06:07:52 AM UTC 24
Peak memory 220560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754893383 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3754893383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/103.uart_fifo_reset.393738567
Short name T1030
Test name
Test status
Simulation time 130068136638 ps
CPU time 89.6 seconds
Started Sep 24 06:34:10 AM UTC 24
Finished Sep 24 06:35:42 AM UTC 24
Peak memory 209316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393738567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.393738567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/103.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_fifo_full.3621595416
Short name T100
Test name
Test status
Simulation time 29815170200 ps
CPU time 61.01 seconds
Started Sep 24 06:07:07 AM UTC 24
Finished Sep 24 06:08:10 AM UTC 24
Peak memory 209292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621595416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3621595416
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/144.uart_fifo_reset.2625625803
Short name T1052
Test name
Test status
Simulation time 55240531161 ps
CPU time 66.29 seconds
Started Sep 24 06:35:16 AM UTC 24
Finished Sep 24 06:36:24 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625625803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2625625803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/144.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/216.uart_fifo_reset.3635098458
Short name T242
Test name
Test status
Simulation time 257413031765 ps
CPU time 47.9 seconds
Started Sep 24 06:37:16 AM UTC 24
Finished Sep 24 06:38:05 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635098458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3635098458
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/216.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_fifo_reset.3142642247
Short name T183
Test name
Test status
Simulation time 65821277004 ps
CPU time 129.31 seconds
Started Sep 24 06:20:57 AM UTC 24
Finished Sep 24 06:23:09 AM UTC 24
Peak memory 204028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142642247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3142642247
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_stress_all.2618295323
Short name T175
Test name
Test status
Simulation time 360852513397 ps
CPU time 354.83 seconds
Started Sep 24 06:25:55 AM UTC 24
Finished Sep 24 06:31:54 AM UTC 24
Peak memory 207932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618295323 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2618295323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_tx_rx.1756336090
Short name T400
Test name
Test status
Simulation time 11957599411 ps
CPU time 12.74 seconds
Started Sep 24 06:09:15 AM UTC 24
Finished Sep 24 06:09:29 AM UTC 24
Peak memory 209420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756336090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1756336090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/152.uart_fifo_reset.1669136021
Short name T205
Test name
Test status
Simulation time 156850158658 ps
CPU time 83.98 seconds
Started Sep 24 06:35:35 AM UTC 24
Finished Sep 24 06:37:01 AM UTC 24
Peak memory 209320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669136021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1669136021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/152.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_fifo_reset.231834372
Short name T202
Test name
Test status
Simulation time 33952885925 ps
CPU time 56.87 seconds
Started Sep 24 06:17:07 AM UTC 24
Finished Sep 24 06:18:06 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231834372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.231834372
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_stress_all_with_rand_reset.3824802413
Short name T724
Test name
Test status
Simulation time 6732241885 ps
CPU time 41.16 seconds
Started Sep 24 06:23:24 AM UTC 24
Finished Sep 24 06:24:07 AM UTC 24
Peak memory 218544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3824802413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all
_with_rand_reset.3824802413
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_rx_parity_err.3616424527
Short name T291
Test name
Test status
Simulation time 61283633110 ps
CPU time 60.77 seconds
Started Sep 24 06:05:12 AM UTC 24
Finished Sep 24 06:06:14 AM UTC 24
Peak memory 203976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616424527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3616424527
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.410709991
Short name T11
Test name
Test status
Simulation time 29052855300 ps
CPU time 28.19 seconds
Started Sep 24 05:58:44 AM UTC 24
Finished Sep 24 05:59:14 AM UTC 24
Peak memory 209204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410709991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.410709991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_fifo_reset.3038909409
Short name T120
Test name
Test status
Simulation time 12966960525 ps
CPU time 30.96 seconds
Started Sep 24 06:05:38 AM UTC 24
Finished Sep 24 06:06:10 AM UTC 24
Peak memory 209452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038909409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3038909409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/168.uart_fifo_reset.1286201172
Short name T1069
Test name
Test status
Simulation time 93220088418 ps
CPU time 95.55 seconds
Started Sep 24 06:35:53 AM UTC 24
Finished Sep 24 06:37:31 AM UTC 24
Peak memory 209080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286201172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1286201172
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/168.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/186.uart_fifo_reset.2596055769
Short name T244
Test name
Test status
Simulation time 80494020660 ps
CPU time 43.53 seconds
Started Sep 24 06:36:19 AM UTC 24
Finished Sep 24 06:37:04 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596055769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2596055769
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/186.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_noise_filter.495583277
Short name T529
Test name
Test status
Simulation time 8469332072 ps
CPU time 33.12 seconds
Started Sep 24 06:14:26 AM UTC 24
Finished Sep 24 06:15:00 AM UTC 24
Peak memory 209928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495583277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.495583277
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_stress_all.1832087530
Short name T406
Test name
Test status
Simulation time 145314381699 ps
CPU time 257.13 seconds
Started Sep 24 06:15:13 AM UTC 24
Finished Sep 24 06:19:34 AM UTC 24
Peak memory 218488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832087530 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1832087530
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_fifo_reset.2382556610
Short name T230
Test name
Test status
Simulation time 145066191780 ps
CPU time 437.21 seconds
Started Sep 24 06:18:43 AM UTC 24
Finished Sep 24 06:26:06 AM UTC 24
Peak memory 204144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382556610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2382556610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.62926315
Short name T49
Test name
Test status
Simulation time 77036931172 ps
CPU time 217.81 seconds
Started Sep 24 05:59:02 AM UTC 24
Finished Sep 24 06:02:43 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62926315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.62926315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.3464348293
Short name T371
Test name
Test status
Simulation time 40401880507 ps
CPU time 178.62 seconds
Started Sep 24 06:06:29 AM UTC 24
Finished Sep 24 06:09:30 AM UTC 24
Peak memory 209256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464348293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3464348293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_fifo_reset.2788796952
Short name T315
Test name
Test status
Simulation time 39872224291 ps
CPU time 97.58 seconds
Started Sep 24 06:06:34 AM UTC 24
Finished Sep 24 06:08:14 AM UTC 24
Peak memory 203772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788796952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2788796952
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/119.uart_fifo_reset.113544388
Short name T250
Test name
Test status
Simulation time 79498584839 ps
CPU time 33.56 seconds
Started Sep 24 06:34:40 AM UTC 24
Finished Sep 24 06:35:15 AM UTC 24
Peak memory 204104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113544388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.113544388
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/119.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/125.uart_fifo_reset.661561131
Short name T184
Test name
Test status
Simulation time 21732573611 ps
CPU time 54.68 seconds
Started Sep 24 06:34:50 AM UTC 24
Finished Sep 24 06:35:46 AM UTC 24
Peak memory 203796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661561131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.661561131
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/125.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/132.uart_fifo_reset.3714102907
Short name T255
Test name
Test status
Simulation time 38998499072 ps
CPU time 32.02 seconds
Started Sep 24 06:35:06 AM UTC 24
Finished Sep 24 06:35:40 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714102907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3714102907
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/132.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/135.uart_fifo_reset.616074806
Short name T246
Test name
Test status
Simulation time 42176345231 ps
CPU time 77.84 seconds
Started Sep 24 06:35:11 AM UTC 24
Finished Sep 24 06:36:30 AM UTC 24
Peak memory 204116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616074806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.616074806
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/135.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/151.uart_fifo_reset.1873735172
Short name T233
Test name
Test status
Simulation time 35894006806 ps
CPU time 78.58 seconds
Started Sep 24 06:35:31 AM UTC 24
Finished Sep 24 06:36:51 AM UTC 24
Peak memory 209592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873735172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1873735172
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/151.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/158.uart_fifo_reset.3101790349
Short name T260
Test name
Test status
Simulation time 18568927065 ps
CPU time 42.67 seconds
Started Sep 24 06:35:40 AM UTC 24
Finished Sep 24 06:36:25 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101790349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3101790349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/158.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/165.uart_fifo_reset.3642794030
Short name T204
Test name
Test status
Simulation time 134607722719 ps
CPU time 61.73 seconds
Started Sep 24 06:35:49 AM UTC 24
Finished Sep 24 06:36:52 AM UTC 24
Peak memory 209396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642794030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.3642794030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/165.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_fifo_full.2477277950
Short name T308
Test name
Test status
Simulation time 123822002819 ps
CPU time 369.37 seconds
Started Sep 24 06:10:30 AM UTC 24
Finished Sep 24 06:16:46 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477277950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2477277950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/172.uart_fifo_reset.2142624688
Short name T181
Test name
Test status
Simulation time 82681260500 ps
CPU time 61.33 seconds
Started Sep 24 06:35:59 AM UTC 24
Finished Sep 24 06:37:02 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142624688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2142624688
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/172.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/175.uart_fifo_reset.2863222081
Short name T240
Test name
Test status
Simulation time 59391176508 ps
CPU time 42.12 seconds
Started Sep 24 06:36:03 AM UTC 24
Finished Sep 24 06:36:46 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863222081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.2863222081
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/175.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/180.uart_fifo_reset.2838475312
Short name T1062
Test name
Test status
Simulation time 97861998811 ps
CPU time 55.75 seconds
Started Sep 24 06:36:11 AM UTC 24
Finished Sep 24 06:37:08 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838475312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2838475312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/180.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/183.uart_fifo_reset.1745397235
Short name T254
Test name
Test status
Simulation time 32857545440 ps
CPU time 62.56 seconds
Started Sep 24 06:36:15 AM UTC 24
Finished Sep 24 06:37:19 AM UTC 24
Peak memory 209428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745397235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1745397235
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/183.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/191.uart_fifo_reset.2662626940
Short name T236
Test name
Test status
Simulation time 101942925535 ps
CPU time 15.16 seconds
Started Sep 24 06:36:25 AM UTC 24
Finished Sep 24 06:36:41 AM UTC 24
Peak memory 209128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662626940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2662626940
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/191.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/204.uart_fifo_reset.765455389
Short name T261
Test name
Test status
Simulation time 171230541327 ps
CPU time 68.94 seconds
Started Sep 24 06:36:52 AM UTC 24
Finished Sep 24 06:38:02 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765455389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.765455389
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/204.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/213.uart_fifo_reset.1523051468
Short name T249
Test name
Test status
Simulation time 78608348354 ps
CPU time 27.64 seconds
Started Sep 24 06:37:10 AM UTC 24
Finished Sep 24 06:37:39 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523051468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1523051468
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/213.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/220.uart_fifo_reset.56771200
Short name T218
Test name
Test status
Simulation time 88671496027 ps
CPU time 37.16 seconds
Started Sep 24 06:37:27 AM UTC 24
Finished Sep 24 06:38:06 AM UTC 24
Peak memory 203516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56771200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.56771200
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/220.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/224.uart_fifo_reset.3533909511
Short name T262
Test name
Test status
Simulation time 95666857041 ps
CPU time 23.07 seconds
Started Sep 24 06:37:31 AM UTC 24
Finished Sep 24 06:37:56 AM UTC 24
Peak memory 209664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533909511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3533909511
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/224.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/228.uart_fifo_reset.3325537989
Short name T253
Test name
Test status
Simulation time 153264487209 ps
CPU time 50.65 seconds
Started Sep 24 06:37:38 AM UTC 24
Finished Sep 24 06:38:30 AM UTC 24
Peak memory 203844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325537989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3325537989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/228.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/233.uart_fifo_reset.2107229341
Short name T216
Test name
Test status
Simulation time 132023578942 ps
CPU time 255.78 seconds
Started Sep 24 06:37:40 AM UTC 24
Finished Sep 24 06:41:59 AM UTC 24
Peak memory 203712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107229341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2107229341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/233.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/236.uart_fifo_reset.3215137530
Short name T263
Test name
Test status
Simulation time 155019539318 ps
CPU time 120.33 seconds
Started Sep 24 06:37:45 AM UTC 24
Finished Sep 24 06:39:48 AM UTC 24
Peak memory 203772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215137530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3215137530
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/236.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_intr.1249105012
Short name T378
Test name
Test status
Simulation time 30930164549 ps
CPU time 60.28 seconds
Started Sep 24 06:15:29 AM UTC 24
Finished Sep 24 06:16:32 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249105012 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1249105012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/245.uart_fifo_reset.160963112
Short name T214
Test name
Test status
Simulation time 141655641740 ps
CPU time 125.84 seconds
Started Sep 24 06:37:56 AM UTC 24
Finished Sep 24 06:40:04 AM UTC 24
Peak memory 209200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160963112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.160963112
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/245.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/261.uart_fifo_reset.934924358
Short name T251
Test name
Test status
Simulation time 61869993312 ps
CPU time 102.51 seconds
Started Sep 24 06:38:15 AM UTC 24
Finished Sep 24 06:40:00 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934924358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.934924358
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/261.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/263.uart_fifo_reset.4279384757
Short name T209
Test name
Test status
Simulation time 45235682583 ps
CPU time 69.29 seconds
Started Sep 24 06:38:18 AM UTC 24
Finished Sep 24 06:39:29 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279384757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.4279384757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/263.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_fifo_reset.2443396961
Short name T200
Test name
Test status
Simulation time 58044340052 ps
CPU time 112.1 seconds
Started Sep 24 06:24:19 AM UTC 24
Finished Sep 24 06:26:13 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443396961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.2443396961
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_fifo_reset.2005123974
Short name T248
Test name
Test status
Simulation time 492279961944 ps
CPU time 56.34 seconds
Started Sep 24 06:27:55 AM UTC 24
Finished Sep 24 06:28:53 AM UTC 24
Peak memory 209320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005123974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.2005123974
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/58.uart_fifo_reset.2157517354
Short name T212
Test name
Test status
Simulation time 67935944018 ps
CPU time 56.43 seconds
Started Sep 24 06:31:23 AM UTC 24
Finished Sep 24 06:32:21 AM UTC 24
Peak memory 209428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157517354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.2157517354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/58.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/97.uart_fifo_reset.796452211
Short name T258
Test name
Test status
Simulation time 111707078451 ps
CPU time 271.4 seconds
Started Sep 24 06:33:50 AM UTC 24
Finished Sep 24 06:38:26 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796452211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.796452211
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/97.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.1816376719
Short name T60
Test name
Test status
Simulation time 130872529 ps
CPU time 2.05 seconds
Started Sep 24 06:39:28 AM UTC 24
Finished Sep 24 06:39:31 AM UTC 24
Peak memory 202576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816376719 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1816376719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.1420939728
Short name T50
Test name
Test status
Simulation time 27583760 ps
CPU time 0.89 seconds
Started Sep 24 06:39:27 AM UTC 24
Finished Sep 24 06:39:29 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420939728 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1420939728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.194954084
Short name T1182
Test name
Test status
Simulation time 75067952 ps
CPU time 1 seconds
Started Sep 24 06:39:30 AM UTC 24
Finished Sep 24 06:39:32 AM UTC 24
Peak memory 201708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=194954084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_re
set.194954084
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.2196849685
Short name T1181
Test name
Test status
Simulation time 11165341 ps
CPU time 0.82 seconds
Started Sep 24 06:39:26 AM UTC 24
Finished Sep 24 06:39:27 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196849685 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2196849685
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.568704401
Short name T66
Test name
Test status
Simulation time 38843664 ps
CPU time 0.92 seconds
Started Sep 24 06:39:30 AM UTC 24
Finished Sep 24 06:39:32 AM UTC 24
Peak memory 203692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568704401 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_outstanding.568704401
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2313101123
Short name T1180
Test name
Test status
Simulation time 189644478 ps
CPU time 2.22 seconds
Started Sep 24 06:39:19 AM UTC 24
Finished Sep 24 06:39:23 AM UTC 24
Peak memory 202700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313101123 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2313101123
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.376107052
Short name T1185
Test name
Test status
Simulation time 18569226 ps
CPU time 0.99 seconds
Started Sep 24 06:39:34 AM UTC 24
Finished Sep 24 06:39:35 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376107052 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.376107052
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.57727152
Short name T1188
Test name
Test status
Simulation time 214030801 ps
CPU time 3.26 seconds
Started Sep 24 06:39:33 AM UTC 24
Finished Sep 24 06:39:38 AM UTC 24
Peak memory 202632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57727152 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.57727152
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.580253642
Short name T52
Test name
Test status
Simulation time 13069624 ps
CPU time 0.87 seconds
Started Sep 24 06:39:32 AM UTC 24
Finished Sep 24 06:39:34 AM UTC 24
Peak memory 200920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580253642 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.580253642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1132073961
Short name T1187
Test name
Test status
Simulation time 19132988 ps
CPU time 1.17 seconds
Started Sep 24 06:39:35 AM UTC 24
Finished Sep 24 06:39:37 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1132073961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_r
eset.1132073961
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.3162746167
Short name T67
Test name
Test status
Simulation time 42219408 ps
CPU time 0.95 seconds
Started Sep 24 06:39:33 AM UTC 24
Finished Sep 24 06:39:35 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162746167 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3162746167
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.318124703
Short name T1184
Test name
Test status
Simulation time 48376465 ps
CPU time 0.87 seconds
Started Sep 24 06:39:32 AM UTC 24
Finished Sep 24 06:39:34 AM UTC 24
Peak memory 200896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318124703 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.318124703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.1053117775
Short name T68
Test name
Test status
Simulation time 19784631 ps
CPU time 0.98 seconds
Started Sep 24 06:39:35 AM UTC 24
Finished Sep 24 06:39:37 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053117775 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_outstanding.1053117775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2556323366
Short name T1183
Test name
Test status
Simulation time 100628005 ps
CPU time 2.7 seconds
Started Sep 24 06:39:30 AM UTC 24
Finished Sep 24 06:39:34 AM UTC 24
Peak memory 202704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556323366 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2556323366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.3949587887
Short name T78
Test name
Test status
Simulation time 41068019 ps
CPU time 1.31 seconds
Started Sep 24 06:39:31 AM UTC 24
Finished Sep 24 06:39:33 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949587887 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.3949587887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1210958650
Short name T1227
Test name
Test status
Simulation time 106677961 ps
CPU time 0.93 seconds
Started Sep 24 06:39:51 AM UTC 24
Finished Sep 24 06:39:53 AM UTC 24
Peak memory 201768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1210958650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_
reset.1210958650
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.3069919827
Short name T1225
Test name
Test status
Simulation time 15219638 ps
CPU time 0.74 seconds
Started Sep 24 06:39:51 AM UTC 24
Finished Sep 24 06:39:52 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069919827 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.3069919827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.1786678859
Short name T1223
Test name
Test status
Simulation time 26557122 ps
CPU time 0.78 seconds
Started Sep 24 06:39:51 AM UTC 24
Finished Sep 24 06:39:52 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786678859 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1786678859
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.1197059451
Short name T1228
Test name
Test status
Simulation time 18031870 ps
CPU time 1.12 seconds
Started Sep 24 06:39:51 AM UTC 24
Finished Sep 24 06:39:53 AM UTC 24
Peak memory 205660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197059451 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr_outstanding.1197059451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.2174071902
Short name T1231
Test name
Test status
Simulation time 61571047 ps
CPU time 2.49 seconds
Started Sep 24 06:39:50 AM UTC 24
Finished Sep 24 06:39:54 AM UTC 24
Peak memory 202764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174071902 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2174071902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.2473311553
Short name T1229
Test name
Test status
Simulation time 84747363 ps
CPU time 1.87 seconds
Started Sep 24 06:39:51 AM UTC 24
Finished Sep 24 06:39:53 AM UTC 24
Peak memory 201776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473311553 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2473311553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1888218255
Short name T1239
Test name
Test status
Simulation time 23298143 ps
CPU time 1.11 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1888218255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_
reset.1888218255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.3558126800
Short name T1234
Test name
Test status
Simulation time 72211276 ps
CPU time 0.71 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558126800 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3558126800
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.3955657484
Short name T1235
Test name
Test status
Simulation time 50515572 ps
CPU time 0.73 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955657484 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3955657484
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.37325874
Short name T1237
Test name
Test status
Simulation time 54601409 ps
CPU time 1.03 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 205736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37325874 -assert nopostproc +UVM_
TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr_outstanding.37325874
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.461131875
Short name T1232
Test name
Test status
Simulation time 261694439 ps
CPU time 2.58 seconds
Started Sep 24 06:39:51 AM UTC 24
Finished Sep 24 06:39:54 AM UTC 24
Peak memory 202704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461131875 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.461131875
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.556814732
Short name T1230
Test name
Test status
Simulation time 93701664 ps
CPU time 1.61 seconds
Started Sep 24 06:39:51 AM UTC 24
Finished Sep 24 06:39:53 AM UTC 24
Peak memory 201716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556814732 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.556814732
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.785100154
Short name T1245
Test name
Test status
Simulation time 45221757 ps
CPU time 1.29 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:56 AM UTC 24
Peak memory 201720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=785100154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_r
eset.785100154
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1670151336
Short name T1233
Test name
Test status
Simulation time 49982952 ps
CPU time 0.62 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 201632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670151336 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1670151336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2620710449
Short name T1236
Test name
Test status
Simulation time 15724186 ps
CPU time 0.82 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620710449 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2620710449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.2874486454
Short name T1238
Test name
Test status
Simulation time 28054421 ps
CPU time 0.9 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 205796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874486454 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr_outstanding.2874486454
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.2702855559
Short name T1246
Test name
Test status
Simulation time 91845070 ps
CPU time 1.59 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:56 AM UTC 24
Peak memory 201760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702855559 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2702855559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.4051058557
Short name T1247
Test name
Test status
Simulation time 237207435 ps
CPU time 1.66 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:56 AM UTC 24
Peak memory 201780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051058557 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.4051058557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1603862216
Short name T1240
Test name
Test status
Simulation time 83202224 ps
CPU time 0.76 seconds
Started Sep 24 06:39:54 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1603862216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_
reset.1603862216
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.3035077537
Short name T1243
Test name
Test status
Simulation time 12025894 ps
CPU time 0.92 seconds
Started Sep 24 06:39:54 AM UTC 24
Finished Sep 24 06:39:56 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035077537 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3035077537
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1631020227
Short name T1242
Test name
Test status
Simulation time 34855462 ps
CPU time 0.79 seconds
Started Sep 24 06:39:54 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631020227 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1631020227
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.3745314466
Short name T1241
Test name
Test status
Simulation time 107283480 ps
CPU time 0.74 seconds
Started Sep 24 06:39:54 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745314466 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr_outstanding.3745314466
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.1758345727
Short name T1248
Test name
Test status
Simulation time 186893915 ps
CPU time 2.43 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:57 AM UTC 24
Peak memory 204752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758345727 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1758345727
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.1430956697
Short name T1244
Test name
Test status
Simulation time 315611319 ps
CPU time 1.1 seconds
Started Sep 24 06:39:53 AM UTC 24
Finished Sep 24 06:39:56 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430956697 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1430956697
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1234171223
Short name T1255
Test name
Test status
Simulation time 82069515 ps
CPU time 0.89 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1234171223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_
reset.1234171223
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.3768113603
Short name T1250
Test name
Test status
Simulation time 48015207 ps
CPU time 0.61 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768113603 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3768113603
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.3989640021
Short name T1253
Test name
Test status
Simulation time 24173998 ps
CPU time 0.77 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989640021 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3989640021
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.3604106210
Short name T1252
Test name
Test status
Simulation time 100262625 ps
CPU time 0.74 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604106210 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr_outstanding.3604106210
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.156512549
Short name T1249
Test name
Test status
Simulation time 192413228 ps
CPU time 2.37 seconds
Started Sep 24 06:39:54 AM UTC 24
Finished Sep 24 06:39:57 AM UTC 24
Peak memory 204812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156512549 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.156512549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.596940158
Short name T82
Test name
Test status
Simulation time 161211250 ps
CPU time 1.23 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596940158 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.596940158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4254162349
Short name T1259
Test name
Test status
Simulation time 27661668 ps
CPU time 0.98 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4254162349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_
reset.4254162349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3074909690
Short name T1254
Test name
Test status
Simulation time 11113109 ps
CPU time 0.65 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074909690 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.3074909690
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.726327984
Short name T1257
Test name
Test status
Simulation time 13704053 ps
CPU time 0.84 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726327984 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.726327984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.1240157409
Short name T1256
Test name
Test status
Simulation time 36311270 ps
CPU time 0.77 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 205736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240157409 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_outstanding.1240157409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.2687550463
Short name T1262
Test name
Test status
Simulation time 40432568 ps
CPU time 1.42 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:59 AM UTC 24
Peak memory 201716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687550463 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2687550463
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1810553779
Short name T1263
Test name
Test status
Simulation time 112219496 ps
CPU time 1.49 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:59 AM UTC 24
Peak memory 201776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810553779 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1810553779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1256693322
Short name T1266
Test name
Test status
Simulation time 18310491 ps
CPU time 0.7 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1256693322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_
reset.1256693322
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.1476107922
Short name T63
Test name
Test status
Simulation time 13337503 ps
CPU time 0.76 seconds
Started Sep 24 06:39:57 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476107922 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1476107922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.537624337
Short name T1258
Test name
Test status
Simulation time 27156130 ps
CPU time 0.71 seconds
Started Sep 24 06:39:57 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537624337 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.537624337
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.2683725466
Short name T1264
Test name
Test status
Simulation time 24752265 ps
CPU time 0.65 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:01 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683725466 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr_outstanding.2683725466
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2249323419
Short name T1261
Test name
Test status
Simulation time 24054321 ps
CPU time 1.21 seconds
Started Sep 24 06:39:56 AM UTC 24
Finished Sep 24 06:39:59 AM UTC 24
Peak memory 201716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249323419 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2249323419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.3115200093
Short name T1260
Test name
Test status
Simulation time 46093608 ps
CPU time 1.09 seconds
Started Sep 24 06:39:57 AM UTC 24
Finished Sep 24 06:39:59 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115200093 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3115200093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1720649638
Short name T1270
Test name
Test status
Simulation time 83887639 ps
CPU time 0.82 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1720649638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_
reset.1720649638
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.3647017936
Short name T1265
Test name
Test status
Simulation time 47512251 ps
CPU time 0.57 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647017936 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3647017936
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.1963727967
Short name T1267
Test name
Test status
Simulation time 116313353 ps
CPU time 0.68 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963727967 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1963727967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.1689880239
Short name T1269
Test name
Test status
Simulation time 21763197 ps
CPU time 0.84 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689880239 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr_outstanding.1689880239
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.918246998
Short name T1282
Test name
Test status
Simulation time 240208536 ps
CPU time 1.59 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:03 AM UTC 24
Peak memory 201716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918246998 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.918246998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.2800804707
Short name T1280
Test name
Test status
Simulation time 172482422 ps
CPU time 1.43 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800804707 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.2800804707
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.457360810
Short name T1273
Test name
Test status
Simulation time 17114502 ps
CPU time 0.75 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=457360810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_r
eset.457360810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.2660345477
Short name T1272
Test name
Test status
Simulation time 14124403 ps
CPU time 0.78 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660345477 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2660345477
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3288732031
Short name T1271
Test name
Test status
Simulation time 31459341 ps
CPU time 0.78 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288732031 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3288732031
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2661903032
Short name T1268
Test name
Test status
Simulation time 22511307 ps
CPU time 0.74 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661903032 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr_outstanding.2661903032
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.2588809933
Short name T1281
Test name
Test status
Simulation time 210664443 ps
CPU time 1.36 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588809933 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2588809933
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.2740303951
Short name T1274
Test name
Test status
Simulation time 48338638 ps
CPU time 1 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740303951 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.2740303951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.585283804
Short name T1279
Test name
Test status
Simulation time 28657460 ps
CPU time 0.83 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=585283804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_r
eset.585283804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.1647169796
Short name T1278
Test name
Test status
Simulation time 17044391 ps
CPU time 0.72 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647169796 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1647169796
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.1933885011
Short name T1277
Test name
Test status
Simulation time 31153536 ps
CPU time 0.73 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933885011 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1933885011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2934844037
Short name T1276
Test name
Test status
Simulation time 48891217 ps
CPU time 0.82 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934844037 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr_outstanding.2934844037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.2887392842
Short name T1284
Test name
Test status
Simulation time 176455469 ps
CPU time 2.04 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:03 AM UTC 24
Peak memory 204616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887392842 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2887392842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.2647007718
Short name T1283
Test name
Test status
Simulation time 93490515 ps
CPU time 1.52 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:03 AM UTC 24
Peak memory 201708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647007718 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2647007718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.2721036630
Short name T55
Test name
Test status
Simulation time 49592491 ps
CPU time 0.97 seconds
Started Sep 24 06:39:36 AM UTC 24
Finished Sep 24 06:39:38 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721036630 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2721036630
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.2435569374
Short name T1191
Test name
Test status
Simulation time 694405231 ps
CPU time 2.96 seconds
Started Sep 24 06:39:36 AM UTC 24
Finished Sep 24 06:39:40 AM UTC 24
Peak memory 202764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435569374 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2435569374
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.3042174616
Short name T53
Test name
Test status
Simulation time 127766936 ps
CPU time 0.87 seconds
Started Sep 24 06:39:36 AM UTC 24
Finished Sep 24 06:39:38 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042174616 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3042174616
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.995414485
Short name T1190
Test name
Test status
Simulation time 29010077 ps
CPU time 1.69 seconds
Started Sep 24 06:39:37 AM UTC 24
Finished Sep 24 06:39:40 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=995414485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_re
set.995414485
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.4042302892
Short name T54
Test name
Test status
Simulation time 49354853 ps
CPU time 0.92 seconds
Started Sep 24 06:39:36 AM UTC 24
Finished Sep 24 06:39:38 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042302892 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4042302892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.167201830
Short name T1186
Test name
Test status
Simulation time 23604902 ps
CPU time 0.88 seconds
Started Sep 24 06:39:35 AM UTC 24
Finished Sep 24 06:39:37 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167201830 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.167201830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.455736530
Short name T69
Test name
Test status
Simulation time 580499699 ps
CPU time 1.11 seconds
Started Sep 24 06:39:37 AM UTC 24
Finished Sep 24 06:39:40 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455736530 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_outstanding.455736530
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.1266204115
Short name T1189
Test name
Test status
Simulation time 162613626 ps
CPU time 3.6 seconds
Started Sep 24 06:39:35 AM UTC 24
Finished Sep 24 06:39:39 AM UTC 24
Peak memory 202636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266204115 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1266204115
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.1003159655
Short name T79
Test name
Test status
Simulation time 160775165 ps
CPU time 1.9 seconds
Started Sep 24 06:39:35 AM UTC 24
Finished Sep 24 06:39:38 AM UTC 24
Peak memory 201760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003159655 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1003159655
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.1680831265
Short name T1275
Test name
Test status
Simulation time 13997836 ps
CPU time 0.66 seconds
Started Sep 24 06:40:00 AM UTC 24
Finished Sep 24 06:40:02 AM UTC 24
Peak memory 201632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680831265 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1680831265
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1398442675
Short name T1287
Test name
Test status
Simulation time 13766095 ps
CPU time 0.65 seconds
Started Sep 24 06:40:04 AM UTC 24
Finished Sep 24 06:40:06 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398442675 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1398442675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1919228217
Short name T1286
Test name
Test status
Simulation time 14427171 ps
CPU time 0.62 seconds
Started Sep 24 06:40:04 AM UTC 24
Finished Sep 24 06:40:06 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919228217 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1919228217
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.12232738
Short name T1285
Test name
Test status
Simulation time 64330782 ps
CPU time 0.6 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:06 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12232738 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.12232738
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.660549728
Short name T1293
Test name
Test status
Simulation time 12320836 ps
CPU time 0.76 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660549728 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.660549728
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.2758183937
Short name T1290
Test name
Test status
Simulation time 47504363 ps
CPU time 0.6 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:06 AM UTC 24
Peak memory 201564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758183937 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2758183937
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3597805020
Short name T1289
Test name
Test status
Simulation time 13417470 ps
CPU time 0.6 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:06 AM UTC 24
Peak memory 201552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597805020 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3597805020
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.3132465778
Short name T1292
Test name
Test status
Simulation time 54724709 ps
CPU time 0.61 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132465778 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3132465778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.13034325
Short name T1288
Test name
Test status
Simulation time 11181400 ps
CPU time 0.65 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:06 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13034325 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.13034325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2493779943
Short name T1291
Test name
Test status
Simulation time 23506192 ps
CPU time 0.6 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493779943 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2493779943
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2066685717
Short name T57
Test name
Test status
Simulation time 27987214 ps
CPU time 1.01 seconds
Started Sep 24 06:39:40 AM UTC 24
Finished Sep 24 06:39:42 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066685717 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2066685717
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.404126971
Short name T1195
Test name
Test status
Simulation time 525950298 ps
CPU time 1.84 seconds
Started Sep 24 06:39:39 AM UTC 24
Finished Sep 24 06:39:42 AM UTC 24
Peak memory 201780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404126971 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.404126971
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.95642299
Short name T1193
Test name
Test status
Simulation time 17466225 ps
CPU time 0.88 seconds
Started Sep 24 06:39:39 AM UTC 24
Finished Sep 24 06:39:41 AM UTC 24
Peak memory 201696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95642299 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23
/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.95642299
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4145063268
Short name T1196
Test name
Test status
Simulation time 23758824 ps
CPU time 1.68 seconds
Started Sep 24 06:39:40 AM UTC 24
Finished Sep 24 06:39:43 AM UTC 24
Peak memory 203768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4145063268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_r
eset.4145063268
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2330087009
Short name T56
Test name
Test status
Simulation time 33238646 ps
CPU time 0.82 seconds
Started Sep 24 06:39:39 AM UTC 24
Finished Sep 24 06:39:41 AM UTC 24
Peak memory 201652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330087009 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2330087009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.74957675
Short name T1192
Test name
Test status
Simulation time 59558976 ps
CPU time 0.85 seconds
Started Sep 24 06:39:39 AM UTC 24
Finished Sep 24 06:39:41 AM UTC 24
Peak memory 201532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74957675 -assert nopostproc +UVM_TESTNAME=uart_base_te
st +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.74957675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.252966406
Short name T70
Test name
Test status
Simulation time 43904968 ps
CPU time 0.95 seconds
Started Sep 24 06:39:40 AM UTC 24
Finished Sep 24 06:39:42 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252966406 -assert nopostproc +UVM
_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_outstanding.252966406
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.2814869251
Short name T1194
Test name
Test status
Simulation time 99046487 ps
CPU time 2.66 seconds
Started Sep 24 06:39:38 AM UTC 24
Finished Sep 24 06:39:41 AM UTC 24
Peak memory 202636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814869251 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2814869251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.44973509
Short name T113
Test name
Test status
Simulation time 92950386 ps
CPU time 1.28 seconds
Started Sep 24 06:39:39 AM UTC 24
Finished Sep 24 06:39:41 AM UTC 24
Peak memory 201720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44973509 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.44973509
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.3572087919
Short name T1294
Test name
Test status
Simulation time 48255440 ps
CPU time 0.62 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572087919 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3572087919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.1251621921
Short name T1295
Test name
Test status
Simulation time 15282958 ps
CPU time 0.6 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251621921 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1251621921
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.3229140141
Short name T1299
Test name
Test status
Simulation time 12374411 ps
CPU time 0.66 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229140141 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3229140141
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.196966467
Short name T1297
Test name
Test status
Simulation time 46350698 ps
CPU time 0.62 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196966467 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.196966467
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.402857402
Short name T1296
Test name
Test status
Simulation time 11618951 ps
CPU time 0.54 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402857402 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.402857402
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.3814427461
Short name T1302
Test name
Test status
Simulation time 18137776 ps
CPU time 0.72 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814427461 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3814427461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.2314620614
Short name T1303
Test name
Test status
Simulation time 13714124 ps
CPU time 0.54 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314620614 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2314620614
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.299897096
Short name T1298
Test name
Test status
Simulation time 26440370 ps
CPU time 0.55 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299897096 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.299897096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.2498788541
Short name T1300
Test name
Test status
Simulation time 15486535 ps
CPU time 0.57 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498788541 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2498788541
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.4231418874
Short name T1301
Test name
Test status
Simulation time 24619684 ps
CPU time 0.61 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231418874 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4231418874
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.231458257
Short name T1200
Test name
Test status
Simulation time 19720220 ps
CPU time 0.77 seconds
Started Sep 24 06:39:42 AM UTC 24
Finished Sep 24 06:39:44 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231458257 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_2
3/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.231458257
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.2399751700
Short name T61
Test name
Test status
Simulation time 1615779338 ps
CPU time 2.29 seconds
Started Sep 24 06:39:42 AM UTC 24
Finished Sep 24 06:39:45 AM UTC 24
Peak memory 202572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399751700 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2399751700
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.3612049821
Short name T1205
Test name
Test status
Simulation time 1030062214 ps
CPU time 2.82 seconds
Started Sep 24 06:39:42 AM UTC 24
Finished Sep 24 06:39:46 AM UTC 24
Peak memory 202236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612049821 -assert nopostproc +UVM_TESTNAME=u
art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3612049821
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.3012223106
Short name T1201
Test name
Test status
Simulation time 19670309 ps
CPU time 0.98 seconds
Started Sep 24 06:39:42 AM UTC 24
Finished Sep 24 06:39:44 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3012223106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_r
eset.3012223106
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.388010309
Short name T58
Test name
Test status
Simulation time 51550090 ps
CPU time 0.78 seconds
Started Sep 24 06:39:42 AM UTC 24
Finished Sep 24 06:39:44 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388010309 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.388010309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.3738596668
Short name T1199
Test name
Test status
Simulation time 24141413 ps
CPU time 0.87 seconds
Started Sep 24 06:39:42 AM UTC 24
Finished Sep 24 06:39:44 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738596668 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3738596668
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.2634109889
Short name T71
Test name
Test status
Simulation time 31113793 ps
CPU time 0.96 seconds
Started Sep 24 06:39:42 AM UTC 24
Finished Sep 24 06:39:44 AM UTC 24
Peak memory 205672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634109889 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_outstanding.2634109889
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.680301770
Short name T1198
Test name
Test status
Simulation time 119846884 ps
CPU time 1.74 seconds
Started Sep 24 06:39:40 AM UTC 24
Finished Sep 24 06:39:43 AM UTC 24
Peak memory 201756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680301770 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.680301770
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.1435470213
Short name T83
Test name
Test status
Simulation time 2045521110 ps
CPU time 1.32 seconds
Started Sep 24 06:39:42 AM UTC 24
Finished Sep 24 06:39:44 AM UTC 24
Peak memory 201716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435470213 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1435470213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1517549736
Short name T1304
Test name
Test status
Simulation time 33863044 ps
CPU time 0.66 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517549736 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1517549736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3659492809
Short name T1306
Test name
Test status
Simulation time 23280455 ps
CPU time 0.66 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659492809 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3659492809
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.521421594
Short name T1307
Test name
Test status
Simulation time 42693397 ps
CPU time 0.63 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521421594 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.521421594
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.2004473862
Short name T1305
Test name
Test status
Simulation time 42446069 ps
CPU time 0.53 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004473862 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2004473862
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1270885219
Short name T1308
Test name
Test status
Simulation time 11141770 ps
CPU time 0.67 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270885219 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1270885219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/45.uart_intr_test.1431387181
Short name T1309
Test name
Test status
Simulation time 157915171 ps
CPU time 0.62 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431387181 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1431387181
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/46.uart_intr_test.2406138283
Short name T1310
Test name
Test status
Simulation time 21467010 ps
CPU time 0.53 seconds
Started Sep 24 06:40:05 AM UTC 24
Finished Sep 24 06:40:07 AM UTC 24
Peak memory 201576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406138283 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2406138283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/47.uart_intr_test.3442297049
Short name T1311
Test name
Test status
Simulation time 36123131 ps
CPU time 0.58 seconds
Started Sep 24 06:40:10 AM UTC 24
Finished Sep 24 06:40:12 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442297049 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.3442297049
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/48.uart_intr_test.302668846
Short name T1312
Test name
Test status
Simulation time 17320770 ps
CPU time 0.57 seconds
Started Sep 24 06:40:10 AM UTC 24
Finished Sep 24 06:40:12 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302668846 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.302668846
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/49.uart_intr_test.683499838
Short name T1251
Test name
Test status
Simulation time 37033257 ps
CPU time 0.61 seconds
Started Sep 24 06:40:10 AM UTC 24
Finished Sep 24 06:40:12 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683499838 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.683499838
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3266466517
Short name T1209
Test name
Test status
Simulation time 49131111 ps
CPU time 1.21 seconds
Started Sep 24 06:39:45 AM UTC 24
Finished Sep 24 06:39:47 AM UTC 24
Peak memory 201760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3266466517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_r
eset.3266466517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_csr_rw.3159503530
Short name T1203
Test name
Test status
Simulation time 55492948 ps
CPU time 0.87 seconds
Started Sep 24 06:39:43 AM UTC 24
Finished Sep 24 06:39:45 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159503530 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.3159503530
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_intr_test.3937478356
Short name T1202
Test name
Test status
Simulation time 39423980 ps
CPU time 0.9 seconds
Started Sep 24 06:39:43 AM UTC 24
Finished Sep 24 06:39:45 AM UTC 24
Peak memory 201632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937478356 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3937478356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_same_csr_outstanding.3459816352
Short name T1206
Test name
Test status
Simulation time 22617792 ps
CPU time 0.86 seconds
Started Sep 24 06:39:45 AM UTC 24
Finished Sep 24 06:39:47 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459816352 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_outstanding.3459816352
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_errors.2743565864
Short name T1204
Test name
Test status
Simulation time 28311821 ps
CPU time 1.35 seconds
Started Sep 24 06:39:43 AM UTC 24
Finished Sep 24 06:39:46 AM UTC 24
Peak memory 201716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743565864 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2743565864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/5.uart_tl_intg_err.3215107600
Short name T84
Test name
Test status
Simulation time 133486135 ps
CPU time 1.72 seconds
Started Sep 24 06:39:43 AM UTC 24
Finished Sep 24 06:39:46 AM UTC 24
Peak memory 201720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215107600 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3215107600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.3298332964
Short name T1211
Test name
Test status
Simulation time 21789985 ps
CPU time 1.11 seconds
Started Sep 24 06:39:45 AM UTC 24
Finished Sep 24 06:39:47 AM UTC 24
Peak memory 201768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3298332964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_r
eset.3298332964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_csr_rw.15671996
Short name T1208
Test name
Test status
Simulation time 54982048 ps
CPU time 0.92 seconds
Started Sep 24 06:39:45 AM UTC 24
Finished Sep 24 06:39:47 AM UTC 24
Peak memory 201572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15671996 -assert nopostproc +UVM_TESTNAME=uart_base
_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.15671996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_intr_test.833798593
Short name T1207
Test name
Test status
Simulation time 41442498 ps
CPU time 0.84 seconds
Started Sep 24 06:39:45 AM UTC 24
Finished Sep 24 06:39:47 AM UTC 24
Peak memory 201556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833798593 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.833798593
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_same_csr_outstanding.2011938212
Short name T1210
Test name
Test status
Simulation time 94321077 ps
CPU time 0.98 seconds
Started Sep 24 06:39:45 AM UTC 24
Finished Sep 24 06:39:47 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011938212 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_outstanding.2011938212
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_errors.3076281866
Short name T1217
Test name
Test status
Simulation time 128173530 ps
CPU time 2.98 seconds
Started Sep 24 06:39:45 AM UTC 24
Finished Sep 24 06:39:49 AM UTC 24
Peak memory 204688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076281866 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3076281866
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/6.uart_tl_intg_err.3157850092
Short name T80
Test name
Test status
Simulation time 100285323 ps
CPU time 1.25 seconds
Started Sep 24 06:39:45 AM UTC 24
Finished Sep 24 06:39:47 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157850092 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3157850092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3384061861
Short name T1218
Test name
Test status
Simulation time 196303102 ps
CPU time 1.14 seconds
Started Sep 24 06:39:47 AM UTC 24
Finished Sep 24 06:39:49 AM UTC 24
Peak memory 201768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3384061861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_r
eset.3384061861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_csr_rw.3719505875
Short name T59
Test name
Test status
Simulation time 50700113 ps
CPU time 0.76 seconds
Started Sep 24 06:39:47 AM UTC 24
Finished Sep 24 06:39:48 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719505875 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3719505875
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_intr_test.2120458034
Short name T1214
Test name
Test status
Simulation time 19251346 ps
CPU time 0.85 seconds
Started Sep 24 06:39:47 AM UTC 24
Finished Sep 24 06:39:48 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120458034 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.2120458034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_same_csr_outstanding.2178150947
Short name T1215
Test name
Test status
Simulation time 62018571 ps
CPU time 0.93 seconds
Started Sep 24 06:39:47 AM UTC 24
Finished Sep 24 06:39:49 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178150947 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_outstanding.2178150947
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_errors.422120161
Short name T1212
Test name
Test status
Simulation time 203812821 ps
CPU time 1.6 seconds
Started Sep 24 06:39:45 AM UTC 24
Finished Sep 24 06:39:48 AM UTC 24
Peak memory 201712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422120161 -assert nopostproc +UVM_TESTNAME=uart_base_t
est +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.422120161
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/7.uart_tl_intg_err.56095544
Short name T1216
Test name
Test status
Simulation time 142928445 ps
CPU time 1.18 seconds
Started Sep 24 06:39:46 AM UTC 24
Finished Sep 24 06:39:49 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56095544 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.56095544
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2989623109
Short name T1213
Test name
Test status
Simulation time 36490048 ps
CPU time 1.34 seconds
Started Sep 24 06:39:49 AM UTC 24
Finished Sep 24 06:39:51 AM UTC 24
Peak memory 201784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2989623109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_r
eset.2989623109
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_csr_rw.1062233605
Short name T62
Test name
Test status
Simulation time 44460793 ps
CPU time 0.8 seconds
Started Sep 24 06:39:49 AM UTC 24
Finished Sep 24 06:39:50 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062233605 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1062233605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_intr_test.1244608226
Short name T1219
Test name
Test status
Simulation time 29003473 ps
CPU time 0.87 seconds
Started Sep 24 06:39:48 AM UTC 24
Finished Sep 24 06:39:50 AM UTC 24
Peak memory 201636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244608226 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1244608226
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_same_csr_outstanding.3238937089
Short name T1221
Test name
Test status
Simulation time 53473959 ps
CPU time 0.96 seconds
Started Sep 24 06:39:49 AM UTC 24
Finished Sep 24 06:39:51 AM UTC 24
Peak memory 201640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238937089 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_outstanding.3238937089
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_errors.1832676205
Short name T1222
Test name
Test status
Simulation time 110167967 ps
CPU time 2.86 seconds
Started Sep 24 06:39:47 AM UTC 24
Finished Sep 24 06:39:51 AM UTC 24
Peak memory 204664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832676205 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1832676205
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/8.uart_tl_intg_err.1102908444
Short name T112
Test name
Test status
Simulation time 43454646 ps
CPU time 1.2 seconds
Started Sep 24 06:39:47 AM UTC 24
Finished Sep 24 06:39:49 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102908444 -assert nopostproc +UVM_TESTNAM
E=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1102908444
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2611381636
Short name T1224
Test name
Test status
Simulation time 21055013 ps
CPU time 1 seconds
Started Sep 24 06:39:50 AM UTC 24
Finished Sep 24 06:39:52 AM UTC 24
Peak memory 201768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2611381636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_r
eset.2611381636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_csr_rw.1996493160
Short name T64
Test name
Test status
Simulation time 15231206 ps
CPU time 0.92 seconds
Started Sep 24 06:39:49 AM UTC 24
Finished Sep 24 06:39:51 AM UTC 24
Peak memory 201632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996493160 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1996493160
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_intr_test.1015913068
Short name T1220
Test name
Test status
Simulation time 39992648 ps
CPU time 0.76 seconds
Started Sep 24 06:39:49 AM UTC 24
Finished Sep 24 06:39:50 AM UTC 24
Peak memory 201324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015913068 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1015913068
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_same_csr_outstanding.1478556245
Short name T1226
Test name
Test status
Simulation time 45443506 ps
CPU time 1 seconds
Started Sep 24 06:39:50 AM UTC 24
Finished Sep 24 06:39:52 AM UTC 24
Peak memory 201700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478556245 -assert nopostproc +UV
M_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_23/uart-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_outstanding.1478556245
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/cover_reg_top/9.uart_tl_errors.1493303823
Short name T1197
Test name
Test status
Simulation time 102286013 ps
CPU time 1.81 seconds
Started Sep 24 06:39:49 AM UTC 24
Finished Sep 24 06:39:51 AM UTC 24
Peak memory 201704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493303823 -assert nopostproc +UVM_TESTNAME=uart_base_
test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1493303823
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_fifo_full.2471339740
Short name T13
Test name
Test status
Simulation time 51369679040 ps
CPU time 32.3 seconds
Started Sep 24 05:58:42 AM UTC 24
Finished Sep 24 05:59:16 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471339740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2471339740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_intr.417351102
Short name T290
Test name
Test status
Simulation time 149976925653 ps
CPU time 230.81 seconds
Started Sep 24 05:58:44 AM UTC 24
Finished Sep 24 06:02:38 AM UTC 24
Peak memory 209400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417351102 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.417351102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.1214384950
Short name T298
Test name
Test status
Simulation time 245264217860 ps
CPU time 659.1 seconds
Started Sep 24 05:58:49 AM UTC 24
Finished Sep 24 06:10:00 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214384950 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1214384950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_loopback.1020089463
Short name T2
Test name
Test status
Simulation time 716323232 ps
CPU time 1.64 seconds
Started Sep 24 05:58:46 AM UTC 24
Finished Sep 24 05:58:49 AM UTC 24
Peak memory 205360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020089463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1020089463
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_noise_filter.1095720911
Short name T114
Test name
Test status
Simulation time 142848976425 ps
CPU time 124.13 seconds
Started Sep 24 05:58:44 AM UTC 24
Finished Sep 24 06:00:50 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095720911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1095720911
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_perf.1242151331
Short name T699
Test name
Test status
Simulation time 24607784887 ps
CPU time 1438.66 seconds
Started Sep 24 05:58:47 AM UTC 24
Finished Sep 24 06:23:02 AM UTC 24
Peak memory 212736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242151331 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.1242151331
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2000089100
Short name T4
Test name
Test status
Simulation time 2339646614 ps
CPU time 7.03 seconds
Started Sep 24 05:58:44 AM UTC 24
Finished Sep 24 05:58:52 AM UTC 24
Peak memory 208160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000089100 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2000089100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.1576114600
Short name T35
Test name
Test status
Simulation time 43066034557 ps
CPU time 79 seconds
Started Sep 24 05:58:44 AM UTC 24
Finished Sep 24 06:00:05 AM UTC 24
Peak memory 203580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576114600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1576114600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_smoke.2441384055
Short name T1
Test name
Test status
Simulation time 450335943 ps
CPU time 2.45 seconds
Started Sep 24 05:58:42 AM UTC 24
Finished Sep 24 05:58:46 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441384055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2441384055
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.2614889666
Short name T3
Test name
Test status
Simulation time 682939865 ps
CPU time 2.85 seconds
Started Sep 24 05:58:45 AM UTC 24
Finished Sep 24 05:58:49 AM UTC 24
Peak memory 203720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614889666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2614889666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/0.uart_tx_rx.438412025
Short name T7
Test name
Test status
Simulation time 31418960964 ps
CPU time 13.4 seconds
Started Sep 24 05:58:42 AM UTC 24
Finished Sep 24 05:58:57 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438412025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.438412025
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/0.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_alert_test.52409035
Short name T37
Test name
Test status
Simulation time 21175159 ps
CPU time 0.75 seconds
Started Sep 24 05:59:56 AM UTC 24
Finished Sep 24 05:59:58 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52409035 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.52409035
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_fifo_full.3784696313
Short name T12
Test name
Test status
Simulation time 37065209429 ps
CPU time 30.11 seconds
Started Sep 24 05:58:58 AM UTC 24
Finished Sep 24 05:59:29 AM UTC 24
Peak memory 208568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784696313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3784696313
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_intr.3929351315
Short name T279
Test name
Test status
Simulation time 117879355618 ps
CPU time 236.33 seconds
Started Sep 24 05:59:16 AM UTC 24
Finished Sep 24 06:03:16 AM UTC 24
Peak memory 209260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929351315 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.3929351315
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_loopback.1465231706
Short name T25
Test name
Test status
Simulation time 151353779 ps
CPU time 1.65 seconds
Started Sep 24 05:59:43 AM UTC 24
Finished Sep 24 05:59:45 AM UTC 24
Peak memory 207344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465231706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1465231706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_noise_filter.3425846393
Short name T27
Test name
Test status
Simulation time 4359171472 ps
CPU time 17.59 seconds
Started Sep 24 05:59:18 AM UTC 24
Finished Sep 24 05:59:38 AM UTC 24
Peak memory 209396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425846393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3425846393
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_perf.1862747589
Short name T288
Test name
Test status
Simulation time 19804187229 ps
CPU time 350.65 seconds
Started Sep 24 05:59:45 AM UTC 24
Finished Sep 24 06:05:41 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862747589 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1862747589
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_rx_oversample.3706108310
Short name T21
Test name
Test status
Simulation time 3086607919 ps
CPU time 25.32 seconds
Started Sep 24 05:59:15 AM UTC 24
Finished Sep 24 05:59:42 AM UTC 24
Peak memory 208528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706108310 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3706108310
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.1166747622
Short name T34
Test name
Test status
Simulation time 6143217704 ps
CPU time 2.43 seconds
Started Sep 24 05:59:31 AM UTC 24
Finished Sep 24 05:59:35 AM UTC 24
Peak memory 203836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166747622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1166747622
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_sec_cm.32189555
Short name T36
Test name
Test status
Simulation time 209917618 ps
CPU time 1.17 seconds
Started Sep 24 05:59:56 AM UTC 24
Finished Sep 24 05:59:58 AM UTC 24
Peak memory 237828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32189555 -assert nopostproc +UVM_TESTNAME=uart_bas
e_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.32189555
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_smoke.827773676
Short name T9
Test name
Test status
Simulation time 691784700 ps
CPU time 2.45 seconds
Started Sep 24 05:58:58 AM UTC 24
Finished Sep 24 05:59:01 AM UTC 24
Peak memory 203980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827773676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.uart_smoke.827773676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_stress_all.2230851925
Short name T73
Test name
Test status
Simulation time 119855068595 ps
CPU time 526.54 seconds
Started Sep 24 05:59:48 AM UTC 24
Finished Sep 24 06:08:41 AM UTC 24
Peak memory 206096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230851925 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2230851925
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/1.uart_tx_rx.4080231529
Short name T93
Test name
Test status
Simulation time 40719525991 ps
CPU time 89.03 seconds
Started Sep 24 05:58:58 AM UTC 24
Finished Sep 24 06:00:29 AM UTC 24
Peak memory 209040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080231529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.4080231529
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/1.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_alert_test.69118890
Short name T452
Test name
Test status
Simulation time 32685828 ps
CPU time 0.85 seconds
Started Sep 24 06:06:18 AM UTC 24
Finished Sep 24 06:06:19 AM UTC 24
Peak memory 203184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69118890 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.69118890
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_fifo_full.2716494994
Short name T117
Test name
Test status
Simulation time 57755436511 ps
CPU time 31.66 seconds
Started Sep 24 06:05:32 AM UTC 24
Finished Sep 24 06:06:05 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716494994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2716494994
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2427315580
Short name T392
Test name
Test status
Simulation time 23601220848 ps
CPU time 72.62 seconds
Started Sep 24 06:05:36 AM UTC 24
Finished Sep 24 06:06:50 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427315580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2427315580
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.1840120803
Short name T498
Test name
Test status
Simulation time 123761527657 ps
CPU time 340.39 seconds
Started Sep 24 06:06:12 AM UTC 24
Finished Sep 24 06:11:57 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840120803 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1840120803
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_loopback.2137736448
Short name T451
Test name
Test status
Simulation time 6478482474 ps
CPU time 7.16 seconds
Started Sep 24 06:06:08 AM UTC 24
Finished Sep 24 06:06:16 AM UTC 24
Peak memory 208904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137736448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2137736448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_noise_filter.4040590919
Short name T338
Test name
Test status
Simulation time 89032658073 ps
CPU time 238.01 seconds
Started Sep 24 06:05:46 AM UTC 24
Finished Sep 24 06:09:48 AM UTC 24
Peak memory 218580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040590919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.4040590919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_rx_oversample.3007074242
Short name T450
Test name
Test status
Simulation time 6992863732 ps
CPU time 19.4 seconds
Started Sep 24 06:05:42 AM UTC 24
Finished Sep 24 06:06:02 AM UTC 24
Peak memory 208460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007074242 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3007074242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.2352980341
Short name T320
Test name
Test status
Simulation time 75151136034 ps
CPU time 82.86 seconds
Started Sep 24 06:06:03 AM UTC 24
Finished Sep 24 06:07:28 AM UTC 24
Peak memory 203844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352980341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2352980341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.806888697
Short name T346
Test name
Test status
Simulation time 38032311740 ps
CPU time 25.73 seconds
Started Sep 24 06:06:01 AM UTC 24
Finished Sep 24 06:06:28 AM UTC 24
Peak memory 205888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806888697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.806888697
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_smoke.1279791518
Short name T368
Test name
Test status
Simulation time 843106645 ps
CPU time 6.32 seconds
Started Sep 24 06:05:29 AM UTC 24
Finished Sep 24 06:05:37 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279791518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1279791518
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.2487478608
Short name T46
Test name
Test status
Simulation time 5715645368 ps
CPU time 35.69 seconds
Started Sep 24 06:06:15 AM UTC 24
Finished Sep 24 06:06:52 AM UTC 24
Peak memory 220336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2487478608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all
_with_rand_reset.2487478608
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.326909258
Short name T286
Test name
Test status
Simulation time 1127144124 ps
CPU time 4.45 seconds
Started Sep 24 06:06:06 AM UTC 24
Finished Sep 24 06:06:12 AM UTC 24
Peak memory 203920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326909258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.326909258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/10.uart_tx_rx.1418774413
Short name T306
Test name
Test status
Simulation time 108906999226 ps
CPU time 46.14 seconds
Started Sep 24 06:05:29 AM UTC 24
Finished Sep 24 06:06:17 AM UTC 24
Peak memory 203772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418774413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1418774413
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/10.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/100.uart_fifo_reset.1506080290
Short name T1004
Test name
Test status
Simulation time 40781981672 ps
CPU time 27.69 seconds
Started Sep 24 06:34:05 AM UTC 24
Finished Sep 24 06:34:34 AM UTC 24
Peak memory 209260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506080290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1506080290
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/100.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/101.uart_fifo_reset.2464553230
Short name T232
Test name
Test status
Simulation time 26163326119 ps
CPU time 22.98 seconds
Started Sep 24 06:34:08 AM UTC 24
Finished Sep 24 06:34:32 AM UTC 24
Peak memory 203712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464553230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2464553230
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/101.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/102.uart_fifo_reset.4071996426
Short name T1005
Test name
Test status
Simulation time 39211942377 ps
CPU time 33.99 seconds
Started Sep 24 06:34:09 AM UTC 24
Finished Sep 24 06:34:44 AM UTC 24
Peak memory 209172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071996426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.4071996426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/102.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/104.uart_fifo_reset.912165615
Short name T1009
Test name
Test status
Simulation time 269185117618 ps
CPU time 35.15 seconds
Started Sep 24 06:34:14 AM UTC 24
Finished Sep 24 06:34:50 AM UTC 24
Peak memory 209616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912165615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.912165615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/104.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/105.uart_fifo_reset.453175615
Short name T187
Test name
Test status
Simulation time 146904795373 ps
CPU time 29.33 seconds
Started Sep 24 06:34:16 AM UTC 24
Finished Sep 24 06:34:47 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453175615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.453175615
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/105.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/106.uart_fifo_reset.1694475887
Short name T264
Test name
Test status
Simulation time 4280831630 ps
CPU time 15.01 seconds
Started Sep 24 06:34:24 AM UTC 24
Finished Sep 24 06:34:41 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694475887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1694475887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/106.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/107.uart_fifo_reset.2742685895
Short name T222
Test name
Test status
Simulation time 12336740035 ps
CPU time 44.03 seconds
Started Sep 24 06:34:24 AM UTC 24
Finished Sep 24 06:35:10 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742685895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2742685895
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/107.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/108.uart_fifo_reset.2092571856
Short name T1017
Test name
Test status
Simulation time 37596184589 ps
CPU time 45.24 seconds
Started Sep 24 06:34:25 AM UTC 24
Finished Sep 24 06:35:12 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092571856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2092571856
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/108.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/109.uart_fifo_reset.1692212634
Short name T1047
Test name
Test status
Simulation time 114379112633 ps
CPU time 110.91 seconds
Started Sep 24 06:34:25 AM UTC 24
Finished Sep 24 06:36:19 AM UTC 24
Peak memory 209060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692212634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1692212634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/109.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_alert_test.3840078494
Short name T455
Test name
Test status
Simulation time 11827396 ps
CPU time 0.85 seconds
Started Sep 24 06:07:05 AM UTC 24
Finished Sep 24 06:07:07 AM UTC 24
Peak memory 203312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840078494 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3840078494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_fifo_full.3197972113
Short name T127
Test name
Test status
Simulation time 42824756822 ps
CPU time 31.89 seconds
Started Sep 24 06:06:23 AM UTC 24
Finished Sep 24 06:06:56 AM UTC 24
Peak memory 209200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197972113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.3197972113
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_intr.2661132188
Short name T457
Test name
Test status
Simulation time 12343297722 ps
CPU time 32.67 seconds
Started Sep 24 06:06:49 AM UTC 24
Finished Sep 24 06:07:23 AM UTC 24
Peak memory 203504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661132188 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2661132188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_long_xfer_wo_dly.579591093
Short name T519
Test name
Test status
Simulation time 72169963973 ps
CPU time 435.03 seconds
Started Sep 24 06:06:59 AM UTC 24
Finished Sep 24 06:14:19 AM UTC 24
Peak memory 209264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579591093 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.579591093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_loopback.1995838438
Short name T454
Test name
Test status
Simulation time 3419182084 ps
CPU time 6.99 seconds
Started Sep 24 06:06:56 AM UTC 24
Finished Sep 24 06:07:04 AM UTC 24
Peak memory 203840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995838438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1995838438
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_perf.440429198
Short name T382
Test name
Test status
Simulation time 11144806838 ps
CPU time 380.31 seconds
Started Sep 24 06:06:57 AM UTC 24
Finished Sep 24 06:13:22 AM UTC 24
Peak memory 203840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440429198 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.440429198
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_rx_oversample.3630557544
Short name T456
Test name
Test status
Simulation time 5169511193 ps
CPU time 21.47 seconds
Started Sep 24 06:06:48 AM UTC 24
Finished Sep 24 06:07:11 AM UTC 24
Peak memory 208404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630557544 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3630557544
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.712648147
Short name T292
Test name
Test status
Simulation time 35506797544 ps
CPU time 32.77 seconds
Started Sep 24 06:06:53 AM UTC 24
Finished Sep 24 06:07:28 AM UTC 24
Peak memory 208864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712648147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.712648147
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.2358325213
Short name T295
Test name
Test status
Simulation time 37013696248 ps
CPU time 20.71 seconds
Started Sep 24 06:06:50 AM UTC 24
Finished Sep 24 06:07:12 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358325213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2358325213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_smoke.1512835883
Short name T384
Test name
Test status
Simulation time 905510137 ps
CPU time 2.1 seconds
Started Sep 24 06:06:19 AM UTC 24
Finished Sep 24 06:06:22 AM UTC 24
Peak memory 204116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512835883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1512835883
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_stress_all.2880467333
Short name T192
Test name
Test status
Simulation time 138143392033 ps
CPU time 947.85 seconds
Started Sep 24 06:07:05 AM UTC 24
Finished Sep 24 06:23:04 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880467333 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.2880467333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.2778048431
Short name T317
Test name
Test status
Simulation time 19830347742 ps
CPU time 53.62 seconds
Started Sep 24 06:07:01 AM UTC 24
Finished Sep 24 06:07:56 AM UTC 24
Peak memory 221268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2778048431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all
_with_rand_reset.2778048431
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.1994926678
Short name T453
Test name
Test status
Simulation time 1162863712 ps
CPU time 5.14 seconds
Started Sep 24 06:06:53 AM UTC 24
Finished Sep 24 06:07:00 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994926678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1994926678
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/11.uart_tx_rx.3384029003
Short name T307
Test name
Test status
Simulation time 150218126317 ps
CPU time 169.58 seconds
Started Sep 24 06:06:20 AM UTC 24
Finished Sep 24 06:09:12 AM UTC 24
Peak memory 209516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384029003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3384029003
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/11.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/110.uart_fifo_reset.882780336
Short name T1028
Test name
Test status
Simulation time 26415966604 ps
CPU time 71.94 seconds
Started Sep 24 06:34:26 AM UTC 24
Finished Sep 24 06:35:39 AM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882780336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.882780336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/110.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/111.uart_fifo_reset.1988577888
Short name T1025
Test name
Test status
Simulation time 21842098549 ps
CPU time 65.24 seconds
Started Sep 24 06:34:27 AM UTC 24
Finished Sep 24 06:35:34 AM UTC 24
Peak memory 209324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988577888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1988577888
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/111.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/112.uart_fifo_reset.1880390044
Short name T1115
Test name
Test status
Simulation time 129891918709 ps
CPU time 252.48 seconds
Started Sep 24 06:34:31 AM UTC 24
Finished Sep 24 06:38:46 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880390044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1880390044
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/112.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/113.uart_fifo_reset.352219005
Short name T188
Test name
Test status
Simulation time 243451606073 ps
CPU time 32.87 seconds
Started Sep 24 06:34:33 AM UTC 24
Finished Sep 24 06:35:07 AM UTC 24
Peak memory 203776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352219005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.352219005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/113.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/114.uart_fifo_reset.595100773
Short name T163
Test name
Test status
Simulation time 120844452758 ps
CPU time 60.07 seconds
Started Sep 24 06:34:34 AM UTC 24
Finished Sep 24 06:35:35 AM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595100773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.595100773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/114.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/115.uart_fifo_reset.820075241
Short name T1037
Test name
Test status
Simulation time 27396535329 ps
CPU time 82.24 seconds
Started Sep 24 06:34:35 AM UTC 24
Finished Sep 24 06:35:59 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820075241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.820075241
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/115.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/116.uart_fifo_reset.968212400
Short name T1032
Test name
Test status
Simulation time 27425838099 ps
CPU time 66.53 seconds
Started Sep 24 06:34:35 AM UTC 24
Finished Sep 24 06:35:43 AM UTC 24
Peak memory 204044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968212400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.968212400
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/116.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/117.uart_fifo_reset.1137479356
Short name T1053
Test name
Test status
Simulation time 43763861164 ps
CPU time 105.71 seconds
Started Sep 24 06:34:37 AM UTC 24
Finished Sep 24 06:36:25 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137479356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.1137479356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/117.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/118.uart_fifo_reset.541401797
Short name T1020
Test name
Test status
Simulation time 122033545986 ps
CPU time 39.41 seconds
Started Sep 24 06:34:40 AM UTC 24
Finished Sep 24 06:35:21 AM UTC 24
Peak memory 209396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541401797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.541401797
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/118.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_alert_test.3330835966
Short name T460
Test name
Test status
Simulation time 24836099 ps
CPU time 0.83 seconds
Started Sep 24 06:07:41 AM UTC 24
Finished Sep 24 06:07:43 AM UTC 24
Peak memory 203312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330835966 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3330835966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_fifo_overflow.208882197
Short name T146
Test name
Test status
Simulation time 30202340095 ps
CPU time 25.56 seconds
Started Sep 24 06:07:11 AM UTC 24
Finished Sep 24 06:07:38 AM UTC 24
Peak memory 203580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208882197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.208882197
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_long_xfer_wo_dly.3842046941
Short name T289
Test name
Test status
Simulation time 77081254773 ps
CPU time 222.54 seconds
Started Sep 24 06:07:38 AM UTC 24
Finished Sep 24 06:11:24 AM UTC 24
Peak memory 209576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842046941 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3842046941
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_loopback.3758686938
Short name T459
Test name
Test status
Simulation time 1214465331 ps
CPU time 3.33 seconds
Started Sep 24 06:07:30 AM UTC 24
Finished Sep 24 06:07:34 AM UTC 24
Peak memory 207976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758686938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3758686938
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_noise_filter.569987966
Short name T336
Test name
Test status
Simulation time 38423037419 ps
CPU time 72.73 seconds
Started Sep 24 06:07:27 AM UTC 24
Finished Sep 24 06:08:42 AM UTC 24
Peak memory 209804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569987966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.569987966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_perf.1130745390
Short name T487
Test name
Test status
Simulation time 6447638992 ps
CPU time 203.63 seconds
Started Sep 24 06:07:35 AM UTC 24
Finished Sep 24 06:11:02 AM UTC 24
Peak memory 203968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130745390 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1130745390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_rx_oversample.414505542
Short name T458
Test name
Test status
Simulation time 1683889233 ps
CPU time 9.69 seconds
Started Sep 24 06:07:15 AM UTC 24
Finished Sep 24 06:07:26 AM UTC 24
Peak memory 208140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414505542 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.414505542
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.1352253509
Short name T131
Test name
Test status
Simulation time 147101905020 ps
CPU time 330.28 seconds
Started Sep 24 06:07:29 AM UTC 24
Finished Sep 24 06:13:04 AM UTC 24
Peak memory 203780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352253509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1352253509
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.516583364
Short name T390
Test name
Test status
Simulation time 6649950041 ps
CPU time 10.18 seconds
Started Sep 24 06:07:29 AM UTC 24
Finished Sep 24 06:07:40 AM UTC 24
Peak memory 203840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516583364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.516583364
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_smoke.1166870842
Short name T347
Test name
Test status
Simulation time 11060205636 ps
CPU time 33.48 seconds
Started Sep 24 06:07:05 AM UTC 24
Finished Sep 24 06:07:40 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166870842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1166870842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_stress_all.595477499
Short name T299
Test name
Test status
Simulation time 70536742503 ps
CPU time 155.61 seconds
Started Sep 24 06:07:39 AM UTC 24
Finished Sep 24 06:10:17 AM UTC 24
Peak memory 218508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595477499 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.595477499
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.2756101799
Short name T72
Test name
Test status
Simulation time 52123273348 ps
CPU time 60.07 seconds
Started Sep 24 06:07:39 AM UTC 24
Finished Sep 24 06:08:41 AM UTC 24
Peak memory 222728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2756101799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all
_with_rand_reset.2756101799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.3159442689
Short name T386
Test name
Test status
Simulation time 935754874 ps
CPU time 6.63 seconds
Started Sep 24 06:07:30 AM UTC 24
Finished Sep 24 06:07:37 AM UTC 24
Peak memory 203728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159442689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3159442689
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/12.uart_tx_rx.2201469012
Short name T359
Test name
Test status
Simulation time 6907192604 ps
CPU time 20.94 seconds
Started Sep 24 06:07:07 AM UTC 24
Finished Sep 24 06:07:29 AM UTC 24
Peak memory 207556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201469012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2201469012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/12.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/120.uart_fifo_reset.607133011
Short name T226
Test name
Test status
Simulation time 8285327783 ps
CPU time 31.19 seconds
Started Sep 24 06:34:41 AM UTC 24
Finished Sep 24 06:35:14 AM UTC 24
Peak memory 209316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607133011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.607133011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/120.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/121.uart_fifo_reset.3875353594
Short name T1061
Test name
Test status
Simulation time 71777076704 ps
CPU time 140.16 seconds
Started Sep 24 06:34:45 AM UTC 24
Finished Sep 24 06:37:08 AM UTC 24
Peak memory 204100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875353594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3875353594
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/121.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/122.uart_fifo_reset.2827921136
Short name T1036
Test name
Test status
Simulation time 104562281509 ps
CPU time 68.35 seconds
Started Sep 24 06:34:48 AM UTC 24
Finished Sep 24 06:35:58 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827921136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2827921136
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/122.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/123.uart_fifo_reset.186227658
Short name T1015
Test name
Test status
Simulation time 51418439446 ps
CPU time 19.29 seconds
Started Sep 24 06:34:48 AM UTC 24
Finished Sep 24 06:35:08 AM UTC 24
Peak memory 209524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186227658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.186227658
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/123.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/124.uart_fifo_reset.652505873
Short name T1002
Test name
Test status
Simulation time 61464223290 ps
CPU time 65.75 seconds
Started Sep 24 06:34:50 AM UTC 24
Finished Sep 24 06:35:57 AM UTC 24
Peak memory 209252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652505873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.652505873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/124.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/126.uart_fifo_reset.826389311
Short name T180
Test name
Test status
Simulation time 111199703015 ps
CPU time 105.49 seconds
Started Sep 24 06:34:51 AM UTC 24
Finished Sep 24 06:36:38 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826389311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.826389311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/126.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/127.uart_fifo_reset.3489444749
Short name T179
Test name
Test status
Simulation time 3831022125 ps
CPU time 13.02 seconds
Started Sep 24 06:34:51 AM UTC 24
Finished Sep 24 06:35:05 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489444749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3489444749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/127.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/128.uart_fifo_reset.2262808873
Short name T1076
Test name
Test status
Simulation time 65294264614 ps
CPU time 159.56 seconds
Started Sep 24 06:34:57 AM UTC 24
Finished Sep 24 06:37:39 AM UTC 24
Peak memory 209592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262808873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.2262808873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/128.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/129.uart_fifo_reset.1996779432
Short name T1016
Test name
Test status
Simulation time 2321246265 ps
CPU time 9.44 seconds
Started Sep 24 06:34:59 AM UTC 24
Finished Sep 24 06:35:10 AM UTC 24
Peak memory 209464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996779432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1996779432
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/129.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_alert_test.748093975
Short name T464
Test name
Test status
Simulation time 13312995 ps
CPU time 0.85 seconds
Started Sep 24 06:08:29 AM UTC 24
Finished Sep 24 06:08:32 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748093975 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.748093975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_fifo_full.137043989
Short name T138
Test name
Test status
Simulation time 27808382171 ps
CPU time 34.6 seconds
Started Sep 24 06:07:43 AM UTC 24
Finished Sep 24 06:08:19 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137043989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.137043989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_fifo_reset.403624264
Short name T301
Test name
Test status
Simulation time 83306413125 ps
CPU time 67.5 seconds
Started Sep 24 06:07:53 AM UTC 24
Finished Sep 24 06:09:03 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403624264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.403624264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_intr.2554390251
Short name T402
Test name
Test status
Simulation time 20659618225 ps
CPU time 39.73 seconds
Started Sep 24 06:07:57 AM UTC 24
Finished Sep 24 06:08:39 AM UTC 24
Peak memory 208716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554390251 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2554390251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_loopback.1907089950
Short name T463
Test name
Test status
Simulation time 2872963218 ps
CPU time 11.75 seconds
Started Sep 24 06:08:15 AM UTC 24
Finished Sep 24 06:08:28 AM UTC 24
Peak memory 207952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907089950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1907089950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_noise_filter.4098286673
Short name T328
Test name
Test status
Simulation time 157658392027 ps
CPU time 134.78 seconds
Started Sep 24 06:08:11 AM UTC 24
Finished Sep 24 06:10:28 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098286673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.4098286673
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_perf.2902530368
Short name T642
Test name
Test status
Simulation time 14537171349 ps
CPU time 703.17 seconds
Started Sep 24 06:08:16 AM UTC 24
Finished Sep 24 06:20:08 AM UTC 24
Peak memory 207236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902530368 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2902530368
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_rx_oversample.983610829
Short name T461
Test name
Test status
Simulation time 5051193066 ps
CPU time 16.4 seconds
Started Sep 24 06:07:55 AM UTC 24
Finished Sep 24 06:08:12 AM UTC 24
Peak memory 208204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983610829 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.983610829
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.444876846
Short name T270
Test name
Test status
Simulation time 57689880793 ps
CPU time 104.69 seconds
Started Sep 24 06:08:13 AM UTC 24
Finished Sep 24 06:10:00 AM UTC 24
Peak memory 203844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444876846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.444876846
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.1325001176
Short name T357
Test name
Test status
Simulation time 35384458832 ps
CPU time 81.48 seconds
Started Sep 24 06:08:12 AM UTC 24
Finished Sep 24 06:09:35 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325001176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1325001176
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_smoke.2103776677
Short name T389
Test name
Test status
Simulation time 6282810989 ps
CPU time 11.51 seconds
Started Sep 24 06:07:41 AM UTC 24
Finished Sep 24 06:07:54 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103776677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2103776677
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_stress_all.1696511939
Short name T340
Test name
Test status
Simulation time 98353246556 ps
CPU time 115.26 seconds
Started Sep 24 06:08:28 AM UTC 24
Finished Sep 24 06:10:26 AM UTC 24
Peak memory 205900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696511939 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1696511939
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.1744897936
Short name T87
Test name
Test status
Simulation time 11232639584 ps
CPU time 23.17 seconds
Started Sep 24 06:08:20 AM UTC 24
Finished Sep 24 06:08:45 AM UTC 24
Peak memory 220348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1744897936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all
_with_rand_reset.1744897936
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.4215669953
Short name T462
Test name
Test status
Simulation time 2199629102 ps
CPU time 3.12 seconds
Started Sep 24 06:08:15 AM UTC 24
Finished Sep 24 06:08:19 AM UTC 24
Peak memory 204048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215669953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.4215669953
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/13.uart_tx_rx.2485070122
Short name T387
Test name
Test status
Simulation time 20651669561 ps
CPU time 33.1 seconds
Started Sep 24 06:07:41 AM UTC 24
Finished Sep 24 06:08:16 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485070122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2485070122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/13.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/130.uart_fifo_reset.3575708427
Short name T1027
Test name
Test status
Simulation time 35551579361 ps
CPU time 31.61 seconds
Started Sep 24 06:35:04 AM UTC 24
Finished Sep 24 06:35:37 AM UTC 24
Peak memory 208740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575708427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.3575708427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/130.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/131.uart_fifo_reset.1161107840
Short name T1029
Test name
Test status
Simulation time 45568674828 ps
CPU time 34.81 seconds
Started Sep 24 06:35:05 AM UTC 24
Finished Sep 24 06:35:41 AM UTC 24
Peak memory 209524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161107840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1161107840
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/131.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/133.uart_fifo_reset.3195280229
Short name T167
Test name
Test status
Simulation time 7545806365 ps
CPU time 17.87 seconds
Started Sep 24 06:35:07 AM UTC 24
Finished Sep 24 06:35:26 AM UTC 24
Peak memory 209316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195280229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3195280229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/133.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/134.uart_fifo_reset.2538052990
Short name T1040
Test name
Test status
Simulation time 37490867296 ps
CPU time 55.82 seconds
Started Sep 24 06:35:08 AM UTC 24
Finished Sep 24 06:36:06 AM UTC 24
Peak memory 207808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538052990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2538052990
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/134.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/136.uart_fifo_reset.2953823874
Short name T190
Test name
Test status
Simulation time 17314238265 ps
CPU time 39.76 seconds
Started Sep 24 06:35:11 AM UTC 24
Finished Sep 24 06:35:52 AM UTC 24
Peak memory 209652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953823874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2953823874
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/136.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/137.uart_fifo_reset.1948898897
Short name T1023
Test name
Test status
Simulation time 20444144238 ps
CPU time 16.14 seconds
Started Sep 24 06:35:11 AM UTC 24
Finished Sep 24 06:35:28 AM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948898897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1948898897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/137.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/138.uart_fifo_reset.2938217784
Short name T1056
Test name
Test status
Simulation time 37471094906 ps
CPU time 89.34 seconds
Started Sep 24 06:35:11 AM UTC 24
Finished Sep 24 06:36:42 AM UTC 24
Peak memory 203720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938217784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2938217784
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/138.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/139.uart_fifo_reset.2670978836
Short name T1035
Test name
Test status
Simulation time 14223527133 ps
CPU time 38.37 seconds
Started Sep 24 06:35:13 AM UTC 24
Finished Sep 24 06:35:53 AM UTC 24
Peak memory 203844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670978836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2670978836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/139.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_alert_test.1057059314
Short name T468
Test name
Test status
Simulation time 147482148 ps
CPU time 0.85 seconds
Started Sep 24 06:09:13 AM UTC 24
Finished Sep 24 06:09:14 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057059314 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1057059314
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_fifo_full.585110510
Short name T161
Test name
Test status
Simulation time 66341777007 ps
CPU time 39.5 seconds
Started Sep 24 06:08:33 AM UTC 24
Finished Sep 24 06:09:14 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585110510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.585110510
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_fifo_reset.729137241
Short name T173
Test name
Test status
Simulation time 34487631170 ps
CPU time 34.83 seconds
Started Sep 24 06:08:42 AM UTC 24
Finished Sep 24 06:09:18 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729137241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.729137241
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_intr.3997365744
Short name T559
Test name
Test status
Simulation time 205489626232 ps
CPU time 450.28 seconds
Started Sep 24 06:08:43 AM UTC 24
Finished Sep 24 06:16:19 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997365744 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3997365744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_long_xfer_wo_dly.2179436339
Short name T565
Test name
Test status
Simulation time 165018223506 ps
CPU time 449.84 seconds
Started Sep 24 06:09:08 AM UTC 24
Finished Sep 24 06:16:44 AM UTC 24
Peak memory 209260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179436339 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2179436339
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_loopback.105264754
Short name T399
Test name
Test status
Simulation time 1365156827 ps
CPU time 4.06 seconds
Started Sep 24 06:09:04 AM UTC 24
Finished Sep 24 06:09:09 AM UTC 24
Peak memory 208068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105264754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.uart_loopback.105264754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_noise_filter.3253381120
Short name T283
Test name
Test status
Simulation time 154561206738 ps
CPU time 66.01 seconds
Started Sep 24 06:08:46 AM UTC 24
Finished Sep 24 06:09:54 AM UTC 24
Peak memory 218448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253381120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3253381120
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_perf.3599557656
Short name T355
Test name
Test status
Simulation time 34542007144 ps
CPU time 118.56 seconds
Started Sep 24 06:09:08 AM UTC 24
Finished Sep 24 06:11:09 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599557656 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3599557656
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_rx_oversample.1914855365
Short name T466
Test name
Test status
Simulation time 2099375819 ps
CPU time 12.67 seconds
Started Sep 24 06:08:42 AM UTC 24
Finished Sep 24 06:08:56 AM UTC 24
Peak memory 207880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914855365 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.1914855365
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.3982738357
Short name T305
Test name
Test status
Simulation time 15248301069 ps
CPU time 23.5 seconds
Started Sep 24 06:08:56 AM UTC 24
Finished Sep 24 06:09:21 AM UTC 24
Peak memory 208212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982738357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3982738357
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.2044363217
Short name T475
Test name
Test status
Simulation time 43059711228 ps
CPU time 70.63 seconds
Started Sep 24 06:08:48 AM UTC 24
Finished Sep 24 06:10:00 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044363217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2044363217
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_smoke.3757001186
Short name T465
Test name
Test status
Simulation time 6038371804 ps
CPU time 13.73 seconds
Started Sep 24 06:08:33 AM UTC 24
Finished Sep 24 06:08:47 AM UTC 24
Peak memory 203772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757001186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3757001186
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_stress_all.1450702252
Short name T433
Test name
Test status
Simulation time 52315164973 ps
CPU time 1065.36 seconds
Started Sep 24 06:09:11 AM UTC 24
Finished Sep 24 06:27:08 AM UTC 24
Peak memory 209200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450702252 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1450702252
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.124478359
Short name T467
Test name
Test status
Simulation time 1702110377 ps
CPU time 3.19 seconds
Started Sep 24 06:09:03 AM UTC 24
Finished Sep 24 06:09:07 AM UTC 24
Peak memory 203988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124478359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.124478359
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/14.uart_tx_rx.3834084524
Short name T337
Test name
Test status
Simulation time 28304063887 ps
CPU time 29.55 seconds
Started Sep 24 06:08:33 AM UTC 24
Finished Sep 24 06:09:03 AM UTC 24
Peak memory 209388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834084524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3834084524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/14.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/140.uart_fifo_reset.1777115130
Short name T1034
Test name
Test status
Simulation time 201742331735 ps
CPU time 34.75 seconds
Started Sep 24 06:35:13 AM UTC 24
Finished Sep 24 06:35:49 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777115130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1777115130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/140.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/141.uart_fifo_reset.3650312394
Short name T1033
Test name
Test status
Simulation time 15845155054 ps
CPU time 33.97 seconds
Started Sep 24 06:35:13 AM UTC 24
Finished Sep 24 06:35:48 AM UTC 24
Peak memory 209568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650312394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.3650312394
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/141.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/142.uart_fifo_reset.285960549
Short name T196
Test name
Test status
Simulation time 37120949153 ps
CPU time 64.92 seconds
Started Sep 24 06:35:14 AM UTC 24
Finished Sep 24 06:36:21 AM UTC 24
Peak memory 204116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285960549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.285960549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/142.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/143.uart_fifo_reset.3811767118
Short name T1045
Test name
Test status
Simulation time 157803341822 ps
CPU time 57.46 seconds
Started Sep 24 06:35:15 AM UTC 24
Finished Sep 24 06:36:14 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811767118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3811767118
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/143.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/145.uart_fifo_reset.1618041643
Short name T1024
Test name
Test status
Simulation time 27496529674 ps
CPU time 12.69 seconds
Started Sep 24 06:35:16 AM UTC 24
Finished Sep 24 06:35:30 AM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618041643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1618041643
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/145.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/146.uart_fifo_reset.1519160984
Short name T1169
Test name
Test status
Simulation time 216878338018 ps
CPU time 378.13 seconds
Started Sep 24 06:35:22 AM UTC 24
Finished Sep 24 06:41:45 AM UTC 24
Peak memory 212644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519160984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1519160984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/146.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/147.uart_fifo_reset.2854726935
Short name T191
Test name
Test status
Simulation time 34065325700 ps
CPU time 38.57 seconds
Started Sep 24 06:35:23 AM UTC 24
Finished Sep 24 06:36:03 AM UTC 24
Peak memory 204176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854726935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.2854726935
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/147.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/148.uart_fifo_reset.2086632704
Short name T1051
Test name
Test status
Simulation time 25080091206 ps
CPU time 54.65 seconds
Started Sep 24 06:35:24 AM UTC 24
Finished Sep 24 06:36:21 AM UTC 24
Peak memory 203644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086632704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2086632704
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/148.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/149.uart_fifo_reset.3162436541
Short name T1138
Test name
Test status
Simulation time 147311048690 ps
CPU time 249.46 seconds
Started Sep 24 06:35:28 AM UTC 24
Finished Sep 24 06:39:41 AM UTC 24
Peak memory 209196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162436541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3162436541
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/149.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_alert_test.1112682807
Short name T473
Test name
Test status
Simulation time 28693808 ps
CPU time 0.85 seconds
Started Sep 24 06:09:50 AM UTC 24
Finished Sep 24 06:09:52 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112682807 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1112682807
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_fifo_full.3671942525
Short name T483
Test name
Test status
Simulation time 37686319907 ps
CPU time 88.95 seconds
Started Sep 24 06:09:15 AM UTC 24
Finished Sep 24 06:10:46 AM UTC 24
Peak memory 203864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671942525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.3671942525
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.356171060
Short name T471
Test name
Test status
Simulation time 62677606527 ps
CPU time 22.93 seconds
Started Sep 24 06:09:18 AM UTC 24
Finished Sep 24 06:09:42 AM UTC 24
Peak memory 204040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356171060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.356171060
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_fifo_reset.4195866470
Short name T485
Test name
Test status
Simulation time 49742675961 ps
CPU time 99.23 seconds
Started Sep 24 06:09:19 AM UTC 24
Finished Sep 24 06:11:00 AM UTC 24
Peak memory 209596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195866470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.4195866470
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_intr.3096786718
Short name T472
Test name
Test status
Simulation time 6872747477 ps
CPU time 22.97 seconds
Started Sep 24 06:09:25 AM UTC 24
Finished Sep 24 06:09:49 AM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096786718 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3096786718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_long_xfer_wo_dly.2841516834
Short name T1166
Test name
Test status
Simulation time 175941750154 ps
CPU time 1886.15 seconds
Started Sep 24 06:09:39 AM UTC 24
Finished Sep 24 06:41:26 AM UTC 24
Peak memory 212796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841516834 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2841516834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_loopback.3975676085
Short name T476
Test name
Test status
Simulation time 9845347593 ps
CPU time 34.21 seconds
Started Sep 24 06:09:36 AM UTC 24
Finished Sep 24 06:10:11 AM UTC 24
Peak memory 203856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975676085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3975676085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_noise_filter.2120128296
Short name T353
Test name
Test status
Simulation time 124883584454 ps
CPU time 92 seconds
Started Sep 24 06:09:27 AM UTC 24
Finished Sep 24 06:11:01 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120128296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.2120128296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_perf.2454205972
Short name T662
Test name
Test status
Simulation time 10026947255 ps
CPU time 697.17 seconds
Started Sep 24 06:09:37 AM UTC 24
Finished Sep 24 06:21:23 AM UTC 24
Peak memory 207100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454205972 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2454205972
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_rx_oversample.204572291
Short name T470
Test name
Test status
Simulation time 4817535556 ps
CPU time 11.3 seconds
Started Sep 24 06:09:22 AM UTC 24
Finished Sep 24 06:09:34 AM UTC 24
Peak memory 203980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204572291 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.204572291
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.4142053873
Short name T136
Test name
Test status
Simulation time 121815655675 ps
CPU time 192.14 seconds
Started Sep 24 06:09:31 AM UTC 24
Finished Sep 24 06:12:46 AM UTC 24
Peak memory 204040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142053873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4142053873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.656808096
Short name T490
Test name
Test status
Simulation time 54529251234 ps
CPU time 97.36 seconds
Started Sep 24 06:09:29 AM UTC 24
Finished Sep 24 06:11:09 AM UTC 24
Peak memory 203584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656808096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.656808096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_smoke.2681749724
Short name T469
Test name
Test status
Simulation time 272755567 ps
CPU time 1.63 seconds
Started Sep 24 06:09:15 AM UTC 24
Finished Sep 24 06:09:17 AM UTC 24
Peak memory 203328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681749724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2681749724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_stress_all.1821000792
Short name T157
Test name
Test status
Simulation time 54916725478 ps
CPU time 28.14 seconds
Started Sep 24 06:09:49 AM UTC 24
Finished Sep 24 06:10:18 AM UTC 24
Peak memory 203776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821000792 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1821000792
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.4062540122
Short name T375
Test name
Test status
Simulation time 18344077968 ps
CPU time 45.59 seconds
Started Sep 24 06:09:43 AM UTC 24
Finished Sep 24 06:10:30 AM UTC 24
Peak memory 218288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4062540122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all
_with_rand_reset.4062540122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.3444521681
Short name T377
Test name
Test status
Simulation time 4410916736 ps
CPU time 3.5 seconds
Started Sep 24 06:09:33 AM UTC 24
Finished Sep 24 06:09:38 AM UTC 24
Peak memory 204120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444521681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.3444521681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/15.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/150.uart_fifo_reset.2265654426
Short name T1101
Test name
Test status
Simulation time 77915628844 ps
CPU time 172.41 seconds
Started Sep 24 06:35:29 AM UTC 24
Finished Sep 24 06:38:24 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265654426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2265654426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/150.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/153.uart_fifo_reset.1029986347
Short name T1038
Test name
Test status
Simulation time 39917343171 ps
CPU time 24.65 seconds
Started Sep 24 06:35:36 AM UTC 24
Finished Sep 24 06:36:02 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029986347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.1029986347
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/153.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/154.uart_fifo_reset.4211148192
Short name T1060
Test name
Test status
Simulation time 47615363690 ps
CPU time 86.97 seconds
Started Sep 24 06:35:37 AM UTC 24
Finished Sep 24 06:37:06 AM UTC 24
Peak memory 208696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211148192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.4211148192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/154.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/155.uart_fifo_reset.393164939
Short name T1066
Test name
Test status
Simulation time 112988295948 ps
CPU time 105.22 seconds
Started Sep 24 06:35:38 AM UTC 24
Finished Sep 24 06:37:26 AM UTC 24
Peak memory 203780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393164939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.393164939
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/155.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/156.uart_fifo_reset.1460094356
Short name T1048
Test name
Test status
Simulation time 26672732653 ps
CPU time 36.77 seconds
Started Sep 24 06:35:40 AM UTC 24
Finished Sep 24 06:36:19 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460094356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1460094356
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/156.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/157.uart_fifo_reset.970861918
Short name T1116
Test name
Test status
Simulation time 86443639669 ps
CPU time 183.02 seconds
Started Sep 24 06:35:40 AM UTC 24
Finished Sep 24 06:38:46 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970861918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.970861918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/157.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/159.uart_fifo_reset.1609340332
Short name T1042
Test name
Test status
Simulation time 35584850408 ps
CPU time 26.39 seconds
Started Sep 24 06:35:43 AM UTC 24
Finished Sep 24 06:36:10 AM UTC 24
Peak memory 209196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609340332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1609340332
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/159.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_alert_test.1098543441
Short name T479
Test name
Test status
Simulation time 13078228 ps
CPU time 0.88 seconds
Started Sep 24 06:10:27 AM UTC 24
Finished Sep 24 06:10:29 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098543441 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.1098543441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_fifo_full.228159976
Short name T363
Test name
Test status
Simulation time 368606184083 ps
CPU time 137.31 seconds
Started Sep 24 06:09:54 AM UTC 24
Finished Sep 24 06:12:14 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228159976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.228159976
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_fifo_overflow.2400608864
Short name T313
Test name
Test status
Simulation time 105021675830 ps
CPU time 131.39 seconds
Started Sep 24 06:09:57 AM UTC 24
Finished Sep 24 06:12:11 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400608864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.2400608864
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_fifo_reset.1725576395
Short name T130
Test name
Test status
Simulation time 60999337958 ps
CPU time 44.02 seconds
Started Sep 24 06:09:57 AM UTC 24
Finished Sep 24 06:10:43 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725576395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1725576395
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_intr.7226288
Short name T511
Test name
Test status
Simulation time 130640787450 ps
CPU time 209.66 seconds
Started Sep 24 06:10:00 AM UTC 24
Finished Sep 24 06:13:33 AM UTC 24
Peak memory 207988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7226288 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.7226288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_long_xfer_wo_dly.871058254
Short name T542
Test name
Test status
Simulation time 114037134222 ps
CPU time 304.45 seconds
Started Sep 24 06:10:21 AM UTC 24
Finished Sep 24 06:15:30 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871058254 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.871058254
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_loopback.3696163984
Short name T477
Test name
Test status
Simulation time 1202688686 ps
CPU time 1.86 seconds
Started Sep 24 06:10:19 AM UTC 24
Finished Sep 24 06:10:22 AM UTC 24
Peak memory 207164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696163984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3696163984
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_noise_filter.2249004157
Short name T373
Test name
Test status
Simulation time 126803673934 ps
CPU time 181.04 seconds
Started Sep 24 06:10:01 AM UTC 24
Finished Sep 24 06:13:05 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249004157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2249004157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_perf.4199337255
Short name T591
Test name
Test status
Simulation time 10619760605 ps
CPU time 431.26 seconds
Started Sep 24 06:10:19 AM UTC 24
Finished Sep 24 06:17:36 AM UTC 24
Peak memory 204112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199337255 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.4199337255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_rx_oversample.3115191165
Short name T482
Test name
Test status
Simulation time 4589668034 ps
CPU time 41.07 seconds
Started Sep 24 06:09:57 AM UTC 24
Finished Sep 24 06:10:40 AM UTC 24
Peak memory 207944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115191165 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3115191165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_rx_parity_err.3999396942
Short name T316
Test name
Test status
Simulation time 66423732934 ps
CPU time 113.6 seconds
Started Sep 24 06:10:12 AM UTC 24
Finished Sep 24 06:12:07 AM UTC 24
Peak memory 203768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999396942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.3999396942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.3434958281
Short name T480
Test name
Test status
Simulation time 35503819526 ps
CPU time 27.11 seconds
Started Sep 24 06:10:02 AM UTC 24
Finished Sep 24 06:10:30 AM UTC 24
Peak memory 203504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434958281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3434958281
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_smoke.3728707067
Short name T474
Test name
Test status
Simulation time 309293263 ps
CPU time 2.2 seconds
Started Sep 24 06:09:53 AM UTC 24
Finished Sep 24 06:09:56 AM UTC 24
Peak memory 203724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728707067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3728707067
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_stress_all.3368782998
Short name T369
Test name
Test status
Simulation time 96888727888 ps
CPU time 269.04 seconds
Started Sep 24 06:10:25 AM UTC 24
Finished Sep 24 06:14:58 AM UTC 24
Peak memory 203776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368782998 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3368782998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_stress_all_with_rand_reset.3538205652
Short name T396
Test name
Test status
Simulation time 1679518155 ps
CPU time 20.83 seconds
Started Sep 24 06:10:23 AM UTC 24
Finished Sep 24 06:10:45 AM UTC 24
Peak memory 209400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3538205652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all
_with_rand_reset.3538205652
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.88295488
Short name T478
Test name
Test status
Simulation time 936703396 ps
CPU time 5.43 seconds
Started Sep 24 06:10:18 AM UTC 24
Finished Sep 24 06:10:24 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88295488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.88295488
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/16.uart_tx_rx.2497126258
Short name T541
Test name
Test status
Simulation time 69045723306 ps
CPU time 329.17 seconds
Started Sep 24 06:09:54 AM UTC 24
Finished Sep 24 06:15:28 AM UTC 24
Peak memory 204044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497126258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2497126258
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/16.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/160.uart_fifo_reset.590248108
Short name T1063
Test name
Test status
Simulation time 157517968551 ps
CPU time 85.53 seconds
Started Sep 24 06:35:43 AM UTC 24
Finished Sep 24 06:37:10 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590248108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.590248108
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/160.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/161.uart_fifo_reset.1209246523
Short name T185
Test name
Test status
Simulation time 69938596277 ps
CPU time 58.83 seconds
Started Sep 24 06:35:44 AM UTC 24
Finished Sep 24 06:36:44 AM UTC 24
Peak memory 209404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209246523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1209246523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/161.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/162.uart_fifo_reset.849636001
Short name T229
Test name
Test status
Simulation time 25567852338 ps
CPU time 17.01 seconds
Started Sep 24 06:35:44 AM UTC 24
Finished Sep 24 06:36:02 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849636001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.849636001
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/162.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/163.uart_fifo_reset.1587265288
Short name T1039
Test name
Test status
Simulation time 53637927896 ps
CPU time 17.08 seconds
Started Sep 24 06:35:47 AM UTC 24
Finished Sep 24 06:36:05 AM UTC 24
Peak memory 203836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587265288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1587265288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/163.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/164.uart_fifo_reset.293998593
Short name T1044
Test name
Test status
Simulation time 46621345044 ps
CPU time 24.97 seconds
Started Sep 24 06:35:48 AM UTC 24
Finished Sep 24 06:36:14 AM UTC 24
Peak memory 203856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293998593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.293998593
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/164.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/166.uart_fifo_reset.1101906987
Short name T252
Test name
Test status
Simulation time 12442244639 ps
CPU time 10.18 seconds
Started Sep 24 06:35:50 AM UTC 24
Finished Sep 24 06:36:01 AM UTC 24
Peak memory 209444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101906987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1101906987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/166.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/167.uart_fifo_reset.1207014975
Short name T1046
Test name
Test status
Simulation time 22763102366 ps
CPU time 23.2 seconds
Started Sep 24 06:35:53 AM UTC 24
Finished Sep 24 06:36:18 AM UTC 24
Peak memory 209084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207014975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1207014975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/167.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/169.uart_fifo_reset.2784761914
Short name T1054
Test name
Test status
Simulation time 34559198172 ps
CPU time 31.53 seconds
Started Sep 24 06:35:58 AM UTC 24
Finished Sep 24 06:36:31 AM UTC 24
Peak memory 208768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784761914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2784761914
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/169.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_alert_test.2693253038
Short name T488
Test name
Test status
Simulation time 12493289 ps
CPU time 0.89 seconds
Started Sep 24 06:11:02 AM UTC 24
Finished Sep 24 06:11:04 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693253038 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.2693253038
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_fifo_reset.3984412100
Short name T341
Test name
Test status
Simulation time 342193011246 ps
CPU time 76.23 seconds
Started Sep 24 06:10:31 AM UTC 24
Finished Sep 24 06:11:49 AM UTC 24
Peak memory 203836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984412100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3984412100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_intr.3895999234
Short name T104
Test name
Test status
Simulation time 20900387437 ps
CPU time 38.51 seconds
Started Sep 24 06:10:40 AM UTC 24
Finished Sep 24 06:11:20 AM UTC 24
Peak memory 207928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895999234 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.3895999234
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_long_xfer_wo_dly.1635405797
Short name T617
Test name
Test status
Simulation time 72513972411 ps
CPU time 457.17 seconds
Started Sep 24 06:11:01 AM UTC 24
Finished Sep 24 06:18:44 AM UTC 24
Peak memory 206076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635405797 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1635405797
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_loopback.4061390249
Short name T404
Test name
Test status
Simulation time 23585998 ps
CPU time 0.88 seconds
Started Sep 24 06:10:52 AM UTC 24
Finished Sep 24 06:10:54 AM UTC 24
Peak memory 205360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061390249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.uart_loopback.4061390249
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_noise_filter.854711639
Short name T422
Test name
Test status
Simulation time 30304285192 ps
CPU time 28.4 seconds
Started Sep 24 06:10:41 AM UTC 24
Finished Sep 24 06:11:10 AM UTC 24
Peak memory 209656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854711639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.854711639
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_perf.1807540516
Short name T547
Test name
Test status
Simulation time 18876295303 ps
CPU time 290.4 seconds
Started Sep 24 06:10:55 AM UTC 24
Finished Sep 24 06:15:50 AM UTC 24
Peak memory 203780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807540516 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1807540516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_rx_oversample.315008181
Short name T489
Test name
Test status
Simulation time 2942181249 ps
CPU time 29.18 seconds
Started Sep 24 06:10:35 AM UTC 24
Finished Sep 24 06:11:05 AM UTC 24
Peak memory 207876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315008181 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.315008181
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_rx_parity_err.3343757836
Short name T535
Test name
Test status
Simulation time 126496199844 ps
CPU time 262.79 seconds
Started Sep 24 06:10:46 AM UTC 24
Finished Sep 24 06:15:12 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343757836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3343757836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.2704881256
Short name T486
Test name
Test status
Simulation time 4570558763 ps
CPU time 15.67 seconds
Started Sep 24 06:10:44 AM UTC 24
Finished Sep 24 06:11:01 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704881256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2704881256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_smoke.708772354
Short name T481
Test name
Test status
Simulation time 717780503 ps
CPU time 2.98 seconds
Started Sep 24 06:10:29 AM UTC 24
Finished Sep 24 06:10:34 AM UTC 24
Peak memory 203984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708772354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.uart_smoke.708772354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_stress_all.518275838
Short name T750
Test name
Test status
Simulation time 60516594204 ps
CPU time 835.04 seconds
Started Sep 24 06:11:01 AM UTC 24
Finished Sep 24 06:25:07 AM UTC 24
Peak memory 213044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518275838 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.518275838
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_stress_all_with_rand_reset.1306415390
Short name T88
Test name
Test status
Simulation time 4335583274 ps
CPU time 57.91 seconds
Started Sep 24 06:11:01 AM UTC 24
Finished Sep 24 06:12:01 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1306415390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all
_with_rand_reset.1306415390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_tx_ovrd.1068233422
Short name T484
Test name
Test status
Simulation time 1526428890 ps
CPU time 2.8 seconds
Started Sep 24 06:10:47 AM UTC 24
Finished Sep 24 06:10:51 AM UTC 24
Peak memory 204056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068233422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1068233422
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/17.uart_tx_rx.558207759
Short name T314
Test name
Test status
Simulation time 41811595098 ps
CPU time 29.54 seconds
Started Sep 24 06:10:29 AM UTC 24
Finished Sep 24 06:11:01 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558207759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.558207759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/17.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/170.uart_fifo_reset.3557703523
Short name T1144
Test name
Test status
Simulation time 97323401544 ps
CPU time 227.83 seconds
Started Sep 24 06:35:58 AM UTC 24
Finished Sep 24 06:39:50 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557703523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3557703523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/170.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/171.uart_fifo_reset.2214984830
Short name T1070
Test name
Test status
Simulation time 135365641422 ps
CPU time 89.34 seconds
Started Sep 24 06:35:59 AM UTC 24
Finished Sep 24 06:37:31 AM UTC 24
Peak memory 209212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214984830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2214984830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/171.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/173.uart_fifo_reset.920123703
Short name T1074
Test name
Test status
Simulation time 98236032210 ps
CPU time 92.46 seconds
Started Sep 24 06:36:03 AM UTC 24
Finished Sep 24 06:37:37 AM UTC 24
Peak memory 204044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920123703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.920123703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/173.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/174.uart_fifo_reset.2974803744
Short name T1055
Test name
Test status
Simulation time 22031296910 ps
CPU time 30.52 seconds
Started Sep 24 06:36:03 AM UTC 24
Finished Sep 24 06:36:34 AM UTC 24
Peak memory 209584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974803744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2974803744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/174.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/176.uart_fifo_reset.4120471657
Short name T224
Test name
Test status
Simulation time 15919922213 ps
CPU time 69.69 seconds
Started Sep 24 06:36:04 AM UTC 24
Finished Sep 24 06:37:15 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120471657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.4120471657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/176.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/177.uart_fifo_reset.1361732386
Short name T237
Test name
Test status
Simulation time 124850573884 ps
CPU time 125.26 seconds
Started Sep 24 06:36:06 AM UTC 24
Finished Sep 24 06:38:13 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361732386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1361732386
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/177.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/178.uart_fifo_reset.3586076440
Short name T1096
Test name
Test status
Simulation time 43808448633 ps
CPU time 126.54 seconds
Started Sep 24 06:36:07 AM UTC 24
Finished Sep 24 06:38:16 AM UTC 24
Peak memory 203720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586076440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.3586076440
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/178.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/179.uart_fifo_reset.2528541719
Short name T186
Test name
Test status
Simulation time 73883720559 ps
CPU time 58.69 seconds
Started Sep 24 06:36:08 AM UTC 24
Finished Sep 24 06:37:08 AM UTC 24
Peak memory 204108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528541719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2528541719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/179.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_alert_test.3826055067
Short name T496
Test name
Test status
Simulation time 29781678 ps
CPU time 0.84 seconds
Started Sep 24 06:11:46 AM UTC 24
Finished Sep 24 06:11:47 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826055067 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3826055067
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_fifo_full.3623507308
Short name T147
Test name
Test status
Simulation time 26719954619 ps
CPU time 25.12 seconds
Started Sep 24 06:11:06 AM UTC 24
Finished Sep 24 06:11:32 AM UTC 24
Peak memory 203712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623507308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3623507308
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_fifo_overflow.442174799
Short name T515
Test name
Test status
Simulation time 98810653644 ps
CPU time 166.64 seconds
Started Sep 24 06:11:07 AM UTC 24
Finished Sep 24 06:13:56 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442174799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.442174799
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_fifo_reset.3186132187
Short name T362
Test name
Test status
Simulation time 180599883434 ps
CPU time 88.95 seconds
Started Sep 24 06:11:10 AM UTC 24
Finished Sep 24 06:12:41 AM UTC 24
Peak memory 209112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186132187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3186132187
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_intr.3366121634
Short name T108
Test name
Test status
Simulation time 43971035767 ps
CPU time 28.31 seconds
Started Sep 24 06:11:11 AM UTC 24
Finished Sep 24 06:11:40 AM UTC 24
Peak memory 209656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366121634 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3366121634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_long_xfer_wo_dly.1803686411
Short name T670
Test name
Test status
Simulation time 112680775725 ps
CPU time 596.61 seconds
Started Sep 24 06:11:32 AM UTC 24
Finished Sep 24 06:21:36 AM UTC 24
Peak memory 212728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803686411 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1803686411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_loopback.3314503189
Short name T495
Test name
Test status
Simulation time 5185502113 ps
CPU time 17.93 seconds
Started Sep 24 06:11:26 AM UTC 24
Finished Sep 24 06:11:45 AM UTC 24
Peak memory 204096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314503189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3314503189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_noise_filter.3919848318
Short name T374
Test name
Test status
Simulation time 181053292089 ps
CPU time 136.88 seconds
Started Sep 24 06:11:21 AM UTC 24
Finished Sep 24 06:13:40 AM UTC 24
Peak memory 209624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919848318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3919848318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_perf.2454812392
Short name T573
Test name
Test status
Simulation time 19276831173 ps
CPU time 328.27 seconds
Started Sep 24 06:11:30 AM UTC 24
Finished Sep 24 06:17:04 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454812392 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2454812392
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_rx_oversample.2440033312
Short name T491
Test name
Test status
Simulation time 5724311451 ps
CPU time 10.65 seconds
Started Sep 24 06:11:10 AM UTC 24
Finished Sep 24 06:11:21 AM UTC 24
Peak memory 203760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440033312 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2440033312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_rx_parity_err.412428292
Short name T158
Test name
Test status
Simulation time 316954712201 ps
CPU time 29.47 seconds
Started Sep 24 06:11:22 AM UTC 24
Finished Sep 24 06:11:53 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412428292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.412428292
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_rx_start_bit_filter.321800584
Short name T494
Test name
Test status
Simulation time 45345951492 ps
CPU time 22.75 seconds
Started Sep 24 06:11:21 AM UTC 24
Finished Sep 24 06:11:45 AM UTC 24
Peak memory 203584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321800584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.321800584
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_smoke.3966964223
Short name T492
Test name
Test status
Simulation time 6168558899 ps
CPU time 21.39 seconds
Started Sep 24 06:11:02 AM UTC 24
Finished Sep 24 06:11:25 AM UTC 24
Peak memory 204116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966964223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_smoke.3966964223
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_stress_all.4192355476
Short name T423
Test name
Test status
Simulation time 141452861738 ps
CPU time 85.56 seconds
Started Sep 24 06:11:42 AM UTC 24
Finished Sep 24 06:13:09 AM UTC 24
Peak memory 203780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192355476 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.4192355476
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_stress_all_with_rand_reset.477235050
Short name T110
Test name
Test status
Simulation time 9543305913 ps
CPU time 61.15 seconds
Started Sep 24 06:11:35 AM UTC 24
Finished Sep 24 06:12:37 AM UTC 24
Peak memory 218556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=477235050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all_
with_rand_reset.477235050
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_tx_ovrd.1410095743
Short name T493
Test name
Test status
Simulation time 1604917822 ps
CPU time 4.39 seconds
Started Sep 24 06:11:24 AM UTC 24
Finished Sep 24 06:11:30 AM UTC 24
Peak memory 203712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410095743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1410095743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/18.uart_tx_rx.3156156567
Short name T356
Test name
Test status
Simulation time 14350673041 ps
CPU time 13.81 seconds
Started Sep 24 06:11:06 AM UTC 24
Finished Sep 24 06:11:20 AM UTC 24
Peak memory 207676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156156567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3156156567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/18.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/181.uart_fifo_reset.571773942
Short name T1075
Test name
Test status
Simulation time 58648920917 ps
CPU time 80.03 seconds
Started Sep 24 06:36:15 AM UTC 24
Finished Sep 24 06:37:37 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571773942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.571773942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/181.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/182.uart_fifo_reset.1883258126
Short name T1059
Test name
Test status
Simulation time 54283538152 ps
CPU time 45.99 seconds
Started Sep 24 06:36:15 AM UTC 24
Finished Sep 24 06:37:03 AM UTC 24
Peak memory 204040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883258126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1883258126
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/182.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/184.uart_fifo_reset.4025253093
Short name T1094
Test name
Test status
Simulation time 145972193234 ps
CPU time 112.53 seconds
Started Sep 24 06:36:18 AM UTC 24
Finished Sep 24 06:38:13 AM UTC 24
Peak memory 209592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025253093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.4025253093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/184.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/185.uart_fifo_reset.2242970851
Short name T1106
Test name
Test status
Simulation time 271275025048 ps
CPU time 128.52 seconds
Started Sep 24 06:36:19 AM UTC 24
Finished Sep 24 06:38:30 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242970851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2242970851
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/185.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/187.uart_fifo_reset.2393238985
Short name T1178
Test name
Test status
Simulation time 312354146877 ps
CPU time 669.15 seconds
Started Sep 24 06:36:20 AM UTC 24
Finished Sep 24 06:47:38 AM UTC 24
Peak memory 207296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393238985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2393238985
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/187.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/188.uart_fifo_reset.3340017845
Short name T1097
Test name
Test status
Simulation time 127635291069 ps
CPU time 114.79 seconds
Started Sep 24 06:36:21 AM UTC 24
Finished Sep 24 06:38:17 AM UTC 24
Peak memory 203724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340017845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3340017845
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/188.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/189.uart_fifo_reset.3735247407
Short name T1120
Test name
Test status
Simulation time 149377703218 ps
CPU time 149.32 seconds
Started Sep 24 06:36:22 AM UTC 24
Finished Sep 24 06:38:53 AM UTC 24
Peak memory 203724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735247407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3735247407
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/189.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_alert_test.3818350005
Short name T502
Test name
Test status
Simulation time 26622025 ps
CPU time 0.83 seconds
Started Sep 24 06:12:32 AM UTC 24
Finished Sep 24 06:12:34 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818350005 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3818350005
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_fifo_reset.2093684203
Short name T194
Test name
Test status
Simulation time 144543386173 ps
CPU time 324.5 seconds
Started Sep 24 06:11:50 AM UTC 24
Finished Sep 24 06:17:19 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093684203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2093684203
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_long_xfer_wo_dly.4223886145
Short name T621
Test name
Test status
Simulation time 81998452137 ps
CPU time 389.7 seconds
Started Sep 24 06:12:17 AM UTC 24
Finished Sep 24 06:18:52 AM UTC 24
Peak memory 209324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223886145 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.4223886145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_loopback.2198716475
Short name T500
Test name
Test status
Simulation time 1486917375 ps
CPU time 2 seconds
Started Sep 24 06:12:13 AM UTC 24
Finished Sep 24 06:12:16 AM UTC 24
Peak memory 205360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198716475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2198716475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_noise_filter.2708942703
Short name T427
Test name
Test status
Simulation time 13919576405 ps
CPU time 54.85 seconds
Started Sep 24 06:12:01 AM UTC 24
Finished Sep 24 06:12:58 AM UTC 24
Peak memory 209940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708942703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.2708942703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_perf.4275027672
Short name T607
Test name
Test status
Simulation time 5907968673 ps
CPU time 356.52 seconds
Started Sep 24 06:12:15 AM UTC 24
Finished Sep 24 06:18:16 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275027672 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.4275027672
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_rx_oversample.202093406
Short name T499
Test name
Test status
Simulation time 3569161185 ps
CPU time 10.92 seconds
Started Sep 24 06:11:53 AM UTC 24
Finished Sep 24 06:12:05 AM UTC 24
Peak memory 208268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202093406 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.202093406
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_rx_parity_err.3228104950
Short name T505
Test name
Test status
Simulation time 86497263604 ps
CPU time 50.72 seconds
Started Sep 24 06:12:08 AM UTC 24
Finished Sep 24 06:13:01 AM UTC 24
Peak memory 204104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228104950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3228104950
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_rx_start_bit_filter.2823569518
Short name T513
Test name
Test status
Simulation time 47560314476 ps
CPU time 104.44 seconds
Started Sep 24 06:12:06 AM UTC 24
Finished Sep 24 06:13:53 AM UTC 24
Peak memory 203896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823569518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2823569518
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_smoke.812895473
Short name T497
Test name
Test status
Simulation time 734559411 ps
CPU time 2.41 seconds
Started Sep 24 06:11:46 AM UTC 24
Finished Sep 24 06:11:49 AM UTC 24
Peak memory 203728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812895473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.uart_smoke.812895473
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_stress_all_with_rand_reset.539325528
Short name T397
Test name
Test status
Simulation time 19250614560 ps
CPU time 84.54 seconds
Started Sep 24 06:12:27 AM UTC 24
Finished Sep 24 06:13:54 AM UTC 24
Peak memory 218304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=539325528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all_
with_rand_reset.539325528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_tx_ovrd.3682686047
Short name T501
Test name
Test status
Simulation time 6228348567 ps
CPU time 15.34 seconds
Started Sep 24 06:12:11 AM UTC 24
Finished Sep 24 06:12:28 AM UTC 24
Peak memory 203980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682686047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3682686047
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/19.uart_tx_rx.535831125
Short name T271
Test name
Test status
Simulation time 100197042010 ps
CPU time 36.75 seconds
Started Sep 24 06:11:48 AM UTC 24
Finished Sep 24 06:12:26 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535831125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.535831125
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/19.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/190.uart_fifo_reset.1244746738
Short name T1067
Test name
Test status
Simulation time 134703362556 ps
CPU time 63.32 seconds
Started Sep 24 06:36:22 AM UTC 24
Finished Sep 24 06:37:27 AM UTC 24
Peak memory 209308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244746738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1244746738
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/190.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/192.uart_fifo_reset.903679811
Short name T1171
Test name
Test status
Simulation time 54225431011 ps
CPU time 360.15 seconds
Started Sep 24 06:36:26 AM UTC 24
Finished Sep 24 06:42:31 AM UTC 24
Peak memory 212660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903679811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.903679811
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/192.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/193.uart_fifo_reset.3750594082
Short name T1092
Test name
Test status
Simulation time 78536289253 ps
CPU time 103.47 seconds
Started Sep 24 06:36:26 AM UTC 24
Finished Sep 24 06:38:11 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750594082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3750594082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/193.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/194.uart_fifo_reset.3253732413
Short name T1064
Test name
Test status
Simulation time 166791145014 ps
CPU time 45.51 seconds
Started Sep 24 06:36:28 AM UTC 24
Finished Sep 24 06:37:15 AM UTC 24
Peak memory 209580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253732413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3253732413
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/194.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/195.uart_fifo_reset.1480697213
Short name T1173
Test name
Test status
Simulation time 118043507476 ps
CPU time 440.16 seconds
Started Sep 24 06:36:31 AM UTC 24
Finished Sep 24 06:43:57 AM UTC 24
Peak memory 207440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480697213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1480697213
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/195.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/196.uart_fifo_reset.3525173902
Short name T234
Test name
Test status
Simulation time 153664135714 ps
CPU time 73.21 seconds
Started Sep 24 06:36:32 AM UTC 24
Finished Sep 24 06:37:47 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525173902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3525173902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/196.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/197.uart_fifo_reset.531806194
Short name T238
Test name
Test status
Simulation time 254417054431 ps
CPU time 119.56 seconds
Started Sep 24 06:36:35 AM UTC 24
Finished Sep 24 06:38:37 AM UTC 24
Peak memory 203976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531806194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.531806194
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/197.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/198.uart_fifo_reset.3405420549
Short name T1135
Test name
Test status
Simulation time 147182244341 ps
CPU time 173.05 seconds
Started Sep 24 06:36:39 AM UTC 24
Finished Sep 24 06:39:35 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405420549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.3405420549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/198.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1900613266
Short name T154
Test name
Test status
Simulation time 43220261392 ps
CPU time 50.24 seconds
Started Sep 24 06:36:41 AM UTC 24
Finished Sep 24 06:37:33 AM UTC 24
Peak memory 203856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900613266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1900613266
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/199.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_alert_test.1733522942
Short name T38
Test name
Test status
Simulation time 59671899 ps
CPU time 0.86 seconds
Started Sep 24 06:00:48 AM UTC 24
Finished Sep 24 06:00:50 AM UTC 24
Peak memory 203256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733522942 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.1733522942
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_fifo_full.4092257902
Short name T115
Test name
Test status
Simulation time 24823475407 ps
CPU time 59.57 seconds
Started Sep 24 06:00:08 AM UTC 24
Finished Sep 24 06:01:10 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092257902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.4092257902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_intr.3674605402
Short name T391
Test name
Test status
Simulation time 6985211747 ps
CPU time 26.73 seconds
Started Sep 24 06:00:23 AM UTC 24
Finished Sep 24 06:00:51 AM UTC 24
Peak memory 205680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674605402 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3674605402
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_loopback.621700561
Short name T26
Test name
Test status
Simulation time 13215300912 ps
CPU time 10.05 seconds
Started Sep 24 06:00:31 AM UTC 24
Finished Sep 24 06:00:43 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621700561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.uart_loopback.621700561
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_noise_filter.2162454219
Short name T309
Test name
Test status
Simulation time 97130484417 ps
CPU time 279.44 seconds
Started Sep 24 06:00:25 AM UTC 24
Finished Sep 24 06:05:08 AM UTC 24
Peak memory 209604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162454219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2162454219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_perf.872938944
Short name T277
Test name
Test status
Simulation time 5638464942 ps
CPU time 151.65 seconds
Started Sep 24 06:00:33 AM UTC 24
Finished Sep 24 06:03:08 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872938944 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.872938944
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_rx_oversample.3358381718
Short name T17
Test name
Test status
Simulation time 7420390908 ps
CPU time 21.64 seconds
Started Sep 24 06:00:15 AM UTC 24
Finished Sep 24 06:00:38 AM UTC 24
Peak memory 207948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358381718 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3358381718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.3835685428
Short name T30
Test name
Test status
Simulation time 23126370860 ps
CPU time 66.37 seconds
Started Sep 24 06:00:27 AM UTC 24
Finished Sep 24 06:01:35 AM UTC 24
Peak memory 208444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835685428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3835685428
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.32577090
Short name T95
Test name
Test status
Simulation time 1794513707 ps
CPU time 7.18 seconds
Started Sep 24 06:00:26 AM UTC 24
Finished Sep 24 06:00:35 AM UTC 24
Peak memory 203524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32577090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.32577090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_sec_cm.191073903
Short name T39
Test name
Test status
Simulation time 266621602 ps
CPU time 1.95 seconds
Started Sep 24 06:00:44 AM UTC 24
Finished Sep 24 06:00:47 AM UTC 24
Peak memory 237812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191073903 -assert nopostproc +UVM_TESTNAME=uart_ba
se_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.191073903
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_smoke.4194888007
Short name T280
Test name
Test status
Simulation time 490520982 ps
CPU time 4 seconds
Started Sep 24 06:00:00 AM UTC 24
Finished Sep 24 06:00:05 AM UTC 24
Peak memory 204056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194888007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_smoke.4194888007
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.3817772046
Short name T32
Test name
Test status
Simulation time 5911258536 ps
CPU time 20.77 seconds
Started Sep 24 06:00:39 AM UTC 24
Finished Sep 24 06:01:01 AM UTC 24
Peak memory 209440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3817772046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all_
with_rand_reset.3817772046
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.82563797
Short name T23
Test name
Test status
Simulation time 613128369 ps
CPU time 2.51 seconds
Started Sep 24 06:00:29 AM UTC 24
Finished Sep 24 06:00:33 AM UTC 24
Peak memory 204052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82563797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.82563797
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/2.uart_tx_rx.3519415560
Short name T33
Test name
Test status
Simulation time 60298182294 ps
CPU time 36.72 seconds
Started Sep 24 06:00:00 AM UTC 24
Finished Sep 24 06:00:38 AM UTC 24
Peak memory 209584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519415560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3519415560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/2.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_alert_test.3588524023
Short name T509
Test name
Test status
Simulation time 37154462 ps
CPU time 0.86 seconds
Started Sep 24 06:13:06 AM UTC 24
Finished Sep 24 06:13:08 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588524023 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3588524023
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_fifo_full.2491338333
Short name T148
Test name
Test status
Simulation time 36826765159 ps
CPU time 23.26 seconds
Started Sep 24 06:12:38 AM UTC 24
Finished Sep 24 06:13:03 AM UTC 24
Peak memory 209392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491338333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2491338333
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_fifo_overflow.67801092
Short name T335
Test name
Test status
Simulation time 139742667728 ps
CPU time 68.21 seconds
Started Sep 24 06:12:39 AM UTC 24
Finished Sep 24 06:13:49 AM UTC 24
Peak memory 209444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67801092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.67801092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_fifo_reset.1203390514
Short name T510
Test name
Test status
Simulation time 56491114202 ps
CPU time 29.12 seconds
Started Sep 24 06:12:39 AM UTC 24
Finished Sep 24 06:13:10 AM UTC 24
Peak memory 209068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203390514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.1203390514
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_intr.1272515210
Short name T109
Test name
Test status
Simulation time 29098474812 ps
CPU time 95.13 seconds
Started Sep 24 06:12:47 AM UTC 24
Finished Sep 24 06:14:25 AM UTC 24
Peak memory 209180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272515210 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1272515210
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_long_xfer_wo_dly.3912174900
Short name T938
Test name
Test status
Simulation time 148879887559 ps
CPU time 1127.42 seconds
Started Sep 24 06:13:04 AM UTC 24
Finished Sep 24 06:32:05 AM UTC 24
Peak memory 212580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912174900 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3912174900
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_loopback.2413747755
Short name T508
Test name
Test status
Simulation time 667507813 ps
CPU time 1.75 seconds
Started Sep 24 06:13:03 AM UTC 24
Finished Sep 24 06:13:06 AM UTC 24
Peak memory 203376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413747755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2413747755
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_noise_filter.3431363427
Short name T528
Test name
Test status
Simulation time 30117963690 ps
CPU time 118.87 seconds
Started Sep 24 06:12:59 AM UTC 24
Finished Sep 24 06:15:00 AM UTC 24
Peak memory 208976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431363427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.3431363427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_perf.3856259310
Short name T421
Test name
Test status
Simulation time 11509056371 ps
CPU time 146.06 seconds
Started Sep 24 06:13:04 AM UTC 24
Finished Sep 24 06:15:33 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856259310 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3856259310
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_rx_oversample.2910305301
Short name T504
Test name
Test status
Simulation time 4109565795 ps
CPU time 16.2 seconds
Started Sep 24 06:12:41 AM UTC 24
Finished Sep 24 06:12:59 AM UTC 24
Peak memory 207872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910305301 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2910305301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_rx_parity_err.3234333083
Short name T420
Test name
Test status
Simulation time 7429453200 ps
CPU time 25.89 seconds
Started Sep 24 06:13:00 AM UTC 24
Finished Sep 24 06:13:27 AM UTC 24
Peak memory 209264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234333083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3234333083
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_rx_start_bit_filter.2398789654
Short name T506
Test name
Test status
Simulation time 722686590 ps
CPU time 1.55 seconds
Started Sep 24 06:13:00 AM UTC 24
Finished Sep 24 06:13:02 AM UTC 24
Peak memory 203376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398789654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2398789654
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_smoke.1086087524
Short name T503
Test name
Test status
Simulation time 670970977 ps
CPU time 2.24 seconds
Started Sep 24 06:12:35 AM UTC 24
Finished Sep 24 06:12:39 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086087524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_smoke.1086087524
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_stress_all.3395912181
Short name T150
Test name
Test status
Simulation time 172768789113 ps
CPU time 51.35 seconds
Started Sep 24 06:13:06 AM UTC 24
Finished Sep 24 06:13:59 AM UTC 24
Peak memory 218508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395912181 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3395912181
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_stress_all_with_rand_reset.3951405336
Short name T89
Test name
Test status
Simulation time 6535154626 ps
CPU time 31.4 seconds
Started Sep 24 06:13:06 AM UTC 24
Finished Sep 24 06:13:39 AM UTC 24
Peak memory 224704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3951405336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all
_with_rand_reset.3951405336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_tx_ovrd.1874373457
Short name T507
Test name
Test status
Simulation time 1596860089 ps
CPU time 2.49 seconds
Started Sep 24 06:13:02 AM UTC 24
Finished Sep 24 06:13:05 AM UTC 24
Peak memory 203652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874373457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.1874373457
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/20.uart_tx_rx.2983712297
Short name T367
Test name
Test status
Simulation time 16947925015 ps
CPU time 22.46 seconds
Started Sep 24 06:12:35 AM UTC 24
Finished Sep 24 06:12:59 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983712297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2983712297
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/20.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/200.uart_fifo_reset.668664789
Short name T1088
Test name
Test status
Simulation time 38259433146 ps
CPU time 73.71 seconds
Started Sep 24 06:36:43 AM UTC 24
Finished Sep 24 06:37:58 AM UTC 24
Peak memory 209232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668664789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.668664789
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/200.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/201.uart_fifo_reset.2054843619
Short name T1082
Test name
Test status
Simulation time 38007589157 ps
CPU time 61.64 seconds
Started Sep 24 06:36:45 AM UTC 24
Finished Sep 24 06:37:48 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054843619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2054843619
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/201.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/202.uart_fifo_reset.2039765462
Short name T1077
Test name
Test status
Simulation time 39448642895 ps
CPU time 51.25 seconds
Started Sep 24 06:36:47 AM UTC 24
Finished Sep 24 06:37:39 AM UTC 24
Peak memory 208884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039765462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2039765462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/202.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/203.uart_fifo_reset.2104755453
Short name T1161
Test name
Test status
Simulation time 135916786225 ps
CPU time 245.45 seconds
Started Sep 24 06:36:47 AM UTC 24
Finished Sep 24 06:40:56 AM UTC 24
Peak memory 209364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104755453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2104755453
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/203.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/205.uart_fifo_reset.3938023626
Short name T256
Test name
Test status
Simulation time 165776924402 ps
CPU time 71.07 seconds
Started Sep 24 06:36:52 AM UTC 24
Finished Sep 24 06:38:05 AM UTC 24
Peak memory 203984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938023626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3938023626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/205.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/206.uart_fifo_reset.2445925498
Short name T1065
Test name
Test status
Simulation time 20026460926 ps
CPU time 25.81 seconds
Started Sep 24 06:36:53 AM UTC 24
Finished Sep 24 06:37:20 AM UTC 24
Peak memory 209248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445925498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.2445925498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/206.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/207.uart_fifo_reset.1538777881
Short name T1087
Test name
Test status
Simulation time 19517945231 ps
CPU time 53.91 seconds
Started Sep 24 06:37:02 AM UTC 24
Finished Sep 24 06:37:58 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538777881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1538777881
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/207.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/208.uart_fifo_reset.2577145760
Short name T1132
Test name
Test status
Simulation time 113549801771 ps
CPU time 146.44 seconds
Started Sep 24 06:37:03 AM UTC 24
Finished Sep 24 06:39:32 AM UTC 24
Peak memory 209208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577145760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2577145760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/208.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/209.uart_fifo_reset.4044781501
Short name T1068
Test name
Test status
Simulation time 42098408813 ps
CPU time 23.24 seconds
Started Sep 24 06:37:03 AM UTC 24
Finished Sep 24 06:37:28 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044781501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.4044781501
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/209.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_alert_test.2591261712
Short name T516
Test name
Test status
Simulation time 32241079 ps
CPU time 0.85 seconds
Started Sep 24 06:13:56 AM UTC 24
Finished Sep 24 06:13:58 AM UTC 24
Peak memory 203312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591261712 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2591261712
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_fifo_full.3395902699
Short name T365
Test name
Test status
Simulation time 303112923707 ps
CPU time 29.78 seconds
Started Sep 24 06:13:11 AM UTC 24
Finished Sep 24 06:13:42 AM UTC 24
Peak memory 209312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395902699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3395902699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_fifo_overflow.3902892341
Short name T383
Test name
Test status
Simulation time 115181503932 ps
CPU time 47.9 seconds
Started Sep 24 06:13:22 AM UTC 24
Finished Sep 24 06:14:12 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902892341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3902892341
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_fifo_reset.3906763068
Short name T182
Test name
Test status
Simulation time 28573403936 ps
CPU time 61.76 seconds
Started Sep 24 06:13:26 AM UTC 24
Finished Sep 24 06:14:30 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906763068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3906763068
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_intr.3256224781
Short name T602
Test name
Test status
Simulation time 165013340820 ps
CPU time 265.29 seconds
Started Sep 24 06:13:34 AM UTC 24
Finished Sep 24 06:18:02 AM UTC 24
Peak memory 205620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256224781 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3256224781
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_long_xfer_wo_dly.2232329734
Short name T551
Test name
Test status
Simulation time 48692391713 ps
CPU time 131.01 seconds
Started Sep 24 06:13:53 AM UTC 24
Finished Sep 24 06:16:07 AM UTC 24
Peak memory 209520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232329734 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2232329734
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_loopback.1146257773
Short name T514
Test name
Test status
Simulation time 7722507930 ps
CPU time 3.55 seconds
Started Sep 24 06:13:50 AM UTC 24
Finished Sep 24 06:13:55 AM UTC 24
Peak memory 207952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146257773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1146257773
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_noise_filter.3597552257
Short name T412
Test name
Test status
Simulation time 161989943004 ps
CPU time 167.21 seconds
Started Sep 24 06:13:40 AM UTC 24
Finished Sep 24 06:16:30 AM UTC 24
Peak memory 218704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597552257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.3597552257
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_perf.3015788872
Short name T520
Test name
Test status
Simulation time 567497124 ps
CPU time 36.75 seconds
Started Sep 24 06:13:50 AM UTC 24
Finished Sep 24 06:14:28 AM UTC 24
Peak memory 203704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015788872 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3015788872
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_rx_oversample.1549311912
Short name T522
Test name
Test status
Simulation time 5077759462 ps
CPU time 58.9 seconds
Started Sep 24 06:13:28 AM UTC 24
Finished Sep 24 06:14:28 AM UTC 24
Peak memory 207944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549311912 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1549311912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_rx_parity_err.1099535016
Short name T381
Test name
Test status
Simulation time 131686377631 ps
CPU time 115.27 seconds
Started Sep 24 06:13:41 AM UTC 24
Finished Sep 24 06:15:38 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099535016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1099535016
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_rx_start_bit_filter.4193574067
Short name T540
Test name
Test status
Simulation time 42118557197 ps
CPU time 101.67 seconds
Started Sep 24 06:13:41 AM UTC 24
Finished Sep 24 06:15:25 AM UTC 24
Peak memory 203704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193574067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.4193574067
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_smoke.1040931544
Short name T372
Test name
Test status
Simulation time 5476573323 ps
CPU time 29.39 seconds
Started Sep 24 06:13:09 AM UTC 24
Finished Sep 24 06:13:40 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040931544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1040931544
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_stress_all.1072422710
Short name T564
Test name
Test status
Simulation time 107995617544 ps
CPU time 154.81 seconds
Started Sep 24 06:13:55 AM UTC 24
Finished Sep 24 06:16:33 AM UTC 24
Peak memory 203840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072422710 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1072422710
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_stress_all_with_rand_reset.523142636
Short name T90
Test name
Test status
Simulation time 3264622896 ps
CPU time 34.68 seconds
Started Sep 24 06:13:54 AM UTC 24
Finished Sep 24 06:14:31 AM UTC 24
Peak memory 209396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=523142636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all_
with_rand_reset.523142636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_tx_ovrd.2438581887
Short name T512
Test name
Test status
Simulation time 661735476 ps
CPU time 5.66 seconds
Started Sep 24 06:13:43 AM UTC 24
Finished Sep 24 06:13:50 AM UTC 24
Peak memory 203728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438581887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2438581887
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/21.uart_tx_rx.3709826898
Short name T517
Test name
Test status
Simulation time 14984305845 ps
CPU time 48.98 seconds
Started Sep 24 06:13:10 AM UTC 24
Finished Sep 24 06:14:01 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709826898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3709826898
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/21.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/210.uart_fifo_reset.1001803148
Short name T245
Test name
Test status
Simulation time 33599825648 ps
CPU time 48.18 seconds
Started Sep 24 06:37:05 AM UTC 24
Finished Sep 24 06:37:55 AM UTC 24
Peak memory 209140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001803148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1001803148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/210.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/211.uart_fifo_reset.632540670
Short name T1078
Test name
Test status
Simulation time 26067527008 ps
CPU time 35.04 seconds
Started Sep 24 06:37:07 AM UTC 24
Finished Sep 24 06:37:44 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632540670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.632540670
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/211.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/212.uart_fifo_reset.2242953135
Short name T1081
Test name
Test status
Simulation time 61093535525 ps
CPU time 35.56 seconds
Started Sep 24 06:37:08 AM UTC 24
Finished Sep 24 06:37:46 AM UTC 24
Peak memory 209260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242953135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.2242953135
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/212.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/214.uart_fifo_reset.2333178804
Short name T1105
Test name
Test status
Simulation time 74766599130 ps
CPU time 77.12 seconds
Started Sep 24 06:37:10 AM UTC 24
Finished Sep 24 06:38:29 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333178804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2333178804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/214.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/215.uart_fifo_reset.753104676
Short name T1079
Test name
Test status
Simulation time 11817900075 ps
CPU time 32.13 seconds
Started Sep 24 06:37:11 AM UTC 24
Finished Sep 24 06:37:45 AM UTC 24
Peak memory 209456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753104676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.753104676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/215.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/217.uart_fifo_reset.3133195162
Short name T1098
Test name
Test status
Simulation time 19492499242 ps
CPU time 61.44 seconds
Started Sep 24 06:37:16 AM UTC 24
Finished Sep 24 06:38:19 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133195162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3133195162
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/217.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/218.uart_fifo_reset.1140914912
Short name T1073
Test name
Test status
Simulation time 20775640639 ps
CPU time 15.57 seconds
Started Sep 24 06:37:20 AM UTC 24
Finished Sep 24 06:37:37 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140914912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.1140914912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/218.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/219.uart_fifo_reset.1154226391
Short name T1095
Test name
Test status
Simulation time 113689620297 ps
CPU time 51.61 seconds
Started Sep 24 06:37:21 AM UTC 24
Finished Sep 24 06:38:14 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154226391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1154226391
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/219.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_alert_test.3920463383
Short name T525
Test name
Test status
Simulation time 24567207 ps
CPU time 0.85 seconds
Started Sep 24 06:14:51 AM UTC 24
Finished Sep 24 06:14:52 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920463383 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.3920463383
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_fifo_full.3694844925
Short name T165
Test name
Test status
Simulation time 108399460421 ps
CPU time 54.37 seconds
Started Sep 24 06:14:01 AM UTC 24
Finished Sep 24 06:14:58 AM UTC 24
Peak memory 204104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694844925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3694844925
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_fifo_overflow.586785743
Short name T610
Test name
Test status
Simulation time 161997725823 ps
CPU time 256.36 seconds
Started Sep 24 06:14:03 AM UTC 24
Finished Sep 24 06:18:23 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586785743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.586785743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_fifo_reset.3962831191
Short name T417
Test name
Test status
Simulation time 34089765402 ps
CPU time 52.26 seconds
Started Sep 24 06:14:13 AM UTC 24
Finished Sep 24 06:15:07 AM UTC 24
Peak memory 204044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962831191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3962831191
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_intr.2142864410
Short name T521
Test name
Test status
Simulation time 7517859038 ps
CPU time 7.39 seconds
Started Sep 24 06:14:20 AM UTC 24
Finished Sep 24 06:14:28 AM UTC 24
Peak memory 207928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142864410 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2142864410
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_long_xfer_wo_dly.1202251539
Short name T645
Test name
Test status
Simulation time 44970908530 ps
CPU time 348.1 seconds
Started Sep 24 06:14:32 AM UTC 24
Finished Sep 24 06:20:25 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202251539 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1202251539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_loopback.3332420128
Short name T526
Test name
Test status
Simulation time 6436971523 ps
CPU time 20.06 seconds
Started Sep 24 06:14:31 AM UTC 24
Finished Sep 24 06:14:52 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332420128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3332420128
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_perf.1345458892
Short name T533
Test name
Test status
Simulation time 12577009197 ps
CPU time 38.55 seconds
Started Sep 24 06:14:31 AM UTC 24
Finished Sep 24 06:15:11 AM UTC 24
Peak memory 203780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345458892 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.1345458892
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_rx_oversample.2217085255
Short name T530
Test name
Test status
Simulation time 7403914400 ps
CPU time 41.42 seconds
Started Sep 24 06:14:20 AM UTC 24
Finished Sep 24 06:15:03 AM UTC 24
Peak memory 207880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217085255 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2217085255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_rx_parity_err.2698753000
Short name T538
Test name
Test status
Simulation time 119978917336 ps
CPU time 50.36 seconds
Started Sep 24 06:14:29 AM UTC 24
Finished Sep 24 06:15:21 AM UTC 24
Peak memory 209312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698753000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2698753000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_rx_start_bit_filter.3772242795
Short name T524
Test name
Test status
Simulation time 482273652 ps
CPU time 2.5 seconds
Started Sep 24 06:14:29 AM UTC 24
Finished Sep 24 06:14:33 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772242795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3772242795
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_smoke.1292498636
Short name T518
Test name
Test status
Simulation time 329238095 ps
CPU time 1.44 seconds
Started Sep 24 06:13:59 AM UTC 24
Finished Sep 24 06:14:02 AM UTC 24
Peak memory 203332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292498636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1292498636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_tx_ovrd.1153258980
Short name T523
Test name
Test status
Simulation time 6967291055 ps
CPU time 1.73 seconds
Started Sep 24 06:14:29 AM UTC 24
Finished Sep 24 06:14:32 AM UTC 24
Peak memory 207348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153258980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.1153258980
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/22.uart_tx_rx.3412165077
Short name T572
Test name
Test status
Simulation time 90523991183 ps
CPU time 176.05 seconds
Started Sep 24 06:13:59 AM UTC 24
Finished Sep 24 06:16:59 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412165077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3412165077
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/22.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/221.uart_fifo_reset.2124435901
Short name T1150
Test name
Test status
Simulation time 99648723411 ps
CPU time 148.48 seconds
Started Sep 24 06:37:27 AM UTC 24
Finished Sep 24 06:39:59 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124435901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2124435901
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/221.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/222.uart_fifo_reset.3380199659
Short name T1104
Test name
Test status
Simulation time 34207855402 ps
CPU time 58.56 seconds
Started Sep 24 06:37:28 AM UTC 24
Finished Sep 24 06:38:29 AM UTC 24
Peak memory 209604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380199659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3380199659
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/222.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/223.uart_fifo_reset.1020849993
Short name T1085
Test name
Test status
Simulation time 45112832904 ps
CPU time 22.42 seconds
Started Sep 24 06:37:31 AM UTC 24
Finished Sep 24 06:37:55 AM UTC 24
Peak memory 203644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020849993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1020849993
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/223.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/225.uart_fifo_reset.3056170858
Short name T1080
Test name
Test status
Simulation time 79848263348 ps
CPU time 11.38 seconds
Started Sep 24 06:37:33 AM UTC 24
Finished Sep 24 06:37:46 AM UTC 24
Peak memory 209100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056170858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3056170858
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/225.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/226.uart_fifo_reset.2762284096
Short name T1093
Test name
Test status
Simulation time 17510917150 ps
CPU time 35.95 seconds
Started Sep 24 06:37:35 AM UTC 24
Finished Sep 24 06:38:12 AM UTC 24
Peak memory 208764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762284096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2762284096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/226.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/227.uart_fifo_reset.858104660
Short name T1154
Test name
Test status
Simulation time 325807726975 ps
CPU time 153.14 seconds
Started Sep 24 06:37:36 AM UTC 24
Finished Sep 24 06:40:11 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858104660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.858104660
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/227.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/229.uart_fifo_reset.2980356701
Short name T1083
Test name
Test status
Simulation time 41186890794 ps
CPU time 9.96 seconds
Started Sep 24 06:37:38 AM UTC 24
Finished Sep 24 06:37:49 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980356701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2980356701
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/229.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_alert_test.3360059666
Short name T536
Test name
Test status
Simulation time 44930165 ps
CPU time 0.84 seconds
Started Sep 24 06:15:13 AM UTC 24
Finished Sep 24 06:15:15 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360059666 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3360059666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_fifo_full.1688357927
Short name T388
Test name
Test status
Simulation time 33194311358 ps
CPU time 65.73 seconds
Started Sep 24 06:14:59 AM UTC 24
Finished Sep 24 06:16:06 AM UTC 24
Peak memory 209208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688357927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1688357927
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_fifo_overflow.1699057902
Short name T151
Test name
Test status
Simulation time 15802390907 ps
CPU time 30 seconds
Started Sep 24 06:14:59 AM UTC 24
Finished Sep 24 06:15:30 AM UTC 24
Peak memory 203856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699057902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1699057902
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_fifo_reset.2667860164
Short name T552
Test name
Test status
Simulation time 43284649834 ps
CPU time 67.45 seconds
Started Sep 24 06:15:00 AM UTC 24
Finished Sep 24 06:16:09 AM UTC 24
Peak memory 204108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667860164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2667860164
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_intr.1871212335
Short name T575
Test name
Test status
Simulation time 184206938566 ps
CPU time 124.18 seconds
Started Sep 24 06:15:01 AM UTC 24
Finished Sep 24 06:17:08 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871212335 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1871212335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_long_xfer_wo_dly.1310382605
Short name T629
Test name
Test status
Simulation time 145977591607 ps
CPU time 242.12 seconds
Started Sep 24 06:15:12 AM UTC 24
Finished Sep 24 06:19:18 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310382605 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1310382605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_loopback.921178562
Short name T532
Test name
Test status
Simulation time 1856438319 ps
CPU time 2.46 seconds
Started Sep 24 06:15:08 AM UTC 24
Finished Sep 24 06:15:11 AM UTC 24
Peak memory 207872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921178562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.uart_loopback.921178562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_noise_filter.570233201
Short name T566
Test name
Test status
Simulation time 312340815292 ps
CPU time 102.66 seconds
Started Sep 24 06:15:01 AM UTC 24
Finished Sep 24 06:16:46 AM UTC 24
Peak memory 218768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570233201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.570233201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_perf.3438054731
Short name T968
Test name
Test status
Simulation time 18176137956 ps
CPU time 1069.83 seconds
Started Sep 24 06:15:08 AM UTC 24
Finished Sep 24 06:33:10 AM UTC 24
Peak memory 207432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438054731 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3438054731
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_rx_oversample.620139393
Short name T531
Test name
Test status
Simulation time 1599789839 ps
CPU time 4.27 seconds
Started Sep 24 06:15:01 AM UTC 24
Finished Sep 24 06:15:06 AM UTC 24
Peak memory 207884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620139393 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.620139393
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_rx_parity_err.234385380
Short name T145
Test name
Test status
Simulation time 60598582015 ps
CPU time 59 seconds
Started Sep 24 06:15:06 AM UTC 24
Finished Sep 24 06:16:07 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234385380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.234385380
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_rx_start_bit_filter.71180957
Short name T537
Test name
Test status
Simulation time 3199541321 ps
CPU time 13.1 seconds
Started Sep 24 06:15:03 AM UTC 24
Finished Sep 24 06:15:18 AM UTC 24
Peak memory 203644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71180957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.71180957
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_smoke.3309130204
Short name T527
Test name
Test status
Simulation time 485700643 ps
CPU time 4.15 seconds
Started Sep 24 06:14:54 AM UTC 24
Finished Sep 24 06:14:59 AM UTC 24
Peak memory 203980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309130204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3309130204
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_stress_all_with_rand_reset.1652481353
Short name T91
Test name
Test status
Simulation time 16758097529 ps
CPU time 35.22 seconds
Started Sep 24 06:15:12 AM UTC 24
Finished Sep 24 06:15:48 AM UTC 24
Peak memory 220608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1652481353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all
_with_rand_reset.1652481353
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_tx_ovrd.4282081037
Short name T534
Test name
Test status
Simulation time 1815837141 ps
CPU time 3.29 seconds
Started Sep 24 06:15:07 AM UTC 24
Finished Sep 24 06:15:12 AM UTC 24
Peak memory 204044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282081037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4282081037
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/23.uart_tx_rx.428403118
Short name T550
Test name
Test status
Simulation time 37221907722 ps
CPU time 65.04 seconds
Started Sep 24 06:14:54 AM UTC 24
Finished Sep 24 06:16:00 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428403118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.428403118
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/23.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/230.uart_fifo_reset.3620859925
Short name T1089
Test name
Test status
Simulation time 9294451250 ps
CPU time 22.64 seconds
Started Sep 24 06:37:38 AM UTC 24
Finished Sep 24 06:38:02 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620859925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3620859925
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/230.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/231.uart_fifo_reset.1276124458
Short name T1090
Test name
Test status
Simulation time 30769962264 ps
CPU time 27.39 seconds
Started Sep 24 06:37:39 AM UTC 24
Finished Sep 24 06:38:08 AM UTC 24
Peak memory 204088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276124458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1276124458
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/231.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/232.uart_fifo_reset.287257255
Short name T1155
Test name
Test status
Simulation time 89429345712 ps
CPU time 158.27 seconds
Started Sep 24 06:37:40 AM UTC 24
Finished Sep 24 06:40:21 AM UTC 24
Peak memory 209036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287257255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.287257255
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/232.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/234.uart_fifo_reset.3801617557
Short name T1142
Test name
Test status
Simulation time 48977303939 ps
CPU time 125.49 seconds
Started Sep 24 06:37:40 AM UTC 24
Finished Sep 24 06:39:48 AM UTC 24
Peak memory 209008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801617557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3801617557
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/234.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/235.uart_fifo_reset.1182938555
Short name T1086
Test name
Test status
Simulation time 10243301932 ps
CPU time 10.16 seconds
Started Sep 24 06:37:44 AM UTC 24
Finished Sep 24 06:37:55 AM UTC 24
Peak memory 208104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182938555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1182938555
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/235.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/237.uart_fifo_reset.1805113597
Short name T1122
Test name
Test status
Simulation time 50830115368 ps
CPU time 68.27 seconds
Started Sep 24 06:37:46 AM UTC 24
Finished Sep 24 06:38:56 AM UTC 24
Peak memory 209192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805113597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1805113597
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/237.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/238.uart_fifo_reset.3330114140
Short name T1103
Test name
Test status
Simulation time 30274471726 ps
CPU time 38.83 seconds
Started Sep 24 06:37:47 AM UTC 24
Finished Sep 24 06:38:28 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330114140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3330114140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/238.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/239.uart_fifo_reset.1776448987
Short name T1124
Test name
Test status
Simulation time 102407627893 ps
CPU time 70.05 seconds
Started Sep 24 06:37:49 AM UTC 24
Finished Sep 24 06:39:00 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776448987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.1776448987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/239.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_alert_test.3198794078
Short name T548
Test name
Test status
Simulation time 21906940 ps
CPU time 0.89 seconds
Started Sep 24 06:15:49 AM UTC 24
Finished Sep 24 06:15:51 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198794078 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3198794078
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_fifo_full.3152937606
Short name T555
Test name
Test status
Simulation time 131451318859 ps
CPU time 55.7 seconds
Started Sep 24 06:15:18 AM UTC 24
Finished Sep 24 06:16:15 AM UTC 24
Peak memory 206092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152937606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3152937606
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_fifo_overflow.4260080176
Short name T585
Test name
Test status
Simulation time 39083714794 ps
CPU time 125.78 seconds
Started Sep 24 06:15:21 AM UTC 24
Finished Sep 24 06:17:29 AM UTC 24
Peak memory 209168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260080176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.4260080176
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_fifo_reset.122543274
Short name T544
Test name
Test status
Simulation time 25992633793 ps
CPU time 14.32 seconds
Started Sep 24 06:15:23 AM UTC 24
Finished Sep 24 06:15:39 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122543274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.122543274
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_long_xfer_wo_dly.1253163945
Short name T692
Test name
Test status
Simulation time 85631750219 ps
CPU time 416.78 seconds
Started Sep 24 06:15:40 AM UTC 24
Finished Sep 24 06:22:43 AM UTC 24
Peak memory 205752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253163945 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1253163945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_loopback.2898535446
Short name T546
Test name
Test status
Simulation time 6831276279 ps
CPU time 6.61 seconds
Started Sep 24 06:15:39 AM UTC 24
Finished Sep 24 06:15:47 AM UTC 24
Peak memory 209216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898535446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.uart_loopback.2898535446
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_noise_filter.498286390
Short name T410
Test name
Test status
Simulation time 19056880684 ps
CPU time 17.55 seconds
Started Sep 24 06:15:30 AM UTC 24
Finished Sep 24 06:15:50 AM UTC 24
Peak memory 209400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498286390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.498286390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_perf.2595147875
Short name T623
Test name
Test status
Simulation time 13903538443 ps
CPU time 205.31 seconds
Started Sep 24 06:15:39 AM UTC 24
Finished Sep 24 06:19:08 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595147875 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2595147875
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_rx_oversample.3079423056
Short name T545
Test name
Test status
Simulation time 2876837574 ps
CPU time 13.64 seconds
Started Sep 24 06:15:25 AM UTC 24
Finished Sep 24 06:15:40 AM UTC 24
Peak memory 208200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079423056 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3079423056
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_rx_parity_err.1539401379
Short name T553
Test name
Test status
Simulation time 24625550562 ps
CPU time 35.36 seconds
Started Sep 24 06:15:34 AM UTC 24
Finished Sep 24 06:16:10 AM UTC 24
Peak memory 203856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539401379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1539401379
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_rx_start_bit_filter.3311884706
Short name T543
Test name
Test status
Simulation time 5888195485 ps
CPU time 5.23 seconds
Started Sep 24 06:15:32 AM UTC 24
Finished Sep 24 06:15:38 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311884706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3311884706
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_smoke.2921979772
Short name T539
Test name
Test status
Simulation time 715089802 ps
CPU time 5.75 seconds
Started Sep 24 06:15:16 AM UTC 24
Finished Sep 24 06:15:23 AM UTC 24
Peak memory 203796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921979772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_smoke.2921979772
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_stress_all.831071736
Short name T578
Test name
Test status
Simulation time 29478585493 ps
CPU time 83.7 seconds
Started Sep 24 06:15:47 AM UTC 24
Finished Sep 24 06:17:13 AM UTC 24
Peak memory 203916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831071736 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.831071736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_stress_all_with_rand_reset.3769594691
Short name T563
Test name
Test status
Simulation time 11725243746 ps
CPU time 48.96 seconds
Started Sep 24 06:15:41 AM UTC 24
Finished Sep 24 06:16:32 AM UTC 24
Peak memory 222656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3769594691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all
_with_rand_reset.3769594691
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_tx_ovrd.1643306604
Short name T554
Test name
Test status
Simulation time 6296125475 ps
CPU time 30.43 seconds
Started Sep 24 06:15:39 AM UTC 24
Finished Sep 24 06:16:11 AM UTC 24
Peak memory 203864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643306604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1643306604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/24.uart_tx_rx.3908174158
Short name T587
Test name
Test status
Simulation time 61126116330 ps
CPU time 129.72 seconds
Started Sep 24 06:15:18 AM UTC 24
Finished Sep 24 06:17:30 AM UTC 24
Peak memory 209196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908174158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3908174158
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/24.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/240.uart_fifo_reset.2849142642
Short name T1147
Test name
Test status
Simulation time 82127477836 ps
CPU time 121.86 seconds
Started Sep 24 06:37:49 AM UTC 24
Finished Sep 24 06:39:53 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849142642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2849142642
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/240.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/241.uart_fifo_reset.2810493296
Short name T259
Test name
Test status
Simulation time 42378113634 ps
CPU time 19.28 seconds
Started Sep 24 06:37:50 AM UTC 24
Finished Sep 24 06:38:10 AM UTC 24
Peak memory 209288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810493296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2810493296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/241.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/242.uart_fifo_reset.162276764
Short name T1091
Test name
Test status
Simulation time 51660081828 ps
CPU time 14.43 seconds
Started Sep 24 06:37:54 AM UTC 24
Finished Sep 24 06:38:09 AM UTC 24
Peak memory 203712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162276764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.162276764
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/242.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/243.uart_fifo_reset.598927277
Short name T1111
Test name
Test status
Simulation time 33474151981 ps
CPU time 42.67 seconds
Started Sep 24 06:37:56 AM UTC 24
Finished Sep 24 06:38:40 AM UTC 24
Peak memory 203844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598927277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.598927277
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/243.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/244.uart_fifo_reset.642432102
Short name T1176
Test name
Test status
Simulation time 61107134909 ps
CPU time 466.51 seconds
Started Sep 24 06:37:56 AM UTC 24
Finished Sep 24 06:45:49 AM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642432102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.642432102
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/244.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/246.uart_fifo_reset.3648985498
Short name T1102
Test name
Test status
Simulation time 12943178128 ps
CPU time 26.46 seconds
Started Sep 24 06:37:57 AM UTC 24
Finished Sep 24 06:38:25 AM UTC 24
Peak memory 209576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648985498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3648985498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/246.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/247.uart_fifo_reset.2655737740
Short name T1108
Test name
Test status
Simulation time 58514137350 ps
CPU time 31.61 seconds
Started Sep 24 06:37:58 AM UTC 24
Finished Sep 24 06:38:31 AM UTC 24
Peak memory 208720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655737740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2655737740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/247.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/248.uart_fifo_reset.61318662
Short name T219
Test name
Test status
Simulation time 89819627755 ps
CPU time 69.82 seconds
Started Sep 24 06:37:59 AM UTC 24
Finished Sep 24 06:39:11 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61318662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.61318662
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/248.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/249.uart_fifo_reset.4128161413
Short name T1117
Test name
Test status
Simulation time 89467320445 ps
CPU time 45.71 seconds
Started Sep 24 06:38:02 AM UTC 24
Finished Sep 24 06:38:49 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128161413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.4128161413
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/249.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_alert_test.1729494532
Short name T561
Test name
Test status
Simulation time 46640788 ps
CPU time 0.85 seconds
Started Sep 24 06:16:21 AM UTC 24
Finished Sep 24 06:16:23 AM UTC 24
Peak memory 203312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729494532 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1729494532
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_fifo_full.3665618104
Short name T655
Test name
Test status
Simulation time 180240831541 ps
CPU time 299.47 seconds
Started Sep 24 06:15:52 AM UTC 24
Finished Sep 24 06:20:56 AM UTC 24
Peak memory 209280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665618104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3665618104
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_fifo_overflow.3806584846
Short name T159
Test name
Test status
Simulation time 33726244654 ps
CPU time 24.92 seconds
Started Sep 24 06:15:55 AM UTC 24
Finished Sep 24 06:16:21 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806584846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3806584846
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_fifo_reset.2834217631
Short name T201
Test name
Test status
Simulation time 235928072702 ps
CPU time 115.46 seconds
Started Sep 24 06:16:02 AM UTC 24
Finished Sep 24 06:17:59 AM UTC 24
Peak memory 203864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834217631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2834217631
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_intr.1327514122
Short name T405
Test name
Test status
Simulation time 22262852008 ps
CPU time 48.57 seconds
Started Sep 24 06:16:07 AM UTC 24
Finished Sep 24 06:16:57 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327514122 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1327514122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_long_xfer_wo_dly.2965582845
Short name T736
Test name
Test status
Simulation time 198157408934 ps
CPU time 487.54 seconds
Started Sep 24 06:16:16 AM UTC 24
Finished Sep 24 06:24:30 AM UTC 24
Peak memory 210424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965582845 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2965582845
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_loopback.763368169
Short name T556
Test name
Test status
Simulation time 315007297 ps
CPU time 2.53 seconds
Started Sep 24 06:16:12 AM UTC 24
Finished Sep 24 06:16:16 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763368169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_loopback.763368169
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_noise_filter.162563710
Short name T611
Test name
Test status
Simulation time 201762331164 ps
CPU time 134.66 seconds
Started Sep 24 06:16:08 AM UTC 24
Finished Sep 24 06:18:25 AM UTC 24
Peak memory 209544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162563710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.162563710
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_perf.2620691395
Short name T1013
Test name
Test status
Simulation time 21964372732 ps
CPU time 1114.67 seconds
Started Sep 24 06:16:16 AM UTC 24
Finished Sep 24 06:35:04 AM UTC 24
Peak memory 207172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620691395 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2620691395
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_rx_oversample.259994861
Short name T557
Test name
Test status
Simulation time 3181518235 ps
CPU time 10.27 seconds
Started Sep 24 06:16:06 AM UTC 24
Finished Sep 24 06:16:17 AM UTC 24
Peak memory 208144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259994861 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.259994861
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_rx_parity_err.1951006793
Short name T156
Test name
Test status
Simulation time 34221438528 ps
CPU time 14.48 seconds
Started Sep 24 06:16:10 AM UTC 24
Finished Sep 24 06:16:26 AM UTC 24
Peak memory 203772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951006793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.1951006793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_rx_start_bit_filter.3188366232
Short name T562
Test name
Test status
Simulation time 30402292241 ps
CPU time 16.25 seconds
Started Sep 24 06:16:08 AM UTC 24
Finished Sep 24 06:16:25 AM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188366232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3188366232
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_smoke.354255905
Short name T549
Test name
Test status
Simulation time 639009412 ps
CPU time 2.29 seconds
Started Sep 24 06:15:50 AM UTC 24
Finished Sep 24 06:15:54 AM UTC 24
Peak memory 203728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354255905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.uart_smoke.354255905
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_stress_all.4134046467
Short name T579
Test name
Test status
Simulation time 16544938526 ps
CPU time 55.21 seconds
Started Sep 24 06:16:19 AM UTC 24
Finished Sep 24 06:17:16 AM UTC 24
Peak memory 204096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134046467 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.4134046467
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_stress_all_with_rand_reset.4045807983
Short name T595
Test name
Test status
Simulation time 36883839001 ps
CPU time 82.66 seconds
Started Sep 24 06:16:17 AM UTC 24
Finished Sep 24 06:17:42 AM UTC 24
Peak memory 218316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4045807983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all
_with_rand_reset.4045807983
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_tx_ovrd.2185253793
Short name T560
Test name
Test status
Simulation time 7857513591 ps
CPU time 8.82 seconds
Started Sep 24 06:16:11 AM UTC 24
Finished Sep 24 06:16:21 AM UTC 24
Peak memory 203904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185253793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2185253793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/25.uart_tx_rx.213821776
Short name T576
Test name
Test status
Simulation time 30461351216 ps
CPU time 78.7 seconds
Started Sep 24 06:15:50 AM UTC 24
Finished Sep 24 06:17:11 AM UTC 24
Peak memory 203864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213821776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.213821776
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/25.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/250.uart_fifo_reset.2674338839
Short name T1153
Test name
Test status
Simulation time 159910238381 ps
CPU time 124.88 seconds
Started Sep 24 06:38:03 AM UTC 24
Finished Sep 24 06:40:10 AM UTC 24
Peak memory 204116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674338839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2674338839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/250.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/251.uart_fifo_reset.2538532470
Short name T1109
Test name
Test status
Simulation time 60990317268 ps
CPU time 29.58 seconds
Started Sep 24 06:38:06 AM UTC 24
Finished Sep 24 06:38:36 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538532470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2538532470
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/251.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/252.uart_fifo_reset.2091970854
Short name T1114
Test name
Test status
Simulation time 44309870145 ps
CPU time 38.61 seconds
Started Sep 24 06:38:06 AM UTC 24
Finished Sep 24 06:38:46 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091970854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.2091970854
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/252.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/253.uart_fifo_reset.521970071
Short name T1125
Test name
Test status
Simulation time 50622687245 ps
CPU time 59.96 seconds
Started Sep 24 06:38:07 AM UTC 24
Finished Sep 24 06:39:08 AM UTC 24
Peak memory 209512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521970071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.521970071
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/253.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/254.uart_fifo_reset.1173501667
Short name T1107
Test name
Test status
Simulation time 117597712409 ps
CPU time 20.28 seconds
Started Sep 24 06:38:09 AM UTC 24
Finished Sep 24 06:38:30 AM UTC 24
Peak memory 209148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173501667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1173501667
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/254.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/255.uart_fifo_reset.360583144
Short name T1148
Test name
Test status
Simulation time 51172511654 ps
CPU time 103.51 seconds
Started Sep 24 06:38:10 AM UTC 24
Finished Sep 24 06:39:55 AM UTC 24
Peak memory 209596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360583144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.360583144
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/255.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/256.uart_fifo_reset.3091010417
Short name T1128
Test name
Test status
Simulation time 137666009682 ps
CPU time 60.75 seconds
Started Sep 24 06:38:11 AM UTC 24
Finished Sep 24 06:39:13 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091010417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3091010417
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/256.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/257.uart_fifo_reset.2187207853
Short name T1146
Test name
Test status
Simulation time 45435221284 ps
CPU time 96.77 seconds
Started Sep 24 06:38:12 AM UTC 24
Finished Sep 24 06:39:51 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187207853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2187207853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/257.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/258.uart_fifo_reset.2463980778
Short name T1152
Test name
Test status
Simulation time 40164720743 ps
CPU time 112.42 seconds
Started Sep 24 06:38:13 AM UTC 24
Finished Sep 24 06:40:08 AM UTC 24
Peak memory 209396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463980778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2463980778
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/258.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/259.uart_fifo_reset.1723659616
Short name T1110
Test name
Test status
Simulation time 83260974698 ps
CPU time 22.15 seconds
Started Sep 24 06:38:14 AM UTC 24
Finished Sep 24 06:38:38 AM UTC 24
Peak memory 209080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723659616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1723659616
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/259.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_alert_test.1966838708
Short name T571
Test name
Test status
Simulation time 18510722 ps
CPU time 0.88 seconds
Started Sep 24 06:16:57 AM UTC 24
Finished Sep 24 06:16:59 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966838708 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1966838708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_fifo_full.3827995026
Short name T588
Test name
Test status
Simulation time 34105147129 ps
CPU time 61.96 seconds
Started Sep 24 06:16:27 AM UTC 24
Finished Sep 24 06:17:31 AM UTC 24
Peak memory 209264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827995026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3827995026
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_fifo_overflow.3860400793
Short name T408
Test name
Test status
Simulation time 21358372824 ps
CPU time 10.53 seconds
Started Sep 24 06:16:27 AM UTC 24
Finished Sep 24 06:16:39 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860400793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3860400793
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_fifo_reset.1056691976
Short name T616
Test name
Test status
Simulation time 56890914234 ps
CPU time 129.1 seconds
Started Sep 24 06:16:31 AM UTC 24
Finished Sep 24 06:18:42 AM UTC 24
Peak memory 204040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056691976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1056691976
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_intr.1400042934
Short name T589
Test name
Test status
Simulation time 37641875934 ps
CPU time 57.58 seconds
Started Sep 24 06:16:33 AM UTC 24
Finished Sep 24 06:17:32 AM UTC 24
Peak memory 208524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400042934 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1400042934
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_long_xfer_wo_dly.2470601192
Short name T804
Test name
Test status
Simulation time 117369431223 ps
CPU time 607.9 seconds
Started Sep 24 06:16:53 AM UTC 24
Finished Sep 24 06:27:08 AM UTC 24
Peak memory 209140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470601192 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2470601192
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_loopback.1526617761
Short name T574
Test name
Test status
Simulation time 3723985243 ps
CPU time 19.24 seconds
Started Sep 24 06:16:46 AM UTC 24
Finished Sep 24 06:17:07 AM UTC 24
Peak memory 208208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526617761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1526617761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_noise_filter.3919631954
Short name T403
Test name
Test status
Simulation time 48280020738 ps
CPU time 49.93 seconds
Started Sep 24 06:16:34 AM UTC 24
Finished Sep 24 06:17:25 AM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919631954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3919631954
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_perf.4287819671
Short name T639
Test name
Test status
Simulation time 12246183938 ps
CPU time 189.1 seconds
Started Sep 24 06:16:47 AM UTC 24
Finished Sep 24 06:20:00 AM UTC 24
Peak memory 204112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287819671 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4287819671
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_rx_oversample.3922349251
Short name T401
Test name
Test status
Simulation time 4534217309 ps
CPU time 22.6 seconds
Started Sep 24 06:16:32 AM UTC 24
Finished Sep 24 06:16:56 AM UTC 24
Peak memory 208396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922349251 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.3922349251
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_rx_parity_err.1703685947
Short name T599
Test name
Test status
Simulation time 46894998453 ps
CPU time 65.9 seconds
Started Sep 24 06:16:45 AM UTC 24
Finished Sep 24 06:17:53 AM UTC 24
Peak memory 208336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703685947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.1703685947
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_rx_start_bit_filter.2763605505
Short name T567
Test name
Test status
Simulation time 2512144820 ps
CPU time 6.42 seconds
Started Sep 24 06:16:39 AM UTC 24
Finished Sep 24 06:16:47 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763605505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2763605505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_smoke.3414965634
Short name T569
Test name
Test status
Simulation time 5724360451 ps
CPU time 29.59 seconds
Started Sep 24 06:16:22 AM UTC 24
Finished Sep 24 06:16:53 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414965634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_smoke.3414965634
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_stress_all.843443651
Short name T1001
Test name
Test status
Simulation time 230757393534 ps
CPU time 1043.12 seconds
Started Sep 24 06:16:55 AM UTC 24
Finished Sep 24 06:34:30 AM UTC 24
Peak memory 211252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843443651 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.843443651
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_stress_all_with_rand_reset.1061800590
Short name T592
Test name
Test status
Simulation time 5395155769 ps
CPU time 42 seconds
Started Sep 24 06:16:54 AM UTC 24
Finished Sep 24 06:17:37 AM UTC 24
Peak memory 218240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1061800590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all
_with_rand_reset.1061800590
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_tx_ovrd.3994474327
Short name T570
Test name
Test status
Simulation time 8287637374 ps
CPU time 6.35 seconds
Started Sep 24 06:16:46 AM UTC 24
Finished Sep 24 06:16:54 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994474327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3994474327
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/26.uart_tx_rx.2472399998
Short name T568
Test name
Test status
Simulation time 63005694836 ps
CPU time 25.46 seconds
Started Sep 24 06:16:25 AM UTC 24
Finished Sep 24 06:16:51 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472399998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2472399998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/26.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/260.uart_fifo_reset.3505388759
Short name T1130
Test name
Test status
Simulation time 29677066540 ps
CPU time 72.27 seconds
Started Sep 24 06:38:14 AM UTC 24
Finished Sep 24 06:39:28 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505388759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3505388759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/260.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/262.uart_fifo_reset.3828175947
Short name T1137
Test name
Test status
Simulation time 73263140320 ps
CPU time 81.3 seconds
Started Sep 24 06:38:16 AM UTC 24
Finished Sep 24 06:39:39 AM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828175947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3828175947
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/262.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/264.uart_fifo_reset.922207051
Short name T1113
Test name
Test status
Simulation time 10240972544 ps
CPU time 23.98 seconds
Started Sep 24 06:38:20 AM UTC 24
Finished Sep 24 06:38:45 AM UTC 24
Peak memory 209436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922207051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.922207051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/264.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/265.uart_fifo_reset.2468861989
Short name T1136
Test name
Test status
Simulation time 40959188221 ps
CPU time 75.06 seconds
Started Sep 24 06:38:22 AM UTC 24
Finished Sep 24 06:39:38 AM UTC 24
Peak memory 209016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468861989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2468861989
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/265.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/266.uart_fifo_reset.2870661549
Short name T1141
Test name
Test status
Simulation time 302693254952 ps
CPU time 78.88 seconds
Started Sep 24 06:38:25 AM UTC 24
Finished Sep 24 06:39:45 AM UTC 24
Peak memory 209096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870661549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2870661549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/266.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/267.uart_fifo_reset.439336382
Short name T1121
Test name
Test status
Simulation time 43312769914 ps
CPU time 28.27 seconds
Started Sep 24 06:38:26 AM UTC 24
Finished Sep 24 06:38:55 AM UTC 24
Peak memory 203772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439336382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.439336382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/267.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/268.uart_fifo_reset.1991214119
Short name T1118
Test name
Test status
Simulation time 6825761059 ps
CPU time 22.19 seconds
Started Sep 24 06:38:27 AM UTC 24
Finished Sep 24 06:38:50 AM UTC 24
Peak memory 204088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991214119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1991214119
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/268.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/269.uart_fifo_reset.4050244325
Short name T1112
Test name
Test status
Simulation time 15092934470 ps
CPU time 10.62 seconds
Started Sep 24 06:38:29 AM UTC 24
Finished Sep 24 06:38:41 AM UTC 24
Peak memory 209284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050244325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4050244325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/269.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_alert_test.1157106966
Short name T586
Test name
Test status
Simulation time 53256728 ps
CPU time 0.84 seconds
Started Sep 24 06:17:28 AM UTC 24
Finished Sep 24 06:17:30 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157106966 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1157106966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_fifo_full.736557011
Short name T430
Test name
Test status
Simulation time 96062293487 ps
CPU time 60.34 seconds
Started Sep 24 06:17:00 AM UTC 24
Finished Sep 24 06:18:02 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736557011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.736557011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_intr.2957423692
Short name T596
Test name
Test status
Simulation time 58148134166 ps
CPU time 29.7 seconds
Started Sep 24 06:17:12 AM UTC 24
Finished Sep 24 06:17:43 AM UTC 24
Peak memory 209252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957423692 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2957423692
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_long_xfer_wo_dly.229570699
Short name T691
Test name
Test status
Simulation time 102791545216 ps
CPU time 310.15 seconds
Started Sep 24 06:17:27 AM UTC 24
Finished Sep 24 06:22:41 AM UTC 24
Peak memory 205740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229570699 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.229570699
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_loopback.3146326107
Short name T582
Test name
Test status
Simulation time 2007588639 ps
CPU time 2.46 seconds
Started Sep 24 06:17:22 AM UTC 24
Finished Sep 24 06:17:26 AM UTC 24
Peak memory 203640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146326107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3146326107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_noise_filter.2268070534
Short name T604
Test name
Test status
Simulation time 72170090390 ps
CPU time 57.56 seconds
Started Sep 24 06:17:12 AM UTC 24
Finished Sep 24 06:18:11 AM UTC 24
Peak memory 209928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268070534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2268070534
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_perf.91922760
Short name T641
Test name
Test status
Simulation time 16796031381 ps
CPU time 160.02 seconds
Started Sep 24 06:17:23 AM UTC 24
Finished Sep 24 06:20:06 AM UTC 24
Peak memory 203768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91922760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.91922760
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_rx_oversample.3140467193
Short name T580
Test name
Test status
Simulation time 2318534830 ps
CPU time 11.04 seconds
Started Sep 24 06:17:08 AM UTC 24
Finished Sep 24 06:17:20 AM UTC 24
Peak memory 208200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140467193 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3140467193
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_rx_parity_err.2516711588
Short name T603
Test name
Test status
Simulation time 197265886143 ps
CPU time 51.3 seconds
Started Sep 24 06:17:17 AM UTC 24
Finished Sep 24 06:18:11 AM UTC 24
Peak memory 209192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516711588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2516711588
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_rx_start_bit_filter.1410907385
Short name T581
Test name
Test status
Simulation time 2953400196 ps
CPU time 7.69 seconds
Started Sep 24 06:17:13 AM UTC 24
Finished Sep 24 06:17:22 AM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410907385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1410907385
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_smoke.3896373282
Short name T577
Test name
Test status
Simulation time 6323978137 ps
CPU time 12.92 seconds
Started Sep 24 06:16:58 AM UTC 24
Finished Sep 24 06:17:12 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896373282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3896373282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_stress_all.4175406917
Short name T779
Test name
Test status
Simulation time 150866706916 ps
CPU time 523.36 seconds
Started Sep 24 06:17:28 AM UTC 24
Finished Sep 24 06:26:18 AM UTC 24
Peak memory 205384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175406917 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.4175406917
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_stress_all_with_rand_reset.3993939041
Short name T558
Test name
Test status
Simulation time 1968762245 ps
CPU time 36.39 seconds
Started Sep 24 06:17:27 AM UTC 24
Finished Sep 24 06:18:05 AM UTC 24
Peak memory 220288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3993939041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all
_with_rand_reset.3993939041
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_tx_ovrd.866945805
Short name T584
Test name
Test status
Simulation time 1060169988 ps
CPU time 5.98 seconds
Started Sep 24 06:17:19 AM UTC 24
Finished Sep 24 06:17:27 AM UTC 24
Peak memory 203652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866945805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.866945805
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/27.uart_tx_rx.4246438428
Short name T583
Test name
Test status
Simulation time 9328965616 ps
CPU time 25.25 seconds
Started Sep 24 06:17:00 AM UTC 24
Finished Sep 24 06:17:26 AM UTC 24
Peak memory 209280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246438428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.4246438428
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/27.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/270.uart_fifo_reset.713962909
Short name T1157
Test name
Test status
Simulation time 65704833548 ps
CPU time 116.47 seconds
Started Sep 24 06:38:30 AM UTC 24
Finished Sep 24 06:40:29 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713962909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.713962909
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/270.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/271.uart_fifo_reset.3435384228
Short name T207
Test name
Test status
Simulation time 22623055387 ps
CPU time 53.21 seconds
Started Sep 24 06:38:30 AM UTC 24
Finished Sep 24 06:39:25 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435384228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3435384228
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/271.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/272.uart_fifo_reset.1865050316
Short name T1119
Test name
Test status
Simulation time 32889407545 ps
CPU time 19.81 seconds
Started Sep 24 06:38:31 AM UTC 24
Finished Sep 24 06:38:52 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865050316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1865050316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/272.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/273.uart_fifo_reset.983084432
Short name T1127
Test name
Test status
Simulation time 127777693659 ps
CPU time 38.26 seconds
Started Sep 24 06:38:31 AM UTC 24
Finished Sep 24 06:39:11 AM UTC 24
Peak memory 209564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983084432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.983084432
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/273.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/274.uart_fifo_reset.1056751247
Short name T1145
Test name
Test status
Simulation time 43208774609 ps
CPU time 76.8 seconds
Started Sep 24 06:38:31 AM UTC 24
Finished Sep 24 06:39:50 AM UTC 24
Peak memory 209196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056751247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1056751247
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/274.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/275.uart_fifo_reset.1228873969
Short name T206
Test name
Test status
Simulation time 14870345346 ps
CPU time 28.8 seconds
Started Sep 24 06:38:32 AM UTC 24
Finished Sep 24 06:39:03 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228873969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1228873969
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/275.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/276.uart_fifo_reset.1781213782
Short name T1123
Test name
Test status
Simulation time 48535634995 ps
CPU time 21.19 seconds
Started Sep 24 06:38:37 AM UTC 24
Finished Sep 24 06:39:00 AM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781213782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.1781213782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/276.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/277.uart_fifo_reset.2023724610
Short name T1162
Test name
Test status
Simulation time 93003693719 ps
CPU time 141.61 seconds
Started Sep 24 06:38:38 AM UTC 24
Finished Sep 24 06:41:02 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023724610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2023724610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/277.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/278.uart_fifo_reset.1065218535
Short name T1134
Test name
Test status
Simulation time 93482480192 ps
CPU time 54.3 seconds
Started Sep 24 06:38:39 AM UTC 24
Finished Sep 24 06:39:35 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065218535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.1065218535
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/278.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/279.uart_fifo_reset.409867328
Short name T1164
Test name
Test status
Simulation time 89488663845 ps
CPU time 153.61 seconds
Started Sep 24 06:38:41 AM UTC 24
Finished Sep 24 06:41:17 AM UTC 24
Peak memory 209180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409867328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.409867328
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/279.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_alert_test.1487528435
Short name T601
Test name
Test status
Simulation time 26016776 ps
CPU time 0.73 seconds
Started Sep 24 06:17:53 AM UTC 24
Finished Sep 24 06:17:55 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487528435 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1487528435
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_fifo_full.1517604945
Short name T631
Test name
Test status
Simulation time 50413666580 ps
CPU time 119.7 seconds
Started Sep 24 06:17:31 AM UTC 24
Finished Sep 24 06:19:33 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517604945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1517604945
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_fifo_overflow.2280220827
Short name T765
Test name
Test status
Simulation time 135229061626 ps
CPU time 491.84 seconds
Started Sep 24 06:17:31 AM UTC 24
Finished Sep 24 06:25:49 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280220827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2280220827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_fifo_reset.537287836
Short name T199
Test name
Test status
Simulation time 36972452026 ps
CPU time 58.74 seconds
Started Sep 24 06:17:33 AM UTC 24
Finished Sep 24 06:18:34 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537287836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.537287836
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_intr.3739886716
Short name T593
Test name
Test status
Simulation time 448619411 ps
CPU time 2.08 seconds
Started Sep 24 06:17:36 AM UTC 24
Finished Sep 24 06:17:40 AM UTC 24
Peak memory 205560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739886716 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3739886716
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_long_xfer_wo_dly.2108561050
Short name T658
Test name
Test status
Simulation time 96092307683 ps
CPU time 199.38 seconds
Started Sep 24 06:17:45 AM UTC 24
Finished Sep 24 06:21:07 AM UTC 24
Peak memory 209320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108561050 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2108561050
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_loopback.865578004
Short name T600
Test name
Test status
Simulation time 6991127716 ps
CPU time 8.68 seconds
Started Sep 24 06:17:43 AM UTC 24
Finished Sep 24 06:17:53 AM UTC 24
Peak memory 203976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865578004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.uart_loopback.865578004
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_noise_filter.1122839138
Short name T618
Test name
Test status
Simulation time 104368001190 ps
CPU time 65.8 seconds
Started Sep 24 06:17:38 AM UTC 24
Finished Sep 24 06:18:45 AM UTC 24
Peak memory 220756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122839138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1122839138
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_perf.3851766416
Short name T666
Test name
Test status
Simulation time 21106458079 ps
CPU time 224.55 seconds
Started Sep 24 06:17:44 AM UTC 24
Finished Sep 24 06:21:32 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851766416 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3851766416
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_rx_oversample.205505034
Short name T594
Test name
Test status
Simulation time 1167212369 ps
CPU time 3.79 seconds
Started Sep 24 06:17:35 AM UTC 24
Finished Sep 24 06:17:40 AM UTC 24
Peak memory 207536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205505034 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.205505034
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_rx_parity_err.3430091553
Short name T719
Test name
Test status
Simulation time 151097235699 ps
CPU time 368.3 seconds
Started Sep 24 06:17:41 AM UTC 24
Finished Sep 24 06:23:54 AM UTC 24
Peak memory 203716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430091553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3430091553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_rx_start_bit_filter.3800977512
Short name T597
Test name
Test status
Simulation time 3468354216 ps
CPU time 4.4 seconds
Started Sep 24 06:17:39 AM UTC 24
Finished Sep 24 06:17:45 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800977512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3800977512
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_smoke.1067696725
Short name T590
Test name
Test status
Simulation time 890124699 ps
CPU time 3.47 seconds
Started Sep 24 06:17:30 AM UTC 24
Finished Sep 24 06:17:35 AM UTC 24
Peak memory 204052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067696725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1067696725
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_stress_all.473180744
Short name T679
Test name
Test status
Simulation time 184542966917 ps
CPU time 259.66 seconds
Started Sep 24 06:17:53 AM UTC 24
Finished Sep 24 06:22:16 AM UTC 24
Peak memory 217360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473180744 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.473180744
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_tx_ovrd.3683811201
Short name T598
Test name
Test status
Simulation time 1173163164 ps
CPU time 4.22 seconds
Started Sep 24 06:17:41 AM UTC 24
Finished Sep 24 06:17:46 AM UTC 24
Peak memory 203728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683811201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3683811201
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/28.uart_tx_rx.2652780094
Short name T615
Test name
Test status
Simulation time 104137720989 ps
CPU time 67.82 seconds
Started Sep 24 06:17:31 AM UTC 24
Finished Sep 24 06:18:41 AM UTC 24
Peak memory 209664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652780094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2652780094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/28.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/280.uart_fifo_reset.2091643966
Short name T1099
Test name
Test status
Simulation time 63853278403 ps
CPU time 125.17 seconds
Started Sep 24 06:38:42 AM UTC 24
Finished Sep 24 06:40:50 AM UTC 24
Peak memory 209540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091643966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2091643966
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/280.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/281.uart_fifo_reset.3286411449
Short name T208
Test name
Test status
Simulation time 20675119437 ps
CPU time 38.26 seconds
Started Sep 24 06:38:46 AM UTC 24
Finished Sep 24 06:39:26 AM UTC 24
Peak memory 203772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286411449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3286411449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/281.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/282.uart_fifo_reset.2959324505
Short name T1131
Test name
Test status
Simulation time 21750770319 ps
CPU time 41.06 seconds
Started Sep 24 06:38:47 AM UTC 24
Finished Sep 24 06:39:29 AM UTC 24
Peak memory 209592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959324505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2959324505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/282.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/283.uart_fifo_reset.3405975188
Short name T1149
Test name
Test status
Simulation time 20006319843 ps
CPU time 69.56 seconds
Started Sep 24 06:38:47 AM UTC 24
Finished Sep 24 06:39:58 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405975188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3405975188
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/283.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/284.uart_fifo_reset.987169517
Short name T1156
Test name
Test status
Simulation time 44243203409 ps
CPU time 95.78 seconds
Started Sep 24 06:38:47 AM UTC 24
Finished Sep 24 06:40:25 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987169517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.987169517
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/284.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/285.uart_fifo_reset.4276641149
Short name T1140
Test name
Test status
Simulation time 22517243764 ps
CPU time 50.96 seconds
Started Sep 24 06:38:50 AM UTC 24
Finished Sep 24 06:39:43 AM UTC 24
Peak memory 209284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276641149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.4276641149
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/285.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/286.uart_fifo_reset.3362234482
Short name T1126
Test name
Test status
Simulation time 35206920943 ps
CPU time 17.37 seconds
Started Sep 24 06:38:51 AM UTC 24
Finished Sep 24 06:39:10 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362234482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3362234482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/286.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/287.uart_fifo_reset.4061810335
Short name T1168
Test name
Test status
Simulation time 191705869720 ps
CPU time 157.63 seconds
Started Sep 24 06:38:53 AM UTC 24
Finished Sep 24 06:41:34 AM UTC 24
Peak memory 204100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061810335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.4061810335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/287.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/288.uart_fifo_reset.3642284855
Short name T1158
Test name
Test status
Simulation time 79442665388 ps
CPU time 95.06 seconds
Started Sep 24 06:38:54 AM UTC 24
Finished Sep 24 06:40:32 AM UTC 24
Peak memory 209216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642284855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.3642284855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/288.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/289.uart_fifo_reset.2067354204
Short name T247
Test name
Test status
Simulation time 139615810789 ps
CPU time 172.52 seconds
Started Sep 24 06:38:57 AM UTC 24
Finished Sep 24 06:41:52 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067354204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.2067354204
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/289.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_alert_test.4016111443
Short name T613
Test name
Test status
Simulation time 33338185 ps
CPU time 0.84 seconds
Started Sep 24 06:18:30 AM UTC 24
Finished Sep 24 06:18:31 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016111443 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.4016111443
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_fifo_full.623427148
Short name T361
Test name
Test status
Simulation time 69909133606 ps
CPU time 121.49 seconds
Started Sep 24 06:18:03 AM UTC 24
Finished Sep 24 06:20:07 AM UTC 24
Peak memory 205820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623427148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.623427148
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_fifo_overflow.4051542518
Short name T656
Test name
Test status
Simulation time 180803514515 ps
CPU time 178.21 seconds
Started Sep 24 06:18:04 AM UTC 24
Finished Sep 24 06:21:05 AM UTC 24
Peak memory 208864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051542518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.4051542518
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_fifo_reset.676050419
Short name T428
Test name
Test status
Simulation time 27161432046 ps
CPU time 49.06 seconds
Started Sep 24 06:18:06 AM UTC 24
Finished Sep 24 06:18:56 AM UTC 24
Peak memory 209052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676050419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.676050419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_intr.3200119953
Short name T624
Test name
Test status
Simulation time 36536732291 ps
CPU time 56.67 seconds
Started Sep 24 06:18:11 AM UTC 24
Finished Sep 24 06:19:09 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200119953 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3200119953
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_long_xfer_wo_dly.481716804
Short name T718
Test name
Test status
Simulation time 66379024001 ps
CPU time 320.62 seconds
Started Sep 24 06:18:21 AM UTC 24
Finished Sep 24 06:23:46 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481716804 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.481716804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_loopback.2731270178
Short name T612
Test name
Test status
Simulation time 6579310718 ps
CPU time 10.2 seconds
Started Sep 24 06:18:17 AM UTC 24
Finished Sep 24 06:18:28 AM UTC 24
Peak memory 209324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731270178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2731270178
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_noise_filter.3447894579
Short name T414
Test name
Test status
Simulation time 156225284513 ps
CPU time 126.82 seconds
Started Sep 24 06:18:12 AM UTC 24
Finished Sep 24 06:20:21 AM UTC 24
Peak memory 209668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447894579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3447894579
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_perf.1575689694
Short name T660
Test name
Test status
Simulation time 16012858196 ps
CPU time 174.42 seconds
Started Sep 24 06:18:20 AM UTC 24
Finished Sep 24 06:21:17 AM UTC 24
Peak memory 203844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575689694 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1575689694
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_rx_oversample.2448157610
Short name T605
Test name
Test status
Simulation time 4105415748 ps
CPU time 6.24 seconds
Started Sep 24 06:18:07 AM UTC 24
Finished Sep 24 06:18:14 AM UTC 24
Peak memory 207944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448157610 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2448157610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_rx_parity_err.2633116395
Short name T674
Test name
Test status
Simulation time 121478930803 ps
CPU time 221.97 seconds
Started Sep 24 06:18:15 AM UTC 24
Finished Sep 24 06:22:00 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633116395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2633116395
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_rx_start_bit_filter.600022138
Short name T608
Test name
Test status
Simulation time 3500743199 ps
CPU time 6.4 seconds
Started Sep 24 06:18:12 AM UTC 24
Finished Sep 24 06:18:19 AM UTC 24
Peak memory 203904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600022138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.600022138
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_smoke.3594743607
Short name T606
Test name
Test status
Simulation time 5983738444 ps
CPU time 19.01 seconds
Started Sep 24 06:17:55 AM UTC 24
Finished Sep 24 06:18:16 AM UTC 24
Peak memory 204180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594743607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3594743607
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_stress_all.1649355702
Short name T763
Test name
Test status
Simulation time 102533610126 ps
CPU time 432.02 seconds
Started Sep 24 06:18:26 AM UTC 24
Finished Sep 24 06:25:43 AM UTC 24
Peak memory 218484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649355702 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.1649355702
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_stress_all_with_rand_reset.1962536804
Short name T394
Test name
Test status
Simulation time 19193718527 ps
CPU time 45 seconds
Started Sep 24 06:18:23 AM UTC 24
Finished Sep 24 06:19:10 AM UTC 24
Peak memory 218624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1962536804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all
_with_rand_reset.1962536804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_tx_ovrd.1310552751
Short name T609
Test name
Test status
Simulation time 1719020050 ps
CPU time 3.67 seconds
Started Sep 24 06:18:16 AM UTC 24
Finished Sep 24 06:18:21 AM UTC 24
Peak memory 208168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310552751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.1310552751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/29.uart_tx_rx.2884477370
Short name T413
Test name
Test status
Simulation time 51172905039 ps
CPU time 97.5 seconds
Started Sep 24 06:18:00 AM UTC 24
Finished Sep 24 06:19:40 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884477370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2884477370
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/29.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/290.uart_fifo_reset.2120513011
Short name T1129
Test name
Test status
Simulation time 128060459258 ps
CPU time 18.97 seconds
Started Sep 24 06:38:58 AM UTC 24
Finished Sep 24 06:39:18 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120513011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2120513011
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/290.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/291.uart_fifo_reset.1845159897
Short name T1143
Test name
Test status
Simulation time 16474953175 ps
CPU time 46.94 seconds
Started Sep 24 06:39:01 AM UTC 24
Finished Sep 24 06:39:49 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845159897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1845159897
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/291.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/292.uart_fifo_reset.3125981500
Short name T1165
Test name
Test status
Simulation time 133672425015 ps
CPU time 140.95 seconds
Started Sep 24 06:39:01 AM UTC 24
Finished Sep 24 06:41:24 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125981500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.3125981500
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/292.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/293.uart_fifo_reset.207775901
Short name T1133
Test name
Test status
Simulation time 45590308131 ps
CPU time 28.94 seconds
Started Sep 24 06:39:04 AM UTC 24
Finished Sep 24 06:39:34 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207775901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.207775901
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/293.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/294.uart_fifo_reset.821457948
Short name T215
Test name
Test status
Simulation time 40729002807 ps
CPU time 48.53 seconds
Started Sep 24 06:39:09 AM UTC 24
Finished Sep 24 06:39:59 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821457948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.821457948
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/294.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/295.uart_fifo_reset.1642264831
Short name T1163
Test name
Test status
Simulation time 178784716508 ps
CPU time 111.26 seconds
Started Sep 24 06:39:11 AM UTC 24
Finished Sep 24 06:41:04 AM UTC 24
Peak memory 203700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642264831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1642264831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/295.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/296.uart_fifo_reset.1624601532
Short name T1159
Test name
Test status
Simulation time 39873185238 ps
CPU time 94.06 seconds
Started Sep 24 06:39:12 AM UTC 24
Finished Sep 24 06:40:48 AM UTC 24
Peak memory 204052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624601532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1624601532
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/296.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/297.uart_fifo_reset.1231865115
Short name T1151
Test name
Test status
Simulation time 18613436009 ps
CPU time 51.08 seconds
Started Sep 24 06:39:12 AM UTC 24
Finished Sep 24 06:40:05 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231865115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1231865115
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/297.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/298.uart_fifo_reset.217706263
Short name T1160
Test name
Test status
Simulation time 50255527532 ps
CPU time 97.01 seconds
Started Sep 24 06:39:14 AM UTC 24
Finished Sep 24 06:40:53 AM UTC 24
Peak memory 209200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217706263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.217706263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/298.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/299.uart_fifo_reset.3391949022
Short name T1167
Test name
Test status
Simulation time 76945859314 ps
CPU time 127.56 seconds
Started Sep 24 06:39:18 AM UTC 24
Finished Sep 24 06:41:28 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391949022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3391949022
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/299.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_alert_test.1557275445
Short name T434
Test name
Test status
Simulation time 37702479 ps
CPU time 0.84 seconds
Started Sep 24 06:01:36 AM UTC 24
Finished Sep 24 06:01:39 AM UTC 24
Peak memory 203256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557275445 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1557275445
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_fifo_full.1427339091
Short name T122
Test name
Test status
Simulation time 90008182733 ps
CPU time 160.56 seconds
Started Sep 24 06:00:51 AM UTC 24
Finished Sep 24 06:03:34 AM UTC 24
Peak memory 205908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427339091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1427339091
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.3791232101
Short name T273
Test name
Test status
Simulation time 85473760502 ps
CPU time 304.45 seconds
Started Sep 24 06:00:51 AM UTC 24
Finished Sep 24 06:06:00 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791232101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3791232101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_fifo_reset.1871388434
Short name T265
Test name
Test status
Simulation time 151438133649 ps
CPU time 214.23 seconds
Started Sep 24 06:00:52 AM UTC 24
Finished Sep 24 06:04:30 AM UTC 24
Peak memory 209572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871388434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1871388434
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_intr.1019144701
Short name T281
Test name
Test status
Simulation time 23113042661 ps
CPU time 18.62 seconds
Started Sep 24 06:01:01 AM UTC 24
Finished Sep 24 06:01:21 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019144701 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1019144701
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_long_xfer_wo_dly.921624289
Short name T379
Test name
Test status
Simulation time 63560174493 ps
CPU time 528.86 seconds
Started Sep 24 06:01:25 AM UTC 24
Finished Sep 24 06:10:21 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921624289 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.921624289
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_loopback.3629331338
Short name T29
Test name
Test status
Simulation time 3330414371 ps
CPU time 9.21 seconds
Started Sep 24 06:01:21 AM UTC 24
Finished Sep 24 06:01:31 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629331338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3629331338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_noise_filter.1482366853
Short name T97
Test name
Test status
Simulation time 37859921550 ps
CPU time 70.5 seconds
Started Sep 24 06:01:10 AM UTC 24
Finished Sep 24 06:02:23 AM UTC 24
Peak memory 209676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482366853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1482366853
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_perf.2065521382
Short name T796
Test name
Test status
Simulation time 22943813569 ps
CPU time 1499.97 seconds
Started Sep 24 06:01:22 AM UTC 24
Finished Sep 24 06:26:38 AM UTC 24
Peak memory 207504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065521382 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2065521382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_rx_oversample.3710717469
Short name T18
Test name
Test status
Simulation time 5235120900 ps
CPU time 16.81 seconds
Started Sep 24 06:00:53 AM UTC 24
Finished Sep 24 06:01:11 AM UTC 24
Peak memory 208204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710717469 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3710717469
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.2555550050
Short name T269
Test name
Test status
Simulation time 3969627177 ps
CPU time 12.12 seconds
Started Sep 24 06:01:13 AM UTC 24
Finished Sep 24 06:01:26 AM UTC 24
Peak memory 203836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555550050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2555550050
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_sec_cm.4086718567
Short name T85
Test name
Test status
Simulation time 68669066 ps
CPU time 1.19 seconds
Started Sep 24 06:01:35 AM UTC 24
Finished Sep 24 06:01:38 AM UTC 24
Peak memory 237820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086718567 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.4086718567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_smoke.2373794175
Short name T329
Test name
Test status
Simulation time 453208970 ps
CPU time 2.12 seconds
Started Sep 24 06:00:49 AM UTC 24
Finished Sep 24 06:00:52 AM UTC 24
Peak memory 203800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373794175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2373794175
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.281125484
Short name T40
Test name
Test status
Simulation time 1662184477 ps
CPU time 23.72 seconds
Started Sep 24 06:01:26 AM UTC 24
Finished Sep 24 06:01:51 AM UTC 24
Peak memory 218564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=281125484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all_w
ith_rand_reset.281125484
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.2505439545
Short name T354
Test name
Test status
Simulation time 1412016426 ps
CPU time 2.92 seconds
Started Sep 24 06:01:20 AM UTC 24
Finished Sep 24 06:01:24 AM UTC 24
Peak memory 203724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505439545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2505439545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/3.uart_tx_rx.3511960422
Short name T48
Test name
Test status
Simulation time 106636880239 ps
CPU time 54.28 seconds
Started Sep 24 06:00:50 AM UTC 24
Finished Sep 24 06:01:46 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511960422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3511960422
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/3.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_alert_test.2678931639
Short name T625
Test name
Test status
Simulation time 14480687 ps
CPU time 0.9 seconds
Started Sep 24 06:19:09 AM UTC 24
Finished Sep 24 06:19:11 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678931639 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2678931639
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_fifo_full.2956664860
Short name T650
Test name
Test status
Simulation time 47653722497 ps
CPU time 117.53 seconds
Started Sep 24 06:18:39 AM UTC 24
Finished Sep 24 06:20:39 AM UTC 24
Peak memory 209316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956664860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.2956664860
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_fifo_overflow.2855536155
Short name T918
Test name
Test status
Simulation time 130466255600 ps
CPU time 740.99 seconds
Started Sep 24 06:18:42 AM UTC 24
Finished Sep 24 06:31:11 AM UTC 24
Peak memory 207556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855536155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2855536155
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_intr.1516055658
Short name T620
Test name
Test status
Simulation time 13633544483 ps
CPU time 3.23 seconds
Started Sep 24 06:18:44 AM UTC 24
Finished Sep 24 06:18:49 AM UTC 24
Peak memory 205552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516055658 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.1516055658
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_long_xfer_wo_dly.3260702220
Short name T732
Test name
Test status
Simulation time 145873203759 ps
CPU time 325.43 seconds
Started Sep 24 06:18:57 AM UTC 24
Finished Sep 24 06:24:27 AM UTC 24
Peak memory 209576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260702220 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3260702220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_loopback.3447845755
Short name T622
Test name
Test status
Simulation time 4779604881 ps
CPU time 10.52 seconds
Started Sep 24 06:18:50 AM UTC 24
Finished Sep 24 06:19:02 AM UTC 24
Peak memory 207952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447845755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3447845755
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_noise_filter.2502241335
Short name T431
Test name
Test status
Simulation time 16694470021 ps
CPU time 9.58 seconds
Started Sep 24 06:18:45 AM UTC 24
Finished Sep 24 06:18:56 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502241335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2502241335
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_perf.610753296
Short name T680
Test name
Test status
Simulation time 11761924890 ps
CPU time 204.73 seconds
Started Sep 24 06:18:53 AM UTC 24
Finished Sep 24 06:22:21 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610753296 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.610753296
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_rx_oversample.2799900964
Short name T619
Test name
Test status
Simulation time 4552849941 ps
CPU time 3.95 seconds
Started Sep 24 06:18:43 AM UTC 24
Finished Sep 24 06:18:48 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799900964 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2799900964
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_rx_parity_err.3290546441
Short name T698
Test name
Test status
Simulation time 115800146388 ps
CPU time 250.15 seconds
Started Sep 24 06:18:47 AM UTC 24
Finished Sep 24 06:23:01 AM UTC 24
Peak memory 203856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290546441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.3290546441
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_rx_start_bit_filter.1596547556
Short name T630
Test name
Test status
Simulation time 51572928520 ps
CPU time 29.98 seconds
Started Sep 24 06:18:46 AM UTC 24
Finished Sep 24 06:19:18 AM UTC 24
Peak memory 203640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596547556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1596547556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_smoke.493847559
Short name T614
Test name
Test status
Simulation time 716506332 ps
CPU time 3.86 seconds
Started Sep 24 06:18:33 AM UTC 24
Finished Sep 24 06:18:38 AM UTC 24
Peak memory 203732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493847559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.uart_smoke.493847559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_stress_all.2526888775
Short name T1174
Test name
Test status
Simulation time 213027955752 ps
CPU time 1560.27 seconds
Started Sep 24 06:19:02 AM UTC 24
Finished Sep 24 06:45:20 AM UTC 24
Peak memory 211512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526888775 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.2526888775
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_stress_all_with_rand_reset.443897917
Short name T634
Test name
Test status
Simulation time 41235606431 ps
CPU time 44.62 seconds
Started Sep 24 06:18:57 AM UTC 24
Finished Sep 24 06:19:43 AM UTC 24
Peak memory 222668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=443897917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all_
with_rand_reset.443897917
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_tx_ovrd.3213483873
Short name T626
Test name
Test status
Simulation time 13145514135 ps
CPU time 21.43 seconds
Started Sep 24 06:18:49 AM UTC 24
Finished Sep 24 06:19:12 AM UTC 24
Peak memory 203852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213483873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3213483873
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/30.uart_tx_rx.3579591751
Short name T671
Test name
Test status
Simulation time 166493581516 ps
CPU time 182.57 seconds
Started Sep 24 06:18:35 AM UTC 24
Finished Sep 24 06:21:40 AM UTC 24
Peak memory 204116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579591751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.3579591751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/30.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_alert_test.2820482591
Short name T637
Test name
Test status
Simulation time 33705348 ps
CPU time 0.89 seconds
Started Sep 24 06:19:57 AM UTC 24
Finished Sep 24 06:19:58 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820482591 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2820482591
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_fifo_full.1783550987
Short name T654
Test name
Test status
Simulation time 48578678379 ps
CPU time 90.97 seconds
Started Sep 24 06:19:13 AM UTC 24
Finished Sep 24 06:20:45 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783550987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1783550987
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_fifo_overflow.579239523
Short name T164
Test name
Test status
Simulation time 182028895020 ps
CPU time 184.35 seconds
Started Sep 24 06:19:13 AM UTC 24
Finished Sep 24 06:22:20 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579239523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.579239523
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_fifo_reset.149636543
Short name T227
Test name
Test status
Simulation time 308271221477 ps
CPU time 177.76 seconds
Started Sep 24 06:19:13 AM UTC 24
Finished Sep 24 06:22:13 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149636543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.149636543
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_intr.1273992147
Short name T632
Test name
Test status
Simulation time 5359942543 ps
CPU time 16.43 seconds
Started Sep 24 06:19:18 AM UTC 24
Finished Sep 24 06:19:35 AM UTC 24
Peak memory 209188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273992147 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1273992147
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_long_xfer_wo_dly.4002370298
Short name T687
Test name
Test status
Simulation time 87318292493 ps
CPU time 170.39 seconds
Started Sep 24 06:19:40 AM UTC 24
Finished Sep 24 06:22:33 AM UTC 24
Peak memory 209320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002370298 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.4002370298
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_loopback.3659122516
Short name T636
Test name
Test status
Simulation time 8752732552 ps
CPU time 18.39 seconds
Started Sep 24 06:19:36 AM UTC 24
Finished Sep 24 06:19:56 AM UTC 24
Peak memory 208112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659122516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3659122516
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_noise_filter.3430977539
Short name T706
Test name
Test status
Simulation time 175427636275 ps
CPU time 237.7 seconds
Started Sep 24 06:19:19 AM UTC 24
Finished Sep 24 06:23:20 AM UTC 24
Peak memory 209852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430977539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3430977539
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_perf.416512541
Short name T820
Test name
Test status
Simulation time 8328490621 ps
CPU time 468.34 seconds
Started Sep 24 06:19:38 AM UTC 24
Finished Sep 24 06:27:32 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416512541 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.416512541
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_rx_oversample.9296719
Short name T628
Test name
Test status
Simulation time 1509924794 ps
CPU time 1.98 seconds
Started Sep 24 06:19:14 AM UTC 24
Finished Sep 24 06:19:17 AM UTC 24
Peak memory 207360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9296719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM
_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.9296719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_rx_parity_err.660217761
Short name T643
Test name
Test status
Simulation time 131601128024 ps
CPU time 43.43 seconds
Started Sep 24 06:19:34 AM UTC 24
Finished Sep 24 06:20:19 AM UTC 24
Peak memory 203772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660217761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.660217761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_rx_start_bit_filter.4126558782
Short name T635
Test name
Test status
Simulation time 39863875313 ps
CPU time 32.84 seconds
Started Sep 24 06:19:19 AM UTC 24
Finished Sep 24 06:19:53 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126558782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4126558782
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_smoke.1069044390
Short name T627
Test name
Test status
Simulation time 813316086 ps
CPU time 1.15 seconds
Started Sep 24 06:19:10 AM UTC 24
Finished Sep 24 06:19:12 AM UTC 24
Peak memory 208504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069044390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1069044390
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_stress_all.814593008
Short name T211
Test name
Test status
Simulation time 229483177771 ps
CPU time 954.12 seconds
Started Sep 24 06:19:53 AM UTC 24
Finished Sep 24 06:35:58 AM UTC 24
Peak memory 212712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814593008 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.814593008
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_stress_all_with_rand_reset.1894338291
Short name T395
Test name
Test status
Simulation time 2215331607 ps
CPU time 10.5 seconds
Started Sep 24 06:19:44 AM UTC 24
Finished Sep 24 06:19:56 AM UTC 24
Peak memory 220344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1894338291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all
_with_rand_reset.1894338291
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_tx_ovrd.4177622064
Short name T633
Test name
Test status
Simulation time 430465960 ps
CPU time 1.44 seconds
Started Sep 24 06:19:35 AM UTC 24
Finished Sep 24 06:19:38 AM UTC 24
Peak memory 203280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177622064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.4177622064
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/31.uart_tx_rx.3719193564
Short name T640
Test name
Test status
Simulation time 43225359855 ps
CPU time 48.64 seconds
Started Sep 24 06:19:11 AM UTC 24
Finished Sep 24 06:20:02 AM UTC 24
Peak memory 209260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719193564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3719193564
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/31.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_alert_test.928743264
Short name T651
Test name
Test status
Simulation time 53344372 ps
CPU time 0.85 seconds
Started Sep 24 06:20:40 AM UTC 24
Finished Sep 24 06:20:42 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928743264 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.928743264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_fifo_full.2997835306
Short name T685
Test name
Test status
Simulation time 231389626508 ps
CPU time 143.81 seconds
Started Sep 24 06:20:00 AM UTC 24
Finished Sep 24 06:22:26 AM UTC 24
Peak memory 209608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997835306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2997835306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_fifo_overflow.2780794269
Short name T644
Test name
Test status
Simulation time 12249792700 ps
CPU time 20 seconds
Started Sep 24 06:20:01 AM UTC 24
Finished Sep 24 06:20:22 AM UTC 24
Peak memory 209128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780794269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2780794269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_fifo_reset.1265793635
Short name T648
Test name
Test status
Simulation time 51426152618 ps
CPU time 26.47 seconds
Started Sep 24 06:20:02 AM UTC 24
Finished Sep 24 06:20:30 AM UTC 24
Peak memory 209516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265793635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1265793635
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_intr.60470507
Short name T657
Test name
Test status
Simulation time 29146307664 ps
CPU time 57.11 seconds
Started Sep 24 06:20:08 AM UTC 24
Finished Sep 24 06:21:07 AM UTC 24
Peak memory 204052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60470507 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.60470507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_long_xfer_wo_dly.4219899475
Short name T917
Test name
Test status
Simulation time 62566429335 ps
CPU time 631.24 seconds
Started Sep 24 06:20:31 AM UTC 24
Finished Sep 24 06:31:10 AM UTC 24
Peak memory 212596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219899475 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.4219899475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_loopback.2780800721
Short name T647
Test name
Test status
Simulation time 1206144259 ps
CPU time 1.79 seconds
Started Sep 24 06:20:26 AM UTC 24
Finished Sep 24 06:20:29 AM UTC 24
Peak memory 203376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780800721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2780800721
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_noise_filter.422648012
Short name T411
Test name
Test status
Simulation time 49821067879 ps
CPU time 51.05 seconds
Started Sep 24 06:20:09 AM UTC 24
Finished Sep 24 06:21:02 AM UTC 24
Peak memory 208868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422648012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.422648012
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_perf.784445469
Short name T978
Test name
Test status
Simulation time 18883361396 ps
CPU time 788 seconds
Started Sep 24 06:20:27 AM UTC 24
Finished Sep 24 06:33:44 AM UTC 24
Peak memory 207228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784445469 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.784445469
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_rx_oversample.3696788821
Short name T652
Test name
Test status
Simulation time 4422850662 ps
CPU time 35.72 seconds
Started Sep 24 06:20:07 AM UTC 24
Finished Sep 24 06:20:44 AM UTC 24
Peak memory 208404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696788821 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3696788821
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_rx_parity_err.2916467620
Short name T168
Test name
Test status
Simulation time 116386764170 ps
CPU time 227.29 seconds
Started Sep 24 06:20:22 AM UTC 24
Finished Sep 24 06:24:13 AM UTC 24
Peak memory 209448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916467620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2916467620
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_rx_start_bit_filter.1299527208
Short name T646
Test name
Test status
Simulation time 3132512919 ps
CPU time 4.5 seconds
Started Sep 24 06:20:20 AM UTC 24
Finished Sep 24 06:20:26 AM UTC 24
Peak memory 203512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299527208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1299527208
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_smoke.3129791379
Short name T638
Test name
Test status
Simulation time 109546173 ps
CPU time 1.36 seconds
Started Sep 24 06:19:57 AM UTC 24
Finished Sep 24 06:19:59 AM UTC 24
Peak memory 207364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129791379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_smoke.3129791379
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_stress_all_with_rand_reset.2869917086
Short name T418
Test name
Test status
Simulation time 13509583598 ps
CPU time 58.28 seconds
Started Sep 24 06:20:31 AM UTC 24
Finished Sep 24 06:21:31 AM UTC 24
Peak memory 218232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2869917086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all
_with_rand_reset.2869917086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_tx_ovrd.555742299
Short name T649
Test name
Test status
Simulation time 949553992 ps
CPU time 9.22 seconds
Started Sep 24 06:20:23 AM UTC 24
Finished Sep 24 06:20:34 AM UTC 24
Peak memory 203728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555742299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.555742299
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/32.uart_tx_rx.4095007212
Short name T661
Test name
Test status
Simulation time 28044755315 ps
CPU time 80.49 seconds
Started Sep 24 06:20:00 AM UTC 24
Finished Sep 24 06:21:22 AM UTC 24
Peak memory 204056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095007212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.4095007212
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/32.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_alert_test.1749647284
Short name T667
Test name
Test status
Simulation time 69026606 ps
CPU time 0.86 seconds
Started Sep 24 06:21:32 AM UTC 24
Finished Sep 24 06:21:34 AM UTC 24
Peak memory 203312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749647284 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1749647284
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_fifo_full.4025098220
Short name T775
Test name
Test status
Simulation time 170073069138 ps
CPU time 321.04 seconds
Started Sep 24 06:20:46 AM UTC 24
Finished Sep 24 06:26:12 AM UTC 24
Peak memory 209468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025098220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.4025098220
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_fifo_overflow.1597379918
Short name T669
Test name
Test status
Simulation time 24581090450 ps
CPU time 48.31 seconds
Started Sep 24 06:20:46 AM UTC 24
Finished Sep 24 06:21:36 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597379918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1597379918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_intr.223703024
Short name T673
Test name
Test status
Simulation time 49179983477 ps
CPU time 50.97 seconds
Started Sep 24 06:21:05 AM UTC 24
Finished Sep 24 06:21:58 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223703024 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.223703024
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_long_xfer_wo_dly.857243586
Short name T757
Test name
Test status
Simulation time 87502228549 ps
CPU time 235.14 seconds
Started Sep 24 06:21:26 AM UTC 24
Finished Sep 24 06:25:25 AM UTC 24
Peak memory 209596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857243586 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.857243586
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_loopback.2764276572
Short name T672
Test name
Test status
Simulation time 9050995092 ps
CPU time 32.85 seconds
Started Sep 24 06:21:23 AM UTC 24
Finished Sep 24 06:21:57 AM UTC 24
Peak memory 209492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764276572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.uart_loopback.2764276572
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_noise_filter.638084810
Short name T684
Test name
Test status
Simulation time 96057557533 ps
CPU time 76.17 seconds
Started Sep 24 06:21:07 AM UTC 24
Finished Sep 24 06:22:26 AM UTC 24
Peak memory 218700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638084810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.638084810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_perf.1541767647
Short name T843
Test name
Test status
Simulation time 8268614800 ps
CPU time 409.05 seconds
Started Sep 24 06:21:24 AM UTC 24
Finished Sep 24 06:28:18 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541767647 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1541767647
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_rx_oversample.1443763661
Short name T665
Test name
Test status
Simulation time 3155143190 ps
CPU time 25.91 seconds
Started Sep 24 06:21:02 AM UTC 24
Finished Sep 24 06:21:29 AM UTC 24
Peak memory 203776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443763661 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.1443763661
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_rx_parity_err.3175773843
Short name T676
Test name
Test status
Simulation time 30251056571 ps
CPU time 53.22 seconds
Started Sep 24 06:21:14 AM UTC 24
Finished Sep 24 06:22:08 AM UTC 24
Peak memory 203912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175773843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3175773843
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_rx_start_bit_filter.804874306
Short name T664
Test name
Test status
Simulation time 4489190965 ps
CPU time 15.85 seconds
Started Sep 24 06:21:09 AM UTC 24
Finished Sep 24 06:21:26 AM UTC 24
Peak memory 203584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804874306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.804874306
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_smoke.3629058594
Short name T653
Test name
Test status
Simulation time 110810126 ps
CPU time 1.33 seconds
Started Sep 24 06:20:43 AM UTC 24
Finished Sep 24 06:20:45 AM UTC 24
Peak memory 203380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629058594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3629058594
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_stress_all.515771970
Short name T744
Test name
Test status
Simulation time 649484650289 ps
CPU time 202.34 seconds
Started Sep 24 06:21:30 AM UTC 24
Finished Sep 24 06:24:56 AM UTC 24
Peak memory 205812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515771970 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.515771970
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_stress_all_with_rand_reset.1462244041
Short name T678
Test name
Test status
Simulation time 2474448935 ps
CPU time 47.02 seconds
Started Sep 24 06:21:26 AM UTC 24
Finished Sep 24 06:22:15 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1462244041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all
_with_rand_reset.1462244041
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_tx_ovrd.758982991
Short name T663
Test name
Test status
Simulation time 733632132 ps
CPU time 4.97 seconds
Started Sep 24 06:21:19 AM UTC 24
Finished Sep 24 06:21:25 AM UTC 24
Peak memory 203724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758982991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.758982991
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/33.uart_tx_rx.446829449
Short name T659
Test name
Test status
Simulation time 32687550276 ps
CPU time 26.18 seconds
Started Sep 24 06:20:45 AM UTC 24
Finished Sep 24 06:21:12 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446829449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.446829449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/33.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_alert_test.3632568178
Short name T682
Test name
Test status
Simulation time 94608853 ps
CPU time 0.88 seconds
Started Sep 24 06:22:21 AM UTC 24
Finished Sep 24 06:22:23 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632568178 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3632568178
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_fifo_full.3756610207
Short name T849
Test name
Test status
Simulation time 164780989844 ps
CPU time 407.62 seconds
Started Sep 24 06:21:36 AM UTC 24
Finished Sep 24 06:28:29 AM UTC 24
Peak memory 209280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756610207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3756610207
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_fifo_overflow.2035928055
Short name T690
Test name
Test status
Simulation time 33719354446 ps
CPU time 59.57 seconds
Started Sep 24 06:21:36 AM UTC 24
Finished Sep 24 06:22:38 AM UTC 24
Peak memory 209452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035928055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.2035928055
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_fifo_reset.187210142
Short name T197
Test name
Test status
Simulation time 107850683093 ps
CPU time 182.4 seconds
Started Sep 24 06:21:37 AM UTC 24
Finished Sep 24 06:24:42 AM UTC 24
Peak memory 209460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187210142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.187210142
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_intr.805574320
Short name T705
Test name
Test status
Simulation time 55691694166 ps
CPU time 72.04 seconds
Started Sep 24 06:21:58 AM UTC 24
Finished Sep 24 06:23:12 AM UTC 24
Peak memory 209396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805574320 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.805574320
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_long_xfer_wo_dly.1489431956
Short name T756
Test name
Test status
Simulation time 43171166847 ps
CPU time 182.23 seconds
Started Sep 24 06:22:17 AM UTC 24
Finished Sep 24 06:25:23 AM UTC 24
Peak memory 209260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489431956 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1489431956
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_loopback.3538770459
Short name T688
Test name
Test status
Simulation time 6273500332 ps
CPU time 18.96 seconds
Started Sep 24 06:22:14 AM UTC 24
Finished Sep 24 06:22:34 AM UTC 24
Peak memory 208464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538770459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3538770459
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_noise_filter.2844770189
Short name T683
Test name
Test status
Simulation time 15314095099 ps
CPU time 24.41 seconds
Started Sep 24 06:21:59 AM UTC 24
Finished Sep 24 06:22:25 AM UTC 24
Peak memory 209596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844770189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2844770189
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_perf.1510367184
Short name T702
Test name
Test status
Simulation time 5207954430 ps
CPU time 48.67 seconds
Started Sep 24 06:22:15 AM UTC 24
Finished Sep 24 06:23:06 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510367184 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1510367184
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_rx_oversample.3852866466
Short name T681
Test name
Test status
Simulation time 6286481539 ps
CPU time 40.32 seconds
Started Sep 24 06:21:42 AM UTC 24
Finished Sep 24 06:22:23 AM UTC 24
Peak memory 208396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852866466 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.3852866466
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_rx_parity_err.1841050215
Short name T696
Test name
Test status
Simulation time 107824322077 ps
CPU time 49.97 seconds
Started Sep 24 06:22:05 AM UTC 24
Finished Sep 24 06:22:56 AM UTC 24
Peak memory 209600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841050215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1841050215
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_rx_start_bit_filter.1585793896
Short name T675
Test name
Test status
Simulation time 911088394 ps
CPU time 1.7 seconds
Started Sep 24 06:22:01 AM UTC 24
Finished Sep 24 06:22:04 AM UTC 24
Peak memory 203376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585793896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1585793896
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_smoke.1773458556
Short name T668
Test name
Test status
Simulation time 142703633 ps
CPU time 1.13 seconds
Started Sep 24 06:21:33 AM UTC 24
Finished Sep 24 06:21:35 AM UTC 24
Peak memory 203380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773458556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_smoke.1773458556
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_stress_all.149183779
Short name T432
Test name
Test status
Simulation time 76568722668 ps
CPU time 117.35 seconds
Started Sep 24 06:22:21 AM UTC 24
Finished Sep 24 06:24:21 AM UTC 24
Peak memory 220484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149183779 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.149183779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_stress_all_with_rand_reset.3106195427
Short name T210
Test name
Test status
Simulation time 3378774664 ps
CPU time 105.18 seconds
Started Sep 24 06:22:17 AM UTC 24
Finished Sep 24 06:24:05 AM UTC 24
Peak memory 222324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3106195427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all
_with_rand_reset.3106195427
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_tx_ovrd.827407743
Short name T686
Test name
Test status
Simulation time 6238411701 ps
CPU time 21.15 seconds
Started Sep 24 06:22:09 AM UTC 24
Finished Sep 24 06:22:31 AM UTC 24
Peak memory 203716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827407743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.827407743
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/34.uart_tx_rx.4272994848
Short name T409
Test name
Test status
Simulation time 70738060956 ps
CPU time 71.06 seconds
Started Sep 24 06:21:35 AM UTC 24
Finished Sep 24 06:22:48 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272994848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.4272994848
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/34.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_alert_test.3885172236
Short name T697
Test name
Test status
Simulation time 36341277 ps
CPU time 0.83 seconds
Started Sep 24 06:22:57 AM UTC 24
Finished Sep 24 06:22:59 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885172236 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3885172236
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_fifo_full.3237597349
Short name T407
Test name
Test status
Simulation time 158595874725 ps
CPU time 139.44 seconds
Started Sep 24 06:22:26 AM UTC 24
Finished Sep 24 06:24:48 AM UTC 24
Peak memory 209208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237597349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3237597349
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_fifo_overflow.2894377344
Short name T162
Test name
Test status
Simulation time 135142971763 ps
CPU time 52.37 seconds
Started Sep 24 06:22:27 AM UTC 24
Finished Sep 24 06:23:21 AM UTC 24
Peak memory 209500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894377344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.2894377344
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_fifo_reset.3793064317
Short name T716
Test name
Test status
Simulation time 77948095443 ps
CPU time 75.09 seconds
Started Sep 24 06:22:27 AM UTC 24
Finished Sep 24 06:23:44 AM UTC 24
Peak memory 209216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793064317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3793064317
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_intr.4220849676
Short name T721
Test name
Test status
Simulation time 52638512374 ps
CPU time 82.79 seconds
Started Sep 24 06:22:34 AM UTC 24
Finished Sep 24 06:23:59 AM UTC 24
Peak memory 203712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220849676 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.4220849676
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_long_xfer_wo_dly.892905618
Short name T1049
Test name
Test status
Simulation time 118569700625 ps
CPU time 801.38 seconds
Started Sep 24 06:22:49 AM UTC 24
Finished Sep 24 06:36:19 AM UTC 24
Peak memory 212720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892905618 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.892905618
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_loopback.3778130291
Short name T693
Test name
Test status
Simulation time 1314682398 ps
CPU time 1.66 seconds
Started Sep 24 06:22:43 AM UTC 24
Finished Sep 24 06:22:46 AM UTC 24
Peak memory 203376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778130291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3778130291
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_noise_filter.2961142237
Short name T730
Test name
Test status
Simulation time 47238491034 ps
CPU time 100.78 seconds
Started Sep 24 06:22:35 AM UTC 24
Finished Sep 24 06:24:18 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961142237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2961142237
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_perf.1271881627
Short name T755
Test name
Test status
Simulation time 14988755828 ps
CPU time 153.42 seconds
Started Sep 24 06:22:47 AM UTC 24
Finished Sep 24 06:25:23 AM UTC 24
Peak memory 209196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271881627 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1271881627
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_rx_oversample.3214002919
Short name T695
Test name
Test status
Simulation time 5160243070 ps
CPU time 18.65 seconds
Started Sep 24 06:22:32 AM UTC 24
Finished Sep 24 06:22:52 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214002919 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3214002919
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_rx_parity_err.3964398004
Short name T717
Test name
Test status
Simulation time 21861899625 ps
CPU time 64.54 seconds
Started Sep 24 06:22:38 AM UTC 24
Finished Sep 24 06:23:44 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964398004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3964398004
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_rx_start_bit_filter.844116990
Short name T704
Test name
Test status
Simulation time 33891181099 ps
CPU time 26.35 seconds
Started Sep 24 06:22:38 AM UTC 24
Finished Sep 24 06:23:06 AM UTC 24
Peak memory 205632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844116990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.844116990
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_smoke.1798218812
Short name T689
Test name
Test status
Simulation time 977423914 ps
CPU time 11.38 seconds
Started Sep 24 06:22:25 AM UTC 24
Finished Sep 24 06:22:37 AM UTC 24
Peak memory 203660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798218812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1798218812
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_stress_all.2754387378
Short name T866
Test name
Test status
Simulation time 142432023538 ps
CPU time 357.57 seconds
Started Sep 24 06:22:53 AM UTC 24
Finished Sep 24 06:28:55 AM UTC 24
Peak memory 206140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754387378 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2754387378
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_stress_all_with_rand_reset.2721293842
Short name T709
Test name
Test status
Simulation time 3653018968 ps
CPU time 32.63 seconds
Started Sep 24 06:22:50 AM UTC 24
Finished Sep 24 06:23:24 AM UTC 24
Peak memory 210032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2721293842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all
_with_rand_reset.2721293842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_tx_ovrd.2973319549
Short name T694
Test name
Test status
Simulation time 1068140388 ps
CPU time 5.32 seconds
Started Sep 24 06:22:42 AM UTC 24
Finished Sep 24 06:22:49 AM UTC 24
Peak memory 204056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973319549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.2973319549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/35.uart_tx_rx.4011695999
Short name T731
Test name
Test status
Simulation time 195396550567 ps
CPU time 117.49 seconds
Started Sep 24 06:22:25 AM UTC 24
Finished Sep 24 06:24:24 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011695999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.4011695999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/35.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_alert_test.1800425838
Short name T713
Test name
Test status
Simulation time 36402111 ps
CPU time 0.82 seconds
Started Sep 24 06:23:32 AM UTC 24
Finished Sep 24 06:23:34 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800425838 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1800425838
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_fifo_full.403921482
Short name T715
Test name
Test status
Simulation time 31020747333 ps
CPU time 40.06 seconds
Started Sep 24 06:23:02 AM UTC 24
Finished Sep 24 06:23:44 AM UTC 24
Peak memory 209324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403921482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.403921482
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_fifo_overflow.1426740830
Short name T712
Test name
Test status
Simulation time 10046127270 ps
CPU time 27.75 seconds
Started Sep 24 06:23:03 AM UTC 24
Finished Sep 24 06:23:32 AM UTC 24
Peak memory 209152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426740830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1426740830
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_fifo_reset.3161130673
Short name T733
Test name
Test status
Simulation time 66977929865 ps
CPU time 82.07 seconds
Started Sep 24 06:23:04 AM UTC 24
Finished Sep 24 06:24:28 AM UTC 24
Peak memory 209244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161130673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3161130673
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_intr.326069450
Short name T714
Test name
Test status
Simulation time 16010082209 ps
CPU time 31.47 seconds
Started Sep 24 06:23:06 AM UTC 24
Finished Sep 24 06:23:39 AM UTC 24
Peak memory 209188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326069450 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.326069450
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_long_xfer_wo_dly.1259958670
Short name T1011
Test name
Test status
Simulation time 82266971494 ps
CPU time 685.68 seconds
Started Sep 24 06:23:23 AM UTC 24
Finished Sep 24 06:34:57 AM UTC 24
Peak memory 212840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259958670 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1259958670
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_loopback.562370632
Short name T710
Test name
Test status
Simulation time 81797064 ps
CPU time 1.13 seconds
Started Sep 24 06:23:22 AM UTC 24
Finished Sep 24 06:23:24 AM UTC 24
Peak memory 203436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562370632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.uart_loopback.562370632
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_noise_filter.34583765
Short name T770
Test name
Test status
Simulation time 123097950791 ps
CPU time 167.36 seconds
Started Sep 24 06:23:06 AM UTC 24
Finished Sep 24 06:25:56 AM UTC 24
Peak memory 218704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34583765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.34583765
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_perf.1443586553
Short name T809
Test name
Test status
Simulation time 17203764972 ps
CPU time 231.28 seconds
Started Sep 24 06:23:22 AM UTC 24
Finished Sep 24 06:27:17 AM UTC 24
Peak memory 203768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443586553 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1443586553
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_rx_oversample.1245406093
Short name T722
Test name
Test status
Simulation time 4776654033 ps
CPU time 54.91 seconds
Started Sep 24 06:23:05 AM UTC 24
Finished Sep 24 06:24:02 AM UTC 24
Peak memory 208772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245406093 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.1245406093
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_rx_parity_err.496801918
Short name T707
Test name
Test status
Simulation time 9273250889 ps
CPU time 7.22 seconds
Started Sep 24 06:23:13 AM UTC 24
Finished Sep 24 06:23:21 AM UTC 24
Peak memory 203776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496801918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.496801918
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_rx_start_bit_filter.1657087109
Short name T708
Test name
Test status
Simulation time 3225244828 ps
CPU time 10.79 seconds
Started Sep 24 06:23:10 AM UTC 24
Finished Sep 24 06:23:21 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657087109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1657087109
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_smoke.3097606545
Short name T700
Test name
Test status
Simulation time 299310761 ps
CPU time 1.76 seconds
Started Sep 24 06:23:00 AM UTC 24
Finished Sep 24 06:23:03 AM UTC 24
Peak memory 203332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097606545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3097606545
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_stress_all.2956404042
Short name T877
Test name
Test status
Simulation time 122806571284 ps
CPU time 358.63 seconds
Started Sep 24 06:23:25 AM UTC 24
Finished Sep 24 06:29:29 AM UTC 24
Peak memory 206144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956404042 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2956404042
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_tx_ovrd.3939513979
Short name T711
Test name
Test status
Simulation time 10145578713 ps
CPU time 9.23 seconds
Started Sep 24 06:23:21 AM UTC 24
Finished Sep 24 06:23:32 AM UTC 24
Peak memory 207964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939513979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3939513979
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/36.uart_tx_rx.3827952225
Short name T758
Test name
Test status
Simulation time 48042790966 ps
CPU time 146.67 seconds
Started Sep 24 06:23:02 AM UTC 24
Finished Sep 24 06:25:31 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827952225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.3827952225
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/36.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_alert_test.817410183
Short name T727
Test name
Test status
Simulation time 25793087 ps
CPU time 0.83 seconds
Started Sep 24 06:24:09 AM UTC 24
Finished Sep 24 06:24:10 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817410183 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.817410183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_fifo_full.2292512754
Short name T747
Test name
Test status
Simulation time 131505049063 ps
CPU time 81.04 seconds
Started Sep 24 06:23:40 AM UTC 24
Finished Sep 24 06:25:04 AM UTC 24
Peak memory 209196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292512754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2292512754
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_fifo_overflow.343494155
Short name T743
Test name
Test status
Simulation time 67298305532 ps
CPU time 66.23 seconds
Started Sep 24 06:23:45 AM UTC 24
Finished Sep 24 06:24:53 AM UTC 24
Peak memory 204100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343494155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.343494155
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_fifo_reset.2655452429
Short name T243
Test name
Test status
Simulation time 381495553252 ps
CPU time 239.87 seconds
Started Sep 24 06:23:46 AM UTC 24
Finished Sep 24 06:27:49 AM UTC 24
Peak memory 209156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655452429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2655452429
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_long_xfer_wo_dly.3660350577
Short name T831
Test name
Test status
Simulation time 157562173992 ps
CPU time 223.34 seconds
Started Sep 24 06:24:05 AM UTC 24
Finished Sep 24 06:27:52 AM UTC 24
Peak memory 209516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660350577 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3660350577
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_loopback.3752999404
Short name T728
Test name
Test status
Simulation time 10094933328 ps
CPU time 8.7 seconds
Started Sep 24 06:24:03 AM UTC 24
Finished Sep 24 06:24:13 AM UTC 24
Peak memory 209544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752999404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3752999404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_noise_filter.1012244946
Short name T788
Test name
Test status
Simulation time 38730335623 ps
CPU time 152.23 seconds
Started Sep 24 06:23:55 AM UTC 24
Finished Sep 24 06:26:30 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012244946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1012244946
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_perf.837231107
Short name T767
Test name
Test status
Simulation time 15621153285 ps
CPU time 107.39 seconds
Started Sep 24 06:24:04 AM UTC 24
Finished Sep 24 06:25:54 AM UTC 24
Peak memory 203776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837231107 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.837231107
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_rx_oversample.2985862305
Short name T720
Test name
Test status
Simulation time 1477547723 ps
CPU time 7.85 seconds
Started Sep 24 06:23:46 AM UTC 24
Finished Sep 24 06:23:55 AM UTC 24
Peak memory 207700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985862305 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2985862305
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_rx_parity_err.1744113582
Short name T783
Test name
Test status
Simulation time 344019078559 ps
CPU time 139.33 seconds
Started Sep 24 06:23:59 AM UTC 24
Finished Sep 24 06:26:21 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744113582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1744113582
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_rx_start_bit_filter.1248654451
Short name T725
Test name
Test status
Simulation time 2828249801 ps
CPU time 10.19 seconds
Started Sep 24 06:23:56 AM UTC 24
Finished Sep 24 06:24:07 AM UTC 24
Peak memory 203704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248654451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1248654451
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_smoke.793868419
Short name T723
Test name
Test status
Simulation time 5900140140 ps
CPU time 27.22 seconds
Started Sep 24 06:23:33 AM UTC 24
Finished Sep 24 06:24:02 AM UTC 24
Peak memory 203776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793868419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.uart_smoke.793868419
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_stress_all.1958681073
Short name T189
Test name
Test status
Simulation time 42854758195 ps
CPU time 623.77 seconds
Started Sep 24 06:24:08 AM UTC 24
Finished Sep 24 06:34:40 AM UTC 24
Peak memory 212688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958681073 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1958681073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_stress_all_with_rand_reset.2582248362
Short name T740
Test name
Test status
Simulation time 46688946790 ps
CPU time 33.7 seconds
Started Sep 24 06:24:08 AM UTC 24
Finished Sep 24 06:24:43 AM UTC 24
Peak memory 226148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2582248362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all
_with_rand_reset.2582248362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_tx_ovrd.706996604
Short name T735
Test name
Test status
Simulation time 6346168014 ps
CPU time 25.95 seconds
Started Sep 24 06:24:03 AM UTC 24
Finished Sep 24 06:24:30 AM UTC 24
Peak memory 203796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706996604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.706996604
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/37.uart_tx_rx.3182384571
Short name T726
Test name
Test status
Simulation time 47099321636 ps
CPU time 31.7 seconds
Started Sep 24 06:23:34 AM UTC 24
Finished Sep 24 06:24:07 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182384571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.3182384571
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/37.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_alert_test.1947396508
Short name T741
Test name
Test status
Simulation time 18052134 ps
CPU time 0.88 seconds
Started Sep 24 06:24:43 AM UTC 24
Finished Sep 24 06:24:45 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947396508 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1947396508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_fifo_full.3517975101
Short name T748
Test name
Test status
Simulation time 13925000137 ps
CPU time 50.01 seconds
Started Sep 24 06:24:14 AM UTC 24
Finished Sep 24 06:25:05 AM UTC 24
Peak memory 209584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517975101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3517975101
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_fifo_overflow.2046212263
Short name T742
Test name
Test status
Simulation time 38460990990 ps
CPU time 35.13 seconds
Started Sep 24 06:24:14 AM UTC 24
Finished Sep 24 06:24:50 AM UTC 24
Peak memory 204096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046212263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2046212263
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_intr.3937487411
Short name T844
Test name
Test status
Simulation time 169182030594 ps
CPU time 232.06 seconds
Started Sep 24 06:24:25 AM UTC 24
Finished Sep 24 06:28:20 AM UTC 24
Peak memory 205624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937487411 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3937487411
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_long_xfer_wo_dly.1061650392
Short name T874
Test name
Test status
Simulation time 66749672503 ps
CPU time 272.85 seconds
Started Sep 24 06:24:36 AM UTC 24
Finished Sep 24 06:29:13 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061650392 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1061650392
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_loopback.1702733448
Short name T739
Test name
Test status
Simulation time 6086594976 ps
CPU time 6.71 seconds
Started Sep 24 06:24:32 AM UTC 24
Finished Sep 24 06:24:39 AM UTC 24
Peak memory 208260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702733448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1702733448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_noise_filter.3480427506
Short name T768
Test name
Test status
Simulation time 47195179942 ps
CPU time 84.06 seconds
Started Sep 24 06:24:28 AM UTC 24
Finished Sep 24 06:25:54 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480427506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3480427506
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_perf.3146391999
Short name T840
Test name
Test status
Simulation time 16000459867 ps
CPU time 218.37 seconds
Started Sep 24 06:24:32 AM UTC 24
Finished Sep 24 06:28:13 AM UTC 24
Peak memory 203780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146391999 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3146391999
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_rx_oversample.1163065230
Short name T745
Test name
Test status
Simulation time 4108648558 ps
CPU time 36.52 seconds
Started Sep 24 06:24:22 AM UTC 24
Finished Sep 24 06:25:00 AM UTC 24
Peak memory 209092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163065230 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.1163065230
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_rx_parity_err.3578473510
Short name T860
Test name
Test status
Simulation time 96191170215 ps
CPU time 253.89 seconds
Started Sep 24 06:24:29 AM UTC 24
Finished Sep 24 06:28:47 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578473510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.3578473510
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_rx_start_bit_filter.1613961712
Short name T737
Test name
Test status
Simulation time 41322464442 ps
CPU time 5.55 seconds
Started Sep 24 06:24:28 AM UTC 24
Finished Sep 24 06:24:35 AM UTC 24
Peak memory 205624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613961712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1613961712
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_smoke.2870052132
Short name T729
Test name
Test status
Simulation time 733541620 ps
CPU time 1.54 seconds
Started Sep 24 06:24:11 AM UTC 24
Finished Sep 24 06:24:13 AM UTC 24
Peak memory 203328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870052132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2870052132
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_stress_all.2537930784
Short name T886
Test name
Test status
Simulation time 104183563543 ps
CPU time 316.2 seconds
Started Sep 24 06:24:40 AM UTC 24
Finished Sep 24 06:30:00 AM UTC 24
Peak memory 206068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537930784 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.2537930784
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_stress_all_with_rand_reset.4159339626
Short name T777
Test name
Test status
Simulation time 3988957260 ps
CPU time 97.89 seconds
Started Sep 24 06:24:36 AM UTC 24
Finished Sep 24 06:26:16 AM UTC 24
Peak memory 220604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4159339626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all
_with_rand_reset.4159339626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_tx_ovrd.1568086304
Short name T738
Test name
Test status
Simulation time 2015903926 ps
CPU time 3.58 seconds
Started Sep 24 06:24:30 AM UTC 24
Finished Sep 24 06:24:35 AM UTC 24
Peak memory 208132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568086304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1568086304
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/38.uart_tx_rx.2304557480
Short name T734
Test name
Test status
Simulation time 4688359266 ps
CPU time 14.47 seconds
Started Sep 24 06:24:14 AM UTC 24
Finished Sep 24 06:24:29 AM UTC 24
Peak memory 209016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304557480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2304557480
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/38.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_alert_test.483559087
Short name T677
Test name
Test status
Simulation time 22593368 ps
CPU time 0.88 seconds
Started Sep 24 06:25:18 AM UTC 24
Finished Sep 24 06:25:20 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483559087 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.483559087
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_fifo_full.2839512100
Short name T152
Test name
Test status
Simulation time 71949493507 ps
CPU time 83.54 seconds
Started Sep 24 06:24:45 AM UTC 24
Finished Sep 24 06:26:11 AM UTC 24
Peak memory 203800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839512100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2839512100
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_fifo_overflow.2737421311
Short name T752
Test name
Test status
Simulation time 113097872568 ps
CPU time 25 seconds
Started Sep 24 06:24:48 AM UTC 24
Finished Sep 24 06:25:15 AM UTC 24
Peak memory 209192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737421311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2737421311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_fifo_reset.2851210986
Short name T835
Test name
Test status
Simulation time 107094938666 ps
CPU time 189.79 seconds
Started Sep 24 06:24:51 AM UTC 24
Finished Sep 24 06:28:05 AM UTC 24
Peak memory 209200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851210986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2851210986
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_intr.117964294
Short name T703
Test name
Test status
Simulation time 23321607303 ps
CPU time 19.18 seconds
Started Sep 24 06:24:57 AM UTC 24
Finished Sep 24 06:25:17 AM UTC 24
Peak memory 204112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117964294 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.117964294
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_long_xfer_wo_dly.1736722834
Short name T947
Test name
Test status
Simulation time 258925156189 ps
CPU time 422.64 seconds
Started Sep 24 06:25:10 AM UTC 24
Finished Sep 24 06:32:19 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736722834 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1736722834
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_loopback.853922569
Short name T754
Test name
Test status
Simulation time 3963117910 ps
CPU time 9.79 seconds
Started Sep 24 06:25:07 AM UTC 24
Finished Sep 24 06:25:18 AM UTC 24
Peak memory 208184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853922569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_loopback.853922569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_noise_filter.2933638810
Short name T760
Test name
Test status
Simulation time 45963585039 ps
CPU time 34.56 seconds
Started Sep 24 06:25:01 AM UTC 24
Finished Sep 24 06:25:37 AM UTC 24
Peak memory 208964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933638810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.2933638810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_perf.325952303
Short name T885
Test name
Test status
Simulation time 7606985089 ps
CPU time 275.95 seconds
Started Sep 24 06:25:08 AM UTC 24
Finished Sep 24 06:29:48 AM UTC 24
Peak memory 204112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325952303 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.325952303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_rx_oversample.3099945491
Short name T746
Test name
Test status
Simulation time 2972015267 ps
CPU time 7.34 seconds
Started Sep 24 06:24:54 AM UTC 24
Finished Sep 24 06:25:02 AM UTC 24
Peak memory 208200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099945491 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3099945491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_rx_parity_err.3692546242
Short name T759
Test name
Test status
Simulation time 31733425397 ps
CPU time 25.2 seconds
Started Sep 24 06:25:05 AM UTC 24
Finished Sep 24 06:25:31 AM UTC 24
Peak memory 204024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692546242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3692546242
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_rx_start_bit_filter.2265184758
Short name T749
Test name
Test status
Simulation time 4522053051 ps
CPU time 2.54 seconds
Started Sep 24 06:25:03 AM UTC 24
Finished Sep 24 06:25:06 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265184758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2265184758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_smoke.3139827893
Short name T753
Test name
Test status
Simulation time 6019459257 ps
CPU time 31.11 seconds
Started Sep 24 06:24:44 AM UTC 24
Finished Sep 24 06:25:17 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139827893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3139827893
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_stress_all.1429942292
Short name T257
Test name
Test status
Simulation time 111253131624 ps
CPU time 1422.7 seconds
Started Sep 24 06:25:17 AM UTC 24
Finished Sep 24 06:49:18 AM UTC 24
Peak memory 209208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429942292 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1429942292
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_stress_all_with_rand_reset.1686088746
Short name T762
Test name
Test status
Simulation time 2975484011 ps
CPU time 21.64 seconds
Started Sep 24 06:25:15 AM UTC 24
Finished Sep 24 06:25:38 AM UTC 24
Peak memory 220352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1686088746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all
_with_rand_reset.1686088746
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_tx_ovrd.1235459931
Short name T751
Test name
Test status
Simulation time 1443015396 ps
CPU time 2.38 seconds
Started Sep 24 06:25:06 AM UTC 24
Finished Sep 24 06:25:09 AM UTC 24
Peak memory 203928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235459931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1235459931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/39.uart_tx_rx.4123963449
Short name T787
Test name
Test status
Simulation time 45822828884 ps
CPU time 101.56 seconds
Started Sep 24 06:24:45 AM UTC 24
Finished Sep 24 06:26:29 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123963449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4123963449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/39.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_alert_test.100431091
Short name T436
Test name
Test status
Simulation time 16180152 ps
CPU time 0.9 seconds
Started Sep 24 06:02:20 AM UTC 24
Finished Sep 24 06:02:22 AM UTC 24
Peak memory 203192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100431091 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.100431091
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_fifo_full.2960461331
Short name T276
Test name
Test status
Simulation time 31859669418 ps
CPU time 28.45 seconds
Started Sep 24 06:01:40 AM UTC 24
Finished Sep 24 06:02:10 AM UTC 24
Peak memory 204040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960461331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2960461331
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.2290528912
Short name T15
Test name
Test status
Simulation time 64336700828 ps
CPU time 52.13 seconds
Started Sep 24 06:01:40 AM UTC 24
Finished Sep 24 06:02:34 AM UTC 24
Peak memory 209200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290528912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2290528912
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_fifo_reset.1474123431
Short name T142
Test name
Test status
Simulation time 53827863776 ps
CPU time 46.9 seconds
Started Sep 24 06:01:47 AM UTC 24
Finished Sep 24 06:02:35 AM UTC 24
Peak memory 203976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474123431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1474123431
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_intr.3384828297
Short name T364
Test name
Test status
Simulation time 13097528664 ps
CPU time 11.72 seconds
Started Sep 24 06:01:55 AM UTC 24
Finished Sep 24 06:02:08 AM UTC 24
Peak memory 209064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384828297 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.3384828297
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_long_xfer_wo_dly.1420428426
Short name T268
Test name
Test status
Simulation time 43799823003 ps
CPU time 312.27 seconds
Started Sep 24 06:02:13 AM UTC 24
Finished Sep 24 06:07:29 AM UTC 24
Peak memory 204176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420428426 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1420428426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_loopback.1104605009
Short name T435
Test name
Test status
Simulation time 3477675216 ps
CPU time 4.23 seconds
Started Sep 24 06:02:11 AM UTC 24
Finished Sep 24 06:02:16 AM UTC 24
Peak memory 205624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104605009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1104605009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_noise_filter.107335804
Short name T285
Test name
Test status
Simulation time 62196464660 ps
CPU time 123.77 seconds
Started Sep 24 06:01:56 AM UTC 24
Finished Sep 24 06:04:02 AM UTC 24
Peak memory 209388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107335804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.107335804
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_perf.914305810
Short name T267
Test name
Test status
Simulation time 11705480431 ps
CPU time 172.09 seconds
Started Sep 24 06:02:11 AM UTC 24
Finished Sep 24 06:05:05 AM UTC 24
Peak memory 204096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914305810 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.914305810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_rx_oversample.3346064144
Short name T76
Test name
Test status
Simulation time 3282734847 ps
CPU time 4.89 seconds
Started Sep 24 06:01:52 AM UTC 24
Finished Sep 24 06:01:58 AM UTC 24
Peak memory 208076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346064144 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.3346064144
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.3180841654
Short name T116
Test name
Test status
Simulation time 31988766805 ps
CPU time 94.37 seconds
Started Sep 24 06:02:07 AM UTC 24
Finished Sep 24 06:03:44 AM UTC 24
Peak memory 209592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180841654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3180841654
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.499500465
Short name T284
Test name
Test status
Simulation time 52794102639 ps
CPU time 36.4 seconds
Started Sep 24 06:01:59 AM UTC 24
Finished Sep 24 06:02:37 AM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499500465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.499500465
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_sec_cm.2251163288
Short name T86
Test name
Test status
Simulation time 109499104 ps
CPU time 1.19 seconds
Started Sep 24 06:02:17 AM UTC 24
Finished Sep 24 06:02:19 AM UTC 24
Peak memory 237820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251163288 -assert nopostproc +UVM_TESTNAME=uart_b
ase_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2251163288
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_smoke.993417810
Short name T318
Test name
Test status
Simulation time 5835145692 ps
CPU time 34.54 seconds
Started Sep 24 06:01:36 AM UTC 24
Finished Sep 24 06:02:14 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993417810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 4.uart_smoke.993417810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.1799709096
Short name T41
Test name
Test status
Simulation time 3948226322 ps
CPU time 18.4 seconds
Started Sep 24 06:02:14 AM UTC 24
Finished Sep 24 06:02:33 AM UTC 24
Peak memory 209708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1799709096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all_
with_rand_reset.1799709096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.3990450128
Short name T332
Test name
Test status
Simulation time 536190111 ps
CPU time 2.62 seconds
Started Sep 24 06:02:08 AM UTC 24
Finished Sep 24 06:02:12 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990450128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3990450128
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/4.uart_tx_rx.3019934931
Short name T393
Test name
Test status
Simulation time 34569120430 ps
CPU time 26.31 seconds
Started Sep 24 06:01:39 AM UTC 24
Finished Sep 24 06:02:07 AM UTC 24
Peak memory 207680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019934931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3019934931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/4.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_alert_test.3932459426
Short name T771
Test name
Test status
Simulation time 15186245 ps
CPU time 0.85 seconds
Started Sep 24 06:25:55 AM UTC 24
Finished Sep 24 06:25:57 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932459426 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3932459426
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_fifo_full.2675762739
Short name T141
Test name
Test status
Simulation time 14925575537 ps
CPU time 50.62 seconds
Started Sep 24 06:25:24 AM UTC 24
Finished Sep 24 06:26:16 AM UTC 24
Peak memory 209604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675762739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2675762739
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_fifo_overflow.3117679503
Short name T808
Test name
Test status
Simulation time 139036649911 ps
CPU time 108.36 seconds
Started Sep 24 06:25:24 AM UTC 24
Finished Sep 24 06:27:14 AM UTC 24
Peak memory 209208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117679503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.3117679503
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_fifo_reset.292902931
Short name T220
Test name
Test status
Simulation time 54805031304 ps
CPU time 126.3 seconds
Started Sep 24 06:25:26 AM UTC 24
Finished Sep 24 06:27:35 AM UTC 24
Peak memory 209400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292902931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.292902931
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_intr.3612575467
Short name T769
Test name
Test status
Simulation time 17908619040 ps
CPU time 22.64 seconds
Started Sep 24 06:25:32 AM UTC 24
Finished Sep 24 06:25:56 AM UTC 24
Peak memory 203760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612575467 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3612575467
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_long_xfer_wo_dly.3048190599
Short name T1072
Test name
Test status
Simulation time 107614427037 ps
CPU time 694.59 seconds
Started Sep 24 06:25:51 AM UTC 24
Finished Sep 24 06:37:34 AM UTC 24
Peak memory 212912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048190599 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3048190599
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_loopback.1910225395
Short name T766
Test name
Test status
Simulation time 1511103853 ps
CPU time 3.59 seconds
Started Sep 24 06:25:46 AM UTC 24
Finished Sep 24 06:25:51 AM UTC 24
Peak memory 207864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910225395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.uart_loopback.1910225395
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_noise_filter.671508827
Short name T415
Test name
Test status
Simulation time 3815049992 ps
CPU time 6.55 seconds
Started Sep 24 06:25:38 AM UTC 24
Finished Sep 24 06:25:46 AM UTC 24
Peak memory 209736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671508827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.671508827
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_perf.1844505772
Short name T935
Test name
Test status
Simulation time 18147966612 ps
CPU time 356.78 seconds
Started Sep 24 06:25:49 AM UTC 24
Finished Sep 24 06:31:50 AM UTC 24
Peak memory 203764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844505772 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1844505772
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_rx_oversample.2850226935
Short name T776
Test name
Test status
Simulation time 3795677951 ps
CPU time 38.43 seconds
Started Sep 24 06:25:32 AM UTC 24
Finished Sep 24 06:26:12 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850226935 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2850226935
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_rx_parity_err.3161716323
Short name T774
Test name
Test status
Simulation time 46287314532 ps
CPU time 31.29 seconds
Started Sep 24 06:25:39 AM UTC 24
Finished Sep 24 06:26:12 AM UTC 24
Peak memory 203712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161716323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3161716323
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_rx_start_bit_filter.2299954316
Short name T773
Test name
Test status
Simulation time 30747465070 ps
CPU time 28.11 seconds
Started Sep 24 06:25:38 AM UTC 24
Finished Sep 24 06:26:07 AM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299954316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2299954316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_smoke.1612127689
Short name T761
Test name
Test status
Simulation time 5860138133 ps
CPU time 18 seconds
Started Sep 24 06:25:19 AM UTC 24
Finished Sep 24 06:25:38 AM UTC 24
Peak memory 204180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612127689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1612127689
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_stress_all_with_rand_reset.215902368
Short name T824
Test name
Test status
Simulation time 11777830742 ps
CPU time 107.85 seconds
Started Sep 24 06:25:52 AM UTC 24
Finished Sep 24 06:27:42 AM UTC 24
Peak memory 218888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=215902368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all_
with_rand_reset.215902368
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_tx_ovrd.3933602069
Short name T764
Test name
Test status
Simulation time 496221303 ps
CPU time 2.88 seconds
Started Sep 24 06:25:43 AM UTC 24
Finished Sep 24 06:25:47 AM UTC 24
Peak memory 203800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933602069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3933602069
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/40.uart_tx_rx.4145452542
Short name T791
Test name
Test status
Simulation time 104758346447 ps
CPU time 69.33 seconds
Started Sep 24 06:25:22 AM UTC 24
Finished Sep 24 06:26:33 AM UTC 24
Peak memory 204100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145452542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4145452542
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/40.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_alert_test.2071450746
Short name T784
Test name
Test status
Simulation time 14481760 ps
CPU time 0.86 seconds
Started Sep 24 06:26:21 AM UTC 24
Finished Sep 24 06:26:23 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071450746 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2071450746
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_fifo_full.2535214334
Short name T782
Test name
Test status
Simulation time 54999678551 ps
CPU time 21.99 seconds
Started Sep 24 06:25:57 AM UTC 24
Finished Sep 24 06:26:20 AM UTC 24
Peak memory 204048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535214334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.2535214334
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_fifo_overflow.2811827809
Short name T800
Test name
Test status
Simulation time 40795879287 ps
CPU time 38.82 seconds
Started Sep 24 06:26:06 AM UTC 24
Finished Sep 24 06:26:46 AM UTC 24
Peak memory 209324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811827809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2811827809
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_fifo_reset.1515774567
Short name T228
Test name
Test status
Simulation time 15094109012 ps
CPU time 31.99 seconds
Started Sep 24 06:26:07 AM UTC 24
Finished Sep 24 06:26:41 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515774567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1515774567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_intr.3197859488
Short name T794
Test name
Test status
Simulation time 13717687339 ps
CPU time 24.48 seconds
Started Sep 24 06:26:11 AM UTC 24
Finished Sep 24 06:26:37 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197859488 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.3197859488
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_long_xfer_wo_dly.2565333154
Short name T1021
Test name
Test status
Simulation time 227828253164 ps
CPU time 536.93 seconds
Started Sep 24 06:26:18 AM UTC 24
Finished Sep 24 06:35:22 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565333154 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2565333154
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_loopback.1652794552
Short name T781
Test name
Test status
Simulation time 4133515558 ps
CPU time 2.33 seconds
Started Sep 24 06:26:17 AM UTC 24
Finished Sep 24 06:26:20 AM UTC 24
Peak memory 208852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652794552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1652794552
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_noise_filter.1437487061
Short name T786
Test name
Test status
Simulation time 45821035349 ps
CPU time 14.57 seconds
Started Sep 24 06:26:12 AM UTC 24
Finished Sep 24 06:26:28 AM UTC 24
Peak memory 209608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437487061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1437487061
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_perf.3889255846
Short name T1175
Test name
Test status
Simulation time 20821783414 ps
CPU time 1131.62 seconds
Started Sep 24 06:26:17 AM UTC 24
Finished Sep 24 06:45:22 AM UTC 24
Peak memory 207188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889255846 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3889255846
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_rx_oversample.1391720082
Short name T780
Test name
Test status
Simulation time 3157565898 ps
CPU time 8.3 seconds
Started Sep 24 06:26:08 AM UTC 24
Finished Sep 24 06:26:18 AM UTC 24
Peak memory 207944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391720082 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1391720082
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_rx_parity_err.3455202774
Short name T801
Test name
Test status
Simulation time 30082007239 ps
CPU time 33.19 seconds
Started Sep 24 06:26:13 AM UTC 24
Finished Sep 24 06:26:47 AM UTC 24
Peak memory 209380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455202774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3455202774
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_rx_start_bit_filter.3715110494
Short name T778
Test name
Test status
Simulation time 4116383582 ps
CPU time 3.03 seconds
Started Sep 24 06:26:13 AM UTC 24
Finished Sep 24 06:26:17 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715110494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3715110494
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_smoke.2741928256
Short name T772
Test name
Test status
Simulation time 6247168746 ps
CPU time 7.86 seconds
Started Sep 24 06:25:57 AM UTC 24
Finished Sep 24 06:26:06 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741928256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2741928256
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_stress_all.1208027132
Short name T426
Test name
Test status
Simulation time 168376981261 ps
CPU time 770.52 seconds
Started Sep 24 06:26:19 AM UTC 24
Finished Sep 24 06:39:19 AM UTC 24
Peak memory 211336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208027132 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1208027132
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_stress_all_with_rand_reset.3387361044
Short name T797
Test name
Test status
Simulation time 3714810034 ps
CPU time 21.29 seconds
Started Sep 24 06:26:18 AM UTC 24
Finished Sep 24 06:26:40 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3387361044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all
_with_rand_reset.3387361044
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_tx_ovrd.2388111498
Short name T789
Test name
Test status
Simulation time 16234506939 ps
CPU time 15.42 seconds
Started Sep 24 06:26:14 AM UTC 24
Finished Sep 24 06:26:30 AM UTC 24
Peak memory 203780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388111498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2388111498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/41.uart_tx_rx.1977651342
Short name T790
Test name
Test status
Simulation time 58821800712 ps
CPU time 33.52 seconds
Started Sep 24 06:25:57 AM UTC 24
Finished Sep 24 06:26:32 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977651342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1977651342
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/41.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_alert_test.3755182443
Short name T799
Test name
Test status
Simulation time 70191798 ps
CPU time 0.84 seconds
Started Sep 24 06:26:41 AM UTC 24
Finished Sep 24 06:26:43 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755182443 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3755182443
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_fifo_full.968698779
Short name T814
Test name
Test status
Simulation time 120488752633 ps
CPU time 58.04 seconds
Started Sep 24 06:26:23 AM UTC 24
Finished Sep 24 06:27:23 AM UTC 24
Peak memory 204044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968698779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.968698779
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_fifo_overflow.1100445123
Short name T802
Test name
Test status
Simulation time 16717582164 ps
CPU time 28.09 seconds
Started Sep 24 06:26:25 AM UTC 24
Finished Sep 24 06:26:55 AM UTC 24
Peak memory 203988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100445123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1100445123
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_fifo_reset.3814789904
Short name T231
Test name
Test status
Simulation time 10274122637 ps
CPU time 14.62 seconds
Started Sep 24 06:26:28 AM UTC 24
Finished Sep 24 06:26:44 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814789904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3814789904
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_intr.1784782128
Short name T792
Test name
Test status
Simulation time 947226456 ps
CPU time 1.57 seconds
Started Sep 24 06:26:31 AM UTC 24
Finished Sep 24 06:26:33 AM UTC 24
Peak memory 203440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784782128 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1784782128
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_long_xfer_wo_dly.939658122
Short name T921
Test name
Test status
Simulation time 100144683362 ps
CPU time 274.11 seconds
Started Sep 24 06:26:39 AM UTC 24
Finished Sep 24 06:31:17 AM UTC 24
Peak memory 209156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939658122 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.939658122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_loopback.4194503536
Short name T798
Test name
Test status
Simulation time 2650553432 ps
CPU time 3.58 seconds
Started Sep 24 06:26:38 AM UTC 24
Finished Sep 24 06:26:43 AM UTC 24
Peak memory 204100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194503536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.uart_loopback.4194503536
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_noise_filter.519993528
Short name T811
Test name
Test status
Simulation time 56007722990 ps
CPU time 47.32 seconds
Started Sep 24 06:26:31 AM UTC 24
Finished Sep 24 06:27:20 AM UTC 24
Peak memory 209592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519993528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.519993528
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_perf.1292471282
Short name T871
Test name
Test status
Simulation time 9842921693 ps
CPU time 147.79 seconds
Started Sep 24 06:26:38 AM UTC 24
Finished Sep 24 06:29:08 AM UTC 24
Peak memory 203856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292471282 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1292471282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_rx_oversample.2076988309
Short name T815
Test name
Test status
Simulation time 4806905595 ps
CPU time 53.17 seconds
Started Sep 24 06:26:30 AM UTC 24
Finished Sep 24 06:27:24 AM UTC 24
Peak memory 208836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076988309 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2076988309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_rx_parity_err.1495189481
Short name T829
Test name
Test status
Simulation time 28120699253 ps
CPU time 75.13 seconds
Started Sep 24 06:26:34 AM UTC 24
Finished Sep 24 06:27:51 AM UTC 24
Peak memory 203856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495189481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1495189481
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_rx_start_bit_filter.2492360068
Short name T793
Test name
Test status
Simulation time 4590559108 ps
CPU time 2.13 seconds
Started Sep 24 06:26:33 AM UTC 24
Finished Sep 24 06:26:37 AM UTC 24
Peak memory 203896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492360068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.2492360068
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_smoke.2839964687
Short name T785
Test name
Test status
Simulation time 668301436 ps
CPU time 2.82 seconds
Started Sep 24 06:26:21 AM UTC 24
Finished Sep 24 06:26:25 AM UTC 24
Peak memory 203724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839964687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2839964687
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_stress_all.290594774
Short name T878
Test name
Test status
Simulation time 93436641513 ps
CPU time 165.51 seconds
Started Sep 24 06:26:41 AM UTC 24
Finished Sep 24 06:29:30 AM UTC 24
Peak memory 205884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290594774 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.290594774
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_stress_all_with_rand_reset.207057219
Short name T813
Test name
Test status
Simulation time 9957957784 ps
CPU time 41.35 seconds
Started Sep 24 06:26:39 AM UTC 24
Finished Sep 24 06:27:22 AM UTC 24
Peak memory 218200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=207057219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all_
with_rand_reset.207057219
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_tx_ovrd.686114934
Short name T795
Test name
Test status
Simulation time 910290706 ps
CPU time 3.01 seconds
Started Sep 24 06:26:34 AM UTC 24
Finished Sep 24 06:26:38 AM UTC 24
Peak memory 203732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686114934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.686114934
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/42.uart_tx_rx.1813970403
Short name T856
Test name
Test status
Simulation time 52541603917 ps
CPU time 138.25 seconds
Started Sep 24 06:26:22 AM UTC 24
Finished Sep 24 06:28:43 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813970403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1813970403
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/42.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_alert_test.1701872591
Short name T816
Test name
Test status
Simulation time 61381899 ps
CPU time 0.87 seconds
Started Sep 24 06:27:23 AM UTC 24
Finished Sep 24 06:27:25 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701872591 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1701872591
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_fifo_full.918109680
Short name T879
Test name
Test status
Simulation time 114212763602 ps
CPU time 164.95 seconds
Started Sep 24 06:26:46 AM UTC 24
Finished Sep 24 06:29:33 AM UTC 24
Peak memory 209660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918109680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.918109680
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_fifo_overflow.1362465497
Short name T827
Test name
Test status
Simulation time 15787953267 ps
CPU time 58.19 seconds
Started Sep 24 06:26:47 AM UTC 24
Finished Sep 24 06:27:47 AM UTC 24
Peak memory 209512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362465497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1362465497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_fifo_reset.698300759
Short name T806
Test name
Test status
Simulation time 14565712582 ps
CPU time 23.82 seconds
Started Sep 24 06:26:48 AM UTC 24
Finished Sep 24 06:27:13 AM UTC 24
Peak memory 208912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698300759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.698300759
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_intr.3633089956
Short name T817
Test name
Test status
Simulation time 26328830141 ps
CPU time 16.53 seconds
Started Sep 24 06:27:08 AM UTC 24
Finished Sep 24 06:27:26 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633089956 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3633089956
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_long_xfer_wo_dly.254975471
Short name T958
Test name
Test status
Simulation time 61477836283 ps
CPU time 319.18 seconds
Started Sep 24 06:27:17 AM UTC 24
Finished Sep 24 06:32:41 AM UTC 24
Peak memory 203700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254975471 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.254975471
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_loopback.271222432
Short name T819
Test name
Test status
Simulation time 7236145987 ps
CPU time 16.36 seconds
Started Sep 24 06:27:14 AM UTC 24
Finished Sep 24 06:27:32 AM UTC 24
Peak memory 203768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271222432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.uart_loopback.271222432
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_noise_filter.795476392
Short name T810
Test name
Test status
Simulation time 15866064538 ps
CPU time 8.16 seconds
Started Sep 24 06:27:09 AM UTC 24
Finished Sep 24 06:27:18 AM UTC 24
Peak memory 209656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795476392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.795476392
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_perf.1736177820
Short name T919
Test name
Test status
Simulation time 3170126210 ps
CPU time 232.83 seconds
Started Sep 24 06:27:15 AM UTC 24
Finished Sep 24 06:31:12 AM UTC 24
Peak memory 203844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736177820 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1736177820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_rx_oversample.1578133108
Short name T805
Test name
Test status
Simulation time 4989644138 ps
CPU time 12.29 seconds
Started Sep 24 06:26:56 AM UTC 24
Finished Sep 24 06:27:09 AM UTC 24
Peak memory 207872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578133108 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1578133108
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_rx_parity_err.2362728461
Short name T833
Test name
Test status
Simulation time 14540114415 ps
CPU time 43.98 seconds
Started Sep 24 06:27:10 AM UTC 24
Finished Sep 24 06:27:56 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362728461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2362728461
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_rx_start_bit_filter.47842387
Short name T807
Test name
Test status
Simulation time 5583622214 ps
CPU time 3.17 seconds
Started Sep 24 06:27:09 AM UTC 24
Finished Sep 24 06:27:13 AM UTC 24
Peak memory 203580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47842387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.47842387
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_smoke.830496729
Short name T803
Test name
Test status
Simulation time 5369219413 ps
CPU time 22.74 seconds
Started Sep 24 06:26:43 AM UTC 24
Finished Sep 24 06:27:07 AM UTC 24
Peak memory 203796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830496729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.uart_smoke.830496729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_stress_all.3589164172
Short name T909
Test name
Test status
Simulation time 91589633317 ps
CPU time 209.47 seconds
Started Sep 24 06:27:21 AM UTC 24
Finished Sep 24 06:30:53 AM UTC 24
Peak memory 205760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589164172 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3589164172
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_stress_all_with_rand_reset.2302787297
Short name T832
Test name
Test status
Simulation time 4083332560 ps
CPU time 34.16 seconds
Started Sep 24 06:27:19 AM UTC 24
Finished Sep 24 06:27:55 AM UTC 24
Peak memory 226168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2302787297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all
_with_rand_reset.2302787297
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_tx_ovrd.4287497311
Short name T812
Test name
Test status
Simulation time 1192672895 ps
CPU time 6.55 seconds
Started Sep 24 06:27:14 AM UTC 24
Finished Sep 24 06:27:22 AM UTC 24
Peak memory 203652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287497311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.4287497311
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/43.uart_tx_rx.1586530086
Short name T822
Test name
Test status
Simulation time 105437497853 ps
CPU time 50.13 seconds
Started Sep 24 06:26:43 AM UTC 24
Finished Sep 24 06:27:35 AM UTC 24
Peak memory 209400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586530086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1586530086
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/43.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_alert_test.3988101233
Short name T830
Test name
Test status
Simulation time 19759910 ps
CPU time 0.83 seconds
Started Sep 24 06:27:50 AM UTC 24
Finished Sep 24 06:27:52 AM UTC 24
Peak memory 203136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988101233 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3988101233
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_fifo_full.305640748
Short name T854
Test name
Test status
Simulation time 43360828285 ps
CPU time 74.22 seconds
Started Sep 24 06:27:25 AM UTC 24
Finished Sep 24 06:28:41 AM UTC 24
Peak memory 204040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305640748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.305640748
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_fifo_overflow.1401411720
Short name T848
Test name
Test status
Simulation time 35622292169 ps
CPU time 58.17 seconds
Started Sep 24 06:27:25 AM UTC 24
Finished Sep 24 06:28:25 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401411720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1401411720
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_fifo_reset.2199039229
Short name T198
Test name
Test status
Simulation time 63845229751 ps
CPU time 40.12 seconds
Started Sep 24 06:27:25 AM UTC 24
Finished Sep 24 06:28:07 AM UTC 24
Peak memory 209264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199039229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2199039229
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_intr.3427070139
Short name T834
Test name
Test status
Simulation time 16772195504 ps
CPU time 29.68 seconds
Started Sep 24 06:27:26 AM UTC 24
Finished Sep 24 06:27:57 AM UTC 24
Peak memory 207672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427070139 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.3427070139
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_long_xfer_wo_dly.3753000610
Short name T1170
Test name
Test status
Simulation time 141168339098 ps
CPU time 837.29 seconds
Started Sep 24 06:27:43 AM UTC 24
Finished Sep 24 06:41:50 AM UTC 24
Peak memory 212716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753000610 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.3753000610
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_loopback.37421911
Short name T826
Test name
Test status
Simulation time 4349439483 ps
CPU time 7.82 seconds
Started Sep 24 06:27:36 AM UTC 24
Finished Sep 24 06:27:45 AM UTC 24
Peak memory 208000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37421911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.uart_loopback.37421911
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_noise_filter.473833657
Short name T850
Test name
Test status
Simulation time 21168007933 ps
CPU time 57.39 seconds
Started Sep 24 06:27:32 AM UTC 24
Finished Sep 24 06:28:31 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473833657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.473833657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_perf.3227066053
Short name T932
Test name
Test status
Simulation time 16696027938 ps
CPU time 245.04 seconds
Started Sep 24 06:27:39 AM UTC 24
Finished Sep 24 06:31:48 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227066053 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3227066053
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_rx_oversample.250678309
Short name T821
Test name
Test status
Simulation time 4789166931 ps
CPU time 5.29 seconds
Started Sep 24 06:27:26 AM UTC 24
Finished Sep 24 06:27:33 AM UTC 24
Peak memory 203852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250678309 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.250678309
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_rx_parity_err.3188090340
Short name T837
Test name
Test status
Simulation time 73406738297 ps
CPU time 31.33 seconds
Started Sep 24 06:27:34 AM UTC 24
Finished Sep 24 06:28:06 AM UTC 24
Peak memory 209064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188090340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3188090340
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_rx_start_bit_filter.3920034663
Short name T823
Test name
Test status
Simulation time 2784652509 ps
CPU time 3.45 seconds
Started Sep 24 06:27:34 AM UTC 24
Finished Sep 24 06:27:38 AM UTC 24
Peak memory 203544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920034663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3920034663
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_smoke.1089341338
Short name T818
Test name
Test status
Simulation time 723558584 ps
CPU time 2.19 seconds
Started Sep 24 06:27:23 AM UTC 24
Finished Sep 24 06:27:26 AM UTC 24
Peak memory 203964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089341338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1089341338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_stress_all.1193096467
Short name T1014
Test name
Test status
Simulation time 224066394657 ps
CPU time 431.61 seconds
Started Sep 24 06:27:47 AM UTC 24
Finished Sep 24 06:35:04 AM UTC 24
Peak memory 205828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193096467 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1193096467
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_stress_all_with_rand_reset.1735453740
Short name T867
Test name
Test status
Simulation time 3347569307 ps
CPU time 72.26 seconds
Started Sep 24 06:27:45 AM UTC 24
Finished Sep 24 06:28:59 AM UTC 24
Peak memory 226116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1735453740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all
_with_rand_reset.1735453740
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_tx_ovrd.2607372898
Short name T828
Test name
Test status
Simulation time 8095016003 ps
CPU time 12.95 seconds
Started Sep 24 06:27:36 AM UTC 24
Finished Sep 24 06:27:50 AM UTC 24
Peak memory 208556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607372898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2607372898
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/44.uart_tx_rx.2872800053
Short name T855
Test name
Test status
Simulation time 256223820239 ps
CPU time 77.43 seconds
Started Sep 24 06:27:24 AM UTC 24
Finished Sep 24 06:28:43 AM UTC 24
Peak memory 205832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872800053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2872800053
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/44.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_alert_test.2511279412
Short name T845
Test name
Test status
Simulation time 18341202 ps
CPU time 0.81 seconds
Started Sep 24 06:28:19 AM UTC 24
Finished Sep 24 06:28:20 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511279412 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2511279412
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_fifo_full.1681131828
Short name T858
Test name
Test status
Simulation time 216849537346 ps
CPU time 53.12 seconds
Started Sep 24 06:27:52 AM UTC 24
Finished Sep 24 06:28:47 AM UTC 24
Peak memory 203912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681131828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1681131828
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_fifo_overflow.4035765901
Short name T166
Test name
Test status
Simulation time 199466020644 ps
CPU time 121.36 seconds
Started Sep 24 06:27:53 AM UTC 24
Finished Sep 24 06:29:57 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035765901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.4035765901
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_intr.918522485
Short name T841
Test name
Test status
Simulation time 8245042890 ps
CPU time 16.32 seconds
Started Sep 24 06:27:59 AM UTC 24
Finished Sep 24 06:28:16 AM UTC 24
Peak memory 209344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918522485 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.918522485
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_long_xfer_wo_dly.1297794963
Short name T1177
Test name
Test status
Simulation time 128496222368 ps
CPU time 1056.73 seconds
Started Sep 24 06:28:11 AM UTC 24
Finished Sep 24 06:46:01 AM UTC 24
Peak memory 212728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297794963 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.1297794963
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_loopback.3593994260
Short name T847
Test name
Test status
Simulation time 9446717297 ps
CPU time 14.76 seconds
Started Sep 24 06:28:07 AM UTC 24
Finished Sep 24 06:28:23 AM UTC 24
Peak memory 209376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593994260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3593994260
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_noise_filter.1305812505
Short name T852
Test name
Test status
Simulation time 17937049923 ps
CPU time 34.1 seconds
Started Sep 24 06:28:04 AM UTC 24
Finished Sep 24 06:28:39 AM UTC 24
Peak memory 208076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305812505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1305812505
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_perf.2406528899
Short name T971
Test name
Test status
Simulation time 27769851114 ps
CPU time 299.43 seconds
Started Sep 24 06:28:11 AM UTC 24
Finished Sep 24 06:33:15 AM UTC 24
Peak memory 203568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406528899 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2406528899
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_rx_oversample.3278224030
Short name T839
Test name
Test status
Simulation time 4020571861 ps
CPU time 12.5 seconds
Started Sep 24 06:27:57 AM UTC 24
Finished Sep 24 06:28:10 AM UTC 24
Peak memory 208284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278224030 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3278224030
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_rx_parity_err.4250144617
Short name T861
Test name
Test status
Simulation time 78232198312 ps
CPU time 38.95 seconds
Started Sep 24 06:28:07 AM UTC 24
Finished Sep 24 06:28:47 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250144617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.4250144617
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_rx_start_bit_filter.2862347091
Short name T870
Test name
Test status
Simulation time 53945457334 ps
CPU time 59.82 seconds
Started Sep 24 06:28:05 AM UTC 24
Finished Sep 24 06:29:06 AM UTC 24
Peak memory 203504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862347091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2862347091
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_smoke.3168655435
Short name T836
Test name
Test status
Simulation time 5272611106 ps
CPU time 14.6 seconds
Started Sep 24 06:27:50 AM UTC 24
Finished Sep 24 06:28:06 AM UTC 24
Peak memory 204104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168655435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3168655435
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_stress_all.3009789855
Short name T928
Test name
Test status
Simulation time 77605254157 ps
CPU time 198.7 seconds
Started Sep 24 06:28:16 AM UTC 24
Finished Sep 24 06:31:39 AM UTC 24
Peak memory 204036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009789855 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3009789855
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_stress_all_with_rand_reset.641401555
Short name T868
Test name
Test status
Simulation time 2851332086 ps
CPU time 45.91 seconds
Started Sep 24 06:28:14 AM UTC 24
Finished Sep 24 06:29:02 AM UTC 24
Peak memory 218304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=641401555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all_
with_rand_reset.641401555
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_tx_ovrd.3543016195
Short name T838
Test name
Test status
Simulation time 844213800 ps
CPU time 2 seconds
Started Sep 24 06:28:07 AM UTC 24
Finished Sep 24 06:28:10 AM UTC 24
Peak memory 203320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543016195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3543016195
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/45.uart_tx_rx.2325475195
Short name T842
Test name
Test status
Simulation time 10086895177 ps
CPU time 24.09 seconds
Started Sep 24 06:27:52 AM UTC 24
Finished Sep 24 06:28:18 AM UTC 24
Peak memory 207672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325475195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.2325475195
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/45.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_alert_test.3153744140
Short name T862
Test name
Test status
Simulation time 36644763 ps
CPU time 0.84 seconds
Started Sep 24 06:28:48 AM UTC 24
Finished Sep 24 06:28:50 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153744140 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3153744140
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_fifo_full.1846629283
Short name T950
Test name
Test status
Simulation time 155167087285 ps
CPU time 235.76 seconds
Started Sep 24 06:28:22 AM UTC 24
Finished Sep 24 06:32:21 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846629283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1846629283
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_fifo_overflow.3955675440
Short name T864
Test name
Test status
Simulation time 12447851224 ps
CPU time 28.36 seconds
Started Sep 24 06:28:23 AM UTC 24
Finished Sep 24 06:28:53 AM UTC 24
Peak memory 203844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955675440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3955675440
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_fifo_reset.1720668654
Short name T203
Test name
Test status
Simulation time 47924295046 ps
CPU time 90.93 seconds
Started Sep 24 06:28:24 AM UTC 24
Finished Sep 24 06:29:57 AM UTC 24
Peak memory 204184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720668654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1720668654
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_intr.3985891415
Short name T1043
Test name
Test status
Simulation time 239492325115 ps
CPU time 458.38 seconds
Started Sep 24 06:28:30 AM UTC 24
Finished Sep 24 06:36:14 AM UTC 24
Peak memory 207668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985891415 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3985891415
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_long_xfer_wo_dly.1819651409
Short name T900
Test name
Test status
Simulation time 47163858130 ps
CPU time 111.94 seconds
Started Sep 24 06:28:44 AM UTC 24
Finished Sep 24 06:30:38 AM UTC 24
Peak memory 209324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819651409 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1819651409
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_loopback.3694800338
Short name T859
Test name
Test status
Simulation time 7003332971 ps
CPU time 4.28 seconds
Started Sep 24 06:28:41 AM UTC 24
Finished Sep 24 06:28:47 AM UTC 24
Peak memory 208780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694800338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3694800338
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_noise_filter.3899483889
Short name T953
Test name
Test status
Simulation time 87047765709 ps
CPU time 232.27 seconds
Started Sep 24 06:28:32 AM UTC 24
Finished Sep 24 06:32:28 AM UTC 24
Peak memory 209684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899483889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3899483889
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_perf.3202783949
Short name T1000
Test name
Test status
Simulation time 14841358398 ps
CPU time 337.62 seconds
Started Sep 24 06:28:44 AM UTC 24
Finished Sep 24 06:34:26 AM UTC 24
Peak memory 204104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202783949 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.3202783949
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_rx_oversample.3882580180
Short name T851
Test name
Test status
Simulation time 1594250305 ps
CPU time 7.9 seconds
Started Sep 24 06:28:26 AM UTC 24
Finished Sep 24 06:28:35 AM UTC 24
Peak memory 207816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882580180 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3882580180
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_rx_parity_err.1011017462
Short name T931
Test name
Test status
Simulation time 115190966306 ps
CPU time 184.15 seconds
Started Sep 24 06:28:40 AM UTC 24
Finished Sep 24 06:31:47 AM UTC 24
Peak memory 209664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011017462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1011017462
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_rx_start_bit_filter.746339819
Short name T853
Test name
Test status
Simulation time 2604392216 ps
CPU time 2.4 seconds
Started Sep 24 06:28:36 AM UTC 24
Finished Sep 24 06:28:40 AM UTC 24
Peak memory 203840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746339819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.746339819
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_smoke.2100912139
Short name T846
Test name
Test status
Simulation time 434365959 ps
CPU time 1.86 seconds
Started Sep 24 06:28:19 AM UTC 24
Finished Sep 24 06:28:21 AM UTC 24
Peak memory 203328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100912139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2100912139
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_stress_all.1056935583
Short name T1139
Test name
Test status
Simulation time 323630384351 ps
CPU time 646.35 seconds
Started Sep 24 06:28:48 AM UTC 24
Finished Sep 24 06:39:41 AM UTC 24
Peak memory 221824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056935583 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1056935583
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_stress_all_with_rand_reset.2802502036
Short name T875
Test name
Test status
Simulation time 14817349646 ps
CPU time 29.8 seconds
Started Sep 24 06:28:46 AM UTC 24
Finished Sep 24 06:29:17 AM UTC 24
Peak memory 218304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2802502036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all
_with_rand_reset.2802502036
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_tx_ovrd.3435223124
Short name T857
Test name
Test status
Simulation time 569761795 ps
CPU time 3.15 seconds
Started Sep 24 06:28:40 AM UTC 24
Finished Sep 24 06:28:45 AM UTC 24
Peak memory 203980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435223124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3435223124
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/46.uart_tx_rx.2466441281
Short name T869
Test name
Test status
Simulation time 90174148411 ps
CPU time 40.54 seconds
Started Sep 24 06:28:21 AM UTC 24
Finished Sep 24 06:29:03 AM UTC 24
Peak memory 209588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466441281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2466441281
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/46.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_alert_test.4276180085
Short name T876
Test name
Test status
Simulation time 17084326 ps
CPU time 0.87 seconds
Started Sep 24 06:29:18 AM UTC 24
Finished Sep 24 06:29:20 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276180085 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.4276180085
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_fifo_full.4276043406
Short name T901
Test name
Test status
Simulation time 31543297488 ps
CPU time 105.91 seconds
Started Sep 24 06:28:50 AM UTC 24
Finished Sep 24 06:30:38 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276043406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4276043406
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_fifo_overflow.2334260073
Short name T883
Test name
Test status
Simulation time 31830647462 ps
CPU time 46.25 seconds
Started Sep 24 06:28:52 AM UTC 24
Finished Sep 24 06:29:40 AM UTC 24
Peak memory 209324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334260073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2334260073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_fifo_reset.1319198703
Short name T882
Test name
Test status
Simulation time 43678752758 ps
CPU time 43.61 seconds
Started Sep 24 06:28:53 AM UTC 24
Finished Sep 24 06:29:38 AM UTC 24
Peak memory 204112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319198703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1319198703
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_intr.1138487526
Short name T895
Test name
Test status
Simulation time 37928473863 ps
CPU time 77.03 seconds
Started Sep 24 06:28:55 AM UTC 24
Finished Sep 24 06:30:14 AM UTC 24
Peak memory 204040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138487526 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.1138487526
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_long_xfer_wo_dly.1076580000
Short name T1018
Test name
Test status
Simulation time 130778384478 ps
CPU time 356.79 seconds
Started Sep 24 06:29:11 AM UTC 24
Finished Sep 24 06:35:13 AM UTC 24
Peak memory 209192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076580000 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1076580000
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_loopback.3488043708
Short name T873
Test name
Test status
Simulation time 993583154 ps
CPU time 2.92 seconds
Started Sep 24 06:29:07 AM UTC 24
Finished Sep 24 06:29:11 AM UTC 24
Peak memory 207736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488043708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3488043708
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_noise_filter.1755462688
Short name T884
Test name
Test status
Simulation time 9417456640 ps
CPU time 45.61 seconds
Started Sep 24 06:28:56 AM UTC 24
Finished Sep 24 06:29:43 AM UTC 24
Peak memory 209672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755462688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1755462688
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_perf.3179099330
Short name T1071
Test name
Test status
Simulation time 21954883544 ps
CPU time 497.85 seconds
Started Sep 24 06:29:09 AM UTC 24
Finished Sep 24 06:37:33 AM UTC 24
Peak memory 203844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179099330 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3179099330
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_rx_oversample.636031975
Short name T880
Test name
Test status
Simulation time 5901578170 ps
CPU time 39.15 seconds
Started Sep 24 06:28:54 AM UTC 24
Finished Sep 24 06:29:35 AM UTC 24
Peak memory 204108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636031975 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.636031975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_rx_parity_err.3774582359
Short name T913
Test name
Test status
Simulation time 115996373648 ps
CPU time 115.13 seconds
Started Sep 24 06:29:03 AM UTC 24
Finished Sep 24 06:31:00 AM UTC 24
Peak memory 209004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774582359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3774582359
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_rx_start_bit_filter.3789917395
Short name T888
Test name
Test status
Simulation time 84219379220 ps
CPU time 60.72 seconds
Started Sep 24 06:28:59 AM UTC 24
Finished Sep 24 06:30:02 AM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789917395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3789917395
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_smoke.1820268178
Short name T865
Test name
Test status
Simulation time 932703146 ps
CPU time 5.16 seconds
Started Sep 24 06:28:48 AM UTC 24
Finished Sep 24 06:28:54 AM UTC 24
Peak memory 203852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820268178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1820268178
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_stress_all.1709369718
Short name T1057
Test name
Test status
Simulation time 266189810200 ps
CPU time 446.72 seconds
Started Sep 24 06:29:13 AM UTC 24
Finished Sep 24 06:36:45 AM UTC 24
Peak memory 218736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709369718 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1709369718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_stress_all_with_rand_reset.1058821982
Short name T890
Test name
Test status
Simulation time 19507910600 ps
CPU time 54.93 seconds
Started Sep 24 06:29:12 AM UTC 24
Finished Sep 24 06:30:09 AM UTC 24
Peak memory 220604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1058821982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all
_with_rand_reset.1058821982
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_tx_ovrd.560429090
Short name T872
Test name
Test status
Simulation time 856706234 ps
CPU time 5.02 seconds
Started Sep 24 06:29:04 AM UTC 24
Finished Sep 24 06:29:10 AM UTC 24
Peak memory 203868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560429090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.560429090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/47.uart_tx_rx.367188136
Short name T908
Test name
Test status
Simulation time 188602770327 ps
CPU time 121.74 seconds
Started Sep 24 06:28:48 AM UTC 24
Finished Sep 24 06:30:52 AM UTC 24
Peak memory 209480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367188136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.367188136
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/47.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_alert_test.3406221886
Short name T893
Test name
Test status
Simulation time 13812395 ps
CPU time 0.86 seconds
Started Sep 24 06:30:10 AM UTC 24
Finished Sep 24 06:30:12 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406221886 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.3406221886
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_fifo_full.121963157
Short name T910
Test name
Test status
Simulation time 130579443577 ps
CPU time 81.45 seconds
Started Sep 24 06:29:30 AM UTC 24
Finished Sep 24 06:30:54 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121963157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.121963157
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_fifo_overflow.2909789780
Short name T920
Test name
Test status
Simulation time 90007428657 ps
CPU time 99.29 seconds
Started Sep 24 06:29:33 AM UTC 24
Finished Sep 24 06:31:15 AM UTC 24
Peak memory 209212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909789780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2909789780
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_fifo_reset.1040803282
Short name T177
Test name
Test status
Simulation time 13074904845 ps
CPU time 34.41 seconds
Started Sep 24 06:29:36 AM UTC 24
Finished Sep 24 06:30:11 AM UTC 24
Peak memory 208664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040803282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1040803282
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_intr.824116693
Short name T894
Test name
Test status
Simulation time 31781503232 ps
CPU time 33.11 seconds
Started Sep 24 06:29:39 AM UTC 24
Finished Sep 24 06:30:13 AM UTC 24
Peak memory 209524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824116693 -assert nopostproc +UVM_TESTNAME=uart
_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.824116693
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_long_xfer_wo_dly.804273294
Short name T1022
Test name
Test status
Simulation time 57474314928 ps
CPU time 316.91 seconds
Started Sep 24 06:30:01 AM UTC 24
Finished Sep 24 06:35:23 AM UTC 24
Peak memory 209520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804273294 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.804273294
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_loopback.1972263507
Short name T889
Test name
Test status
Simulation time 3309821887 ps
CPU time 3.05 seconds
Started Sep 24 06:29:58 AM UTC 24
Finished Sep 24 06:30:02 AM UTC 24
Peak memory 207928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972263507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1972263507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_noise_filter.1538821384
Short name T1100
Test name
Test status
Simulation time 89851728806 ps
CPU time 513.86 seconds
Started Sep 24 06:29:41 AM UTC 24
Finished Sep 24 06:38:21 AM UTC 24
Peak memory 209664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538821384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1538821384
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_perf.2798673448
Short name T940
Test name
Test status
Simulation time 18439890433 ps
CPU time 122.16 seconds
Started Sep 24 06:30:01 AM UTC 24
Finished Sep 24 06:32:06 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798673448 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2798673448
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_rx_oversample.680556562
Short name T891
Test name
Test status
Simulation time 4969699622 ps
CPU time 32 seconds
Started Sep 24 06:29:37 AM UTC 24
Finished Sep 24 06:30:10 AM UTC 24
Peak memory 203852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680556562 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.680556562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_rx_parity_err.3299754694
Short name T898
Test name
Test status
Simulation time 13516339281 ps
CPU time 34.42 seconds
Started Sep 24 06:29:49 AM UTC 24
Finished Sep 24 06:30:25 AM UTC 24
Peak memory 209280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299754694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3299754694
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_rx_start_bit_filter.322617103
Short name T892
Test name
Test status
Simulation time 6422978784 ps
CPU time 25.84 seconds
Started Sep 24 06:29:44 AM UTC 24
Finished Sep 24 06:30:11 AM UTC 24
Peak memory 203584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322617103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.322617103
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_smoke.2326105757
Short name T881
Test name
Test status
Simulation time 6198536002 ps
CPU time 13.51 seconds
Started Sep 24 06:29:21 AM UTC 24
Finished Sep 24 06:29:36 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326105757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2326105757
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_stress_all.1312293901
Short name T951
Test name
Test status
Simulation time 213886084883 ps
CPU time 137.82 seconds
Started Sep 24 06:30:03 AM UTC 24
Finished Sep 24 06:32:24 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312293901 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1312293901
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_stress_all_with_rand_reset.3505893269
Short name T915
Test name
Test status
Simulation time 26853791622 ps
CPU time 58.47 seconds
Started Sep 24 06:30:02 AM UTC 24
Finished Sep 24 06:31:03 AM UTC 24
Peak memory 220548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3505893269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all
_with_rand_reset.3505893269
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_tx_ovrd.1113973724
Short name T887
Test name
Test status
Simulation time 1331537269 ps
CPU time 1.9 seconds
Started Sep 24 06:29:58 AM UTC 24
Finished Sep 24 06:30:01 AM UTC 24
Peak memory 203332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113973724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1113973724
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/48.uart_tx_rx.2037329965
Short name T897
Test name
Test status
Simulation time 22906888421 ps
CPU time 44.65 seconds
Started Sep 24 06:29:30 AM UTC 24
Finished Sep 24 06:30:16 AM UTC 24
Peak memory 204104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037329965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2037329965
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/48.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_alert_test.1609561628
Short name T907
Test name
Test status
Simulation time 12133494 ps
CPU time 0.85 seconds
Started Sep 24 06:30:47 AM UTC 24
Finished Sep 24 06:30:49 AM UTC 24
Peak memory 203252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609561628 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1609561628
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_fifo_full.2797414491
Short name T911
Test name
Test status
Simulation time 70172417430 ps
CPU time 41.26 seconds
Started Sep 24 06:30:12 AM UTC 24
Finished Sep 24 06:30:55 AM UTC 24
Peak memory 205912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797414491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2797414491
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_fifo_overflow.2996554529
Short name T899
Test name
Test status
Simulation time 17718345514 ps
CPU time 22.19 seconds
Started Sep 24 06:30:13 AM UTC 24
Finished Sep 24 06:30:36 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996554529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2996554529
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_fifo_reset.2000398262
Short name T912
Test name
Test status
Simulation time 134149727055 ps
CPU time 43.59 seconds
Started Sep 24 06:30:14 AM UTC 24
Finished Sep 24 06:30:59 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000398262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2000398262
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_intr.3230992497
Short name T916
Test name
Test status
Simulation time 22077594629 ps
CPU time 51.22 seconds
Started Sep 24 06:30:16 AM UTC 24
Finished Sep 24 06:31:09 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230992497 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3230992497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_long_xfer_wo_dly.390793796
Short name T1179
Test name
Test status
Simulation time 152892254330 ps
CPU time 1380.75 seconds
Started Sep 24 06:30:42 AM UTC 24
Finished Sep 24 06:53:59 AM UTC 24
Peak memory 207168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390793796 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uar
t-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.390793796
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_loopback.1062375675
Short name T905
Test name
Test status
Simulation time 4742443732 ps
CPU time 4.34 seconds
Started Sep 24 06:30:38 AM UTC 24
Finished Sep 24 06:30:44 AM UTC 24
Peak memory 203764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062375675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1062375675
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_noise_filter.522063498
Short name T906
Test name
Test status
Simulation time 57675052497 ps
CPU time 27.24 seconds
Started Sep 24 06:30:17 AM UTC 24
Finished Sep 24 06:30:46 AM UTC 24
Peak memory 209400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522063498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.522063498
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_perf.2614016224
Short name T1031
Test name
Test status
Simulation time 12764644642 ps
CPU time 299.04 seconds
Started Sep 24 06:30:40 AM UTC 24
Finished Sep 24 06:35:43 AM UTC 24
Peak memory 203984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614016224 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2614016224
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_rx_oversample.3197907122
Short name T902
Test name
Test status
Simulation time 2625463906 ps
CPU time 22.57 seconds
Started Sep 24 06:30:15 AM UTC 24
Finished Sep 24 06:30:39 AM UTC 24
Peak memory 208228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197907122 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3197907122
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_rx_parity_err.1067423267
Short name T1172
Test name
Test status
Simulation time 239968366560 ps
CPU time 730.43 seconds
Started Sep 24 06:30:37 AM UTC 24
Finished Sep 24 06:42:57 AM UTC 24
Peak memory 212648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067423267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1067423267
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_rx_start_bit_filter.1775435770
Short name T903
Test name
Test status
Simulation time 5104959639 ps
CPU time 14.54 seconds
Started Sep 24 06:30:25 AM UTC 24
Finished Sep 24 06:30:41 AM UTC 24
Peak memory 203832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775435770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1775435770
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_smoke.51267507
Short name T896
Test name
Test status
Simulation time 502948662 ps
CPU time 3.06 seconds
Started Sep 24 06:30:11 AM UTC 24
Finished Sep 24 06:30:15 AM UTC 24
Peak memory 203728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51267507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_smoke.51267507
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_stress_all.2473220336
Short name T941
Test name
Test status
Simulation time 413889085599 ps
CPU time 79.29 seconds
Started Sep 24 06:30:45 AM UTC 24
Finished Sep 24 06:32:06 AM UTC 24
Peak memory 209868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473220336 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.2473220336
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_stress_all_with_rand_reset.799555837
Short name T936
Test name
Test status
Simulation time 5484783011 ps
CPU time 69.96 seconds
Started Sep 24 06:30:44 AM UTC 24
Finished Sep 24 06:31:56 AM UTC 24
Peak memory 218620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=799555837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all_
with_rand_reset.799555837
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_tx_ovrd.2261319497
Short name T904
Test name
Test status
Simulation time 1249813249 ps
CPU time 3.43 seconds
Started Sep 24 06:30:38 AM UTC 24
Finished Sep 24 06:30:43 AM UTC 24
Peak memory 203708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261319497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2261319497
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/49.uart_tx_rx.3544192691
Short name T923
Test name
Test status
Simulation time 114770664575 ps
CPU time 65.96 seconds
Started Sep 24 06:30:12 AM UTC 24
Finished Sep 24 06:31:20 AM UTC 24
Peak memory 205836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544192691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3544192691
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/49.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_alert_test.2737677475
Short name T437
Test name
Test status
Simulation time 41296035 ps
CPU time 0.87 seconds
Started Sep 24 06:03:10 AM UTC 24
Finished Sep 24 06:03:12 AM UTC 24
Peak memory 203256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737677475 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2737677475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_fifo_full.3276725312
Short name T303
Test name
Test status
Simulation time 99059484312 ps
CPU time 44.56 seconds
Started Sep 24 06:02:23 AM UTC 24
Finished Sep 24 06:03:09 AM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276725312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3276725312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.2333438368
Short name T125
Test name
Test status
Simulation time 78834631072 ps
CPU time 55.44 seconds
Started Sep 24 06:02:31 AM UTC 24
Finished Sep 24 06:03:28 AM UTC 24
Peak memory 208904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333438368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2333438368
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_fifo_reset.3355998586
Short name T144
Test name
Test status
Simulation time 212520048971 ps
CPU time 388.89 seconds
Started Sep 24 06:02:34 AM UTC 24
Finished Sep 24 06:09:08 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355998586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.3355998586
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_intr.3710020839
Short name T20
Test name
Test status
Simulation time 52255560038 ps
CPU time 83.5 seconds
Started Sep 24 06:02:37 AM UTC 24
Finished Sep 24 06:04:02 AM UTC 24
Peak memory 209256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710020839 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3710020839
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_long_xfer_wo_dly.2030442096
Short name T327
Test name
Test status
Simulation time 209665119289 ps
CPU time 453.95 seconds
Started Sep 24 06:02:49 AM UTC 24
Finished Sep 24 06:10:29 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030442096 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2030442096
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_loopback.2741383405
Short name T438
Test name
Test status
Simulation time 9063457503 ps
CPU time 31.2 seconds
Started Sep 24 06:02:44 AM UTC 24
Finished Sep 24 06:03:16 AM UTC 24
Peak memory 209352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741383405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2741383405
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_perf.1761033145
Short name T701
Test name
Test status
Simulation time 20437724911 ps
CPU time 1204.97 seconds
Started Sep 24 06:02:45 AM UTC 24
Finished Sep 24 06:23:04 AM UTC 24
Peak memory 207176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761033145 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1761033145
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_rx_oversample.877145742
Short name T28
Test name
Test status
Simulation time 2751929674 ps
CPU time 8.73 seconds
Started Sep 24 06:02:34 AM UTC 24
Finished Sep 24 06:02:44 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877145742 -assert nopostproc +UVM_TESTNAME=uart_base_test +U
VM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.877145742
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.3250164983
Short name T128
Test name
Test status
Simulation time 186403403952 ps
CPU time 383.57 seconds
Started Sep 24 06:02:40 AM UTC 24
Finished Sep 24 06:09:08 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250164983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.3250164983
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.319362758
Short name T345
Test name
Test status
Simulation time 2083906972 ps
CPU time 3.1 seconds
Started Sep 24 06:02:38 AM UTC 24
Finished Sep 24 06:02:42 AM UTC 24
Peak memory 203512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319362758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.319362758
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_smoke.1336001811
Short name T348
Test name
Test status
Simulation time 5649360984 ps
CPU time 13.88 seconds
Started Sep 24 06:02:22 AM UTC 24
Finished Sep 24 06:02:37 AM UTC 24
Peak memory 204108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336001811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_smoke.1336001811
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_stress_all.3047543733
Short name T287
Test name
Test status
Simulation time 14344523420 ps
CPU time 65.17 seconds
Started Sep 24 06:03:09 AM UTC 24
Finished Sep 24 06:04:16 AM UTC 24
Peak memory 203796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047543733 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3047543733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.2673164449
Short name T42
Test name
Test status
Simulation time 1861976768 ps
CPU time 26.35 seconds
Started Sep 24 06:03:07 AM UTC 24
Finished Sep 24 06:03:35 AM UTC 24
Peak memory 218812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2673164449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all_
with_rand_reset.2673164449
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.1478796975
Short name T339
Test name
Test status
Simulation time 700056926 ps
CPU time 4.81 seconds
Started Sep 24 06:02:43 AM UTC 24
Finished Sep 24 06:02:49 AM UTC 24
Peak memory 203924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478796975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1478796975
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/5.uart_tx_rx.1733869360
Short name T296
Test name
Test status
Simulation time 271835342323 ps
CPU time 98.84 seconds
Started Sep 24 06:02:23 AM UTC 24
Finished Sep 24 06:04:04 AM UTC 24
Peak memory 209592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733869360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1733869360
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/5.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/50.uart_stress_all_with_rand_reset.3650326407
Short name T926
Test name
Test status
Simulation time 5819772738 ps
CPU time 33.4 seconds
Started Sep 24 06:30:53 AM UTC 24
Finished Sep 24 06:31:28 AM UTC 24
Peak memory 220676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3650326407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_stress_all
_with_rand_reset.3650326407
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/50.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/51.uart_fifo_reset.3488177119
Short name T1084
Test name
Test status
Simulation time 115943756121 ps
CPU time 412.97 seconds
Started Sep 24 06:30:54 AM UTC 24
Finished Sep 24 06:37:53 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488177119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3488177119
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/51.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/51.uart_stress_all_with_rand_reset.4191444051
Short name T925
Test name
Test status
Simulation time 1485047888 ps
CPU time 28 seconds
Started Sep 24 06:30:54 AM UTC 24
Finished Sep 24 06:31:24 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4191444051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_stress_all
_with_rand_reset.4191444051
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/51.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/52.uart_fifo_reset.1880036607
Short name T924
Test name
Test status
Simulation time 29299483032 ps
CPU time 26.08 seconds
Started Sep 24 06:30:55 AM UTC 24
Finished Sep 24 06:31:23 AM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880036607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.1880036607
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/52.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/52.uart_stress_all_with_rand_reset.2949269605
Short name T922
Test name
Test status
Simulation time 2904365517 ps
CPU time 18.22 seconds
Started Sep 24 06:30:59 AM UTC 24
Finished Sep 24 06:31:19 AM UTC 24
Peak memory 222096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2949269605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_stress_all
_with_rand_reset.2949269605
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/52.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/53.uart_fifo_reset.3106603683
Short name T929
Test name
Test status
Simulation time 44817259849 ps
CPU time 39.94 seconds
Started Sep 24 06:31:00 AM UTC 24
Finished Sep 24 06:31:42 AM UTC 24
Peak memory 209608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106603683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3106603683
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/53.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/53.uart_stress_all_with_rand_reset.3837368953
Short name T933
Test name
Test status
Simulation time 43158287495 ps
CPU time 44.59 seconds
Started Sep 24 06:31:03 AM UTC 24
Finished Sep 24 06:31:49 AM UTC 24
Peak memory 226160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3837368953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_stress_all
_with_rand_reset.3837368953
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/53.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/54.uart_fifo_reset.4257467751
Short name T176
Test name
Test status
Simulation time 65491101735 ps
CPU time 131.16 seconds
Started Sep 24 06:31:09 AM UTC 24
Finished Sep 24 06:33:23 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257467751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.4257467751
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/54.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/54.uart_stress_all_with_rand_reset.1589947859
Short name T927
Test name
Test status
Simulation time 2385708894 ps
CPU time 19.22 seconds
Started Sep 24 06:31:11 AM UTC 24
Finished Sep 24 06:31:31 AM UTC 24
Peak memory 208432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1589947859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_stress_all
_with_rand_reset.1589947859
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/54.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/55.uart_fifo_reset.1091937183
Short name T221
Test name
Test status
Simulation time 24429771819 ps
CPU time 17.06 seconds
Started Sep 24 06:31:13 AM UTC 24
Finished Sep 24 06:31:31 AM UTC 24
Peak memory 209604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091937183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1091937183
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/55.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/55.uart_stress_all_with_rand_reset.2708986595
Short name T959
Test name
Test status
Simulation time 16698167356 ps
CPU time 93.54 seconds
Started Sep 24 06:31:13 AM UTC 24
Finished Sep 24 06:32:48 AM UTC 24
Peak memory 220544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2708986595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_stress_all
_with_rand_reset.2708986595
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/55.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/56.uart_fifo_reset.3339218130
Short name T170
Test name
Test status
Simulation time 23370205447 ps
CPU time 47.28 seconds
Started Sep 24 06:31:16 AM UTC 24
Finished Sep 24 06:32:05 AM UTC 24
Peak memory 203852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339218130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3339218130
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/56.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/56.uart_stress_all_with_rand_reset.1363117398
Short name T944
Test name
Test status
Simulation time 3244447985 ps
CPU time 47.57 seconds
Started Sep 24 06:31:18 AM UTC 24
Finished Sep 24 06:32:07 AM UTC 24
Peak memory 220348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1363117398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_stress_all
_with_rand_reset.1363117398
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/56.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/57.uart_fifo_reset.188184621
Short name T930
Test name
Test status
Simulation time 23454951689 ps
CPU time 22.77 seconds
Started Sep 24 06:31:20 AM UTC 24
Finished Sep 24 06:31:44 AM UTC 24
Peak memory 209524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188184621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.188184621
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/57.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/57.uart_stress_all_with_rand_reset.3606232718
Short name T934
Test name
Test status
Simulation time 5093378779 ps
CPU time 27.51 seconds
Started Sep 24 06:31:21 AM UTC 24
Finished Sep 24 06:31:50 AM UTC 24
Peak memory 220288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3606232718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_stress_all
_with_rand_reset.3606232718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/58.uart_stress_all_with_rand_reset.3665158092
Short name T945
Test name
Test status
Simulation time 7854529099 ps
CPU time 44.08 seconds
Started Sep 24 06:31:24 AM UTC 24
Finished Sep 24 06:32:10 AM UTC 24
Peak memory 218632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3665158092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_stress_all
_with_rand_reset.3665158092
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/58.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/59.uart_fifo_reset.1047770231
Short name T225
Test name
Test status
Simulation time 49061483531 ps
CPU time 26 seconds
Started Sep 24 06:31:28 AM UTC 24
Finished Sep 24 06:31:56 AM UTC 24
Peak memory 203864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047770231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1047770231
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/59.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/59.uart_stress_all_with_rand_reset.884894576
Short name T973
Test name
Test status
Simulation time 6920197633 ps
CPU time 112.27 seconds
Started Sep 24 06:31:31 AM UTC 24
Finished Sep 24 06:33:26 AM UTC 24
Peak memory 225812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=884894576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_stress_all_
with_rand_reset.884894576
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/59.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_alert_test.2770945393
Short name T440
Test name
Test status
Simulation time 69415732 ps
CPU time 0.86 seconds
Started Sep 24 06:03:55 AM UTC 24
Finished Sep 24 06:03:57 AM UTC 24
Peak memory 203256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770945393 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2770945393
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_fifo_reset.4251718719
Short name T331
Test name
Test status
Simulation time 34025153120 ps
CPU time 104.13 seconds
Started Sep 24 06:03:18 AM UTC 24
Finished Sep 24 06:05:04 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251718719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.4251718719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_intr.3463169293
Short name T19
Test name
Test status
Simulation time 27590572253 ps
CPU time 28.02 seconds
Started Sep 24 06:03:28 AM UTC 24
Finished Sep 24 06:03:57 AM UTC 24
Peak memory 203704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463169293 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3463169293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_long_xfer_wo_dly.2886618750
Short name T323
Test name
Test status
Simulation time 121562384448 ps
CPU time 181.44 seconds
Started Sep 24 06:03:44 AM UTC 24
Finished Sep 24 06:06:49 AM UTC 24
Peak memory 205960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886618750 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2886618750
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_loopback.2900369692
Short name T439
Test name
Test status
Simulation time 1530382103 ps
CPU time 7.38 seconds
Started Sep 24 06:03:37 AM UTC 24
Finished Sep 24 06:03:45 AM UTC 24
Peak memory 208144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900369692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2900369692
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_noise_filter.3281999813
Short name T300
Test name
Test status
Simulation time 62400198989 ps
CPU time 47.01 seconds
Started Sep 24 06:03:30 AM UTC 24
Finished Sep 24 06:04:19 AM UTC 24
Peak memory 208532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281999813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3281999813
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_perf.71621681
Short name T416
Test name
Test status
Simulation time 11988207508 ps
CPU time 649.11 seconds
Started Sep 24 06:03:44 AM UTC 24
Finished Sep 24 06:14:41 AM UTC 24
Peak memory 207232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71621681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.71621681
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_rx_oversample.3137515562
Short name T398
Test name
Test status
Simulation time 6298614940 ps
CPU time 37.39 seconds
Started Sep 24 06:03:20 AM UTC 24
Finished Sep 24 06:03:59 AM UTC 24
Peak memory 208368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137515562 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3137515562
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.4085250089
Short name T294
Test name
Test status
Simulation time 79637056357 ps
CPU time 24.52 seconds
Started Sep 24 06:03:35 AM UTC 24
Finished Sep 24 06:04:01 AM UTC 24
Peak memory 209512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085250089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.4085250089
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.314105433
Short name T304
Test name
Test status
Simulation time 3078095753 ps
CPU time 3.71 seconds
Started Sep 24 06:03:32 AM UTC 24
Finished Sep 24 06:03:37 AM UTC 24
Peak memory 203576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314105433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.314105433
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_smoke.2390608726
Short name T322
Test name
Test status
Simulation time 290501866 ps
CPU time 2.6 seconds
Started Sep 24 06:03:13 AM UTC 24
Finished Sep 24 06:03:17 AM UTC 24
Peak memory 203728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390608726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2390608726
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.2027587947
Short name T319
Test name
Test status
Simulation time 6171093598 ps
CPU time 30.44 seconds
Started Sep 24 06:03:36 AM UTC 24
Finished Sep 24 06:04:08 AM UTC 24
Peak memory 204104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027587947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2027587947
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/6.uart_tx_rx.669757875
Short name T101
Test name
Test status
Simulation time 34740745597 ps
CPU time 53.65 seconds
Started Sep 24 06:03:16 AM UTC 24
Finished Sep 24 06:04:12 AM UTC 24
Peak memory 209236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669757875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.669757875
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/6.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/60.uart_fifo_reset.2777925031
Short name T942
Test name
Test status
Simulation time 35238485417 ps
CPU time 32.95 seconds
Started Sep 24 06:31:31 AM UTC 24
Finished Sep 24 06:32:06 AM UTC 24
Peak memory 204108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777925031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.2777925031
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/60.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/60.uart_stress_all_with_rand_reset.679820858
Short name T939
Test name
Test status
Simulation time 3242070179 ps
CPU time 23.91 seconds
Started Sep 24 06:31:39 AM UTC 24
Finished Sep 24 06:32:05 AM UTC 24
Peak memory 217360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=679820858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_stress_all_
with_rand_reset.679820858
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/61.uart_fifo_reset.3636062951
Short name T178
Test name
Test status
Simulation time 199163232200 ps
CPU time 98.68 seconds
Started Sep 24 06:31:40 AM UTC 24
Finished Sep 24 06:33:20 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636062951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3636062951
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/61.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/61.uart_stress_all_with_rand_reset.1825367959
Short name T972
Test name
Test status
Simulation time 32970568154 ps
CPU time 92.54 seconds
Started Sep 24 06:31:43 AM UTC 24
Finished Sep 24 06:33:17 AM UTC 24
Peak memory 224720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1825367959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_stress_all
_with_rand_reset.1825367959
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/61.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/62.uart_fifo_reset.1691317318
Short name T169
Test name
Test status
Simulation time 115078685633 ps
CPU time 202.07 seconds
Started Sep 24 06:31:45 AM UTC 24
Finished Sep 24 06:35:10 AM UTC 24
Peak memory 209536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691317318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1691317318
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/62.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/62.uart_stress_all_with_rand_reset.3263179508
Short name T943
Test name
Test status
Simulation time 665061264 ps
CPU time 15.87 seconds
Started Sep 24 06:31:49 AM UTC 24
Finished Sep 24 06:32:06 AM UTC 24
Peak memory 218480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3263179508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_stress_all
_with_rand_reset.3263179508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/62.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/63.uart_fifo_reset.2794962521
Short name T948
Test name
Test status
Simulation time 37865809712 ps
CPU time 28.73 seconds
Started Sep 24 06:31:49 AM UTC 24
Finished Sep 24 06:32:19 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794962521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2794962521
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/63.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/63.uart_stress_all_with_rand_reset.1964504824
Short name T949
Test name
Test status
Simulation time 1732543510 ps
CPU time 27.67 seconds
Started Sep 24 06:31:50 AM UTC 24
Finished Sep 24 06:32:19 AM UTC 24
Peak memory 209384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1964504824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_stress_all
_with_rand_reset.1964504824
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/63.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/64.uart_fifo_reset.2185319450
Short name T171
Test name
Test status
Simulation time 66294430818 ps
CPU time 48.39 seconds
Started Sep 24 06:31:51 AM UTC 24
Finished Sep 24 06:32:41 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185319450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2185319450
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/64.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/65.uart_fifo_reset.1085575857
Short name T1041
Test name
Test status
Simulation time 113571105731 ps
CPU time 247.86 seconds
Started Sep 24 06:31:55 AM UTC 24
Finished Sep 24 06:36:07 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085575857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1085575857
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/65.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/65.uart_stress_all_with_rand_reset.3161614695
Short name T952
Test name
Test status
Simulation time 6255250039 ps
CPU time 27.47 seconds
Started Sep 24 06:31:56 AM UTC 24
Finished Sep 24 06:32:26 AM UTC 24
Peak memory 220280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3161614695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_stress_all
_with_rand_reset.3161614695
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/65.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/66.uart_fifo_reset.224576881
Short name T956
Test name
Test status
Simulation time 37784921700 ps
CPU time 39.99 seconds
Started Sep 24 06:31:56 AM UTC 24
Finished Sep 24 06:32:38 AM UTC 24
Peak memory 209504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224576881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.224576881
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/66.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/66.uart_stress_all_with_rand_reset.1388416456
Short name T963
Test name
Test status
Simulation time 4207111998 ps
CPU time 47.47 seconds
Started Sep 24 06:32:05 AM UTC 24
Finished Sep 24 06:32:55 AM UTC 24
Peak memory 218556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1388416456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_stress_all
_with_rand_reset.1388416456
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/66.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/67.uart_fifo_reset.3468274565
Short name T195
Test name
Test status
Simulation time 51962528183 ps
CPU time 77.48 seconds
Started Sep 24 06:32:06 AM UTC 24
Finished Sep 24 06:33:25 AM UTC 24
Peak memory 209256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468274565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3468274565
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/67.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/67.uart_stress_all_with_rand_reset.3321170094
Short name T960
Test name
Test status
Simulation time 3580129594 ps
CPU time 42.12 seconds
Started Sep 24 06:32:06 AM UTC 24
Finished Sep 24 06:32:49 AM UTC 24
Peak memory 218872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3321170094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_stress_all
_with_rand_reset.3321170094
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/67.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/68.uart_fifo_reset.3359579039
Short name T239
Test name
Test status
Simulation time 89320839079 ps
CPU time 183.24 seconds
Started Sep 24 06:32:06 AM UTC 24
Finished Sep 24 06:35:12 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359579039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3359579039
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/68.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/68.uart_stress_all_with_rand_reset.1265075560
Short name T954
Test name
Test status
Simulation time 9829314308 ps
CPU time 26.29 seconds
Started Sep 24 06:32:07 AM UTC 24
Finished Sep 24 06:32:34 AM UTC 24
Peak memory 218864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1265075560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_stress_all
_with_rand_reset.1265075560
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/68.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/69.uart_fifo_reset.3135008970
Short name T213
Test name
Test status
Simulation time 199771899342 ps
CPU time 84.42 seconds
Started Sep 24 06:32:07 AM UTC 24
Finished Sep 24 06:33:33 AM UTC 24
Peak memory 209604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135008970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3135008970
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/69.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/69.uart_stress_all_with_rand_reset.243543355
Short name T967
Test name
Test status
Simulation time 6405531061 ps
CPU time 59.22 seconds
Started Sep 24 06:32:07 AM UTC 24
Finished Sep 24 06:33:08 AM UTC 24
Peak memory 218544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=243543355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_stress_all_
with_rand_reset.243543355
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/69.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_alert_test.2407649320
Short name T442
Test name
Test status
Simulation time 14216344 ps
CPU time 0.88 seconds
Started Sep 24 06:04:20 AM UTC 24
Finished Sep 24 06:04:22 AM UTC 24
Peak memory 203256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407649320 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2407649320
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_fifo_full.2058534099
Short name T124
Test name
Test status
Simulation time 37535519636 ps
CPU time 71.52 seconds
Started Sep 24 06:03:58 AM UTC 24
Finished Sep 24 06:05:11 AM UTC 24
Peak memory 209348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058534099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2058534099
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.930209146
Short name T123
Test name
Test status
Simulation time 16654460604 ps
CPU time 17.31 seconds
Started Sep 24 06:04:00 AM UTC 24
Finished Sep 24 06:04:18 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930209146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.930209146
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_fifo_reset.469627129
Short name T302
Test name
Test status
Simulation time 11515265305 ps
CPU time 23.86 seconds
Started Sep 24 06:04:02 AM UTC 24
Finished Sep 24 06:04:27 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469627129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.469627129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_intr.3641326889
Short name T105
Test name
Test status
Simulation time 53049889629 ps
CPU time 27.94 seconds
Started Sep 24 06:04:03 AM UTC 24
Finished Sep 24 06:04:32 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641326889 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3641326889
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_loopback.3293018413
Short name T443
Test name
Test status
Simulation time 10424507836 ps
CPU time 16.06 seconds
Started Sep 24 06:04:12 AM UTC 24
Finished Sep 24 06:04:29 AM UTC 24
Peak memory 208304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293018413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3293018413
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_noise_filter.360545025
Short name T282
Test name
Test status
Simulation time 13952524610 ps
CPU time 61.69 seconds
Started Sep 24 06:04:03 AM UTC 24
Finished Sep 24 06:05:06 AM UTC 24
Peak memory 209664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360545025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.360545025
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_perf.2222574195
Short name T330
Test name
Test status
Simulation time 11589029670 ps
CPU time 167.89 seconds
Started Sep 24 06:04:13 AM UTC 24
Finished Sep 24 06:07:04 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222574195 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2222574195
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_rx_oversample.1312359600
Short name T441
Test name
Test status
Simulation time 2392224969 ps
CPU time 2.24 seconds
Started Sep 24 06:04:02 AM UTC 24
Finished Sep 24 06:04:05 AM UTC 24
Peak memory 208264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312359600 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1312359600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.2863743794
Short name T324
Test name
Test status
Simulation time 106772389595 ps
CPU time 262.34 seconds
Started Sep 24 06:04:06 AM UTC 24
Finished Sep 24 06:08:32 AM UTC 24
Peak memory 203916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863743794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.2863743794
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.1929690404
Short name T311
Test name
Test status
Simulation time 4918770959 ps
CPU time 9.18 seconds
Started Sep 24 06:04:05 AM UTC 24
Finished Sep 24 06:04:15 AM UTC 24
Peak memory 203836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929690404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1929690404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_smoke.2385388729
Short name T326
Test name
Test status
Simulation time 692809316 ps
CPU time 2.31 seconds
Started Sep 24 06:03:58 AM UTC 24
Finished Sep 24 06:04:01 AM UTC 24
Peak memory 203728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385388729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2385388729
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.1851598867
Short name T44
Test name
Test status
Simulation time 17367968841 ps
CPU time 56.79 seconds
Started Sep 24 06:04:16 AM UTC 24
Finished Sep 24 06:05:15 AM UTC 24
Peak memory 218296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1851598867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all_
with_rand_reset.1851598867
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.1282481514
Short name T293
Test name
Test status
Simulation time 546692219 ps
CPU time 3.22 seconds
Started Sep 24 06:04:08 AM UTC 24
Finished Sep 24 06:04:12 AM UTC 24
Peak memory 207804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282481514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1282481514
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/7.uart_tx_rx.3217251264
Short name T272
Test name
Test status
Simulation time 78802874429 ps
CPU time 25.46 seconds
Started Sep 24 06:03:58 AM UTC 24
Finished Sep 24 06:04:24 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217251264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3217251264
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/7.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/70.uart_fifo_reset.3916833657
Short name T984
Test name
Test status
Simulation time 60386693619 ps
CPU time 100.72 seconds
Started Sep 24 06:32:07 AM UTC 24
Finished Sep 24 06:33:50 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916833657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3916833657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/70.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/70.uart_stress_all_with_rand_reset.2518277569
Short name T946
Test name
Test status
Simulation time 149341552 ps
CPU time 2.61 seconds
Started Sep 24 06:32:08 AM UTC 24
Finished Sep 24 06:32:12 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2518277569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_stress_all
_with_rand_reset.2518277569
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/70.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/71.uart_fifo_reset.965882733
Short name T429
Test name
Test status
Simulation time 73495326758 ps
CPU time 33.46 seconds
Started Sep 24 06:32:09 AM UTC 24
Finished Sep 24 06:32:44 AM UTC 24
Peak memory 208888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965882733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.965882733
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/71.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/71.uart_stress_all_with_rand_reset.1270624294
Short name T955
Test name
Test status
Simulation time 1430836368 ps
CPU time 24.23 seconds
Started Sep 24 06:32:10 AM UTC 24
Finished Sep 24 06:32:36 AM UTC 24
Peak memory 208880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1270624294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_stress_all
_with_rand_reset.1270624294
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/71.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/72.uart_fifo_reset.2684195742
Short name T235
Test name
Test status
Simulation time 105109819348 ps
CPU time 204.64 seconds
Started Sep 24 06:32:12 AM UTC 24
Finished Sep 24 06:35:40 AM UTC 24
Peak memory 203724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684195742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2684195742
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/72.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/72.uart_stress_all_with_rand_reset.3757917293
Short name T961
Test name
Test status
Simulation time 2336648066 ps
CPU time 29.06 seconds
Started Sep 24 06:32:19 AM UTC 24
Finished Sep 24 06:32:50 AM UTC 24
Peak memory 220344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3757917293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_stress_all
_with_rand_reset.3757917293
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/72.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/73.uart_fifo_reset.2556867325
Short name T979
Test name
Test status
Simulation time 119457898341 ps
CPU time 82.93 seconds
Started Sep 24 06:32:19 AM UTC 24
Finished Sep 24 06:33:44 AM UTC 24
Peak memory 209352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556867325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2556867325
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/73.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/73.uart_stress_all_with_rand_reset.603790348
Short name T965
Test name
Test status
Simulation time 2545589750 ps
CPU time 34.7 seconds
Started Sep 24 06:32:20 AM UTC 24
Finished Sep 24 06:32:57 AM UTC 24
Peak memory 209720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=603790348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_stress_all_
with_rand_reset.603790348
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/73.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/74.uart_fifo_reset.1415410736
Short name T1050
Test name
Test status
Simulation time 105096117148 ps
CPU time 234.57 seconds
Started Sep 24 06:32:22 AM UTC 24
Finished Sep 24 06:36:20 AM UTC 24
Peak memory 209256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415410736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1415410736
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/74.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/74.uart_stress_all_with_rand_reset.3955785362
Short name T957
Test name
Test status
Simulation time 777721238 ps
CPU time 15.91 seconds
Started Sep 24 06:32:23 AM UTC 24
Finished Sep 24 06:32:40 AM UTC 24
Peak memory 224696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3955785362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_stress_all
_with_rand_reset.3955785362
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/74.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/75.uart_fifo_reset.3215749404
Short name T419
Test name
Test status
Simulation time 188438011481 ps
CPU time 93.34 seconds
Started Sep 24 06:32:25 AM UTC 24
Finished Sep 24 06:34:00 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215749404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3215749404
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/75.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/75.uart_stress_all_with_rand_reset.4208597243
Short name T964
Test name
Test status
Simulation time 1979818075 ps
CPU time 27.22 seconds
Started Sep 24 06:32:27 AM UTC 24
Finished Sep 24 06:32:55 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=4208597243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_stress_all
_with_rand_reset.4208597243
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/75.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/76.uart_fifo_reset.2570597402
Short name T962
Test name
Test status
Simulation time 60824059672 ps
CPU time 22.12 seconds
Started Sep 24 06:32:29 AM UTC 24
Finished Sep 24 06:32:52 AM UTC 24
Peak memory 204044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570597402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.2570597402
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/76.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/76.uart_stress_all_with_rand_reset.2681891150
Short name T969
Test name
Test status
Simulation time 28518707577 ps
CPU time 37.39 seconds
Started Sep 24 06:32:35 AM UTC 24
Finished Sep 24 06:33:14 AM UTC 24
Peak memory 222400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2681891150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_stress_all
_with_rand_reset.2681891150
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/77.uart_fifo_reset.1762896009
Short name T424
Test name
Test status
Simulation time 9974202902 ps
CPU time 37.91 seconds
Started Sep 24 06:32:37 AM UTC 24
Finished Sep 24 06:33:16 AM UTC 24
Peak memory 209276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762896009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1762896009
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/77.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/77.uart_stress_all_with_rand_reset.3460026234
Short name T975
Test name
Test status
Simulation time 3603184623 ps
CPU time 53.16 seconds
Started Sep 24 06:32:39 AM UTC 24
Finished Sep 24 06:33:34 AM UTC 24
Peak memory 222400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3460026234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_stress_all
_with_rand_reset.3460026234
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/77.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/78.uart_fifo_reset.3965450626
Short name T994
Test name
Test status
Simulation time 97797884744 ps
CPU time 92.88 seconds
Started Sep 24 06:32:40 AM UTC 24
Finished Sep 24 06:34:15 AM UTC 24
Peak memory 203852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965450626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3965450626
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/78.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/78.uart_stress_all_with_rand_reset.3643677702
Short name T982
Test name
Test status
Simulation time 15968082025 ps
CPU time 63.57 seconds
Started Sep 24 06:32:41 AM UTC 24
Finished Sep 24 06:33:47 AM UTC 24
Peak memory 224240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3643677702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_stress_all
_with_rand_reset.3643677702
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/78.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/79.uart_fifo_reset.3923933702
Short name T981
Test name
Test status
Simulation time 86399072790 ps
CPU time 63.5 seconds
Started Sep 24 06:32:41 AM UTC 24
Finished Sep 24 06:33:46 AM UTC 24
Peak memory 209312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923933702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3923933702
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/79.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/79.uart_stress_all_with_rand_reset.1368922689
Short name T966
Test name
Test status
Simulation time 5762987811 ps
CPU time 21.45 seconds
Started Sep 24 06:32:44 AM UTC 24
Finished Sep 24 06:33:07 AM UTC 24
Peak memory 218304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1368922689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_stress_all
_with_rand_reset.1368922689
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/79.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_alert_test.1398160924
Short name T446
Test name
Test status
Simulation time 19482120 ps
CPU time 0.83 seconds
Started Sep 24 06:04:59 AM UTC 24
Finished Sep 24 06:05:01 AM UTC 24
Peak memory 203256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398160924 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1398160924
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_fifo_full.1803514129
Short name T312
Test name
Test status
Simulation time 49043108853 ps
CPU time 125.45 seconds
Started Sep 24 06:04:25 AM UTC 24
Finished Sep 24 06:06:33 AM UTC 24
Peak memory 209272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803514129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1803514129
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.4086272504
Short name T119
Test name
Test status
Simulation time 59244931148 ps
CPU time 36.22 seconds
Started Sep 24 06:04:28 AM UTC 24
Finished Sep 24 06:05:06 AM UTC 24
Peak memory 209092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086272504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4086272504
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_fifo_reset.813273718
Short name T342
Test name
Test status
Simulation time 14520102449 ps
CPU time 27.92 seconds
Started Sep 24 06:04:28 AM UTC 24
Finished Sep 24 06:04:57 AM UTC 24
Peak memory 204100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813273718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.813273718
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_intr.3641548508
Short name T99
Test name
Test status
Simulation time 26023552313 ps
CPU time 27.2 seconds
Started Sep 24 06:04:30 AM UTC 24
Finished Sep 24 06:04:59 AM UTC 24
Peak memory 209264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641548508 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3641548508
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.3794467709
Short name T370
Test name
Test status
Simulation time 316035308312 ps
CPU time 170.77 seconds
Started Sep 24 06:04:45 AM UTC 24
Finished Sep 24 06:07:38 AM UTC 24
Peak memory 209260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794467709 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3794467709
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_loopback.1548381366
Short name T445
Test name
Test status
Simulation time 12916705086 ps
CPU time 15.29 seconds
Started Sep 24 06:04:42 AM UTC 24
Finished Sep 24 06:04:58 AM UTC 24
Peak memory 208556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548381366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1548381366
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_noise_filter.2012364591
Short name T321
Test name
Test status
Simulation time 229967678935 ps
CPU time 186.52 seconds
Started Sep 24 06:04:31 AM UTC 24
Finished Sep 24 06:07:41 AM UTC 24
Peak memory 218440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012364591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2012364591
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_perf.3116736967
Short name T863
Test name
Test status
Simulation time 21728899512 ps
CPU time 1431.67 seconds
Started Sep 24 06:04:43 AM UTC 24
Finished Sep 24 06:28:51 AM UTC 24
Peak memory 212660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116736967 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3116736967
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_rx_oversample.71052475
Short name T444
Test name
Test status
Simulation time 4717283821 ps
CPU time 12.59 seconds
Started Sep 24 06:04:28 AM UTC 24
Finished Sep 24 06:04:42 AM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71052475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UV
M_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.71052475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.205661511
Short name T334
Test name
Test status
Simulation time 275753339078 ps
CPU time 415.52 seconds
Started Sep 24 06:04:33 AM UTC 24
Finished Sep 24 06:11:34 AM UTC 24
Peak memory 203848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205661511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_rx_parity_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.205661511
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_rx_parity_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.2933162600
Short name T352
Test name
Test status
Simulation time 52155271823 ps
CPU time 43.61 seconds
Started Sep 24 06:04:32 AM UTC 24
Finished Sep 24 06:05:17 AM UTC 24
Peak memory 203580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933162600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2933162600
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_smoke.2505764109
Short name T310
Test name
Test status
Simulation time 677710524 ps
CPU time 2.88 seconds
Started Sep 24 06:04:23 AM UTC 24
Finished Sep 24 06:04:27 AM UTC 24
Peak memory 203800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505764109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2505764109
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.3645649922
Short name T333
Test name
Test status
Simulation time 2538551663 ps
CPU time 4.46 seconds
Started Sep 24 06:04:38 AM UTC 24
Finished Sep 24 06:04:44 AM UTC 24
Peak memory 203788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645649922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3645649922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/8.uart_tx_rx.2929325960
Short name T266
Test name
Test status
Simulation time 78651108818 ps
CPU time 167.86 seconds
Started Sep 24 06:04:24 AM UTC 24
Finished Sep 24 06:07:14 AM UTC 24
Peak memory 206156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929325960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.2929325960
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/8.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/80.uart_fifo_reset.934061623
Short name T992
Test name
Test status
Simulation time 33439353989 ps
CPU time 77.64 seconds
Started Sep 24 06:32:50 AM UTC 24
Finished Sep 24 06:34:09 AM UTC 24
Peak memory 203860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934061623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.934061623
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/80.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.1863596316
Short name T970
Test name
Test status
Simulation time 1558787779 ps
CPU time 23.71 seconds
Started Sep 24 06:32:50 AM UTC 24
Finished Sep 24 06:33:15 AM UTC 24
Peak memory 218824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1863596316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_stress_all
_with_rand_reset.1863596316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/80.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/81.uart_fifo_reset.1189446828
Short name T825
Test name
Test status
Simulation time 78289694708 ps
CPU time 46.62 seconds
Started Sep 24 06:32:51 AM UTC 24
Finished Sep 24 06:33:39 AM UTC 24
Peak memory 209340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189446828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.1189446828
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/81.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/81.uart_stress_all_with_rand_reset.585257815
Short name T977
Test name
Test status
Simulation time 12547073022 ps
CPU time 40.04 seconds
Started Sep 24 06:32:53 AM UTC 24
Finished Sep 24 06:33:34 AM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=585257815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_stress_all_
with_rand_reset.585257815
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/81.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/82.uart_fifo_reset.1285328382
Short name T987
Test name
Test status
Simulation time 77043121719 ps
CPU time 56.73 seconds
Started Sep 24 06:32:56 AM UTC 24
Finished Sep 24 06:33:54 AM UTC 24
Peak memory 209268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285328382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.1285328382
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/82.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/82.uart_stress_all_with_rand_reset.165897090
Short name T976
Test name
Test status
Simulation time 11815287860 ps
CPU time 36.64 seconds
Started Sep 24 06:32:56 AM UTC 24
Finished Sep 24 06:33:34 AM UTC 24
Peak memory 225740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=165897090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_stress_all_
with_rand_reset.165897090
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/82.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/83.uart_fifo_reset.2312001922
Short name T1003
Test name
Test status
Simulation time 137865240858 ps
CPU time 94.95 seconds
Started Sep 24 06:32:57 AM UTC 24
Finished Sep 24 06:34:34 AM UTC 24
Peak memory 209580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312001922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2312001922
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/83.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/83.uart_stress_all_with_rand_reset.2336711820
Short name T974
Test name
Test status
Simulation time 1899739391 ps
CPU time 23.7 seconds
Started Sep 24 06:33:08 AM UTC 24
Finished Sep 24 06:33:33 AM UTC 24
Peak memory 218824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2336711820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_stress_all
_with_rand_reset.2336711820
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/83.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/84.uart_stress_all_with_rand_reset.1602978301
Short name T985
Test name
Test status
Simulation time 2544129197 ps
CPU time 37.85 seconds
Started Sep 24 06:33:10 AM UTC 24
Finished Sep 24 06:33:50 AM UTC 24
Peak memory 218808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1602978301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_stress_all
_with_rand_reset.1602978301
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/84.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/85.uart_fifo_reset.1358031889
Short name T149
Test name
Test status
Simulation time 40008963820 ps
CPU time 76.6 seconds
Started Sep 24 06:33:14 AM UTC 24
Finished Sep 24 06:34:33 AM UTC 24
Peak memory 209336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358031889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1358031889
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/85.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/85.uart_stress_all_with_rand_reset.1352571761
Short name T1008
Test name
Test status
Simulation time 18555105150 ps
CPU time 91.55 seconds
Started Sep 24 06:33:15 AM UTC 24
Finished Sep 24 06:34:49 AM UTC 24
Peak memory 220544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1352571761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_stress_all
_with_rand_reset.1352571761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/85.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/86.uart_fifo_reset.3988572996
Short name T914
Test name
Test status
Simulation time 19869898112 ps
CPU time 18.68 seconds
Started Sep 24 06:33:16 AM UTC 24
Finished Sep 24 06:33:36 AM UTC 24
Peak memory 203916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988572996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.3988572996
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/86.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/86.uart_stress_all_with_rand_reset.795995073
Short name T980
Test name
Test status
Simulation time 19167472598 ps
CPU time 26.35 seconds
Started Sep 24 06:33:18 AM UTC 24
Finished Sep 24 06:33:45 AM UTC 24
Peak memory 218236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=795995073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_stress_all_
with_rand_reset.795995073
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/86.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/87.uart_fifo_reset.3988200737
Short name T174
Test name
Test status
Simulation time 12027851161 ps
CPU time 21.11 seconds
Started Sep 24 06:33:18 AM UTC 24
Finished Sep 24 06:33:40 AM UTC 24
Peak memory 209184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988200737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.3988200737
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/87.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/87.uart_stress_all_with_rand_reset.3708446165
Short name T986
Test name
Test status
Simulation time 2121835504 ps
CPU time 31.83 seconds
Started Sep 24 06:33:21 AM UTC 24
Finished Sep 24 06:33:54 AM UTC 24
Peak memory 209396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3708446165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_stress_all
_with_rand_reset.3708446165
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/88.uart_fifo_reset.3606413761
Short name T1058
Test name
Test status
Simulation time 106505929328 ps
CPU time 203.9 seconds
Started Sep 24 06:33:24 AM UTC 24
Finished Sep 24 06:36:51 AM UTC 24
Peak memory 209320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606413761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3606413761
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/88.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.2525876657
Short name T991
Test name
Test status
Simulation time 2678541361 ps
CPU time 41.16 seconds
Started Sep 24 06:33:26 AM UTC 24
Finished Sep 24 06:34:09 AM UTC 24
Peak memory 218560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2525876657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_stress_all
_with_rand_reset.2525876657
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/88.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/89.uart_fifo_reset.256098792
Short name T241
Test name
Test status
Simulation time 129458103871 ps
CPU time 34.58 seconds
Started Sep 24 06:33:27 AM UTC 24
Finished Sep 24 06:34:03 AM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256098792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.256098792
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/89.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/89.uart_stress_all_with_rand_reset.425492080
Short name T983
Test name
Test status
Simulation time 756339257 ps
CPU time 11.98 seconds
Started Sep 24 06:33:34 AM UTC 24
Finished Sep 24 06:33:47 AM UTC 24
Peak memory 218568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=425492080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_stress_all_
with_rand_reset.425492080
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/89.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_alert_test.3191678885
Short name T449
Test name
Test status
Simulation time 46557370 ps
CPU time 0.84 seconds
Started Sep 24 06:05:27 AM UTC 24
Finished Sep 24 06:05:29 AM UTC 24
Peak memory 203256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191678885 -assert nopostproc +UVM_TESTNAME=uart_
base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3191678885
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.1504328998
Short name T133
Test name
Test status
Simulation time 32676863033 ps
CPU time 63.45 seconds
Started Sep 24 06:05:02 AM UTC 24
Finished Sep 24 06:06:07 AM UTC 24
Peak memory 209328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504328998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1504328998
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_fifo_reset.4237630590
Short name T129
Test name
Test status
Simulation time 49835598131 ps
CPU time 119.26 seconds
Started Sep 24 06:05:04 AM UTC 24
Finished Sep 24 06:07:06 AM UTC 24
Peak memory 203912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237630590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.4237630590
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_intr.3450441666
Short name T74
Test name
Test status
Simulation time 12207892977 ps
CPU time 27.48 seconds
Started Sep 24 06:05:06 AM UTC 24
Finished Sep 24 06:05:35 AM UTC 24
Peak memory 209260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450441666 -assert nopostproc +UVM_TESTNAME=uar
t_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/u
art-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3450441666
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.3456773209
Short name T385
Test name
Test status
Simulation time 100836120823 ps
CPU time 248.36 seconds
Started Sep 24 06:05:21 AM UTC 24
Finished Sep 24 06:09:33 AM UTC 24
Peak memory 209332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456773209 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/ua
rt-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.3456773209
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_long_xfer_wo_dly/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_loopback.3400551485
Short name T448
Test name
Test status
Simulation time 8427197436 ps
CPU time 8.99 seconds
Started Sep 24 06:05:18 AM UTC 24
Finished Sep 24 06:05:28 AM UTC 24
Peak memory 209240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400551485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.uart_loopback.3400551485
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_loopback/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_noise_filter.646894719
Short name T325
Test name
Test status
Simulation time 113158629751 ps
CPU time 99.39 seconds
Started Sep 24 06:05:08 AM UTC 24
Finished Sep 24 06:06:50 AM UTC 24
Peak memory 209932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646894719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_noise_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.646894719
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_noise_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_rx_oversample.2961439567
Short name T447
Test name
Test status
Simulation time 4906572798 ps
CPU time 12.48 seconds
Started Sep 24 06:05:06 AM UTC 24
Finished Sep 24 06:05:20 AM UTC 24
Peak memory 203776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961439567 -assert nopostproc +UVM_TESTNAME=uart_base_test +
UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2961439567
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_rx_oversample/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.3603153857
Short name T343
Test name
Test status
Simulation time 4021586623 ps
CPU time 15.78 seconds
Started Sep 24 06:05:09 AM UTC 24
Finished Sep 24 06:05:26 AM UTC 24
Peak memory 203580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603153857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_rx_start_bit_filter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3603153857
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_rx_start_bit_filter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_smoke.2173908303
Short name T349
Test name
Test status
Simulation time 705760637 ps
CPU time 1.62 seconds
Started Sep 24 06:04:59 AM UTC 24
Finished Sep 24 06:05:02 AM UTC 24
Peak memory 207360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173908303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2173908303
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_stress_all.1588544139
Short name T937
Test name
Test status
Simulation time 264080707439 ps
CPU time 1580.1 seconds
Started Sep 24 06:05:25 AM UTC 24
Finished Sep 24 06:32:04 AM UTC 24
Peak memory 209304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588544139 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1588544139
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3095365475
Short name T45
Test name
Test status
Simulation time 11969035038 ps
CPU time 52.33 seconds
Started Sep 24 06:05:24 AM UTC 24
Finished Sep 24 06:06:18 AM UTC 24
Peak memory 218292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=3095365475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all_
with_rand_reset.3095365475
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1038165810
Short name T380
Test name
Test status
Simulation time 1219495097 ps
CPU time 6.28 seconds
Started Sep 24 06:05:16 AM UTC 24
Finished Sep 24 06:05:23 AM UTC 24
Peak memory 204052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038165810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1038165810
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_tx_ovrd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/9.uart_tx_rx.1525499661
Short name T344
Test name
Test status
Simulation time 8548696419 ps
CPU time 16.55 seconds
Started Sep 24 06:05:01 AM UTC 24
Finished Sep 24 06:05:19 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525499661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.1525499661
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/9.uart_tx_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/90.uart_fifo_reset.1745084575
Short name T217
Test name
Test status
Simulation time 224107309818 ps
CPU time 130.33 seconds
Started Sep 24 06:33:34 AM UTC 24
Finished Sep 24 06:35:47 AM UTC 24
Peak memory 209532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745084575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1745084575
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/90.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/90.uart_stress_all_with_rand_reset.2054929354
Short name T1012
Test name
Test status
Simulation time 26031093461 ps
CPU time 81 seconds
Started Sep 24 06:33:35 AM UTC 24
Finished Sep 24 06:34:58 AM UTC 24
Peak memory 218336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2054929354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_stress_all
_with_rand_reset.2054929354
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/90.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/91.uart_fifo_reset.3084146549
Short name T997
Test name
Test status
Simulation time 29227043594 ps
CPU time 47.23 seconds
Started Sep 24 06:33:35 AM UTC 24
Finished Sep 24 06:34:24 AM UTC 24
Peak memory 203792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084146549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3084146549
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/91.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.2886181035
Short name T990
Test name
Test status
Simulation time 1714252910 ps
CPU time 30.41 seconds
Started Sep 24 06:33:35 AM UTC 24
Finished Sep 24 06:34:07 AM UTC 24
Peak memory 209412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2886181035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_stress_all
_with_rand_reset.2886181035
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/91.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/92.uart_fifo_reset.3610378212
Short name T1026
Test name
Test status
Simulation time 49124165001 ps
CPU time 116.51 seconds
Started Sep 24 06:33:37 AM UTC 24
Finished Sep 24 06:35:36 AM UTC 24
Peak memory 203784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610378212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3610378212
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/92.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.2807466962
Short name T993
Test name
Test status
Simulation time 9100074115 ps
CPU time 32.07 seconds
Started Sep 24 06:33:39 AM UTC 24
Finished Sep 24 06:34:13 AM UTC 24
Peak memory 218288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2807466962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_stress_all
_with_rand_reset.2807466962
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/92.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/93.uart_fifo_reset.66400506
Short name T988
Test name
Test status
Simulation time 37976198692 ps
CPU time 19.85 seconds
Started Sep 24 06:33:41 AM UTC 24
Finished Sep 24 06:34:02 AM UTC 24
Peak memory 209592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66400506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart
_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.66400506
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/93.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/94.uart_fifo_reset.189080842
Short name T425
Test name
Test status
Simulation time 273336490119 ps
CPU time 229.61 seconds
Started Sep 24 06:33:45 AM UTC 24
Finished Sep 24 06:37:38 AM UTC 24
Peak memory 209528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189080842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.189080842
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/94.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.1694651651
Short name T989
Test name
Test status
Simulation time 7761136726 ps
CPU time 16.13 seconds
Started Sep 24 06:33:46 AM UTC 24
Finished Sep 24 06:34:03 AM UTC 24
Peak memory 218228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=1694651651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_stress_all
_with_rand_reset.1694651651
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/95.uart_fifo_reset.3546349312
Short name T995
Test name
Test status
Simulation time 18042958058 ps
CPU time 34.78 seconds
Started Sep 24 06:33:47 AM UTC 24
Finished Sep 24 06:34:23 AM UTC 24
Peak memory 209256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546349312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3546349312
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/95.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.467659119
Short name T1006
Test name
Test status
Simulation time 27141596862 ps
CPU time 58.31 seconds
Started Sep 24 06:33:47 AM UTC 24
Finished Sep 24 06:34:47 AM UTC 24
Peak memory 218636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=467659119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_stress_all_
with_rand_reset.467659119
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/95.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/96.uart_fifo_reset.2818565636
Short name T998
Test name
Test status
Simulation time 243283037645 ps
CPU time 35.35 seconds
Started Sep 24 06:33:48 AM UTC 24
Finished Sep 24 06:34:25 AM UTC 24
Peak memory 204044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818565636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.2818565636
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/96.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.856970316
Short name T1007
Test name
Test status
Simulation time 3313807747 ps
CPU time 56.05 seconds
Started Sep 24 06:33:50 AM UTC 24
Finished Sep 24 06:34:49 AM UTC 24
Peak memory 220340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=856970316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_stress_all_
with_rand_reset.856970316
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/96.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.973322637
Short name T193
Test name
Test status
Simulation time 42801497609 ps
CPU time 72.82 seconds
Started Sep 24 06:33:55 AM UTC 24
Finished Sep 24 06:35:10 AM UTC 24
Peak memory 218280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=973322637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_stress_all_
with_rand_reset.973322637
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/97.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2991405749
Short name T1019
Test name
Test status
Simulation time 121258639740 ps
CPU time 78.52 seconds
Started Sep 24 06:33:55 AM UTC 24
Finished Sep 24 06:35:16 AM UTC 24
Peak memory 203748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991405749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=ua
rt_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2991405749
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/98.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.2305774831
Short name T996
Test name
Test status
Simulation time 4200006483 ps
CPU time 21.59 seconds
Started Sep 24 06:34:00 AM UTC 24
Finished Sep 24 06:34:23 AM UTC 24
Peak memory 220280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=2305774831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_stress_all
_with_rand_reset.2305774831
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/98.uart_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/99.uart_fifo_reset.896571807
Short name T1010
Test name
Test status
Simulation time 32968639539 ps
CPU time 46.49 seconds
Started Sep 24 06:34:03 AM UTC 24
Finished Sep 24 06:34:50 AM UTC 24
Peak memory 204116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896571807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uar
t_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.896571807
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/99.uart_fifo_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default/99.uart_stress_all_with_rand_reset.474442559
Short name T999
Test name
Test status
Simulation time 3001910738 ps
CPU time 19.76 seconds
Started Sep 24 06:34:04 AM UTC 24
Finished Sep 24 06:34:25 AM UTC 24
Peak memory 218556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=u
art_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tc
l +ntb_random_seed=474442559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_stress_all_
with_rand_reset.474442559
Directory /workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/99.uart_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%