USBDEV Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: 30db5a999

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 9.190s 10.011ms 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.840s 74.907us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.140s 85.213us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.740s 1.184ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.620s 356.434us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 8.570s 10.009ms 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.140s 85.213us 20 20 100.00
usbdev_csr_aliasing 3.620s 356.434us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.360s 703.517us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.290s 175.071us 5 5 100.00
V1 TOTAL 64 115 55.65
V2 intr_test usbdev_intr_test 0.800s 45.028us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.200s 280.630us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.200s 280.630us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.840s 74.907us 5 5 100.00
usbdev_csr_rw 1.140s 85.213us 20 20 100.00
usbdev_csr_aliasing 3.620s 356.434us 5 5 100.00
usbdev_same_csr_outstanding 1.600s 143.734us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.840s 74.907us 5 5 100.00
usbdev_csr_rw 1.140s 85.213us 20 20 100.00
usbdev_csr_aliasing 3.620s 356.434us 5 5 100.00
usbdev_same_csr_outstanding 1.600s 143.734us 20 20 100.00
V2 TOTAL 90 90 100.00
V2S tl_intg_err usbdev_sec_cm 10.620s 10.005ms 2 5 40.00
usbdev_tl_intg_err 10.660s 10.010ms 1 20 5.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 10.660s 10.010ms 1 20 5.00
V2S TOTAL 3 25 12.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_stress_all_with_rand_reset 0.610s 2.102us 0 50 0.00
usbdev_stress_all 0.600s 0 50 0.00
TOTAL 157 330 47.58

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 6 75.00
V2 3 3 3 100.00
V2S 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.28 90.13 74.19 95.23 0.00 86.85 92.01 95.54

Failure Buckets

Past Results