Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
82.72	89.92	54.76	93.90		75.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	34858330	10268	0	0
ep_in_enable_rd_A	34858330	1002	0	0
ep_out_enable_rd_A	34858330	1008	0	0
in_iso_rd_A	34858330	892	0	0
intr_enable_rd_A	34858330	1210	0	0
out_iso_rd_A	34858330	897	0	0
phy_config_rd_A	34858330	543	0	0
phy_pins_drive_rd_A	34858330	907	0	0
rxenable_setup_rd_A	34858330	914	0	0
set_nak_out_rd_A	34858330	1046	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	10268	0	0
T16	1697	2	0	0
T17	2222	3	0	0
T18	7935	523	0	0
T19	5621	1	0	0
T20	14692	0	0	0
T21	0	331	0	0
T24	1587	0	0	0
T25	8221	3	0	0
T26	2202	0	0	0
T27	6932	3	0	0
T48	14022	1	0	0
T50	0	3	0	0
T57	0	6	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	1002	0	0
T19	5621	7	0	0
T20	14692	0	0	0
T21	5500	0	0	0
T25	8221	0	0	0
T26	2202	0	0	0
T37	3401	104	0	0
T38	0	4	0	0
T47	6898	48	0	0
T48	14022	0	0	0
T56	3290	0	0	0
T60	1251	0	0	0
T68	0	2	0	0
T80	0	8	0	0
T81	0	27	0	0
T82	0	64	0	0
T83	0	11	0	0
T84	0	136	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	1008	0	0
T19	5621	2	0	0
T20	14692	0	0	0
T21	5500	0	0	0
T25	8221	0	0	0
T26	2202	0	0	0
T30	0	2	0	0
T37	3401	49	0	0
T38	0	1	0	0
T47	6898	54	0	0
T48	14022	0	0	0
T56	3290	0	0	0
T60	1251	0	0	0
T68	0	93	0	0
T81	0	33	0	0
T82	0	32	0	0
T83	0	5	0	0
T84	0	135	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	892	0	0
T19	5621	12	0	0
T20	14692	0	0	0
T21	5500	0	0	0
T25	8221	0	0	0
T26	2202	0	0	0
T30	0	6	0	0
T37	3401	46	0	0
T38	0	3	0	0
T47	6898	3	0	0
T48	14022	0	0	0
T56	3290	0	0	0
T60	1251	0	0	0
T68	0	2	0	0
T80	0	1	0	0
T81	0	14	0	0
T82	0	17	0	0
T84	0	130	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	1210	0	0
T19	5621	3	0	0
T20	14692	0	0	0
T24	1587	7	0	0
T25	8221	0	0	0
T26	2202	0	0	0
T35	1980	23	0	0
T37	3401	54	0	0
T38	0	1	0	0
T47	6898	1	0	0
T48	14022	0	0	0
T56	3290	0	0	0
T81	0	18	0	0
T82	0	59	0	0
T83	0	4	0	0
T85	0	8	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	897	0	0
T22	3391	0	0	0
T23	999	0	0	0
T30	0	5	0	0
T37	3401	5	0	0
T38	1751	2	0	0
T47	6898	6	0	0
T50	7889	0	0	0
T59	0	112	0	0
T61	4081	0	0	0
T62	1806	0	0	0
T63	2070	0	0	0
T64	1650	0	0	0
T68	0	40	0	0
T81	0	13	0	0
T82	0	36	0	0
T83	0	15	0	0
T84	0	120	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	543	0	0
T19	5621	1	0	0
T20	14692	0	0	0
T21	5500	6	0	0
T25	8221	0	0	0
T26	2202	0	0	0
T37	3401	37	0	0
T38	0	4	0	0
T47	6898	1	0	0
T48	14022	0	0	0
T56	3290	0	0	0
T59	0	53	0	0
T60	1251	0	0	0
T68	0	7	0	0
T81	0	16	0	0
T82	0	66	0	0
T84	0	128	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	907	0	0
T19	5621	7	0	0
T20	14692	0	0	0
T21	5500	0	0	0
T25	8221	0	0	0
T26	2202	0	0	0
T37	3401	69	0	0
T38	0	6	0	0
T47	6898	7	0	0
T48	14022	0	0	0
T56	3290	0	0	0
T60	1251	0	0	0
T68	0	41	0	0
T80	0	8	0	0
T81	0	60	0	0
T82	0	16	0	0
T83	0	4	0	0
T84	0	127	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	914	0	0
T19	5621	2	0	0
T20	14692	0	0	0
T21	5500	0	0	0
T25	8221	0	0	0
T26	2202	0	0	0
T37	3401	12	0	0
T38	0	4	0	0
T47	6898	71	0	0
T48	14022	0	0	0
T56	3290	0	0	0
T59	0	175	0	0
T60	1251	0	0	0
T68	0	62	0	0
T81	0	25	0	0
T82	0	22	0	0
T84	0	151	0	0
T86	0	1	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34858330	1046	0	0
T19	5621	5	0	0
T20	14692	0	0	0
T21	5500	0	0	0
T25	8221	0	0	0
T26	2202	0	0	0
T30	0	5	0	0
T37	3401	30	0	0
T47	6898	60	0	0
T48	14022	0	0	0
T56	3290	0	0	0
T59	0	119	0	0
T60	1251	0	0	0
T68	0	51	0	0
T81	0	28	0	0
T82	0	59	0	0
T83	0	6	0	0
T84	0	149	0	0