Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.72 89.92 54.76 93.90 75.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 82.72 89.92 54.76 93.90 75.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.72 89.92 54.76 93.90 75.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.08 94.26 82.58 97.14 31.25 92.22 95.05


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_event 100.00 100.00 100.00
gen_no_stubbed_memory.u_memory_1p 81.46 79.17 66.67 80.00 100.00
gen_no_stubbed_memory.u_tlul2sram 59.54 73.11 43.16 50.00 71.88
i_usbdev_iomux 61.67 88.89 44.44 83.33 30.00
intr_av_empty 89.58 100.00 58.33 100.00 100.00
intr_av_overflow 81.25 100.00 25.00 100.00 100.00
intr_disconnected 89.58 100.00 58.33 100.00 100.00
intr_frame 81.25 100.00 25.00 100.00 100.00
intr_host_lost 81.25 100.00 25.00 100.00 100.00
intr_hw_pkt_received 91.67 100.00 66.67 100.00 100.00
intr_hw_pkt_sent 81.25 100.00 25.00 100.00 100.00
intr_link_in_err 81.25 100.00 25.00 100.00 100.00
intr_link_out_err 81.25 100.00 25.00 100.00 100.00
intr_link_reset 89.58 100.00 58.33 100.00 100.00
intr_link_resume 81.25 100.00 25.00 100.00 100.00
intr_link_suspend 81.25 100.00 25.00 100.00 100.00
intr_powered 89.58 100.00 58.33 100.00 100.00
intr_rx_bitstuff_err 81.25 100.00 25.00 100.00 100.00
intr_rx_crc_err 81.25 100.00 25.00 100.00 100.00
intr_rx_full 81.25 100.00 25.00 100.00 100.00
intr_rx_pid_err 81.25 100.00 25.00 100.00 100.00
tlul_assert_device 95.24 100.00 85.71 100.00
u_reg 95.53 98.33 93.86 100.00 98.34 87.10
usbdev_avfifo 82.08 95.00 58.33 75.00 100.00
usbdev_csr_assert 100.00 100.00
usbdev_impl 72.68 84.21 71.91 31.25 76.03 100.00
usbdev_rxfifo 83.58 95.00 61.54 77.78 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usbdev
Line No.TotalCoveredPercent
TOTAL12911689.92
CONT_ASSIGN11811100.00
CONT_ASSIGN19211100.00
ALWAYS19455100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN24711100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27511100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN280100.00
ALWAYS30300
ALWAYS30333100.00
ALWAYS31100
ALWAYS31144100.00
ALWAYS32000
ALWAYS32033100.00
ALWAYS32700
ALWAYS32733100.00
ALWAYS33400
ALWAYS33433100.00
ALWAYS34100
ALWAYS34122100.00
ALWAYS34733100.00
ALWAYS3543266.67
ALWAYS36100
ALWAYS361300.00
ALWAYS37033100.00
ALWAYS38233100.00
ALWAYS38900
ALWAYS389300.00
ALWAYS39610990.00
ALWAYS41400
ALWAYS41433100.00
ALWAYS42200
ALWAYS42233100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN43411100.00
CONT_ASSIGN53311100.00
CONT_ASSIGN53411100.00
CONT_ASSIGN53611100.00
CONT_ASSIGN53711100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55811100.00
ALWAYS56400
ALWAYS56488100.00
CONT_ASSIGN64411100.00
CONT_ASSIGN64511100.00
CONT_ASSIGN64611100.00
CONT_ASSIGN64711100.00
CONT_ASSIGN65511100.00
ALWAYS6648787.50
CONT_ASSIGN67811100.00
CONT_ASSIGN67900
CONT_ASSIGN682100.00
CONT_ASSIGN68311100.00
CONT_ASSIGN74011100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN74511100.00
CONT_ASSIGN99511100.00
CONT_ASSIGN99611100.00
CONT_ASSIGN99711100.00
CONT_ASSIGN99811100.00
CONT_ASSIGN103811100.00
CONT_ASSIGN104111100.00
CONT_ASSIGN105011100.00
ALWAYS10535360.00
ALWAYS106233100.00
CONT_ASSIGN107511100.00
CONT_ASSIGN107811100.00
CONT_ASSIGN108511100.00
ALWAYS108933100.00
CONT_ASSIGN109611100.00
CONT_ASSIGN110111100.00
CONT_ASSIGN110311100.00
CONT_ASSIGN111100
CONT_ASSIGN111300
CONT_ASSIGN111500
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
118 1 1
192 1 1
194 1 1
195 1 1
197 1 1
198 1 1
200 1 1
221 1 1
222 1 1
223 1 1
247 1 1
272 1 1
273 1 1
274 1 1
275 1 1
276 1 1
280 0 1
303 1 1
304 1 1
305 1 1
311 1 1
312 1 1
313 1 1
314 1 1
320 1 1
321 1 1
322 1 1
327 1 1
328 1 1
329 1 1
334 1 1
335 1 1
336 1 1
341 1 1
342 1 1
347 1 1
348 1 1
349 1 1
354 1 1
355 1 1
356 0 1
MISSING_ELSE
361 0 1
362 0 1
363 0 1
370 1 1
371 1 1
372 1 1
382 1 1
383 1 1
384 1 1
MISSING_ELSE
389 0 1
390 0 1
391 0 1
396 1 1
397 1 1
398 1 1
399 1 1
400 1 1
402 1 1
404 1 1
405 1 1
406 1 1
408 0 1
MISSING_ELSE
414 1 1
415 1 1
416 1 1
422 1 1
423 1 1
424 1 1
432 1 1
433 1 1
434 1 1
533 1 1
534 1 1
536 1 1
537 1 1
555 1 1
558 1 1
564 1 1
565 1 1
566 1 1
567 1 1
568 1 1
569 1 1
571 1 1
572 1 1
644 1 1
645 1 1
646 1 1
647 1 1
655 1 1
664 1 1
665 1 1
666 1 1
667 1 1
669 1 1
670 1 1
672 1 1
673 0 1
MISSING_ELSE
678 1 1
679 unreachable
682 0 1
683 1 1
740 1 1
741 1 1
745 1 1
995 1 1
996 1 1
997 1 1
998 1 1
1038 1 1
1041 1 1
1050 1 1
1053 1 1
1054 1 1
1055 0 1
1056 1 1
1057 0 1
MISSING_ELSE
1062 1 1
1063 1 1
1065 1 1
1075 1 1
1078 1 1
1085 1 1
1089 1 1
1090 1 1
1092 1 1
1096 1 1
1101 1 1
1103 1 1
1111 unreachable
1113 unreachable
1115 unreachable


Cond Coverage for Module : usbdev
TotalCoveredPercent
Conditions844654.76
Logical844654.76
Non-Logical00
Event00

 LINE       192
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       221
 EXPRESSION (connect_en & ((~av_rvalid)))
             -----1----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       222
 EXPRESSION (reg2hw.avbuffer.qe & ((~av_fifo_wready)))
             ---------1--------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       223
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       247
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100Not Covered
1000Not Covered

 LINE       349
 EXPRESSION (reg2hw.data_toggle_clear[i].q & reg2hw.data_toggle_clear[i].qe)
             --------------1--------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       355
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Not Covered

 LINE       383
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T3

 LINE       402
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T4

 LINE       406
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Not Covered

 LINE       424
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       433
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       434
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       537
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       644
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       645
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       646
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       647
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       670
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       678
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       683
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       745
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       1041
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       1050
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1054
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       1056
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       1078
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       1085
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       1085
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1085
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100CoveredT1,T2,T3

 LINE       1101
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       1103
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Toggle Coverage for Module : usbdev
TotalCoveredPercent
Totals 67 60 89.55
Total Bits 426 400 93.90
Total Bits 0->1 213 200 93.90
Total Bits 1->0 213 200 93.90

Ports 67 60 89.55
Port Bits 426 400 93.90
Port Bits 0->1 213 200 93.90
Port Bits 1->0 213 200 93.90

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T27,T16,T17 Yes T27,T16,T17 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T7,T28,T29 Yes T7,T28,T29 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T7,T28,T29 Yes T7,T28,T29 OUTPUT
cio_usb_dp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_usb_dn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
usb_rx_d_i No No No INPUT
cio_usb_dp_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_usb_dp_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_usb_dn_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_usb_dn_en_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
usb_tx_se0_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
usb_tx_d_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_sense_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
usb_dp_pullup_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
usb_dn_pullup_o Yes Yes T30,T31 Yes T30,T31 OUTPUT
usb_rx_enable_o Yes Yes T32,T27,T33 Yes T32,T27,T33 OUTPUT
usb_tx_use_d_se0_o Yes Yes T32,T27,T34 Yes T32,T27,T33 OUTPUT
usb_aon_suspend_req_o Yes Yes T31 Yes T31 OUTPUT
usb_aon_wake_ack_o Yes Yes T32,T27,T19 Yes T32,T27,T19 OUTPUT
usb_aon_bus_reset_i Unreachable Unreachable Unreachable INPUT
usb_aon_sense_lost_i Unreachable Unreachable Unreachable INPUT
usb_aon_wake_detect_active_i Unreachable Unreachable Unreachable INPUT
usb_ref_val_o No No No OUTPUT
usb_ref_pulse_o No No No OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
intr_pkt_received_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
intr_pkt_sent_o Yes Yes T35,T36,T24 Yes T35,T36,T24 OUTPUT
intr_powered_o Yes Yes T32,T27,T37 Yes T32,T27,T37 OUTPUT
intr_disconnected_o Yes Yes T32,T27,T35 Yes T32,T27,T37 OUTPUT
intr_host_lost_o Yes Yes T35,T36,T24 Yes T35,T36,T24 OUTPUT
intr_link_reset_o Yes Yes T35,T24,T38 Yes T35,T24,T38 OUTPUT
intr_link_suspend_o Yes Yes T36,T24,T38 Yes T36,T24,T38 OUTPUT
intr_link_resume_o Yes Yes T35,T36,T24 Yes T35,T36,T24 OUTPUT
intr_av_empty_o Yes Yes T24,T39,T40 Yes T24,T39,T40 OUTPUT
intr_rx_full_o Yes Yes T35,T36,T24 Yes T35,T36,T24 OUTPUT
intr_av_overflow_o Yes Yes T35,T36,T24 Yes T35,T36,T24 OUTPUT
intr_link_in_err_o Yes Yes T35,T36,T24 Yes T35,T36,T24 OUTPUT
intr_link_out_err_o Yes Yes T35,T36,T39 Yes T35,T36,T39 OUTPUT
intr_rx_crc_err_o Yes Yes T35,T36,T24 Yes T35,T36,T24 OUTPUT
intr_rx_pid_err_o Yes Yes T35,T36,T24 Yes T35,T36,T24 OUTPUT
intr_rx_bitstuff_err_o Yes Yes T35,T24,T39 Yes T35,T24,T39 OUTPUT
intr_frame_o Yes Yes T35,T36,T24 Yes T35,T36,T24 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : usbdev
Line No.TotalCoveredPercent
Branches 40 30 75.00
TERNARY 433 2 1 50.00
TERNARY 434 2 1 50.00
TERNARY 1078 2 1 50.00
TERNARY 1085 3 2 66.67
TERNARY 645 2 2 100.00
TERNARY 646 2 2 100.00
TERNARY 647 2 2 100.00
TERNARY 683 2 1 50.00
IF 194 3 3 100.00
IF 355 2 1 50.00
IF 383 2 2 100.00
IF 398 4 3 75.00
IF 567 2 2 100.00
IF 1054 3 1 33.33
IF 1062 2 2 100.00
IF 1089 2 2 100.00
IF 664 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 433 (cfg_pinflip) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 434 ((!cfg_pinflip)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 1078 (usb_ref_disable) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 1085 (usb_ref_pulse_o) ? -2-: 1085 ((((!link_active) || host_lost) || usb_ref_disable)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 645 (usb_mem_b_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 646 (usb_mem_b_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 647 (usb_mem_b_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 683 (gen_no_stubbed_memory.mem_b_read_q) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((!rst_n)) -2-: 197 if (us_tick)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 355 if ((in_ep_xact_end && in_endpoint_val))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 383 if ((rx_wvalid && out_endpoint_val))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 398 if (event_link_reset) -2-: 402 if ((setup_received & out_endpoint_val)) -3-: 406 if ((in_ep_xact_end & in_endpoint_val))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T4
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 567 if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 1054 if ((use_diff_rcvr & (!usb_rx_enable_o))) -2-: 1056 if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1062 if ((!rst_n))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 1089 if ((!rst_n))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 664 if ((!rst_ni)) -2-: 672 if (gen_no_stubbed_memory.mem_b_read_q)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


Assert Coverage for Module : usbdev
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 34 34 100.00 34 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 34 34 100.00 34 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 34228874 34206381 0 0
CIODnEnKnown_A 34228874 34206381 0 0
CIODnKnown_A 34228874 34206381 0 0
CIODpEnKnown_A 34228874 34206381 0 0
CIODpKnown_A 34228874 34206381 0 0
FpvSecCmRegWeOnehotCheck_A 34228874 40 0 0
TlOAReadyKnown_A 34228874 34206381 0 0
TlODValidKnown_A 34228874 34206381 0 0
USBAonSuspendReqKnown_A 34228874 34206381 0 0
USBAonWakeAckKnown_A 34228874 34206381 0 0
USBDnPUKnown_A 34228874 34206381 0 0
USBDpPUKnown_A 34228874 34206381 0 0
USBIntrAvEmptyKnown_A 34228874 34206381 0 0
USBIntrAvOverKnown_A 34228874 34206381 0 0
USBIntrDisConKnown_A 34228874 34206381 0 0
USBIntrFrameKnown_A 34228874 34206381 0 0
USBIntrHostLostKnown_A 34228874 34206381 0 0
USBIntrLinkInErrKnown_A 34228874 34206381 0 0
USBIntrLinkOutErrKnown_A 34228874 34206381 0 0
USBIntrLinkResKnown_A 34228874 34206381 0 0
USBIntrLinkRstKnown_A 34228874 34206381 0 0
USBIntrLinkSusKnown_A 34228874 34206381 0 0
USBIntrPktRcvdKnown_A 34228874 34206381 0 0
USBIntrPktSentKnown_A 34228874 34206381 0 0
USBIntrPwrdKnown_A 34228874 34206381 0 0
USBIntrRxBitstuffErrKnown_A 34228874 34206381 0 0
USBIntrRxCrCErrKnown_A 34228874 34206381 0 0
USBIntrRxFullKnown_A 34228874 34206381 0 0
USBIntrRxPidErrKnown_A 34228874 34206381 0 0
USBRefPulseKnown_A 34228874 34206381 0 0
USBRefValKnown_A 34228874 34206381 0 0
USBRxEnableKnown_A 34228874 34206381 0 0
USBTxDKnown_A 34228874 34206381 0 0
USBTxSe0Known_A 34228874 34206381 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

CIODnEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

CIODnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

CIODpEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

CIODpKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 40 0 0
T5 403130 0 0 0
T6 401942 0 0 0
T7 4637 10 0 0
T8 401806 0 0 0
T9 401519 0 0 0
T10 401645 0 0 0
T13 401654 0 0 0
T28 0 10 0 0
T29 0 20 0 0
T41 402505 0 0 0
T42 401951 0 0 0
T43 401524 0 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBAonSuspendReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBAonWakeAckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBDnPUKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBDpPUKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrAvEmptyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrAvOverKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrDisConKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrFrameKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrHostLostKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrLinkInErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrLinkOutErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrLinkResKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrLinkRstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrLinkSusKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrPktRcvdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrPktSentKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrPwrdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrRxBitstuffErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrRxCrCErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrRxFullKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBIntrRxPidErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBRefPulseKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBRefValKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBRxEnableKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBTxDKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

USBTxSe0Known_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%