Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usb_fs_nb_in_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
46.43 55.66 34.29 0.00 42.22 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe 46.43 55.66 34.29 0.00 42.22 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
46.43 55.66 34.29 0.00 42.22 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
46.43 55.66 34.29 0.00 42.22 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
77.78 100.00 33.33 100.00 u_usb_fs_nb_pe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usb_fs_nb_in_pe
Line No.TotalCoveredPercent
TOTAL1065955.66
CONT_ASSIGN10211100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15611100.00
ALWAYS16649918.37
ALWAYS26833100.00
ALWAYS27633100.00
ALWAYS28588100.00
ALWAYS2986466.67
ALWAYS3107571.43
ALWAYS3246466.67
ALWAYS33655100.00
ALWAYS3465480.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 1 1
116 1 1
117 1 1
119 1 1
125 1 1
129 1 1
133 1 1
139 1 1
140 1 1
147 1 1
148 1 1
151 1 1
153 1 1
156 1 1
166 1 1
167 1 1
168 1 1
169 1 1
170 1 1
171 1 1
172 1 1
174 1 1
175 0 1
178 1 1
183 0 1
185 0 1
190 0 1
191 0 1
192 0 1
193 0 1
194 0 1
195 0 1
196 0 1
197 0 1
199 0 1
200 0 1
206 0 1
207 0 1
208 0 1
209 0 1
211 0 1
212 0 1
214 0 1
218 0 1
223 0 1
224 0 1
==> MISSING_ELSE
232 0 1
234 0 1
235 0 1
236 0 1
237 0 1
238 0 1
240 0 1
245 0 1
246 0 1
247 0 1
248 0 1
249 0 1
250 0 1
251 0 1
252 0 1
253 0 1
255 0 1
268 1 1
269 1 1
271 1 1
276 1 1
277 1 1
279 1 1
285 1 1
286 1 1
287 1 1
288 1 1
289 1 1
290 1 1
292 1 1
293 1 1
298 1 1
299 1 1
301 1 1
302 1 1
303 0 1
304 0 1
==> MISSING_ELSE
310 1 1
311 1 1
312 1 1
314 1 1
315 0 1
316 0 1
318 1 1
324 1 1
326 1 1
327 0 1
328 1 1
329 0 1
MISSING_ELSE
332 1 1
336 1 1
337 1 1
338 1 1
339 1 1
341 1 1
346 1 1
347 1 1
349 1 1
350 0 1
352 1 1


Cond Coverage for Module : usb_fs_nb_in_pe
TotalCoveredPercent
Conditions702434.29
Logical702434.29
Non-Logical00
Event00

 LINE       119
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101CoveredT1,T2,T3
1110Not Covered
1111CoveredT1,T2,T3

 LINE       119
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       119
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       125
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT3,T5,T6
11CoveredT1,T2,T4

 LINE       125
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T4

 LINE       129
 EXPRESSION (token_received && (rx_pid == UsbPidIn))
             -------1------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       129
 SUB-EXPRESSION (rx_pid == UsbPidIn)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       133
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidAck))
             ------1-----    -------2------    ----------3----------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT1,T2,T3
111Not Covered

 LINE       133
 SUB-EXPRESSION (rx_pid == UsbPidAck)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       140
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       151
 EXPRESSION (in_ep_enabled_i[in_ep_index_d] & ep_in_hw)
             ---------------1--------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       153
 EXPRESSION (in_ep_has_data_i[in_ep_index] & ((~in_ep_data_done_i[in_ep_index])))
             --------------1--------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       156
 EXPRESSION ((logic'((in_xact_state == StSendData))) & more_data_to_send)
             -------------------1-------------------   --------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       174
 EXPRESSION (ep_active && in_token_received)
             ----1----    --------2--------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       206
 EXPRESSION (((!more_data_to_send)) || (((&in_ep_get_addr_o)) && tx_data_get_i))
             -----------1----------    --------------------2-------------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       206
 SUB-EXPRESSION (((&in_ep_get_addr_o)) && tx_data_get_i)
                 ----------1----------    ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       236
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       288
 EXPRESSION (link_reset_i || ((!link_active_i)))
             ------1-----    ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       301
 EXPRESSION (in_xact_state == StIdle)
            ------------1------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       303
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       326
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11Not Covered

 LINE       328
 EXPRESSION ((in_xact_state == StWaitAck) && ack_received)
             --------------1-------------    ------2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       328
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       349
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       349
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

FSM Coverage for Module : usb_fs_nb_in_pe
Summary for FSM :: in_xact_state
TotalCoveredPercent
States 6 1 16.67 (Not included in score)
Transitions 12 0 0.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: in_xact_state
statesLine No.CoveredTests
StIdle 289 Covered T1,T2,T3
StRcvdIn 175 Not Covered
StSendData 190 Not Covered
StWaitAck 235 Not Covered
StWaitAckStart 212 Not Covered
StWaitTxEnd 214 Not Covered


transitionsLine No.CoveredTests
StIdle->StRcvdIn 175 Not Covered
StRcvdIn->StIdle 289 Not Covered
StRcvdIn->StSendData 190 Not Covered
StSendData->StIdle 289 Not Covered
StSendData->StWaitAckStart 212 Not Covered
StSendData->StWaitTxEnd 214 Not Covered
StWaitAck->StIdle 289 Not Covered
StWaitAck->StRcvdIn 249 Not Covered
StWaitAckStart->StIdle 289 Not Covered
StWaitAckStart->StWaitAck 235 Not Covered
StWaitTxEnd->StIdle 289 Not Covered
StWaitTxEnd->StWaitAckStart 224 Not Covered



Branch Coverage for Module : usb_fs_nb_in_pe
Line No.TotalCoveredPercent
Branches 45 19 42.22
TERNARY 140 2 1 50.00
CASE 172 20 1 5.00
IF 268 2 2 100.00
IF 276 2 2 100.00
IF 285 3 3 100.00
IF 298 4 2 50.00
IF 310 3 2 66.67
IF 326 3 1 33.33
IF 336 3 3 100.00
IF 346 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 140 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 172 case (in_xact_state) -2-: 174 if ((ep_active && in_token_received)) -3-: 185 if (in_ep_iso_i[in_ep_index]) -4-: 192 if (in_ep_stall_i[in_ep_index]) -5-: 195 if (in_ep_has_data_i[in_ep_index]) -6-: 206 if (((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i))) -7-: 207 if (in_ep_iso_i[in_ep_index]) -8-: 211 if (tx_pkt_end_i) -9-: 223 if (tx_pkt_end_i) -10-: 234 if (rx_pkt_start_i) -11-: 236 if ((timeout_cntdown_q == '0)) -12-: 245 if (ack_received) -13-: 248 if (in_token_received) -14-: 251 if (rx_pkt_end_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14-StatusTests
StIdle 1 - - - - - - - - - - - - Not Covered
StIdle 0 - - - - - - - - - - - - Covered T1,T2,T3
StRcvdIn - 1 - - - - - - - - - - - Not Covered
StRcvdIn - 0 1 - - - - - - - - - - Not Covered
StRcvdIn - 0 0 1 - - - - - - - - - Not Covered
StRcvdIn - 0 0 0 - - - - - - - - - Not Covered
StSendData - - - - 1 1 - - - - - - - Not Covered
StSendData - - - - 1 0 1 - - - - - - Not Covered
StSendData - - - - 1 0 0 - - - - - - Not Covered
StSendData - - - - 0 - - - - - - - - Not Covered
StWaitTxEnd - - - - - - - 1 - - - - - Not Covered
StWaitTxEnd - - - - - - - 0 - - - - - Not Covered
StWaitAckStart - - - - - - - - 1 - - - - Not Covered
StWaitAckStart - - - - - - - - 0 1 - - - Not Covered
StWaitAckStart - - - - - - - - 0 0 - - - Not Covered
StWaitAck - - - - - - - - - - 1 - - Not Covered
StWaitAck - - - - - - - - - - 0 1 - Not Covered
StWaitAck - - - - - - - - - - 0 0 1 Not Covered
StWaitAck - - - - - - - - - - 0 0 0 Not Covered
default - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 268 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 276 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 285 if ((!rst_ni)) -2-: 288 if ((link_reset_i || (!link_active_i)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 298 if ((!rst_ni)) -2-: 301 if ((in_xact_state == StIdle)) -3-: 303 if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Not Covered


LineNo. Expression -1-: 310 if ((!rst_ni)) -2-: 314 if (in_token_received)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 326 if ((setup_token_received && ep_active)) -2-: 328 if (((in_xact_state == StWaitAck) && ack_received))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 336 if ((!rst_ni)) -2-: 338 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 346 if ((!rst_ni)) -2-: 349 if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


Assert Coverage for Module : usb_fs_nb_in_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InXactStateValid_A 34228874 34206381 0 0


InXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 34228874 34206381 0 0
T1 402267 402054 0 0
T2 401984 401770 0 0
T3 403505 403245 0 0
T4 401643 401397 0 0
T5 403130 402959 0 0
T6 401942 401741 0 0
T7 4637 3841 0 0
T8 401806 401584 0 0
T9 401519 401249 0 0
T10 401645 401388 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%