USBDEV Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 10.600s 8.478ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.950s 75.520us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.040s 85.466us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.150s 1.753ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.620s 388.420us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.390s 87.796us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.040s 85.466us 20 20 100.00
usbdev_csr_aliasing 3.620s 388.420us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.550s 500.333us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.370s 213.672us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 10.490s 8.454ms 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 0.890s 196.015us 50 50 100.00
V2 av_buffer usbdev_av_buffer 10.250s 8.378ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling phy_config_eop_single_bit_handling 0 0 --
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 10.150s 8.400ms 49 50 98.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 10.690s 8.420ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 10.320s 8.391ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 10.110s 8.419ms 50 50 100.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 10.460s 8.420ms 50 50 100.00
V2 in_stall usbdev_in_stall 10.520s 8.382ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 11.130s 8.423ms 50 50 100.00
V2 pkt_received usbdev_pkt_received 10.660s 8.387ms 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 10.540s 8.409ms 50 50 100.00
V2 disconnected disconnected 0 0 --
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend link_suspend 0 0 --
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err link_in_err 0 0 --
V2 rx_crc_err rx_crc_err 0 0 --
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err rx_bitstuff_err 0 0 --
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 10.220s 8.401ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 10.370s 8.406ms 50 50 100.00
V2 in_data_stage in_data_stage 0 0 --
V2 out_data_stage out_data_stage 0 0 --
V2 endpoint_access endpoint_access 0 0 --
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 10.120s 8.418ms 49 50 98.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 10.210s 8.375ms 50 50 100.00
V2 nak_trans usbdev_nak_trans 10.510s 8.429ms 50 50 100.00
V2 stall_trans usbdev_stall_trans 10.400s 8.402ms 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 10.030s 8.459ms 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 10.520s 8.402ms 50 50 100.00
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.028m 30.481ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume aon_wake_resume 0 0 --
V2 aon_wake_reset aon_wake_reset 0 0 --
V2 aon_wake_disconnect aon_wake_disconnect 0 0 --
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore data_toggle_restore 0 0 --
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 2.300s 295.077us 50 50 100.00
V2 intr_test usbdev_intr_test 0.760s 36.299us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.320s 291.074us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.320s 291.074us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.950s 75.520us 5 5 100.00
usbdev_csr_rw 1.040s 85.466us 20 20 100.00
usbdev_csr_aliasing 3.620s 388.420us 5 5 100.00
usbdev_same_csr_outstanding 1.830s 188.374us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.950s 75.520us 5 5 100.00
usbdev_csr_rw 1.040s 85.466us 20 20 100.00
usbdev_csr_aliasing 3.620s 388.420us 5 5 100.00
usbdev_same_csr_outstanding 1.830s 188.374us 20 20 100.00
V2 TOTAL 1188 1190 99.83
V2S tl_intg_err usbdev_sec_cm 1.430s 635.847us 5 5 100.00
usbdev_tl_intg_err 4.990s 749.939us 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 4.990s 749.939us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 32.450s 5.107ms 1 1 100.00
random_length_in_trans 10.170s 8.424ms 50 50 100.00
min_length_in_transaction 10.410s 8.409ms 50 50 100.00
max_length_in_transaction 10.540s 8.514ms 50 50 100.00
usbdev_stress_all_with_rand_reset 0.690s 52.760us 0 50 0.00
usbdev_stress_all 0.620s 0 50 0.00
TOTAL 1329 1431 92.87

Testplan Progress

Items Total Written Passing Progress
N.A. 3 3 1 33.33
V1 8 8 8 100.00
V2 78 25 23 29.49
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
88.83 96.54 89.37 97.32 50.00 94.46 97.56 96.58

Failure Buckets

Past Results