USBDEV Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 13.930s 8.420ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.940s 133.997us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.040s 82.969us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.340s 1.414ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.670s 304.286us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.590s 91.973us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.040s 82.969us 20 20 100.00
usbdev_csr_aliasing 3.670s 304.286us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.680s 694.381us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.200s 151.090us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 13.800s 8.468ms 46 50 92.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 14.150s 8.370ms 50 50 100.00
V2 av_buffer usbdev_av_buffer 13.730s 8.396ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 14.030s 8.425ms 49 50 98.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 13.880s 8.401ms 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 13.610s 8.420ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 13.260s 8.402ms 49 50 98.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 13.740s 8.409ms 49 50 98.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 13.820s 8.407ms 50 50 100.00
V2 in_stall usbdev_in_stall 13.720s 8.365ms 50 50 100.00
V2 out_iso out_iso 0 0 --
V2 in_iso usbdev_in_iso 13.810s 8.469ms 49 50 98.00
V2 pkt_received usbdev_pkt_received 13.700s 8.373ms 49 50 98.00
V2 pkt_sent usbdev_pkt_sent 13.890s 8.430ms 50 50 100.00
V2 disconnected usbdev_disconnected 13.860s 8.350ms 49 50 98.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 17.300s 11.557ms 49 50 98.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 14.550s 8.436ms 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 13.730s 8.373ms 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 13.260s 8.356ms 24 50 48.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 14.800s 8.374ms 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 13.140s 8.414ms 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 15.500s 9.286ms 44 50 88.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 14.830s 8.396ms 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 13.870s 8.363ms 49 50 98.00
V2 nak_trans usbdev_nak_trans 13.570s 8.438ms 50 50 100.00
V2 stall_trans usbdev_stall_trans 13.380s 8.411ms 49 50 98.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 14.070s 8.408ms 48 50 96.00
V2 pending_in_trans usbdev_pending_in_trans 14.170s 8.386ms 50 50 100.00
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 1.011m 30.495ms 42 50 84.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume aon_wake_resume 0 0 --
V2 aon_wake_reset aon_wake_reset 0 0 --
V2 aon_wake_disconnect aon_wake_disconnect 0 0 --
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 15.320s 9.356ms 46 50 92.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 14.980s 8.546ms 50 50 100.00
V2 intr_test usbdev_intr_test 0.750s 63.410us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.640s 313.159us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.640s 313.159us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.940s 133.997us 5 5 100.00
usbdev_csr_rw 1.040s 82.969us 20 20 100.00
usbdev_csr_aliasing 3.670s 304.286us 5 5 100.00
usbdev_same_csr_outstanding 1.690s 305.808us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.940s 133.997us 5 5 100.00
usbdev_csr_rw 1.040s 82.969us 20 20 100.00
usbdev_csr_aliasing 3.670s 304.286us 5 5 100.00
usbdev_same_csr_outstanding 1.690s 305.808us 20 20 100.00
V2 TOTAL 1531 1590 96.29
V2S tl_intg_err usbdev_sec_cm 1.220s 357.508us 5 5 100.00
usbdev_tl_intg_err 6.430s 2.039ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.430s 2.039ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 33.520s 5.108ms 1 1 100.00
usbdev_out_iso 14.290s 8.418ms 49 50 98.00
random_length_in_trans 14.150s 8.489ms 50 50 100.00
min_length_in_transaction 13.660s 8.378ms 50 50 100.00
max_length_in_transaction 13.800s 8.469ms 48 50 96.00
usbdev_stress_all_with_rand_reset 0.660s 17.327us 0 50 0.00
usbdev_stress_all 0.650s 0 50 0.00
TOTAL 1721 1881 91.49

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 1 25.00
V1 8 8 8 100.00
V2 76 33 18 23.68
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.58 96.68 90.82 97.00 60.94 94.71 97.35 96.58

Failure Buckets

Past Results