Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.17	0.00	0.00	92.66		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1916280	11819	0	0
ep_in_enable_rd_A	1916280	3211	0	0
ep_out_enable_rd_A	1916280	3337	0	0
in_iso_rd_A	1916280	3273	0	0
intr_enable_rd_A	1916280	4711	0	0
out_iso_rd_A	1916280	2995	0	0
phy_config_rd_A	1916280	1795	0	0
phy_pins_drive_rd_A	1916280	2693	0	0
rxenable_setup_rd_A	1916280	3853	0	0
set_nak_out_rd_A	1916280	3385	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	11819	0	0
T2	41446	8	0	0
T3	2564	0	0	0
T4	2530	9	0	0
T5	3808	11	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T15	3474	0	0	0
T16	4097	0	0	0
T17	0	21	0	0
T18	0	722	0	0
T20	0	1054	0	0
T21	0	505	0	0
T22	0	11	0	0
T25	82349	5	0	0
T27	0	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	3211	0	0
T2	41446	592	0	0
T3	2564	0	0	0
T4	2530	0	0	0
T5	3808	0	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T15	3474	48	0	0
T16	4097	0	0	0
T25	82349	0	0	0
T32	0	50	0	0
T37	0	6	0	0
T47	0	19	0	0
T48	0	1	0	0
T56	0	351	0	0
T57	0	24	0	0
T58	0	348	0	0
T59	0	60	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	3337	0	0
T2	41446	569	0	0
T3	2564	0	0	0
T4	2530	0	0	0
T5	3808	0	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T15	3474	78	0	0
T16	4097	0	0	0
T25	82349	0	0	0
T32	0	12	0	0
T37	0	67	0	0
T47	0	18	0	0
T48	0	29	0	0
T56	0	317	0	0
T57	0	109	0	0
T58	0	146	0	0
T59	0	23	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	3273	0	0
T2	41446	538	0	0
T3	2564	0	0	0
T4	2530	0	0	0
T5	3808	0	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T15	3474	8	0	0
T16	4097	0	0	0
T18	0	10	0	0
T25	82349	0	0	0
T32	0	102	0	0
T47	0	21	0	0
T48	0	45	0	0
T56	0	388	0	0
T57	0	71	0	0
T58	0	230	0	0
T59	0	27	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	4711	0	0
T1	2323	12	0	0
T2	41446	584	0	0
T3	2564	0	0	0
T4	2530	0	0	0
T5	3808	0	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T14	0	27	0	0
T15	3474	165	0	0
T16	4097	0	0	0
T32	0	84	0	0
T47	0	38	0	0
T56	0	760	0	0
T60	0	16	0	0
T61	0	8	0	0
T62	0	14	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	2995	0	0
T2	41446	342	0	0
T3	2564	0	0	0
T4	2530	0	0	0
T5	3808	0	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T15	3474	56	0	0
T16	4097	0	0	0
T25	82349	0	0	0
T32	0	68	0	0
T37	0	2	0	0
T47	0	31	0	0
T48	0	50	0	0
T56	0	267	0	0
T57	0	47	0	0
T58	0	327	0	0
T59	0	80	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	1795	0	0
T2	41446	193	0	0
T3	2564	0	0	0
T4	2530	0	0	0
T5	3808	0	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T15	3474	24	0	0
T16	4097	0	0	0
T25	82349	0	0	0
T32	0	35	0	0
T37	0	17	0	0
T47	0	23	0	0
T56	0	201	0	0
T57	0	45	0	0
T58	0	77	0	0
T59	0	59	0	0
T63	0	20	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	2693	0	0
T2	41446	362	0	0
T3	2564	0	0	0
T4	2530	0	0	0
T5	3808	0	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T15	3474	58	0	0
T16	4097	0	0	0
T25	82349	0	0	0
T32	0	15	0	0
T37	0	4	0	0
T47	0	30	0	0
T48	0	55	0	0
T56	0	402	0	0
T57	0	14	0	0
T58	0	186	0	0
T59	0	64	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	3853	0	0
T2	41446	593	0	0
T3	2564	0	0	0
T4	2530	0	0	0
T5	3808	0	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T15	3474	51	0	0
T16	4097	0	0	0
T25	82349	0	0	0
T32	0	109	0	0
T37	0	42	0	0
T47	0	20	0	0
T48	0	12	0	0
T56	0	606	0	0
T57	0	105	0	0
T58	0	263	0	0
T59	0	19	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1916280	3385	0	0
T2	41446	611	0	0
T3	2564	0	0	0
T4	2530	0	0	0
T5	3808	0	0	0
T6	14226	0	0	0
T7	4881	0	0	0
T8	9454	0	0	0
T15	3474	67	0	0
T16	4097	0	0	0
T25	82349	0	0	0
T32	0	75	0	0
T37	0	32	0	0
T47	0	39	0	0
T48	0	59	0	0
T56	0	384	0	0
T57	0	54	0	0
T58	0	342	0	0
T59	0	51	0	0