Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61277	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	62341	1		T1	20		T2	408		T3	24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	76878	1		T1	11		T2	2016		T3	20
values[0x0]	23121	1		T1	6		T2	252		T3	11
values[0x1]	23619	1		T1	5		T2	232		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42532	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	81086	1		T1	21		T2	1062		T3	30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	452	1		T6	10		T8	3		T25	14
valid_sources[0x01]	342	1		T2	11		T6	3		T4	7
valid_sources[0x02]	603	1		T2	15		T6	1		T4	4
valid_sources[0x03]	491	1		T2	16		T6	5		T4	1
valid_sources[0x04]	928	1		T2	4		T6	5		T9	1
valid_sources[0x05]	548	1		T2	4		T6	8		T5	2
valid_sources[0x06]	474	1		T6	11		T5	3		T8	4
valid_sources[0x07]	355	1		T2	10		T6	4		T5	1
valid_sources[0x08]	430	1		T2	13		T3	2		T6	5
valid_sources[0x09]	372	1		T2	9		T6	12		T8	1
valid_sources[0x0a]	501	1		T2	11		T6	15		T4	10
valid_sources[0x0b]	321	1		T2	16		T6	10		T5	1
valid_sources[0x0c]	532	1		T2	2		T6	4		T5	2
valid_sources[0x0d]	359	1		T2	7		T6	16		T8	9
valid_sources[0x0e]	374	1		T2	4		T6	4		T4	2
valid_sources[0x0f]	622	1		T2	17		T6	15		T5	1
valid_sources[0x10]	340	1		T2	9		T6	11		T4	2
valid_sources[0x11]	458	1		T2	14		T3	1		T6	14
valid_sources[0x12]	486	1		T2	4		T6	11		T4	5
valid_sources[0x13]	726	1		T2	14		T6	6		T5	2
valid_sources[0x14]	499	1		T2	15		T3	1		T6	11
valid_sources[0x15]	436	1		T2	9		T6	4		T8	4
valid_sources[0x16]	364	1		T2	3		T6	4		T5	7
valid_sources[0x17]	330	1		T2	5		T6	4		T4	3
valid_sources[0x18]	301	1		T2	7		T6	11		T5	2
valid_sources[0x19]	494	1		T2	3		T6	7		T5	6
valid_sources[0x1a]	429	1		T6	16		T8	3		T16	5
valid_sources[0x1b]	594	1		T2	2		T6	7		T4	2
valid_sources[0x1c]	545	1		T2	5		T6	2		T5	1
valid_sources[0x1d]	423	1		T6	9		T4	1		T5	6
valid_sources[0x1e]	432	1		T2	10		T6	7		T5	3
valid_sources[0x1f]	665	1		T2	6		T6	4		T4	1
valid_sources[0x20]	294	1		T2	10		T6	5		T4	1
valid_sources[0x21]	368	1		T2	13		T6	1		T4	1
valid_sources[0x22]	476	1		T2	8		T6	2		T8	2
valid_sources[0x23]	489	1		T2	1		T6	12		T4	7
valid_sources[0x24]	471	1		T2	7		T3	2		T6	11
valid_sources[0x25]	320	1		T2	4		T6	4		T4	4
valid_sources[0x26]	595	1		T2	5		T3	1		T6	1
valid_sources[0x27]	686	1		T2	9		T6	1		T5	7
valid_sources[0x28]	390	1		T2	6		T6	12		T5	5
valid_sources[0x29]	344	1		T2	2		T6	5		T5	3
valid_sources[0x2a]	365	1		T2	8		T6	3		T5	4
valid_sources[0x2b]	346	1		T2	7		T6	17		T5	5
valid_sources[0x2c]	357	1		T2	8		T3	1		T6	6
valid_sources[0x2d]	400	1		T2	13		T6	6		T5	1
valid_sources[0x2e]	404	1		T2	8		T6	11		T15	1
valid_sources[0x2f]	523	1		T2	7		T6	3		T4	1
valid_sources[0x30]	524	1		T2	17		T6	9		T5	2
valid_sources[0x31]	402	1		T2	4		T6	6		T5	4
valid_sources[0x32]	492	1		T2	4		T6	8		T5	4
valid_sources[0x33]	518	1		T2	10		T6	6		T4	2
valid_sources[0x34]	471	1		T2	10		T6	10		T4	1
valid_sources[0x35]	401	1		T2	9		T6	13		T4	7
valid_sources[0x36]	401	1		T2	44		T6	5		T8	10
valid_sources[0x37]	542	1		T2	14		T6	8		T4	6
valid_sources[0x38]	319	1		T2	19		T6	6		T5	8
valid_sources[0x39]	524	1		T2	12		T6	9		T5	8
valid_sources[0x3a]	911	1		T2	12		T3	3		T6	2
valid_sources[0x3b]	538	1		T2	14		T6	4		T4	9
valid_sources[0x3c]	2038	1		T2	4		T6	12		T5	3
valid_sources[0x3d]	311	1		T2	15		T6	10		T4	7
valid_sources[0x3e]	406	1		T2	10		T6	18		T5	2
valid_sources[0x3f]	339	1		T2	8		T6	13		T8	4
valid_sources[0x40]	384	1		T2	21		T3	4		T6	4
valid_sources[0x41]	415	1		T2	13		T6	14		T5	4
valid_sources[0x42]	389	1		T2	22		T6	17		T8	12
valid_sources[0x43]	342	1		T2	11		T6	12		T5	5
valid_sources[0x44]	634	1		T2	9		T6	16		T8	2
valid_sources[0x45]	393	1		T2	4		T6	21		T4	3
valid_sources[0x46]	605	1		T2	16		T6	4		T8	2
valid_sources[0x47]	306	1		T2	9		T6	10		T5	1
valid_sources[0x48]	387	1		T2	4		T6	1		T4	5
valid_sources[0x49]	407	1		T2	8		T6	4		T5	3
valid_sources[0x4a]	761	1		T2	11		T6	14		T4	1
valid_sources[0x4b]	570	1		T2	17		T6	3		T4	4
valid_sources[0x4c]	914	1		T2	8		T6	14		T8	2
valid_sources[0x4d]	362	1		T2	4		T6	8		T8	1
valid_sources[0x4e]	353	1		T2	9		T6	1		T5	2
valid_sources[0x4f]	592	1		T2	10		T6	8		T4	1
valid_sources[0x50]	558	1		T2	5		T6	13		T5	3
valid_sources[0x51]	451	1		T2	8		T6	15		T4	2
valid_sources[0x52]	315	1		T2	16		T6	6		T4	1
valid_sources[0x53]	378	1		T2	9		T6	10		T5	3
valid_sources[0x54]	391	1		T2	7		T6	9		T5	1
valid_sources[0x55]	519	1		T2	4		T6	2		T8	2
valid_sources[0x56]	306	1		T2	1		T6	3		T5	6
valid_sources[0x57]	546	1		T2	7		T6	11		T4	2
valid_sources[0x58]	507	1		T2	19		T6	8		T4	1
valid_sources[0x59]	363	1		T2	18		T6	6		T4	5
valid_sources[0x5a]	546	1		T2	8		T6	10		T4	4
valid_sources[0x5b]	440	1		T2	8		T3	8		T6	5
valid_sources[0x5c]	324	1		T2	19		T6	6		T5	5
valid_sources[0x5d]	1004	1		T2	13		T5	1		T8	1
valid_sources[0x5e]	330	1		T2	30		T6	6		T5	1
valid_sources[0x5f]	567	1		T2	9		T6	7		T4	5
valid_sources[0x60]	507	1		T2	6		T6	9		T5	5
valid_sources[0x61]	458	1		T2	3		T6	11		T5	3
valid_sources[0x62]	370	1		T2	20		T6	8		T5	10
valid_sources[0x63]	439	1		T2	17		T6	12		T5	6
valid_sources[0x64]	542	1		T2	17		T6	16		T4	4
valid_sources[0x65]	430	1		T2	5		T3	1		T6	1
valid_sources[0x66]	350	1		T2	14		T6	8		T5	1
valid_sources[0x67]	387	1		T2	4		T6	4		T4	6
valid_sources[0x68]	523	1		T2	9		T6	9		T5	3
valid_sources[0x69]	428	1		T2	14		T3	2		T6	14
valid_sources[0x6a]	334	1		T2	9		T3	2		T6	2
valid_sources[0x6b]	362	1		T2	14		T6	9		T8	4
valid_sources[0x6c]	489	1		T2	4		T6	7		T4	2
valid_sources[0x6d]	412	1		T2	7		T6	5		T4	4
valid_sources[0x6e]	394	1		T2	11		T6	1		T5	1
valid_sources[0x6f]	451	1		T2	5		T6	11		T4	1
valid_sources[0x70]	444	1		T2	11		T6	8		T4	3
valid_sources[0x71]	329	1		T2	9		T6	15		T4	1
valid_sources[0x72]	498	1		T2	8		T6	8		T8	2
valid_sources[0x73]	479	1		T2	11		T6	4		T8	1
valid_sources[0x74]	440	1		T2	4		T6	16		T5	1
valid_sources[0x75]	337	1		T2	7		T6	5		T5	1
valid_sources[0x76]	502	1		T2	24		T6	2		T5	2
valid_sources[0x77]	845	1		T2	8		T6	7		T5	4
valid_sources[0x78]	606	1		T2	10		T6	12		T4	7
valid_sources[0x79]	468	1		T2	2		T6	9		T4	7
valid_sources[0x7a]	323	1		T2	8		T6	7		T8	2
valid_sources[0x7b]	502	1		T2	3		T6	5		T5	2
valid_sources[0x7c]	482	1		T2	9		T6	9		T5	6
valid_sources[0x7d]	368	1		T2	21		T6	6		T5	1
valid_sources[0x7e]	311	1		T2	9		T6	8		T5	1
valid_sources[0x7f]	531	1		T2	3		T6	5		T5	6
valid_sources[0x80]	421	1		T2	6		T6	7		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25484

1

T1

9

T2

114

T3

9

values[0x0]

all_enables

biggest_size

19633

1

T1

6

T2

174

T3

11

values[0x1]

all_enables

biggest_size

17224

1

T1

5

T2

120

T3

4