Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	76007	1		T1	2		T2	2094		T3	16
full_word	63440	1		T1	20		T2	409		T3	24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	139127	1		T1	22		T2	2483		T3	40
auto[TlIntgErrCmd]	123	1		T2	8		T25	7		T27	5
auto[TlIntgErrData]	102	1		T2	3		T25	9		T27	11
auto[TlIntgErrBoth]	95	1		T2	9		T25	4		T27	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	78954	1		T1	11		T2	2017		T3	20
auto[1]	60493	1		T1	11		T2	486		T3	20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	53127	1		T1	2		T2	1895		T3	11
auto[TlIntgErrNone]	partial	auto[1]	22590	1		T2	183		T3	5		T6	18
auto[TlIntgErrNone]	full_word	auto[0]	25682	1		T1	9		T2	112		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	37728	1		T1	11		T2	293		T3	15
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T2	5		T25	4		T27	2
auto[TlIntgErrCmd]	partial	auto[1]	72	1		T2	2		T25	2		T27	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T2	1		T25	1		T76	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T58	1		T77	1		T81	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T25	7		T27	6		T76	2
auto[TlIntgErrData]	partial	auto[1]	43	1		T2	2		T25	2		T27	3
auto[TlIntgErrData]	full_word	auto[0]	7	1		T2	1		T27	2		T51	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T76	1		T56	1		T82	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T2	3		T25	3		T27	1
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T2	4		T27	2		T76	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T25	1		T77	1		T51	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T2	2		T27	1		T56	1