USBDEV Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.050s 261.975us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.110s 270.730us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.140s 117.044us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 12.490s 2.032ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.990s 373.699us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.220s 189.211us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.140s 117.044us 20 20 100.00
usbdev_csr_aliasing 3.990s 373.699us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.910s 725.981us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.360s 158.647us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.010s 256.610us 50 50 100.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense usbdev_phy_pins_sense 0.740s 59.917us 50 50 100.00
V2 av_buffer usbdev_av_buffer 0.860s 151.071us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 58.240s 22.476ms 50 50 100.00
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.950s 241.787us 50 50 100.00
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.030s 211.401us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0.980s 249.522us 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.020s 241.369us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.870s 173.436us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.910s 211.984us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 0.930s 208.019us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.020s 292.272us 50 50 100.00
V2 out_stall usbdev_out_stall 0.920s 236.451us 50 50 100.00
V2 in_stall usbdev_in_stall 0.840s 222.499us 50 50 100.00
V2 out_iso usbdev_out_iso 0.950s 245.369us 50 50 100.00
V2 in_iso usbdev_in_iso 1.000s 265.008us 50 50 100.00
V2 pkt_received usbdev_pkt_received 0.910s 198.129us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.010s 236.959us 50 50 100.00
V2 disconnected usbdev_disconnected 0.810s 179.863us 50 50 100.00
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend usbdev_link_suspend 4.660s 3.299ms 50 50 100.00
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 link_in_err usbdev_link_in_err 0.990s 203.974us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.860s 233.346us 50 50 100.00
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err usbdev_bitstuff_err 0.900s 196.511us 50 50 100.00
V2 link_out_err link_out_err 0 0 --
V2 enable usbdev_enable 0.730s 115.590us 50 50 100.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage usbdev_setup_stage 0.880s 184.649us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.740s 1.118ms 50 50 100.00
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 0.900s 168.524us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.850s 152.052us 50 50 100.00
V2 nak_trans usbdev_nak_trans 0.960s 254.506us 50 50 100.00
V2 stall_trans usbdev_stall_trans 0.890s 183.972us 50 50 100.00
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.900s 188.743us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.860s 194.254us 50 50 100.00
V2 streaming_test usbdev_streaming_out 6.647m 14.417ms 50 50 100.00
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 58.240s 22.476ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume usbdev_aon_wake_resume 29.830s 23.415ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 17.080s 13.478ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 5.930s 4.367ms 50 50 100.00
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets usbdev_rand_bus_resets 12.610m 30.263ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 14.148m 31.159ms 10 10 100.00
V2 max_usb_traffic usbdev_max_usb_traffic 7.345m 15.103ms 50 50 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 16.150m 37.871ms 5 5 100.00
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 3.510s 1.494ms 50 50 100.00
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 2.660s 422.854us 50 50 100.00
V2 intr_test usbdev_intr_test 0.780s 80.116us 50 50 100.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.430s 258.946us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.430s 258.946us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.110s 270.730us 5 5 100.00
usbdev_csr_rw 1.140s 117.044us 20 20 100.00
usbdev_csr_aliasing 3.990s 373.699us 5 5 100.00
usbdev_same_csr_outstanding 2.010s 231.888us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.110s 270.730us 5 5 100.00
usbdev_csr_rw 1.140s 117.044us 20 20 100.00
usbdev_csr_aliasing 3.990s 373.699us 5 5 100.00
usbdev_same_csr_outstanding 2.010s 231.888us 20 20 100.00
V2 TOTAL 2065 2065 100.00
V2S tl_intg_err usbdev_sec_cm 2.650s 1.986ms 5 5 100.00
usbdev_tl_intg_err 6.870s 2.451ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 6.870s 2.451ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_dpi_config_host 2.215m 5.118ms 1 1 100.00
usbdev_rand_suspends 15.396m 37.179ms 10 10 100.00
usbdev_stress_all_with_rand_reset 0.730s 71.682us 0 50 0.00
usbdev_stress_all 0.640s 0 50 0.00
TOTAL 2216 2316 95.68

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 2 50.00
V1 8 8 8 100.00
V2 75 45 45 60.00
V2S 2 2 2 100.00

Failure Buckets

Past Results