Module Definition
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Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_wake_events_cdc 68.40 94.12 46.15 83.33 50.00
tb.dut.u_reg.u_wake_control_cdc 97.73 100.00 90.91 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.40 94.12 46.15 83.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.15 85.94 51.47 77.19 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.26 99.76 97.27 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 71.47 83.67 55.10 72.09 75.00
u_src_to_dst_req 56.41 92.31 33.33 100.00 0.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.13 96.08 96.43 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.26 99.76 97.27 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.88 87.50 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T8,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T4
11CoveredT2,T8,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12
10CoveredT2,T8,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T8,T4
11CoveredT2,T8,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT12

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T8,T4
0 0 1 Covered T2,T8,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T8,T4
0 0 1 Covered T2,T8,T4
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 3644924 288441 0 0
DstReqKnown_A 38138 30684 0 0
SrcAckBusyChk_A 3644924 889 0 0
SrcBusyKnown_A 3644924 3535564 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3644924 288441 0 0
T2 3901 388 0 0
T3 12967 0 0 0
T4 34427 2934 0 0
T5 0 383 0 0
T6 0 7 0 0
T7 12306 0 0 0
T8 4733 494 0 0
T11 0 1036 0 0
T13 3587 0 0 0
T14 2344 0 0 0
T15 3251 0 0 0
T20 9809 0 0 0
T21 9170 0 0 0
T30 0 3254 0 0
T31 0 284 0 0
T38 0 193 0 0
T46 0 3129 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38138 30684 0 0
T1 110 94 0 0
T2 90 80 0 0
T3 430 410 0 0
T7 200 184 0 0
T8 110 94 0 0
T13 44 34 0 0
T14 74 58 0 0
T15 50 30 0 0
T20 84 72 0 0
T21 114 100 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3644924 889 0 0
T2 3901 2 0 0
T3 12967 0 0 0
T4 34427 20 0 0
T5 0 2 0 0
T7 12306 0 0 0
T8 4733 2 0 0
T11 0 8 0 0
T13 3587 0 0 0
T14 2344 0 0 0
T15 3251 0 0 0
T20 9809 0 0 0
T21 9170 0 0 0
T26 0 9 0 0
T30 0 8 0 0
T31 0 2 0 0
T38 0 1 0 0
T46 0 7 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3644924 3535564 0 0
T1 13856 13738 0 0
T2 7802 7634 0 0
T3 25934 25804 0 0
T7 24612 24420 0 0
T8 9466 9310 0 0
T13 7174 6990 0 0
T14 4688 4494 0 0
T15 6502 6354 0 0
T20 19618 19422 0 0
T21 18340 18192 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
TOTAL171694.12
CONT_ASSIGN6500
ALWAYS715480.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11577100.00
CONT_ASSIGN15000
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 unreachable
71 1 1
72 1 1
73 1 1
74 unreachable
75 1 1
76 0 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 unreachable
124 unreachable
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 unreachable
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalCoveredPercent
Conditions13646.15
Logical13646.15
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12
10Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT12

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
Branches 6 5 83.33
IF 71 3 2 66.67
IF 115 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Covered T12
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1822462 0 0 0
DstReqKnown_A 19069 15342 0 0
SrcAckBusyChk_A 1822462 0 0 0
SrcBusyKnown_A 1822462 1767782 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 19069 15342 0 0
T1 55 47 0 0
T2 45 40 0 0
T3 215 205 0 0
T7 100 92 0 0
T8 55 47 0 0
T13 22 17 0 0
T14 37 29 0 0
T15 25 15 0 0
T20 42 36 0 0
T21 57 50 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T8,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T4
11CoveredT2,T8,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T8,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T8,T4
11CoveredT2,T8,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T8,T4
0 0 1 Covered T2,T8,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T8,T4
0 0 1 Covered T2,T8,T4
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1822462 288441 0 0
DstReqKnown_A 19069 15342 0 0
SrcAckBusyChk_A 1822462 889 0 0
SrcBusyKnown_A 1822462 1767782 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 288441 0 0
T2 3901 388 0 0
T3 12967 0 0 0
T4 34427 2934 0 0
T5 0 383 0 0
T6 0 7 0 0
T7 12306 0 0 0
T8 4733 494 0 0
T11 0 1036 0 0
T13 3587 0 0 0
T14 2344 0 0 0
T15 3251 0 0 0
T20 9809 0 0 0
T21 9170 0 0 0
T30 0 3254 0 0
T31 0 284 0 0
T38 0 193 0 0
T46 0 3129 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 19069 15342 0 0
T1 55 47 0 0
T2 45 40 0 0
T3 215 205 0 0
T7 100 92 0 0
T8 55 47 0 0
T13 22 17 0 0
T14 37 29 0 0
T15 25 15 0 0
T20 42 36 0 0
T21 57 50 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 889 0 0
T2 3901 2 0 0
T3 12967 0 0 0
T4 34427 20 0 0
T5 0 2 0 0
T7 12306 0 0 0
T8 4733 2 0 0
T11 0 8 0 0
T13 3587 0 0 0
T14 2344 0 0 0
T15 3251 0 0 0
T20 9809 0 0 0
T21 9170 0 0 0
T26 0 9 0 0
T30 0 8 0 0
T31 0 2 0 0
T38 0 1 0 0
T46 0 7 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%