USBDEV Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0 50 0.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.950s 130.520us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.150s 161.644us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 9.490s 1.562ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.690s 307.983us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.370s 102.144us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.150s 161.644us 20 20 100.00
usbdev_csr_aliasing 3.690s 307.983us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.500s 521.650us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.340s 194.955us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 in_trans usbdev_in_trans 0 50 0.00
V2 data_toggle_clear usbdev_data_toggle_clear 0 50 0.00
V2 phy_pins_sense usbdev_phy_pins_sense 0 50 0.00
V2 av_buffer usbdev_av_buffer 0 50 0.00
V2 rx_fifo usbdev_pkt_buffer 0 50 0.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 0 1 0.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0 1 0.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 0 50 0.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 0 5 0.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 0 1 0.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 0 1 0.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0 50 0.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0 50 0.00
usbdev_stream_len_max 0 50 0.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 0 50 0.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0 50 0.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0 50 0.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 0 50 0.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 0 50 0.00
V2 out_stall usbdev_out_stall 0 50 0.00
V2 in_stall usbdev_in_stall 0 50 0.00
V2 out_iso usbdev_out_iso 0 50 0.00
V2 in_iso usbdev_in_iso 0 50 0.00
V2 pkt_received usbdev_pkt_received 0 50 0.00
V2 pkt_sent usbdev_pkt_sent 0 50 0.00
V2 disconnected usbdev_disconnected 0 50 0.00
V2 host_lost usbdev_host_lost 0 1 0.00
V2 link_reset usbdev_link_reset 0 1 0.00
V2 link_suspend usbdev_link_suspend 0 50 0.00
V2 link_resume usbdev_link_resume 0 50 0.00
V2 av_empty usbdev_av_empty 0 5 0.00
V2 rx_full usbdev_rx_full 0 1 0.00
V2 av_overflow usbdev_av_overflow 0 5 0.00
V2 link_in_err usbdev_link_in_err 0 50 0.00
V2 rx_crc_err usbdev_rx_crc_err 0 50 0.00
V2 rx_pid_err usbdev_rx_pid_err 0 5 0.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0 50 0.00
V2 link_out_err usbdev_link_out_err 0 1 0.00
V2 enable usbdev_enable 0 50 0.00
V2 resume_link_active usbdev_resume_link_active 0 1 0.00
V2 device_address usbdev_device_address 0 50 0.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 0 1 0.00
V2 setup_stage usbdev_setup_stage 0 50 0.00
V2 endpoint_access usbdev_endpoint_access 0 50 0.00
V2 disable_endpoint usbdev_disable_endpoint 0 50 0.00
V2 out_trans_nak usbdev_out_trans_nak 0 50 0.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0 50 0.00
V2 nak_trans usbdev_nak_trans 0 50 0.00
V2 stall_trans usbdev_stall_trans 0 50 0.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 0 5 0.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0 50 0.00
V2 pending_in_trans usbdev_pending_in_trans 0 50 0.00
V2 streaming_test usbdev_streaming_out 0 50 0.00
V2 max_clock_error_untracked usbdev_freq_hiclk 0 5 0.00
usbdev_freq_loclk 0 5 0.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 0 5 0.00
usbdev_freq_loclk_max 0 5 0.00
V2 max_phase_error usbdev_freq_phase 0 5 0.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 0 50 0.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 0 50 0.00
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 packet_buffer usbdev_pkt_buffer 0 50 0.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 1 0.00
V2 aon_wake_resume usbdev_aon_wake_resume 0 50 0.00
V2 aon_wake_reset usbdev_aon_wake_reset 0 50 0.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 0 50 0.00
V2 invalid_sync usbdev_invalid_sync 0 50 0.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 0 50 0.00
V2 low_speed_traffic usbdev_low_speed_traffic 0 50 0.00
V2 rand_bus_resets usbdev_rand_bus_resets 0 10 0.00
V2 rand_disconnects usbdev_rand_bus_disconnects 0 10 0.00
V2 rand_suspends usbdev_rand_suspends 0 10 0.00
V2 max_usb_traffic usbdev_max_usb_traffic 0 50 0.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 0 5 0.00
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore usbdev_data_toggle_restore 0 50 0.00
V2 setup_priority usbdev_setup_priority 0 5 0.00
V2 fifo_resets usbdev_fifo_rst 0 50 0.00
V2 intr_test usbdev_intr_test 0.750s 64.055us 50 50 100.00
V2 alert_test usbdev_alert_test 0 50 0.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.690s 152.725us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.690s 152.725us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.950s 130.520us 5 5 100.00
usbdev_csr_rw 1.150s 161.644us 20 20 100.00
usbdev_csr_aliasing 3.690s 307.983us 5 5 100.00
usbdev_same_csr_outstanding 1.900s 178.596us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.950s 130.520us 5 5 100.00
usbdev_csr_rw 1.150s 161.644us 20 20 100.00
usbdev_csr_aliasing 3.690s 307.983us 5 5 100.00
usbdev_same_csr_outstanding 1.900s 178.596us 20 20 100.00
V2 TOTAL 90 2691 3.34
V2S tl_intg_err usbdev_sec_cm 0 5 0.00
usbdev_tl_intg_err 5.760s 1.667ms 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.760s 1.667ms 20 20 100.00
V2S TOTAL 20 25 80.00
V3 dpi_config_host usbdev_dpi_config_host 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests usbdev_stress_all_with_rand_reset 0 10 0.00
usbdev_stress_all 0 50 0.00
TOTAL 175 2892 6.05

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 7 87.50
V2 82 79 3 3.66
V2S 2 2 1 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
67.90 65.32 59.60 86.57 0.00 69.84 97.77 96.22

Failure Buckets

Past Results