USBDEV Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: e4c5daa580

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.180s 261.962us 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 1.280s 336.200us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.070s 124.411us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 11.000s 2.570ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 3.580s 369.388us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.740s 178.368us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.070s 124.411us 20 20 100.00
usbdev_csr_aliasing 3.580s 369.388us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.120s 162.698us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 2.200s 76.094us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 in_trans usbdev_in_trans 1.180s 309.714us 50 50 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 1.950s 584.473us 50 50 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.790s 76.731us 50 50 100.00
V2 av_buffer usbdev_av_buffer 1.010s 204.755us 50 50 100.00
V2 rx_fifo usbdev_pkt_buffer 1.056m 22.219ms 50 50 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.080s 314.248us 1 1 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 1.010s 251.018us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 1.170s 220.333us 50 50 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.170s 314.731us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 1.110s 239.194us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.030s 212.885us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.980s 177.963us 50 50 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 1.110s 262.553us 50 50 100.00
usbdev_stream_len_max 3.260s 1.326ms 50 50 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.180s 268.081us 50 50 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.930s 213.683us 50 50 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 1.010s 187.783us 50 50 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.090s 177.082us 50 50 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 1.070s 296.360us 50 50 100.00
V2 out_stall usbdev_out_stall 0.980s 182.362us 50 50 100.00
V2 in_stall usbdev_in_stall 0.980s 144.569us 50 50 100.00
V2 out_iso usbdev_out_iso 1.030s 238.869us 50 50 100.00
V2 in_iso usbdev_in_iso 1.240s 230.809us 50 50 100.00
V2 pkt_received usbdev_pkt_received 1.090s 250.434us 50 50 100.00
V2 pkt_sent usbdev_pkt_sent 1.190s 182.402us 50 50 100.00
V2 disconnected usbdev_disconnected 0.970s 238.756us 50 50 100.00
V2 host_lost usbdev_host_lost 10.530s 4.170ms 1 1 100.00
V2 link_reset usbdev_link_reset 0.870s 170.844us 1 1 100.00
V2 link_suspend usbdev_link_suspend 14.270s 11.327ms 50 50 100.00
V2 link_resume usbdev_link_resume 57.050s 32.519ms 48 50 96.00
V2 av_empty usbdev_av_empty 0.960s 222.219us 5 5 100.00
V2 rx_full usbdev_rx_full 1.540s 399.295us 50 50 100.00
V2 av_overflow usbdev_av_overflow 0.890s 179.661us 5 5 100.00
V2 link_in_err usbdev_link_in_err 1.190s 231.309us 50 50 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.990s 229.511us 50 50 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.960s 203.566us 5 5 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 1.010s 241.127us 50 50 100.00
V2 link_out_err usbdev_link_out_err 1.520s 427.307us 1 1 100.00
V2 enable usbdev_enable 0.810s 108.344us 50 50 100.00
V2 resume_link_active usbdev_resume_link_active 31.110s 20.183ms 20 20 100.00
V2 device_address usbdev_device_address 1.711m 57.456ms 50 50 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.620s 487.167us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.960s 192.402us 50 50 100.00
V2 endpoint_access usbdev_endpoint_access 2.770s 1.127ms 50 50 100.00
V2 disable_endpoint usbdev_disable_endpoint 3.090s 1.265ms 50 50 100.00
V2 endpoint_types usbdev_endpoint_types 2.230s 988.680us 200 200 100.00
V2 out_trans_nak usbdev_out_trans_nak 0.970s 230.049us 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 1.010s 164.035us 50 50 100.00
V2 nak_trans usbdev_nak_trans 1.120s 293.154us 50 50 100.00
V2 stall_trans usbdev_stall_trans 1.050s 176.911us 50 50 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.060s 312.232us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.010s 253.686us 50 50 100.00
V2 pending_in_trans usbdev_pending_in_trans 1.010s 206.022us 50 50 100.00
V2 streaming_test usbdev_streaming_out 1.831m 3.663ms 50 50 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 2.916m 89.184ms 5 5 100.00
usbdev_freq_loclk 3.441m 112.101ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 3.117m 109.404ms 5 5 100.00
usbdev_freq_loclk_max 3.130m 103.998ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 3.030m 103.121ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 1.935m 4.243ms 50 50 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 1.845m 3.654ms 50 50 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 1.013m 9.065ms 50 50 100.00
V2 device_timeout usbdev_device_timeout 46.860s 1.958ms 50 50 100.00
V2 packet_buffer usbdev_pkt_buffer 1.056m 22.219ms 50 50 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.590s 527.818us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 47.080s 31.428ms 50 50 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 28.740s 20.315ms 50 50 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 16.420s 12.126ms 50 50 100.00
V2 invalid_sync usbdev_invalid_sync 2.741m 5.427ms 50 50 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 1.836m 3.878ms 50 50 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 2.476m 5.033ms 50 50 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 3.772m 8.535ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 2.692m 9.482ms 10 10 100.00
V2 rand_suspends usbdev_rand_suspends 3.370m 10.159ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 1.687m 3.591ms 25 25 100.00
usbdev_max_usb_traffic 1.787m 3.369ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 6.875m 17.137ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 2.572m 12.311ms 46 50 92.00
V2 data_toggle_restore usbdev_data_toggle_restore 3.630s 1.380ms 50 50 100.00
V2 setup_priority usbdev_setup_priority 1.790s 469.311us 5 5 100.00
V2 fifo_resets usbdev_fifo_rst 2.800s 336.832us 50 50 100.00
V2 intr_test usbdev_intr_test 0.820s 81.335us 50 50 100.00
V2 alert_test usbdev_alert_test 0.730s 32.940us 50 50 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 3.820s 300.555us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.820s 300.555us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 1.280s 336.200us 5 5 100.00
usbdev_csr_rw 1.070s 124.411us 20 20 100.00
usbdev_csr_aliasing 3.580s 369.388us 5 5 100.00
usbdev_same_csr_outstanding 2.300s 368.255us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 1.280s 336.200us 5 5 100.00
usbdev_csr_rw 1.070s 124.411us 20 20 100.00
usbdev_csr_aliasing 3.580s 369.388us 5 5 100.00
usbdev_same_csr_outstanding 2.300s 368.255us 20 20 100.00
V2 TOTAL 3093 3099 99.81
V2S tl_intg_err usbdev_sec_cm 2.040s 920.838us 5 5 100.00
usbdev_tl_intg_err 5.050s 929.619us 20 20 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 5.050s 929.619us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 dpi_config_host usbdev_dpi_config_host 49.570s 5.134ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.710s 107.773us 0 10 0.00
usbdev_stress_all 0.650s 0 50 0.00
TOTAL 3234 3300 98.00

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 84 84 82 97.62
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.62 97.96 93.90 97.44 81.25 96.42 98.17 90.23

Failure Buckets

Past Results