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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.41 98.23 96.03 97.44 94.92 98.42 98.21 98.64


Total test records in report: 3837
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T3568 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/334.usbdev_tx_rx_disruption.1780997696 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:37 PM UTC 24 475086371 ps
T3569 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/329.usbdev_tx_rx_disruption.2722052059 Oct 02 11:16:34 PM UTC 24 Oct 02 11:16:37 PM UTC 24 531311301 ps
T3570 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/335.usbdev_tx_rx_disruption.1109749882 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:37 PM UTC 24 479222539 ps
T3571 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/333.usbdev_tx_rx_disruption.2946543971 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:37 PM UTC 24 507774408 ps
T3572 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/336.usbdev_tx_rx_disruption.3658524196 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:37 PM UTC 24 538515455 ps
T3573 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/332.usbdev_tx_rx_disruption.2347377202 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:37 PM UTC 24 634663854 ps
T3574 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/337.usbdev_tx_rx_disruption.2805176733 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:37 PM UTC 24 607876446 ps
T3575 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/338.usbdev_tx_rx_disruption.1576512012 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:37 PM UTC 24 480918795 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/313.usbdev_tx_rx_disruption.3670197845 Oct 02 11:16:31 PM UTC 24 Oct 02 11:16:38 PM UTC 24 705416518 ps
T3576 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/339.usbdev_tx_rx_disruption.3721841766 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 619484327 ps
T3577 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/319.usbdev_tx_rx_disruption.726250349 Oct 02 11:16:32 PM UTC 24 Oct 02 11:16:41 PM UTC 24 527227866 ps
T3578 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/342.usbdev_tx_rx_disruption.3528035152 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 612567477 ps
T3579 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/317.usbdev_tx_rx_disruption.2810501909 Oct 02 11:16:32 PM UTC 24 Oct 02 11:16:41 PM UTC 24 550892274 ps
T3580 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/315.usbdev_tx_rx_disruption.2805892266 Oct 02 11:16:32 PM UTC 24 Oct 02 11:16:41 PM UTC 24 591398544 ps
T3581 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/348.usbdev_tx_rx_disruption.670289776 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 453052098 ps
T3582 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/344.usbdev_tx_rx_disruption.1974097995 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 520435584 ps
T3583 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/343.usbdev_tx_rx_disruption.3595920261 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 591120059 ps
T3584 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/323.usbdev_tx_rx_disruption.1580553723 Oct 02 11:16:32 PM UTC 24 Oct 02 11:16:41 PM UTC 24 612503757 ps
T3585 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/352.usbdev_tx_rx_disruption.57462150 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 469602047 ps
T3586 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/320.usbdev_tx_rx_disruption.3753480915 Oct 02 11:16:32 PM UTC 24 Oct 02 11:16:41 PM UTC 24 552001964 ps
T3587 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/346.usbdev_tx_rx_disruption.2728604694 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 580022880 ps
T3588 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/353.usbdev_tx_rx_disruption.2524711045 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 441274226 ps
T3589 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/345.usbdev_tx_rx_disruption.3296902956 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 592826034 ps
T3590 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/324.usbdev_tx_rx_disruption.2196199778 Oct 02 11:16:32 PM UTC 24 Oct 02 11:16:41 PM UTC 24 479280837 ps
T3591 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/350.usbdev_tx_rx_disruption.3445677336 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 627788963 ps
T3592 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/321.usbdev_tx_rx_disruption.2527883621 Oct 02 11:16:32 PM UTC 24 Oct 02 11:16:41 PM UTC 24 625491582 ps
T3593 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/347.usbdev_tx_rx_disruption.3006284755 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 637293363 ps
T3594 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/351.usbdev_tx_rx_disruption.2406061147 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 613214815 ps
T3595 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/349.usbdev_tx_rx_disruption.3022161971 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 661120396 ps
T3596 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/356.usbdev_tx_rx_disruption.2953242405 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 452940795 ps
T3597 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/355.usbdev_tx_rx_disruption.536141049 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 563931891 ps
T3598 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/371.usbdev_tx_rx_disruption.719090529 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:41 PM UTC 24 489756642 ps
T3599 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/358.usbdev_tx_rx_disruption.1915894841 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 551178897 ps
T3600 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/372.usbdev_tx_rx_disruption.544171692 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:41 PM UTC 24 471889743 ps
T3601 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/354.usbdev_tx_rx_disruption.1044194964 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 534482289 ps
T3602 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/360.usbdev_tx_rx_disruption.2056749492 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 538330688 ps
T3603 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/363.usbdev_tx_rx_disruption.565365074 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 563199068 ps
T3604 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/370.usbdev_tx_rx_disruption.2507041780 Oct 02 11:16:38 PM UTC 24 Oct 02 11:16:41 PM UTC 24 548586208 ps
T3605 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/357.usbdev_tx_rx_disruption.250346372 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 596702142 ps
T3606 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/362.usbdev_tx_rx_disruption.4261711293 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 515089594 ps
T3607 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/361.usbdev_tx_rx_disruption.663157455 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 608873227 ps
T3608 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/359.usbdev_tx_rx_disruption.537923779 Oct 02 11:16:35 PM UTC 24 Oct 02 11:16:41 PM UTC 24 650839014 ps
T3609 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/383.usbdev_tx_rx_disruption.4214073708 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:41 PM UTC 24 477586490 ps
T3610 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/385.usbdev_tx_rx_disruption.1859709574 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:42 PM UTC 24 519465152 ps
T3611 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/395.usbdev_tx_rx_disruption.2323616582 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:45 PM UTC 24 424740257 ps
T3612 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/397.usbdev_tx_rx_disruption.3196917845 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:45 PM UTC 24 552721702 ps
T3613 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/399.usbdev_tx_rx_disruption.1000489213 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:45 PM UTC 24 611739634 ps
T3614 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/402.usbdev_tx_rx_disruption.4099104636 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:45 PM UTC 24 479174866 ps
T3615 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/401.usbdev_tx_rx_disruption.4034018478 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:45 PM UTC 24 495878289 ps
T3616 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/404.usbdev_tx_rx_disruption.1529357377 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:45 PM UTC 24 522496859 ps
T3617 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/412.usbdev_tx_rx_disruption.3572948160 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:46 PM UTC 24 467677493 ps
T3618 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/414.usbdev_tx_rx_disruption.3191098714 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:46 PM UTC 24 612120819 ps
T3619 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/417.usbdev_tx_rx_disruption.1996112604 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:46 PM UTC 24 458025794 ps
T3620 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/379.usbdev_tx_rx_disruption.3750951051 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:51 PM UTC 24 450385792 ps
T3621 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/373.usbdev_tx_rx_disruption.1181328138 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:51 PM UTC 24 601252676 ps
T3622 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/366.usbdev_tx_rx_disruption.1777388890 Oct 02 11:16:36 PM UTC 24 Oct 02 11:16:51 PM UTC 24 595034009 ps
T3623 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/375.usbdev_tx_rx_disruption.2188961672 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:51 PM UTC 24 491915057 ps
T3624 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/377.usbdev_tx_rx_disruption.3565500807 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:51 PM UTC 24 549049165 ps
T3625 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/365.usbdev_tx_rx_disruption.988150049 Oct 02 11:16:36 PM UTC 24 Oct 02 11:16:51 PM UTC 24 500092489 ps
T3626 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/376.usbdev_tx_rx_disruption.1392083408 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:51 PM UTC 24 643077215 ps
T3627 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/374.usbdev_tx_rx_disruption.4162360015 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:51 PM UTC 24 637000636 ps
T3628 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/364.usbdev_tx_rx_disruption.889865457 Oct 02 11:16:36 PM UTC 24 Oct 02 11:16:51 PM UTC 24 510863351 ps
T3629 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/380.usbdev_tx_rx_disruption.3452484001 Oct 02 11:16:39 PM UTC 24 Oct 02 11:16:52 PM UTC 24 667571355 ps
T3630 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/418.usbdev_tx_rx_disruption.1882491682 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:56 PM UTC 24 504969941 ps
T3631 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/415.usbdev_tx_rx_disruption.215885036 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:56 PM UTC 24 451800188 ps
T3632 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/413.usbdev_tx_rx_disruption.4058625423 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:56 PM UTC 24 597341138 ps
T3633 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/416.usbdev_tx_rx_disruption.1307705967 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:56 PM UTC 24 650268170 ps
T3634 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/419.usbdev_tx_rx_disruption.2639471960 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:56 PM UTC 24 542614834 ps
T3635 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/420.usbdev_tx_rx_disruption.433976123 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:56 PM UTC 24 524240204 ps
T3636 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/421.usbdev_tx_rx_disruption.2011199738 Oct 02 11:16:43 PM UTC 24 Oct 02 11:16:56 PM UTC 24 627738356 ps
T3637 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/446.usbdev_tx_rx_disruption.3212050737 Oct 02 11:16:57 PM UTC 24 Oct 02 11:17:01 PM UTC 24 496597582 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/445.usbdev_tx_rx_disruption.2333680636 Oct 02 11:16:57 PM UTC 24 Oct 02 11:17:01 PM UTC 24 502826479 ps
T3638 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/434.usbdev_tx_rx_disruption.2460341799 Oct 02 11:16:47 PM UTC 24 Oct 02 11:17:01 PM UTC 24 562284191 ps
T3639 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/448.usbdev_tx_rx_disruption.2290771295 Oct 02 11:16:57 PM UTC 24 Oct 02 11:17:01 PM UTC 24 450508262 ps
T3640 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/449.usbdev_tx_rx_disruption.1618070188 Oct 02 11:16:57 PM UTC 24 Oct 02 11:17:01 PM UTC 24 555263775 ps
T3641 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/450.usbdev_tx_rx_disruption.813444973 Oct 02 11:16:57 PM UTC 24 Oct 02 11:17:01 PM UTC 24 554840998 ps
T3642 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/451.usbdev_tx_rx_disruption.4037557845 Oct 02 11:16:57 PM UTC 24 Oct 02 11:17:01 PM UTC 24 567529798 ps
T3643 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/447.usbdev_tx_rx_disruption.2754505286 Oct 02 11:16:57 PM UTC 24 Oct 02 11:17:01 PM UTC 24 610510172 ps
T3644 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/428.usbdev_tx_rx_disruption.610671045 Oct 02 11:16:46 PM UTC 24 Oct 02 11:17:01 PM UTC 24 517458610 ps
T3645 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/427.usbdev_tx_rx_disruption.1183940182 Oct 02 11:16:46 PM UTC 24 Oct 02 11:17:01 PM UTC 24 523187667 ps
T3646 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/431.usbdev_tx_rx_disruption.1670744177 Oct 02 11:16:46 PM UTC 24 Oct 02 11:17:01 PM UTC 24 467450195 ps
T3647 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/430.usbdev_tx_rx_disruption.1586127888 Oct 02 11:16:46 PM UTC 24 Oct 02 11:17:02 PM UTC 24 540279637 ps
T3648 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/426.usbdev_tx_rx_disruption.498523010 Oct 02 11:16:46 PM UTC 24 Oct 02 11:17:02 PM UTC 24 548365256 ps
T3649 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/429.usbdev_tx_rx_disruption.3680860496 Oct 02 11:16:46 PM UTC 24 Oct 02 11:17:02 PM UTC 24 661606296 ps
T3650 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/409.usbdev_tx_rx_disruption.2904256873 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 445903297 ps
T3651 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/405.usbdev_tx_rx_disruption.2812909665 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 623052294 ps
T3652 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/469.usbdev_tx_rx_disruption.3927165158 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:21 PM UTC 24 649069734 ps
T3653 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/432.usbdev_tx_rx_disruption.1464312966 Oct 02 11:16:47 PM UTC 24 Oct 02 11:17:03 PM UTC 24 517072820 ps
T3654 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/411.usbdev_tx_rx_disruption.877436785 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 449489704 ps
T3655 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/407.usbdev_tx_rx_disruption.4150097763 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 552556268 ps
T3656 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/433.usbdev_tx_rx_disruption.1712554501 Oct 02 11:16:47 PM UTC 24 Oct 02 11:17:03 PM UTC 24 503307582 ps
T3657 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/406.usbdev_tx_rx_disruption.2206677169 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 480673219 ps
T3658 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/408.usbdev_tx_rx_disruption.1185217674 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 495324200 ps
T3659 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/410.usbdev_tx_rx_disruption.4165611404 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 594354661 ps
T3660 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/452.usbdev_tx_rx_disruption.1996481180 Oct 02 11:17:01 PM UTC 24 Oct 02 11:17:03 PM UTC 24 470465721 ps
T3661 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/454.usbdev_tx_rx_disruption.1762568098 Oct 02 11:17:01 PM UTC 24 Oct 02 11:17:03 PM UTC 24 465691279 ps
T3662 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/453.usbdev_tx_rx_disruption.596011857 Oct 02 11:17:01 PM UTC 24 Oct 02 11:17:03 PM UTC 24 534056568 ps
T3663 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/393.usbdev_tx_rx_disruption.3033514790 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 446100435 ps
T3664 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/423.usbdev_tx_rx_disruption.3235782217 Oct 02 11:16:44 PM UTC 24 Oct 02 11:17:03 PM UTC 24 545410166 ps
T3665 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/456.usbdev_tx_rx_disruption.984349110 Oct 02 11:17:01 PM UTC 24 Oct 02 11:17:03 PM UTC 24 533870824 ps
T3666 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/388.usbdev_tx_rx_disruption.4197069508 Oct 02 11:16:42 PM UTC 24 Oct 02 11:17:03 PM UTC 24 580229301 ps
T3667 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/391.usbdev_tx_rx_disruption.3762452295 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 487017791 ps
T3668 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/455.usbdev_tx_rx_disruption.3653782273 Oct 02 11:17:01 PM UTC 24 Oct 02 11:17:03 PM UTC 24 603804810 ps
T3669 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/425.usbdev_tx_rx_disruption.473485641 Oct 02 11:16:44 PM UTC 24 Oct 02 11:17:03 PM UTC 24 588239020 ps
T3670 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/389.usbdev_tx_rx_disruption.4170046263 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 560878306 ps
T3671 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/398.usbdev_tx_rx_disruption.2197556356 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 493367320 ps
T3672 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/400.usbdev_tx_rx_disruption.1352957956 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 450613696 ps
T3673 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/392.usbdev_tx_rx_disruption.2126361213 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 618547792 ps
T3674 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/438.usbdev_tx_rx_disruption.1950409580 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:03 PM UTC 24 596722546 ps
T3675 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/422.usbdev_tx_rx_disruption.1264252427 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 687979289 ps
T3676 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/390.usbdev_tx_rx_disruption.3887290556 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:03 PM UTC 24 606153789 ps
T3677 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/437.usbdev_tx_rx_disruption.55524410 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:03 PM UTC 24 536256985 ps
T3678 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/396.usbdev_tx_rx_disruption.1645033946 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:04 PM UTC 24 487202837 ps
T3679 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/424.usbdev_tx_rx_disruption.468386460 Oct 02 11:16:44 PM UTC 24 Oct 02 11:17:04 PM UTC 24 598777695 ps
T3680 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/444.usbdev_tx_rx_disruption.3943397566 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:04 PM UTC 24 436317866 ps
T3681 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/436.usbdev_tx_rx_disruption.2232411228 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:04 PM UTC 24 489233794 ps
T3682 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/435.usbdev_tx_rx_disruption.4006414603 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:04 PM UTC 24 476318935 ps
T3683 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/403.usbdev_tx_rx_disruption.764874169 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:04 PM UTC 24 526084039 ps
T3684 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/387.usbdev_tx_rx_disruption.839572802 Oct 02 11:16:42 PM UTC 24 Oct 02 11:17:04 PM UTC 24 690595164 ps
T3685 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/440.usbdev_tx_rx_disruption.302499110 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:04 PM UTC 24 517762986 ps
T3686 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/441.usbdev_tx_rx_disruption.3485219631 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:04 PM UTC 24 635567214 ps
T3687 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/394.usbdev_tx_rx_disruption.4212158431 Oct 02 11:16:43 PM UTC 24 Oct 02 11:17:04 PM UTC 24 614764441 ps
T3688 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/439.usbdev_tx_rx_disruption.1442525337 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:04 PM UTC 24 555898996 ps
T3689 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/368.usbdev_tx_rx_disruption.4143775692 Oct 02 11:16:37 PM UTC 24 Oct 02 11:17:04 PM UTC 24 574496761 ps
T3690 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/443.usbdev_tx_rx_disruption.339511357 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:04 PM UTC 24 565842763 ps
T3691 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/481.usbdev_tx_rx_disruption.2573068232 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:22 PM UTC 24 505905564 ps
T3692 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/367.usbdev_tx_rx_disruption.2381511302 Oct 02 11:16:37 PM UTC 24 Oct 02 11:17:04 PM UTC 24 522302796 ps
T3693 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/442.usbdev_tx_rx_disruption.1207879358 Oct 02 11:16:53 PM UTC 24 Oct 02 11:17:04 PM UTC 24 576981818 ps
T3694 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/480.usbdev_tx_rx_disruption.3208394363 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:22 PM UTC 24 574424368 ps
T3695 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/369.usbdev_tx_rx_disruption.4294873798 Oct 02 11:16:37 PM UTC 24 Oct 02 11:17:04 PM UTC 24 604412670 ps
T3696 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/458.usbdev_tx_rx_disruption.120564700 Oct 02 11:17:02 PM UTC 24 Oct 02 11:17:05 PM UTC 24 500497591 ps
T3697 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/457.usbdev_tx_rx_disruption.3220459123 Oct 02 11:17:02 PM UTC 24 Oct 02 11:17:05 PM UTC 24 641011411 ps
T3698 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/459.usbdev_tx_rx_disruption.3680669518 Oct 02 11:17:02 PM UTC 24 Oct 02 11:17:05 PM UTC 24 507823231 ps
T3699 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/482.usbdev_tx_rx_disruption.4006319426 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:22 PM UTC 24 570817808 ps
T3700 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/461.usbdev_tx_rx_disruption.3804916565 Oct 02 11:17:02 PM UTC 24 Oct 02 11:17:05 PM UTC 24 507417539 ps
T3701 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/460.usbdev_tx_rx_disruption.509646487 Oct 02 11:17:02 PM UTC 24 Oct 02 11:17:05 PM UTC 24 645203279 ps
T3702 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/463.usbdev_tx_rx_disruption.820044319 Oct 02 11:17:02 PM UTC 24 Oct 02 11:17:05 PM UTC 24 578304335 ps
T3703 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/462.usbdev_tx_rx_disruption.1163031937 Oct 02 11:17:02 PM UTC 24 Oct 02 11:17:06 PM UTC 24 485705643 ps
T3704 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/467.usbdev_tx_rx_disruption.3701842367 Oct 02 11:17:03 PM UTC 24 Oct 02 11:17:06 PM UTC 24 462637916 ps
T3705 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/466.usbdev_tx_rx_disruption.1788900926 Oct 02 11:17:03 PM UTC 24 Oct 02 11:17:06 PM UTC 24 464081667 ps
T3706 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/464.usbdev_tx_rx_disruption.257784119 Oct 02 11:17:02 PM UTC 24 Oct 02 11:17:06 PM UTC 24 512953647 ps
T3707 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/465.usbdev_tx_rx_disruption.3796873575 Oct 02 11:17:03 PM UTC 24 Oct 02 11:17:06 PM UTC 24 481799547 ps
T3708 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/468.usbdev_tx_rx_disruption.2050103259 Oct 02 11:17:03 PM UTC 24 Oct 02 11:17:06 PM UTC 24 620072038 ps
T3709 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/473.usbdev_tx_rx_disruption.1125086512 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:15 PM UTC 24 590705129 ps
T3710 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/470.usbdev_tx_rx_disruption.2270623304 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:15 PM UTC 24 505995085 ps
T3711 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/471.usbdev_tx_rx_disruption.1332929952 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:15 PM UTC 24 481011513 ps
T3712 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/472.usbdev_tx_rx_disruption.1032406252 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:15 PM UTC 24 645829772 ps
T3713 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/478.usbdev_tx_rx_disruption.4093032935 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:15 PM UTC 24 524062523 ps
T3714 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/476.usbdev_tx_rx_disruption.2052112874 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:15 PM UTC 24 528135476 ps
T3715 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/474.usbdev_tx_rx_disruption.691839707 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:16 PM UTC 24 568379534 ps
T3716 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/475.usbdev_tx_rx_disruption.4148571214 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:16 PM UTC 24 636642217 ps
T3717 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/487.usbdev_tx_rx_disruption.1607065822 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:16 PM UTC 24 482067031 ps
T3718 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/477.usbdev_tx_rx_disruption.601158255 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:16 PM UTC 24 683793324 ps
T3719 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/479.usbdev_tx_rx_disruption.3045160140 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:22 PM UTC 24 656083975 ps
T3720 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/483.usbdev_tx_rx_disruption.2723246697 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:32 PM UTC 24 559531148 ps
T3721 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/485.usbdev_tx_rx_disruption.1528877929 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:32 PM UTC 24 530367129 ps
T3722 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/484.usbdev_tx_rx_disruption.459004399 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:32 PM UTC 24 599269559 ps
T3723 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/486.usbdev_tx_rx_disruption.3005008582 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:32 PM UTC 24 551346575 ps
T3724 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/491.usbdev_tx_rx_disruption.3879737968 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:33 PM UTC 24 541030163 ps
T3725 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/490.usbdev_tx_rx_disruption.4126201013 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:33 PM UTC 24 519468019 ps
T3726 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/489.usbdev_tx_rx_disruption.3628165650 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:33 PM UTC 24 537657942 ps
T3727 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/498.usbdev_tx_rx_disruption.3578020982 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:33 PM UTC 24 452876867 ps
T3728 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/488.usbdev_tx_rx_disruption.56063325 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:33 PM UTC 24 483588882 ps
T3729 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/497.usbdev_tx_rx_disruption.2110114440 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:33 PM UTC 24 478548919 ps
T3730 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/494.usbdev_tx_rx_disruption.3967894705 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:34 PM UTC 24 560133768 ps
T3731 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/492.usbdev_tx_rx_disruption.1924593156 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:34 PM UTC 24 486788023 ps
T3732 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/495.usbdev_tx_rx_disruption.4126229303 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:34 PM UTC 24 522789908 ps
T3733 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/499.usbdev_tx_rx_disruption.3329025865 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:34 PM UTC 24 587363739 ps
T3734 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/493.usbdev_tx_rx_disruption.1729182324 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:34 PM UTC 24 637373494 ps
T3735 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/default/496.usbdev_tx_rx_disruption.3722788291 Oct 02 11:17:06 PM UTC 24 Oct 02 11:17:34 PM UTC 24 560060375 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.2327610107 Oct 02 11:17:08 PM UTC 24 Oct 02 11:17:10 PM UTC 24 57527905 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2209585316 Oct 02 11:17:08 PM UTC 24 Oct 02 11:17:10 PM UTC 24 112795762 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.601679073 Oct 02 11:17:09 PM UTC 24 Oct 02 11:17:12 PM UTC 24 111344833 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.1282410571 Oct 02 11:17:08 PM UTC 24 Oct 02 11:17:13 PM UTC 24 289912834 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2669553925 Oct 02 11:17:08 PM UTC 24 Oct 02 11:17:16 PM UTC 24 1286103140 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.3565464495 Oct 02 11:17:09 PM UTC 24 Oct 02 11:17:20 PM UTC 24 48257497 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2627243314 Oct 02 11:17:09 PM UTC 24 Oct 02 11:17:21 PM UTC 24 120314493 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2273424943 Oct 02 11:17:09 PM UTC 24 Oct 02 11:17:21 PM UTC 24 295421359 ps
T3736 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.2315021762 Oct 02 11:17:09 PM UTC 24 Oct 02 11:17:22 PM UTC 24 281283252 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.3693381592 Oct 02 11:17:09 PM UTC 24 Oct 02 11:17:22 PM UTC 24 607676180 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1990910653 Oct 02 11:17:18 PM UTC 24 Oct 02 11:17:25 PM UTC 24 824957835 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1827529706 Oct 02 11:17:22 PM UTC 24 Oct 02 11:17:31 PM UTC 24 143376413 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1310789869 Oct 02 11:17:17 PM UTC 24 Oct 02 11:17:32 PM UTC 24 58969904 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.4085619182 Oct 02 11:17:22 PM UTC 24 Oct 02 11:17:32 PM UTC 24 166838054 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.2449486760 Oct 02 11:17:22 PM UTC 24 Oct 02 11:17:32 PM UTC 24 78477557 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.1332273118 Oct 02 11:17:17 PM UTC 24 Oct 02 11:17:32 PM UTC 24 59577771 ps
T213 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2340593836 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:32 PM UTC 24 83266352 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.515537649 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:32 PM UTC 24 79508790 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.2047196122 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:32 PM UTC 24 63234542 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.2575045151 Oct 02 11:17:17 PM UTC 24 Oct 02 11:17:32 PM UTC 24 66770457 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.110890249 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:32 PM UTC 24 40087146 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.3648225872 Oct 02 11:17:13 PM UTC 24 Oct 02 11:17:32 PM UTC 24 65325932 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.161431398 Oct 02 11:17:23 PM UTC 24 Oct 02 11:17:33 PM UTC 24 41120301 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_intg_err.36705334 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:37 PM UTC 24 741736070 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.848971242 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:33 PM UTC 24 47596118 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.42292106 Oct 02 11:17:23 PM UTC 24 Oct 02 11:17:33 PM UTC 24 98577715 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1944164648 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:33 PM UTC 24 176510927 ps
T3737 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3007514320 Oct 02 11:17:23 PM UTC 24 Oct 02 11:17:33 PM UTC 24 159897597 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.2947671621 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:33 PM UTC 24 134148273 ps
T3738 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_rw.1393273645 Oct 02 11:17:36 PM UTC 24 Oct 02 11:17:38 PM UTC 24 61565408 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.855361621 Oct 02 11:17:16 PM UTC 24 Oct 02 11:17:33 PM UTC 24 60585313 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3777258499 Oct 02 11:17:16 PM UTC 24 Oct 02 11:17:33 PM UTC 24 226182586 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2852841019 Oct 02 11:17:11 PM UTC 24 Oct 02 11:17:33 PM UTC 24 119348115 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.53885197 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:33 PM UTC 24 173053485 ps
T3739 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.3269779112 Oct 02 11:17:23 PM UTC 24 Oct 02 11:17:33 PM UTC 24 114015950 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.2073077768 Oct 02 11:17:17 PM UTC 24 Oct 02 11:17:33 PM UTC 24 89096462 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.391486210 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:34 PM UTC 24 277344243 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.2806402632 Oct 02 11:17:17 PM UTC 24 Oct 02 11:17:34 PM UTC 24 785011262 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.3018842149 Oct 02 11:17:22 PM UTC 24 Oct 02 11:17:34 PM UTC 24 133990758 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.2603298368 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:34 PM UTC 24 162950191 ps
T3740 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.3163289897 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:34 PM UTC 24 175164931 ps
T3741 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.2604420381 Oct 02 11:17:11 PM UTC 24 Oct 02 11:17:34 PM UTC 24 99222454 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3787101030 Oct 02 11:17:23 PM UTC 24 Oct 02 11:17:34 PM UTC 24 361031584 ps
T3742 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.2485909565 Oct 02 11:17:17 PM UTC 24 Oct 02 11:17:34 PM UTC 24 176784027 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.3668513005 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:35 PM UTC 24 305009264 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.976627683 Oct 02 11:17:17 PM UTC 24 Oct 02 11:17:35 PM UTC 24 260777966 ps
T3743 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.1876665003 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:35 PM UTC 24 197137750 ps
T535 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_intg_err.2031113823 Oct 02 11:17:34 PM UTC 24 Oct 02 11:17:37 PM UTC 24 391297537 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_intr_test.2193339704 Oct 02 11:17:36 PM UTC 24 Oct 02 11:17:38 PM UTC 24 49372019 ps
T532 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.2512082972 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:35 PM UTC 24 447996743 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.4267562042 Oct 02 11:17:16 PM UTC 24 Oct 02 11:17:35 PM UTC 24 401563175 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.1457344819 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:35 PM UTC 24 37511994 ps
T3744 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.3097197011 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:35 PM UTC 24 162641620 ps
T3745 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3506358238 Oct 02 11:17:07 PM UTC 24 Oct 02 11:17:35 PM UTC 24 325095649 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.3706238074 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:35 PM UTC 24 53588878 ps
T3746 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.3216595327 Oct 02 11:17:23 PM UTC 24 Oct 02 11:17:35 PM UTC 24 168520491 ps
T3747 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.2183223602 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:35 PM UTC 24 55252982 ps
T3748 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.704211803 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:35 PM UTC 24 182507148 ps
T3749 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.850820900 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:35 PM UTC 24 100236382 ps
T3750 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_rw.3757306208 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:35 PM UTC 24 138279084 ps
T3751 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3035678150 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:36 PM UTC 24 61248984 ps
T3752 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2899518089 Oct 02 11:17:34 PM UTC 24 Oct 02 11:17:36 PM UTC 24 114825536 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3896626937 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:36 PM UTC 24 166693147 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2528856125 Oct 02 11:17:34 PM UTC 24 Oct 02 11:17:36 PM UTC 24 102290199 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_errors.2625672944 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:36 PM UTC 24 139314314 ps
T3753 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.2931662939 Oct 02 11:17:32 PM UTC 24 Oct 02 11:17:36 PM UTC 24 371287438 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_tl_errors.3146097121 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:36 PM UTC 24 67449323 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_tl_errors.2318798410 Oct 02 11:17:34 PM UTC 24 Oct 02 11:17:36 PM UTC 24 135584461 ps
T533 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_tl_intg_err.2625587408 Oct 02 11:17:33 PM UTC 24 Oct 02 11:17:37 PM UTC 24 379419448 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_intr_test.2776806414 Oct 02 11:17:36 PM UTC 24 Oct 02 11:17:38 PM UTC 24 60781390 ps
T3754 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_rw.3961097785 Oct 02 11:17:36 PM UTC 24 Oct 02 11:17:38 PM UTC 24 55842663 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_intr_test.525816588 Oct 02 11:17:37 PM UTC 24 Oct 02 11:17:38 PM UTC 24 45648583 ps
T3755 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2494524323 Oct 02 11:17:25 PM UTC 24 Oct 02 11:17:39 PM UTC 24 1759680240 ps
T3756 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_csr_rw.2144049513 Oct 02 11:17:37 PM UTC 24 Oct 02 11:17:39 PM UTC 24 50992753 ps
T3757 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2950265373 Oct 02 11:17:36 PM UTC 24 Oct 02 11:17:39 PM UTC 24 59896656 ps
T3758 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2780763418 Oct 02 11:17:37 PM UTC 24 Oct 02 11:17:39 PM UTC 24 140327626 ps
T3759 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3029359483 Oct 02 11:17:36 PM UTC 24 Oct 02 11:17:39 PM UTC 24 377535923 ps
T3760 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2010277527 Oct 02 11:17:36 PM UTC 24 Oct 02 11:17:39 PM UTC 24 158776055 ps
T3761 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1064943672 Oct 02 11:17:36 PM UTC 24 Oct 02 11:17:39 PM UTC 24 328893942 ps
T3762 /workspaces/repo/scratch/os_regression_2024_10_02/usbdev-sim-vcs/coverage/cover_reg_top/8.usbdev_tl_errors.2256560903 Oct 02 11:17:36 PM UTC 24 Oct 02 11:17:39 PM UTC 24 70665463 ps
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