30db5a999| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 16.128m | 5.342ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 16.128m | 5.342ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 15.873m | 5.707ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 15.394m | 6.143ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 16.662m | 4.948ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 1.039h | 22.896ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 1.017h | 22.988ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 40.468m | 23.102ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.373m | 3.697ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.373m | 3.697ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.373m | 3.697ms | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.550m | 2.152ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.101m | 3.043ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.808m | 3.215ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.396m | 2.914ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 27.365m | 8.544ms | 1 | 3 | 33.33 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 7.397m | 6.639ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 9.318m | 5.074ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.351h | 55.302ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.980h | 68.536ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 7.350m | 8.958ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.980h | 68.536ms | 5 | 5 | 100.00 |
| chip_csr_rw | 9.318m | 5.074ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 11.030s | 243.805us | 100 | 100 | 100.00 |
| V1 | TOTAL | 221 | 223 | 99.10 | |||
| V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 7.088m | 3.592ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 3.110h | 71.141ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 14.668m | 7.486ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.701m | 4.597ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 5.560m | 3.256ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.432m | 2.597ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 10.467m | 4.708ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 9.622m | 4.134ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 10.854m | 4.521ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 10.376m | 3.810ms | 3 | 3 | 100.00 |
| V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 29.088m | 7.194ms | 1 | 1 | 100.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 6.036m | 5.361ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 6.036m | 5.361ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.626m | 2.881ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 8.154m | 6.158ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.367m | 4.127ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 28.241m | 15.705ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 11.194m | 8.011ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.850m | 6.852ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 18.016m | 13.011ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.075m | 2.820ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 20.893m | 8.648ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.063m | 6.125ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.063m | 6.125ms | 6 | 6 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 40.599m | 19.053ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 22.423m | 12.733ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.062m | 4.959ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.608m | 5.043ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 8.257m | 5.691ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 8.850m | 6.852ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 11.113m | 17.010ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.049m | 3.320ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 9.127m | 4.598ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 7.077m | 5.686ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 9.127m | 4.598ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 11.314m | 4.680ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.717m | 7.729ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.717m | 7.729ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 10.146m | 7.775ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 22.279m | 8.128ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.434m | 3.478ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 9.323m | 6.376ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.708m | 2.873ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.141m | 2.899ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 3.569m | 3.064ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.985m | 4.302ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 7.490m | 3.866ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 9.006m | 4.102ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 6.071m | 5.108ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 21.417m | 12.176ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 9.699m | 11.703ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 9.244m | 3.682ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.058m | 4.853ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 9.664m | 4.072ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 8.463m | 4.690ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.773m | 4.247ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 8.548m | 5.101ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 9.699m | 11.703ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 9.244m | 3.682ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.058m | 4.853ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 9.664m | 4.072ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 8.463m | 4.690ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.773m | 4.247ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 8.548m | 5.101ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.292m | 5.536ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.959m | 6.717ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 51.453m | 21.037ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.153m | 3.058ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 16.723m | 6.015ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.454m | 2.971ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.351m | 4.096ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.869m | 3.126ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.548m | 4.430ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.030m | 2.711ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.340m | 3.068ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 16.512m | 6.011ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 16.777m | 8.372ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 55.352m | 28.290ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 5.116m | 3.671ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 6.484m | 3.672ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 8.994m | 5.278ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.469m | 3.704ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 11.344m | 5.715ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 30.776m | 22.686ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 56.429m | 22.374ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 15.927m | 7.858ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.173m | 4.448ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.866m | 2.880ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.044m | 6.431ms | 100 | 100 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 8.627m | 10.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 27.717m | 19.543ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.197m | 7.467ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 14.717m | 7.729ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 24.192m | 16.545ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 39.155m | 24.836ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 33.552m | 19.089ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.870m | 5.472ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 8.627m | 10.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 7.581m | 3.707ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 49.800m | 37.977ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 7.957m | 7.724ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 9.363m | 5.770ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 56.063m | 37.199ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 15.778m | 8.065ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 39.929m | 29.593ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.217m | 3.382ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.044m | 6.431ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 7.077m | 5.686ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.062m | 4.959ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 12.549m | 5.465ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 6.386m | 3.044ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 28.274m | 15.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 3.585m | 2.751ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.044m | 6.431ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.096m | 3.103ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 8.127m | 3.999ms | 3 | 3 | 100.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.044m | 6.431ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 22.279m | 8.128ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.499m | 3.375ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 28.274m | 15.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 7.247m | 4.934ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.230m | 3.650ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 21.139m | 10.364ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 25.671m | 6.736ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 25.800m | 7.122ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.354h | 254.403ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 8.127m | 3.999ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 28.241m | 15.705ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 8.850m | 6.852ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 18.016m | 13.011ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.662m | 3.160ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 15.218m | 8.798ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 15.218m | 8.798ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 15.218m | 8.798ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 7.995m | 4.818ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 10.668m | 4.480ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.247h | 43.668ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 9.778m | 3.770ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 19.997m | 8.122ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 19.835m | 9.169ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 21.089m | 7.007ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 15.218m | 8.798ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.470m | 4.779ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.809m | 8.446ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 15.077m | 10.397ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 6.685m | 13.536ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 9.699m | 11.703ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 9.244m | 3.682ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.058m | 4.853ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 9.664m | 4.072ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 8.463m | 4.690ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.773m | 4.247ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 8.548m | 5.101ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 28.241m | 15.705ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.850m | 6.852ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 18.016m | 13.011ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 11.113m | 17.010ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 7.724m | 3.599ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 6.798m | 3.686ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.300m | 4.722ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 30.186m | 22.730ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 30.186m | 22.730ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 30.186m | 22.730ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 48.679m | 19.814ms | 2 | 3 | 66.67 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 48.679m | 19.814ms | 2 | 3 | 66.67 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 10.216m | 5.438ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.075m | 19.624ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.075m | 19.624ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.075m | 19.624ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.783m | 2.629ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.153m | 3.058ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.461m | 2.669ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.708m | 2.873ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 8.869m | 4.242ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.665m | 2.873ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.454m | 2.971ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.141m | 2.899ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 3.548m | 2.892ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.918m | 2.490ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.869m | 3.126ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 9.470m | 4.779ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 15.218m | 8.798ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 3.769m | 2.943ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 3.978m | 3.253ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 3.569m | 3.064ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.046m | 3.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 27.109m | 8.102ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 12.815m | 5.579ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.573m | 2.903ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 27.109m | 8.102ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 9.338m | 5.448ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 11.187m | 5.238ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 3.038m | 2.116ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 40.387m | 13.442ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 16.540m | 4.718ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 9.470m | 4.779ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 8.351m | 4.096ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 10.061m | 4.253ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 8.869m | 4.242ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 41.048m | 9.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 54.536m | 20.348ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 51.453m | 21.037ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 9.323m | 6.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 9.323m | 6.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 9.323m | 6.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 7.599m | 3.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.809m | 8.446ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.809m | 8.446ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 9.654m | 5.338ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.548m | 4.430ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 16.466m | 9.756ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 15.077m | 10.397ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.044m | 6.431ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 12.063m | 6.125ms | 6 | 6 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 15.218m | 8.798ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 33.133m | 18.249ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 7.599m | 3.354ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.470m | 4.779ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 9.654m | 5.338ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.338m | 2.555ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 33.133m | 18.249ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 7.599m | 3.354ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 9.470m | 4.779ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 9.654m | 5.338ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.338m | 2.555ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 15.218m | 8.798ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.820m | 4.261ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.662m | 3.160ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 9.778m | 3.770ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 19.997m | 8.122ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 19.835m | 9.169ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 21.089m | 7.007ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 15.218m | 8.798ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 6.685m | 13.536ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 6.685m | 13.536ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 33.133m | 18.249ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 20.375m | 6.375ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.959m | 6.717ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 14.516m | 5.393ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 13.292m | 5.536ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.247h | 43.668ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 33.133m | 18.249ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.101m | 3.938ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 9.470m | 4.779ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 10.668m | 4.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.247h | 43.668ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 10.668m | 4.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 10.668m | 4.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 10.668m | 4.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 10.668m | 4.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.044m | 6.431ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 6.685m | 13.536ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 19.720m | 5.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 10.393m | 5.017ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 15.927m | 7.858ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 10.547m | 11.057ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.292m | 5.536ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.959m | 6.717ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 51.453m | 21.037ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.153m | 3.058ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 16.723m | 6.015ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.454m | 2.971ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 8.351m | 4.096ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.869m | 3.126ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 8.548m | 4.430ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.030m | 2.711ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.341m | 2.634ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 24.733m | 13.701ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 24.733m | 13.701ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.963m | 5.409ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.785m | 2.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.963m | 5.409ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 14.017m | 4.490ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 16.334m | 5.467ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 4.699m | 2.922ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 5.338m | 2.555ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 12.549m | 5.465ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 12.549m | 5.465ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.458m | 2.411ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.097m | 2.988ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.274m | 3.216ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.737m | 2.310ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.400m | 3.536ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.445m | 3.511ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.933m | 3.515ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.017m | 3.249ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 4.909m | 2.632ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 29.074m | 10.015ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 5.491m | 3.083ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 7.077m | 5.686ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 9.361m | 6.109ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.167m | 2.403ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.596m | 2.930ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.522m | 3.044ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 3.743m | 2.714ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.833m | 2.504ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 9.221m | 4.650ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 27.365m | 8.544ms | 1 | 3 | 33.33 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.110h | 71.141ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 4.473m | 3.457ms | 0 | 3 | 0.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 2.495m | 2.635ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.200m | 2.702ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 3.032m | 3.350ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 3.130m | 3.448ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 33.161m | 30.230ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 11.113m | 17.010ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.292h | 48.263ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.340h | 50.282ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 15.257m | 7.613ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.350h | 47.490ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 33.161m | 30.230ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 4.796m | 4.238ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 6.265m | 4.305ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 6.002m | 3.796ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 5.196h | 119.711ms | 1 | 3 | 33.33 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 12.259m | 4.432ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 12.419m | 10.862ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.743h | 60.560ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 2.962h | 64.141ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 8.776m | 5.318ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 8.776m | 5.318ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.980h | 68.536ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 59.691m | 24.839ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.397m | 6.639ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 9.318m | 5.074ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.980h | 68.536ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 59.691m | 24.839ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.397m | 6.639ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 9.318m | 5.074ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.560m | 2.614ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 8.180s | 54.298us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.067m | 10.153ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 1.829m | 6.406ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 55.530s | 564.493us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 21.372m | 102.497ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 22.902m | 67.551ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.260m | 1.458ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.006m | 1.468ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.580m | 2.627ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.006m | 1.468ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.152m | 3.415ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 49.733m | 161.074ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.327m | 2.508ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 13.013m | 16.502ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 12.841m | 20.169ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 16.937m | 19.661ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 22.113m | 11.777ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 4.473m | 3.457ms | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 5.019m | 3.422ms | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 4.866m | 3.222ms | 0 | 3 | 0.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 4.747m | 3.615ms | 0 | 1 | 0.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 4.816m | 3.272ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 4.974m | 3.144ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 4.457m | 2.675ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 4.540m | 3.552ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 3.603h | 80.465ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 4.054m | 2.838ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 3.853m | 2.970ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 4.040m | 3.098ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 4.891m | 3.074ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 4.256m | 3.568ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 4.708m | 3.157ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 3.692m | 3.528ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 4.779m | 4.050ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 4.196m | 3.622ms | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 5.036m | 3.819ms | 0 | 1 | 0.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 39.968m | 11.256ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 3.413m | 3.292ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 4.368m | 2.749ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 4.498m | 3.377ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.817h | 79.141ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 3.797m | 3.641ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 4.946m | 3.493ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 4.525m | 2.879ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 4.498m | 3.569ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 4.655m | 3.414ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 4.454m | 3.620ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 4.490m | 2.772ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 4.524m | 3.376ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 3.869m | 3.274ms | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 5.000m | 3.359ms | 0 | 3 | 0.00 |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 3.949h | 78.187ms | 1 | 3 | 33.33 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 5.203m | 3.261ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 4.358m | 3.967ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 3.935m | 2.931ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 4.895m | 3.418ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 4.531m | 2.740ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 4.696m | 3.464ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 4.384m | 2.980ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 4.069m | 3.466ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 5.039m | 3.374ms | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 4.751m | 3.038ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 5.154m | 3.288ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 5.095m | 3.566ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 5.956m | 3.431ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 3.712m | 3.138ms | 0 | 3 | 0.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 27.216m | 8.719ms | 1 | 3 | 33.33 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 5.112m | 3.759ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 5.337m | 3.169ms | 0 | 3 | 0.00 |
| V2 | TOTAL | 2557 | 2651 | 96.45 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.279m | 3.256ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 4.373m | 3.125ms | 2 | 3 | 66.67 |
| V2S | TOTAL | 5 | 6 | 83.33 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 50.100m | 13.971ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 28.629m | 10.743ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 22.158m | 11.088ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 27.019m | 11.939ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 8.599m | 4.382ms | 3 | 3 | 100.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.044m | 6.431ms | 100 | 100 | 100.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.663m | 2.245ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 8.728m | 3.981ms | 1 | 1 | 100.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.460s | 0 | 1 | 0.00 | |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 27.483m | 9.016ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 28.629m | 10.743ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 22.158m | 11.088ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 27.019m | 11.939ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 36.281m | 32.886ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 42.890m | 32.928ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 41.793m | 32.246ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | TOTAL | 17 | 18 | 94.44 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 11.648m | 5.209ms | 3 | 3 | 100.00 | |
| TOTAL | 2803 | 2901 | 96.62 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 19 | 19 | 18 | 94.74 |
| V2 | 270 | 270 | 219 | 81.11 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 26 | 12 | 11 | 42.31 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.00 | 95.74 | 94.99 | 98.17 | -- | 95.55 | 97.93 | 99.64 |
Offending '(!dst_pulse_o)' has 95 failures:
Test rom_e2e_smoke has 3 failures.
0.rom_e2e_smoke.1616576705
Line 1068, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3694.792000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3694.792000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_smoke.1578816724
Line 1068, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3457.276500 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3457.276500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test rom_e2e_shutdown_exception_c has 3 failures.
0.rom_e2e_shutdown_exception_c.2406837445
Line 1084, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3221.908000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3221.908000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_shutdown_exception_c.2341669720
Line 1082, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 2907.500000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 2907.500000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test rom_e2e_shutdown_output has 3 failures.
0.rom_e2e_shutdown_output.3675898990
Line 1093, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3189.824000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3189.824000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_shutdown_output.3840506460
Line 1094, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3172.710500 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3172.710500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.
0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2386748641
Line 1124, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3614.840000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3614.840000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.
0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1243299846
Line 1121, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3272.204000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3272.204000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 46 more tests.
UVM_FATAL @ * us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:62) [chip_sw_sysrst_ctrl_ec_rst_l_vseq] Check failed cfg.chip_vif.ec_rst_l_if.sample_pin(0) == exp_ec_rst_l (* [*] vs * [*]) has 1 failures:
0.chip_sw_sysrst_ctrl_ec_rst_l.3865372276
Line 1656, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
UVM_FATAL @ 19814.197200 us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.chip_sw_sysrst_ctrl_ec_rst_l_vseq] Check failed cfg.chip_vif.ec_rst_l_if.sample_pin(0) == exp_ec_rst_l (1 [0x1] vs 0 [0x0])
UVM_INFO @ 19814.197200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing has 1 failures:
0.chip_sw_coremark.3119728493
Line 1046, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:648) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed enable_cmp == *'b* (* [*] vs * [*]) Lockstep comparison disabled, which is illegal. has 1 failures:
2.chip_sw_rv_core_ibex_lockstep_glitch.2046117455
Line 1078, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 1010.672808 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:648) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed enable_cmp == 1'b1 (0 [0x0] vs 1 [0x1]) Lockstep comparison disabled, which is illegal.
UVM_INFO @ 1010.672808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---