Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.40	94.74	69.01			89.83	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	73.04	92.86	63.27			86.05	50.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T19,T85,T86

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	130161	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	322	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	130161	0	0
T19	582923	1952	0	0
T20	54582	453	0	0
T21	83189	588	0	0
T22	89377	828	0	0
T35	645101	8029	0	0
T39	741269	5709	0	0
T53	49581	0	0	0
T55	0	6204	0	0
T64	42173	280	0	0
T65	0	1435	0	0
T66	0	301	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	322	0	0
T19	582923	5	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	20	0	0
T39	741269	13	0	0
T53	49581	0	0	0
T55	0	15	0	0
T64	42173	1	0	0
T65	0	4	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T19,T20,T87

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	105518	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	262	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	105518	0	0
T19	582923	1939	0	0
T20	54582	449	0	0
T21	83189	537	0	0
T22	89377	841	0	0
T35	645101	3605	0	0
T39	741269	7939	0	0
T53	49581	0	0	0
T55	0	2977	0	0
T64	42173	320	0	0
T65	0	3458	0	0
T66	0	320	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	262	0	0
T19	582923	5	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	9	0	0
T39	741269	18	0	0
T53	49581	0	0	0
T55	0	7	0	0
T64	42173	1	0	0
T65	0	9	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T71,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	110597	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	273	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	110597	0	0
T19	582923	2394	0	0
T20	54582	430	0	0
T21	83189	667	0	0
T22	89377	902	0	0
T35	645101	4642	0	0
T39	741269	4599	0	0
T53	49581	0	0	0
T55	0	4662	0	0
T64	42173	267	0	0
T65	0	2214	0	0
T66	0	330	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	273	0	0
T19	582923	6	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	12	0	0
T39	741269	10	0	0
T53	49581	0	0	0
T55	0	11	0	0
T64	42173	1	0	0
T65	0	6	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T70,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	112347	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	281	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	112347	0	0
T19	582923	6402	0	0
T20	54582	446	0	0
T21	83189	599	0	0
T22	89377	751	0	0
T35	645101	3832	0	0
T39	741269	4904	0	0
T53	49581	0	0	0
T55	0	2937	0	0
T64	42173	325	0	0
T65	0	2979	0	0
T66	0	354	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	281	0	0
T19	582923	16	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	10	0	0
T39	741269	11	0	0
T53	49581	0	0	0
T55	0	7	0	0
T64	42173	1	0	0
T65	0	8	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T19,T85,T88

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	108617	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	269	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	108617	0	0
T19	582923	10062	0	0
T20	54582	401	0	0
T21	83189	552	0	0
T22	89377	818	0	0
T35	645101	5121	0	0
T39	741269	4979	0	0
T53	49581	0	0	0
T55	0	6258	0	0
T64	42173	272	0	0
T65	0	775	0	0
T66	0	310	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	269	0	0
T19	582923	25	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	13	0	0
T39	741269	11	0	0
T53	49581	0	0	0
T55	0	15	0	0
T64	42173	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	115008	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	286	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	115008	0	0
T19	582923	2317	0	0
T20	54582	481	0	0
T21	83189	602	0	0
T22	89377	832	0	0
T35	645101	1960	0	0
T39	741269	3250	0	0
T53	49581	0	0	0
T55	0	5785	0	0
T64	42173	311	0	0
T65	0	1786	0	0
T66	0	292	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	286	0	0
T19	582923	6	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	5	0	0
T39	741269	7	0	0
T53	49581	0	0	0
T55	0	14	0	0
T64	42173	1	0	0
T65	0	5	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T14,T84,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	116466	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	288	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	116466	0	0
T19	582923	8496	0	0
T20	54582	469	0	0
T21	83189	680	0	0
T22	89377	827	0	0
T35	645101	3564	0	0
T39	741269	6020	0	0
T53	49581	0	0	0
T55	0	6281	0	0
T64	42173	306	0	0
T65	0	3061	0	0
T66	0	289	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	288	0	0
T19	582923	21	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	9	0	0
T39	741269	14	0	0
T53	49581	0	0	0
T55	0	15	0	0
T64	42173	1	0	0
T65	0	8	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T73,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	98856	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	246	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	98856	0	0
T19	582923	3185	0	0
T20	54582	381	0	0
T21	83189	592	0	0
T22	89377	826	0	0
T35	645101	4373	0	0
T36	0	585	0	0
T39	741269	5071	0	0
T53	49581	0	0	0
T55	0	3016	0	0
T64	42173	322	0	0
T66	0	268	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	246	0	0
T19	582923	8	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	11	0	0
T36	0	2	0	0
T39	741269	11	0	0
T53	49581	0	0	0
T55	0	7	0	0
T64	42173	1	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T14,T73,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Not Covered
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

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Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	122306	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	250	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	122306	0	0
T19	582923	3593	0	0
T20	54582	468	0	0
T21	83189	541	0	0
T22	89377	847	0	0
T35	645101	3096	0	0
T39	741269	6069	0	0
T53	49581	0	0	0
T55	0	947	0	0
T64	42173	307	0	0
T65	0	3323	0	0
T66	0	360	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	250	0	0
T19	582923	7	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	7	0	0
T39	741269	11	0	0
T53	49581	0	0	0
T55	0	2	0	0
T64	42173	1	0	0
T65	0	7	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0