Unified Coverage Report :: Module :: tlul_cmd_intg_chk

Module : tlul_cmd_intg_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk	100.00	100.00					100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.69	97.33	71.67			93.75	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.83	99.44	98.72			97.14	100.00	u_reg_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

Line Coverage for Module : tlul_cmd_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Module : tlul_cmd_intg_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	5797	5797	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	5797	5797	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	3	3	0	0
T14	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0
T29	3	3	0	0
T31	3	3	0	0
T52	3	3	0	0
T53	3	3	0	0
T54	3	3	0	0
T55	3	3	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	1927	1927	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	16	16	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	1927	1927	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	1927	1927	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0