Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	643493020	303275	0	0
DepthKnown_A	643493020	643376160	0	0
RvalidKnown_A	643493020	643376160	0	0
WreadyKnown_A	643493020	643376160	0	0
gen_passthru_fifo.paramCheckPass	11626	11626	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643493020	303275	0	0
T1	265090	7000	0	0
T2	363272	17432	0	0
T3	268802	6592	0	0
T4	380922	19358	0	0
T5	352872	17324	0	0
T6	231070	7703	0	0
T7	327832	15198	0	0
T8	320740	15082	0	0
T9	310302	13949	0	0
T10	344084	17307	0	0
T11	212708	50	0	0
T12	692276	188	0	0
T13	384630	100	0	0
T17	244152	566	0	0
T18	255610	562	0	0
T19	134830	50	0	0
T32	1861426	5632	0	0
T35	297804	162	0	0
T36	380160	204	0	0
T50	110909	7	0	0
T59	79142	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643493020	643376160	0	0
T1	530180	529552	0	0
T2	726544	725828	0	0
T3	537604	536888	0	0
T4	761844	761144	0	0
T5	705744	705060	0	0
T6	462140	461428	0	0
T7	655664	654976	0	0
T8	641480	640840	0	0
T9	620604	619904	0	0
T10	688168	687496	0	0
T11	638124	637092	0	0
T12	2076828	2076150	0	0
T13	1153890	1152534	0	0
T17	732456	732390	0	0
T18	766830	766770	0	0
T19	404490	403830	0	0
T32	5584278	5584212	0	0
T35	893412	892710	0	0
T44	1592334	1590036	0	0
T59	237426	236706	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643493020	643376160	0	0
T1	530180	529552	0	0
T2	726544	725828	0	0
T3	537604	536888	0	0
T4	761844	761144	0	0
T5	705744	705060	0	0
T6	462140	461428	0	0
T7	655664	654976	0	0
T8	641480	640840	0	0
T9	620604	619904	0	0
T10	688168	687496	0	0
T11	638124	637092	0	0
T12	2076828	2076150	0	0
T13	1153890	1152534	0	0
T17	732456	732390	0	0
T18	766830	766770	0	0
T19	404490	403830	0	0
T32	5584278	5584212	0	0
T35	893412	892710	0	0
T44	1592334	1590036	0	0
T59	237426	236706	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643493020	643376160	0	0
T1	530180	529552	0	0
T2	726544	725828	0	0
T3	537604	536888	0	0
T4	761844	761144	0	0
T5	705744	705060	0	0
T6	462140	461428	0	0
T7	655664	654976	0	0
T8	641480	640840	0	0
T9	620604	619904	0	0
T10	688168	687496	0	0
T11	638124	637092	0	0
T12	2076828	2076150	0	0
T13	1153890	1152534	0	0
T17	732456	732390	0	0
T18	766830	766770	0	0
T19	404490	403830	0	0
T32	5584278	5584212	0	0
T35	893412	892710	0	0
T44	1592334	1590036	0	0
T59	237426	236706	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11626	11626	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0
T11	6	6	0	0
T14	6	6	0	0
T15	6	6	0	0
T16	6	6	0	0
T29	6	6	0	0
T31	6	6	0	0
T52	6	6	0	0
T53	6	6	0	0
T54	6	6	0	0
T55	6	6	0	0