Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9002122	0	0	0
DepthKnown_A	9002122	8999748	0	0
RvalidKnown_A	9002122	8999748	0	0
WreadyKnown_A	9002122	8999748	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9002122	0	0	0
DepthKnown_A	9002122	8999748	0	0
RvalidKnown_A	9002122	8999748	0	0
WreadyKnown_A	9002122	8999748	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9002122	34476	0	0
DepthKnown_A	9002122	8999748	0	0
RvalidKnown_A	9002122	8999748	0	0
WreadyKnown_A	9002122	8999748	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	34476	0	0
T1	132545	4510	0	0
T2	181636	3517	0	0
T3	134401	4154	0	0
T4	190461	3933	0	0
T5	176436	3498	0	0
T6	115535	1606	0	0
T7	163916	3147	0	0
T8	160370	3245	0	0
T9	155151	2864	0	0
T10	172042	3768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9002122	103511	0	0
DepthKnown_A	9002122	8999748	0	0
RvalidKnown_A	9002122	8999748	0	0
WreadyKnown_A	9002122	8999748	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	103511	0	0
T1	132545	2490	0	0
T2	181636	13915	0	0
T3	134401	2438	0	0
T4	190461	15425	0	0
T5	176436	13826	0	0
T6	115535	6097	0	0
T7	163916	12051	0	0
T8	160370	11837	0	0
T9	155151	11085	0	0
T10	172042	13539	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9002122	8999748	0	0
T1	132545	132388	0	0
T2	181636	181457	0	0
T3	134401	134222	0	0
T4	190461	190286	0	0
T5	176436	176265	0	0
T6	115535	115357	0	0
T7	163916	163744	0	0
T8	160370	160210	0	0
T9	155151	154976	0	0
T10	172042	171874	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	101247422	39636	0	0
DepthKnown_A	101247422	101229528	0	0
RvalidKnown_A	101247422	101229528	0	0
WreadyKnown_A	101247422	101229528	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	39636	0	0
T11	106354	25	0	0
T12	346138	94	0	0
T13	192315	50	0	0
T17	122076	283	0	0
T18	127805	281	0	0
T19	67415	25	0	0
T32	930713	2816	0	0
T35	148902	81	0	0
T36	190080	102	0	0
T59	39571	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	101247422	43008	0	0
DepthKnown_A	101247422	101229528	0	0
RvalidKnown_A	101247422	101229528	0	0
WreadyKnown_A	101247422	101229528	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	43008	0	0
T11	106354	25	0	0
T12	346138	94	0	0
T13	192315	50	0	0
T17	122076	283	0	0
T18	127805	281	0	0
T19	67415	25	0	0
T32	930713	2816	0	0
T35	148902	81	0	0
T36	190080	102	0	0
T59	39571	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	101247422	17	0	0
DepthKnown_A	101247422	101229528	0	0
RvalidKnown_A	101247422	101229528	0	0
WreadyKnown_A	101247422	101229528	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	17	0	0
T50	110909	7	0	0
T74	102851	10	0	0
T284	42445	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	101247422	17	0	0
DepthKnown_A	101247422	101229528	0	0
RvalidKnown_A	101247422	101229528	0	0
WreadyKnown_A	101247422	101229528	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	17	0	0
T50	110909	7	0	0
T74	102851	10	0	0
T284	42445	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	101247422	39619	0	0
DepthKnown_A	101247422	101229528	0	0
RvalidKnown_A	101247422	101229528	0	0
WreadyKnown_A	101247422	101229528	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	39619	0	0
T11	106354	25	0	0
T12	346138	94	0	0
T13	192315	50	0	0
T17	122076	283	0	0
T18	127805	281	0	0
T19	67415	25	0	0
T32	930713	2816	0	0
T35	148902	81	0	0
T36	190080	102	0	0
T59	39571	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	101247422	42991	0	0
DepthKnown_A	101247422	101229528	0	0
RvalidKnown_A	101247422	101229528	0	0
WreadyKnown_A	101247422	101229528	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	42991	0	0
T11	106354	25	0	0
T12	346138	94	0	0
T13	192315	50	0	0
T17	122076	283	0	0
T18	127805	281	0	0
T19	67415	25	0	0
T32	930713	2816	0	0
T35	148902	81	0	0
T36	190080	102	0	0
T59	39571	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101247422	101229528	0	0
T11	106354	106182	0	0
T12	346138	346025	0	0
T13	192315	192089	0	0
T17	122076	122065	0	0
T18	127805	127795	0	0
T19	67415	67305	0	0
T32	930713	930702	0	0
T35	148902	148785	0	0
T44	265389	265006	0	0
T59	39571	39451	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T29	1	1	0	0
T31	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0