| T864 |
/workspace/coverage/default/2.chip_sw_example_flash.3624388769 |
|
|
Jan 10 01:55:46 PM PST 24 |
Jan 10 01:59:08 PM PST 24 |
2676286824 ps |
| T145 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1601939113 |
|
|
Jan 10 02:07:10 PM PST 24 |
Jan 10 02:14:16 PM PST 24 |
3534948600 ps |
| T628 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.4178036575 |
|
|
Jan 10 01:59:41 PM PST 24 |
Jan 10 02:08:52 PM PST 24 |
5808182286 ps |
| T865 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.2290313813 |
|
|
Jan 10 01:57:39 PM PST 24 |
Jan 10 02:08:20 PM PST 24 |
6878737414 ps |
| T866 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.340045901 |
|
|
Jan 10 01:59:19 PM PST 24 |
Jan 10 02:37:21 PM PST 24 |
12149007390 ps |
| T236 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2254276883 |
|
|
Jan 10 02:00:12 PM PST 24 |
Jan 10 02:03:54 PM PST 24 |
3041765944 ps |
| T156 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.120526008 |
|
|
Jan 10 01:54:53 PM PST 24 |
Jan 10 02:03:31 PM PST 24 |
3952230302 ps |
| T867 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.1200280430 |
|
|
Jan 10 02:00:15 PM PST 24 |
Jan 10 02:04:02 PM PST 24 |
2670086960 ps |
| T868 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3304011898 |
|
|
Jan 10 01:56:07 PM PST 24 |
Jan 10 02:24:24 PM PST 24 |
12766652205 ps |
| T182 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.835542947 |
|
|
Jan 10 01:58:05 PM PST 24 |
Jan 10 02:22:01 PM PST 24 |
13771572432 ps |
| T614 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2658929120 |
|
|
Jan 10 02:05:16 PM PST 24 |
Jan 10 02:13:50 PM PST 24 |
4204482280 ps |
| T627 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2759325887 |
|
|
Jan 10 02:01:27 PM PST 24 |
Jan 10 02:06:59 PM PST 24 |
3882886110 ps |
| T685 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.987053806 |
|
|
Jan 10 01:55:30 PM PST 24 |
Jan 10 02:02:23 PM PST 24 |
4229184468 ps |
| T869 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2543338585 |
|
|
Jan 10 01:59:52 PM PST 24 |
Jan 10 02:09:10 PM PST 24 |
4322595284 ps |
| T171 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2155993285 |
|
|
Jan 10 02:05:01 PM PST 24 |
Jan 10 02:17:04 PM PST 24 |
5927047955 ps |
| T870 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3197901225 |
|
|
Jan 10 02:08:19 PM PST 24 |
Jan 10 02:10:58 PM PST 24 |
2375251062 ps |
| T871 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2281541371 |
|
|
Jan 10 02:05:28 PM PST 24 |
Jan 10 02:15:33 PM PST 24 |
5180444720 ps |
| T872 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1535611639 |
|
|
Jan 10 01:59:27 PM PST 24 |
Jan 10 02:09:14 PM PST 24 |
4924090344 ps |
| T873 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2393420888 |
|
|
Jan 10 01:58:35 PM PST 24 |
Jan 10 02:37:44 PM PST 24 |
22359240196 ps |
| T874 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1012614141 |
|
|
Jan 10 01:56:32 PM PST 24 |
Jan 10 02:13:28 PM PST 24 |
8819602262 ps |
| T186 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1111268376 |
|
|
Jan 10 02:02:02 PM PST 24 |
Jan 10 02:16:44 PM PST 24 |
4697258418 ps |
| T175 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2941571929 |
|
|
Jan 10 01:57:22 PM PST 24 |
Jan 10 02:10:34 PM PST 24 |
5332074792 ps |
| T875 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1748643958 |
|
|
Jan 10 02:04:48 PM PST 24 |
Jan 10 02:12:02 PM PST 24 |
4046485260 ps |
| T255 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3094361246 |
|
|
Jan 10 01:55:18 PM PST 24 |
Jan 10 02:04:58 PM PST 24 |
6333288048 ps |
| T876 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3944155223 |
|
|
Jan 10 01:57:00 PM PST 24 |
Jan 10 02:06:16 PM PST 24 |
5030988326 ps |
| T676 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3424854318 |
|
|
Jan 10 02:07:07 PM PST 24 |
Jan 10 02:12:29 PM PST 24 |
3371542040 ps |
| T877 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3031046130 |
|
|
Jan 10 01:57:28 PM PST 24 |
Jan 10 02:02:58 PM PST 24 |
3531352392 ps |
| T89 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3499282321 |
|
|
Jan 10 01:57:59 PM PST 24 |
Jan 10 02:08:27 PM PST 24 |
12139869593 ps |
| T371 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3882474806 |
|
|
Jan 10 01:58:00 PM PST 24 |
Jan 10 02:04:47 PM PST 24 |
4133871952 ps |
| T114 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3302914325 |
|
|
Jan 10 01:57:36 PM PST 24 |
Jan 10 02:06:09 PM PST 24 |
7689079762 ps |
| T353 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.391432658 |
|
|
Jan 10 01:55:24 PM PST 24 |
Jan 10 01:58:36 PM PST 24 |
3250387548 ps |
| T755 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2410702427 |
|
|
Jan 10 02:06:57 PM PST 24 |
Jan 10 02:15:07 PM PST 24 |
5652803928 ps |
| T878 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.270071295 |
|
|
Jan 10 02:05:05 PM PST 24 |
Jan 10 02:12:58 PM PST 24 |
6856261166 ps |
| T249 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.461613079 |
|
|
Jan 10 01:56:42 PM PST 24 |
Jan 10 02:06:59 PM PST 24 |
6696135048 ps |
| T879 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.703901942 |
|
|
Jan 10 02:04:57 PM PST 24 |
Jan 10 02:31:22 PM PST 24 |
8948055628 ps |
| T140 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3992191382 |
|
|
Jan 10 01:56:11 PM PST 24 |
Jan 10 02:08:42 PM PST 24 |
4047924266 ps |
| T158 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1857507718 |
|
|
Jan 10 01:55:11 PM PST 24 |
Jan 10 02:06:54 PM PST 24 |
7471481744 ps |
| T151 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.51664237 |
|
|
Jan 10 01:56:11 PM PST 24 |
Jan 10 02:04:04 PM PST 24 |
5779325046 ps |
| T880 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2682609269 |
|
|
Jan 10 02:02:06 PM PST 24 |
Jan 10 02:31:45 PM PST 24 |
8888163825 ps |
| T734 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.849675278 |
|
|
Jan 10 02:06:13 PM PST 24 |
Jan 10 02:16:41 PM PST 24 |
4971745768 ps |
| T366 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.4055841041 |
|
|
Jan 10 01:55:28 PM PST 24 |
Jan 10 02:00:11 PM PST 24 |
2418877984 ps |
| T35 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2356844804 |
|
|
Jan 10 01:59:04 PM PST 24 |
Jan 10 02:04:33 PM PST 24 |
4424193390 ps |
| T364 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2386371521 |
|
|
Jan 10 02:02:59 PM PST 24 |
Jan 10 02:09:05 PM PST 24 |
3587410774 ps |
| T881 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.690113330 |
|
|
Jan 10 01:58:47 PM PST 24 |
Jan 10 02:16:15 PM PST 24 |
4994362196 ps |
| T52 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2707410511 |
|
|
Jan 10 01:58:18 PM PST 24 |
Jan 10 02:08:49 PM PST 24 |
4007690012 ps |
| T882 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1622421233 |
|
|
Jan 10 02:04:30 PM PST 24 |
Jan 10 02:23:28 PM PST 24 |
13786912699 ps |
| T48 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.4254108038 |
|
|
Jan 10 02:02:27 PM PST 24 |
Jan 10 02:12:14 PM PST 24 |
7347286885 ps |
| T883 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1943333064 |
|
|
Jan 10 02:05:04 PM PST 24 |
Jan 10 02:13:27 PM PST 24 |
4950420560 ps |
| T50 |
/workspace/coverage/default/3.chip_tap_straps_prod.2188723442 |
|
|
Jan 10 02:02:08 PM PST 24 |
Jan 10 02:23:40 PM PST 24 |
12473673570 ps |
| T884 |
/workspace/coverage/default/2.rom_keymgr_functest.3344820949 |
|
|
Jan 10 02:00:47 PM PST 24 |
Jan 10 02:06:48 PM PST 24 |
3517597650 ps |
| T660 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2646591213 |
|
|
Jan 10 02:06:38 PM PST 24 |
Jan 10 02:17:13 PM PST 24 |
6334167092 ps |
| T212 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1595710958 |
|
|
Jan 10 02:06:13 PM PST 24 |
Jan 10 02:15:59 PM PST 24 |
4619413288 ps |
| T885 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1374582088 |
|
|
Jan 10 02:04:10 PM PST 24 |
Jan 10 02:06:55 PM PST 24 |
2476121764 ps |
| T683 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.383405371 |
|
|
Jan 10 02:04:22 PM PST 24 |
Jan 10 02:12:08 PM PST 24 |
4314923042 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.2421982732 |
|
|
Jan 10 01:56:31 PM PST 24 |
Jan 10 01:59:39 PM PST 24 |
3069988046 ps |
| T886 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4134007157 |
|
|
Jan 10 02:01:02 PM PST 24 |
Jan 10 02:08:49 PM PST 24 |
7389145426 ps |
| T887 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2404583025 |
|
|
Jan 10 01:58:26 PM PST 24 |
Jan 10 02:03:02 PM PST 24 |
2641748797 ps |
| T610 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.3498692174 |
|
|
Jan 10 01:55:44 PM PST 24 |
Jan 10 02:17:26 PM PST 24 |
7303693200 ps |
| T888 |
/workspace/coverage/default/2.chip_sw_example_concurrency.696285925 |
|
|
Jan 10 02:02:21 PM PST 24 |
Jan 10 02:06:33 PM PST 24 |
2780742408 ps |
| T91 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4178509702 |
|
|
Jan 10 01:59:29 PM PST 24 |
Jan 10 02:18:33 PM PST 24 |
8642992375 ps |
| T889 |
/workspace/coverage/default/2.rom_e2e_smoke.2681687939 |
|
|
Jan 10 02:00:24 PM PST 24 |
Jan 10 02:31:30 PM PST 24 |
8390477832 ps |
| T890 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.4289650954 |
|
|
Jan 10 01:56:00 PM PST 24 |
Jan 10 02:00:27 PM PST 24 |
2778454560 ps |
| T891 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3825346799 |
|
|
Jan 10 02:02:30 PM PST 24 |
Jan 10 02:09:20 PM PST 24 |
3607682880 ps |
| T892 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2916600828 |
|
|
Jan 10 01:54:36 PM PST 24 |
Jan 10 02:07:37 PM PST 24 |
4868758616 ps |
| T718 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.943126244 |
|
|
Jan 10 02:05:00 PM PST 24 |
Jan 10 02:12:45 PM PST 24 |
4331454040 ps |
| T893 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.585753588 |
|
|
Jan 10 01:55:54 PM PST 24 |
Jan 10 02:03:29 PM PST 24 |
5197755750 ps |
| T139 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1904124322 |
|
|
Jan 10 01:55:33 PM PST 24 |
Jan 10 02:08:56 PM PST 24 |
5890443796 ps |
| T152 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.326756700 |
|
|
Jan 10 02:00:09 PM PST 24 |
Jan 10 02:08:00 PM PST 24 |
5133240040 ps |
| T95 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1542346163 |
|
|
Jan 10 02:05:01 PM PST 24 |
Jan 10 02:56:26 PM PST 24 |
24386759885 ps |
| T894 |
/workspace/coverage/default/1.chip_sw_aes_entropy.3292254792 |
|
|
Jan 10 01:56:35 PM PST 24 |
Jan 10 02:01:51 PM PST 24 |
2306539200 ps |
| T659 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3038762813 |
|
|
Jan 10 01:55:49 PM PST 24 |
Jan 10 02:04:18 PM PST 24 |
17983149080 ps |
| T895 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.882428515 |
|
|
Jan 10 02:02:37 PM PST 24 |
Jan 10 02:11:32 PM PST 24 |
4980599230 ps |
| T896 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3862382308 |
|
|
Jan 10 02:04:26 PM PST 24 |
Jan 10 02:38:28 PM PST 24 |
23450688904 ps |
| T222 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2264473556 |
|
|
Jan 10 01:54:53 PM PST 24 |
Jan 10 02:05:00 PM PST 24 |
4287355777 ps |
| T686 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3284456670 |
|
|
Jan 10 02:06:02 PM PST 24 |
Jan 10 02:12:52 PM PST 24 |
4105679240 ps |
| T897 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2204656718 |
|
|
Jan 10 01:53:31 PM PST 24 |
Jan 10 02:12:23 PM PST 24 |
5669155382 ps |
| T898 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2990680393 |
|
|
Jan 10 01:56:07 PM PST 24 |
Jan 10 02:00:12 PM PST 24 |
2571480706 ps |
| T115 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2072350738 |
|
|
Jan 10 01:56:26 PM PST 24 |
Jan 10 02:01:38 PM PST 24 |
2550205410 ps |
| T23 |
/workspace/coverage/default/2.chip_sw_alert_test.3334199182 |
|
|
Jan 10 01:59:08 PM PST 24 |
Jan 10 02:04:52 PM PST 24 |
3489557036 ps |
| T354 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4081641000 |
|
|
Jan 10 01:57:12 PM PST 24 |
Jan 10 01:59:40 PM PST 24 |
3274066425 ps |
| T313 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.165005228 |
|
|
Jan 10 01:56:38 PM PST 24 |
Jan 10 02:01:12 PM PST 24 |
3036110392 ps |
| T899 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3719293479 |
|
|
Jan 10 01:56:40 PM PST 24 |
Jan 10 02:11:56 PM PST 24 |
5887485822 ps |
| T176 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3566433380 |
|
|
Jan 10 02:01:04 PM PST 24 |
Jan 10 02:18:20 PM PST 24 |
6005428872 ps |
| T900 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.436523667 |
|
|
Jan 10 01:59:49 PM PST 24 |
Jan 10 02:06:38 PM PST 24 |
4772734838 ps |
| T159 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2223241757 |
|
|
Jan 10 01:59:36 PM PST 24 |
Jan 10 02:09:45 PM PST 24 |
7144221000 ps |
| T14 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3834319490 |
|
|
Jan 10 02:00:32 PM PST 24 |
Jan 10 02:28:32 PM PST 24 |
25380630130 ps |
| T237 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.319774705 |
|
|
Jan 10 02:00:46 PM PST 24 |
Jan 10 02:04:24 PM PST 24 |
3036789544 ps |
| T901 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1872399940 |
|
|
Jan 10 01:56:21 PM PST 24 |
Jan 10 01:59:31 PM PST 24 |
2686608784 ps |
| T902 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1857805137 |
|
|
Jan 10 01:59:29 PM PST 24 |
Jan 10 02:05:25 PM PST 24 |
3192205816 ps |
| T179 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3943026265 |
|
|
Jan 10 01:58:21 PM PST 24 |
Jan 10 02:20:28 PM PST 24 |
13185814776 ps |
| T903 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1971670840 |
|
|
Jan 10 01:59:32 PM PST 24 |
Jan 10 02:13:33 PM PST 24 |
5922792100 ps |
| T706 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909382617 |
|
|
Jan 10 02:02:08 PM PST 24 |
Jan 10 02:07:38 PM PST 24 |
3612421920 ps |
| T367 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1387825872 |
|
|
Jan 10 01:58:57 PM PST 24 |
Jan 10 02:08:43 PM PST 24 |
4167090100 ps |
| T904 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.1813933068 |
|
|
Jan 10 01:58:04 PM PST 24 |
Jan 10 02:03:28 PM PST 24 |
3029502220 ps |
| T905 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1859901511 |
|
|
Jan 10 01:56:26 PM PST 24 |
Jan 10 02:25:08 PM PST 24 |
19936348250 ps |
| T906 |
/workspace/coverage/default/1.chip_jtag_csr_rw.4049336720 |
|
|
Jan 10 01:48:50 PM PST 24 |
Jan 10 02:07:40 PM PST 24 |
11066584482 ps |
| T672 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1954866387 |
|
|
Jan 10 01:55:02 PM PST 24 |
Jan 10 02:43:29 PM PST 24 |
19993843153 ps |
| T907 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.162609661 |
|
|
Jan 10 02:02:14 PM PST 24 |
Jan 10 02:17:21 PM PST 24 |
5383523160 ps |
| T167 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1278892407 |
|
|
Jan 10 01:54:43 PM PST 24 |
Jan 10 02:07:15 PM PST 24 |
4238039608 ps |
| T262 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3102196060 |
|
|
Jan 10 01:59:06 PM PST 24 |
Jan 10 03:01:41 PM PST 24 |
18145879108 ps |
| T908 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.374731214 |
|
|
Jan 10 01:55:02 PM PST 24 |
Jan 10 02:17:14 PM PST 24 |
6335322988 ps |
| T633 |
/workspace/coverage/default/0.chip_sw_power_idle_load.2753650495 |
|
|
Jan 10 02:01:04 PM PST 24 |
Jan 10 02:11:54 PM PST 24 |
3990305476 ps |
| T909 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.659610866 |
|
|
Jan 10 02:06:40 PM PST 24 |
Jan 10 03:09:30 PM PST 24 |
23507041456 ps |
| T910 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3284874036 |
|
|
Jan 10 01:57:00 PM PST 24 |
Jan 10 02:14:13 PM PST 24 |
7940678755 ps |
| T220 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.640227614 |
|
|
Jan 10 02:03:07 PM PST 24 |
Jan 10 02:14:04 PM PST 24 |
4988135960 ps |
| T911 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3114938078 |
|
|
Jan 10 01:59:37 PM PST 24 |
Jan 10 02:05:34 PM PST 24 |
3883018472 ps |
| T608 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.3338209382 |
|
|
Jan 10 01:58:49 PM PST 24 |
Jan 10 02:09:07 PM PST 24 |
4075225544 ps |
| T912 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3623563838 |
|
|
Jan 10 02:00:27 PM PST 24 |
Jan 10 04:43:53 PM PST 24 |
61286273028 ps |
| T913 |
/workspace/coverage/default/1.chip_jtag_mem_access.1292651573 |
|
|
Jan 10 01:48:35 PM PST 24 |
Jan 10 02:13:39 PM PST 24 |
13781822385 ps |
| T914 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3934593963 |
|
|
Jan 10 02:06:42 PM PST 24 |
Jan 10 02:44:17 PM PST 24 |
13314270998 ps |
| T372 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3794054262 |
|
|
Jan 10 01:54:20 PM PST 24 |
Jan 10 02:01:11 PM PST 24 |
4410793420 ps |
| T915 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.3485619366 |
|
|
Jan 10 02:00:11 PM PST 24 |
Jan 10 02:03:42 PM PST 24 |
3171235686 ps |
| T111 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3247505940 |
|
|
Jan 10 01:56:31 PM PST 24 |
Jan 10 02:03:39 PM PST 24 |
5299108892 ps |
| T753 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2540537871 |
|
|
Jan 10 02:05:56 PM PST 24 |
Jan 10 02:14:10 PM PST 24 |
5361596472 ps |
| T190 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1579459425 |
|
|
Jan 10 02:03:09 PM PST 24 |
Jan 10 02:17:52 PM PST 24 |
5593126368 ps |
| T916 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2903527593 |
|
|
Jan 10 02:02:23 PM PST 24 |
Jan 10 02:09:50 PM PST 24 |
5523178112 ps |
| T917 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.2711028847 |
|
|
Jan 10 02:00:34 PM PST 24 |
Jan 10 02:06:11 PM PST 24 |
2956331176 ps |
| T168 |
/workspace/coverage/default/0.chip_sival_flash_info_access.3123330799 |
|
|
Jan 10 01:54:44 PM PST 24 |
Jan 10 02:02:25 PM PST 24 |
4192362624 ps |
| T918 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.2049802487 |
|
|
Jan 10 02:05:12 PM PST 24 |
Jan 10 02:32:46 PM PST 24 |
8699714995 ps |
| T116 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.484559099 |
|
|
Jan 10 01:56:15 PM PST 24 |
Jan 10 02:59:18 PM PST 24 |
18281379622 ps |
| T919 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3461986801 |
|
|
Jan 10 01:58:12 PM PST 24 |
Jan 10 02:02:00 PM PST 24 |
2811186984 ps |
| T920 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1074127285 |
|
|
Jan 10 01:59:41 PM PST 24 |
Jan 10 04:46:11 PM PST 24 |
61811746040 ps |
| T921 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.329361089 |
|
|
Jan 10 01:59:10 PM PST 24 |
Jan 10 02:12:01 PM PST 24 |
10136712362 ps |
| T5 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.559643965 |
|
|
Jan 10 01:57:19 PM PST 24 |
Jan 10 02:00:58 PM PST 24 |
2472875527 ps |
| T922 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1387943147 |
|
|
Jan 10 02:01:37 PM PST 24 |
Jan 10 02:04:23 PM PST 24 |
2540335710 ps |
| T160 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.827386072 |
|
|
Jan 10 01:53:21 PM PST 24 |
Jan 10 02:01:42 PM PST 24 |
4552732038 ps |
| T213 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1283464249 |
|
|
Jan 10 02:00:36 PM PST 24 |
Jan 10 02:09:11 PM PST 24 |
5966942550 ps |
| T205 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2127371464 |
|
|
Jan 10 02:01:37 PM PST 24 |
Jan 10 02:13:21 PM PST 24 |
5006293830 ps |
| T203 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3887959582 |
|
|
Jan 10 02:03:23 PM PST 24 |
Jan 10 02:20:06 PM PST 24 |
5860908528 ps |
| T715 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3420495476 |
|
|
Jan 10 02:05:47 PM PST 24 |
Jan 10 02:17:40 PM PST 24 |
5086447984 ps |
| T51 |
/workspace/coverage/default/4.chip_tap_straps_prod.669522638 |
|
|
Jan 10 02:01:52 PM PST 24 |
Jan 10 02:14:52 PM PST 24 |
7054200213 ps |
| T357 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.15862876 |
|
|
Jan 10 02:00:23 PM PST 24 |
Jan 10 02:29:03 PM PST 24 |
26241854990 ps |
| T923 |
/workspace/coverage/default/2.chip_tap_straps_prod.750143693 |
|
|
Jan 10 01:59:19 PM PST 24 |
Jan 10 02:10:06 PM PST 24 |
7263940699 ps |
| T704 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.4146935959 |
|
|
Jan 10 02:01:25 PM PST 24 |
Jan 10 02:11:33 PM PST 24 |
5904671586 ps |
| T924 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3692420416 |
|
|
Jan 10 01:55:32 PM PST 24 |
Jan 10 02:00:18 PM PST 24 |
2614975160 ps |
| T15 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2617669036 |
|
|
Jan 10 01:58:51 PM PST 24 |
Jan 10 02:22:44 PM PST 24 |
21581208216 ps |
| T925 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3588739592 |
|
|
Jan 10 01:56:32 PM PST 24 |
Jan 10 02:03:46 PM PST 24 |
4511293980 ps |
| T668 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3679858506 |
|
|
Jan 10 02:00:57 PM PST 24 |
Jan 10 02:14:36 PM PST 24 |
5149768372 ps |
| T926 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.919674320 |
|
|
Jan 10 01:57:33 PM PST 24 |
Jan 10 02:10:55 PM PST 24 |
5750894732 ps |
| T726 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.209612087 |
|
|
Jan 10 02:05:08 PM PST 24 |
Jan 10 02:10:20 PM PST 24 |
3641140312 ps |
| T630 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3625799091 |
|
|
Jan 10 02:06:05 PM PST 24 |
Jan 10 02:10:34 PM PST 24 |
3791731052 ps |
| T927 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.1429481771 |
|
|
Jan 10 01:56:33 PM PST 24 |
Jan 10 02:06:28 PM PST 24 |
5406775800 ps |
| T187 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1102288437 |
|
|
Jan 10 02:00:26 PM PST 24 |
Jan 10 02:33:40 PM PST 24 |
13545699844 ps |
| T928 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1587229217 |
|
|
Jan 10 01:55:32 PM PST 24 |
Jan 10 02:00:44 PM PST 24 |
3114300170 ps |
| T929 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3412970937 |
|
|
Jan 10 02:00:42 PM PST 24 |
Jan 10 02:11:53 PM PST 24 |
18453791592 ps |
| T930 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.778613162 |
|
|
Jan 10 02:01:12 PM PST 24 |
Jan 10 02:13:27 PM PST 24 |
10642216762 ps |
| T931 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.1436880249 |
|
|
Jan 10 01:58:00 PM PST 24 |
Jan 10 02:07:10 PM PST 24 |
4801814440 ps |
| T311 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1531057680 |
|
|
Jan 10 01:59:16 PM PST 24 |
Jan 10 02:41:55 PM PST 24 |
12312840442 ps |
| T735 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1075504240 |
|
|
Jan 10 02:05:45 PM PST 24 |
Jan 10 02:17:01 PM PST 24 |
4679111526 ps |
| T932 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2541523008 |
|
|
Jan 10 01:56:36 PM PST 24 |
Jan 10 02:13:04 PM PST 24 |
5661130800 ps |
| T933 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.614801509 |
|
|
Jan 10 01:59:32 PM PST 24 |
Jan 10 02:20:41 PM PST 24 |
7234737300 ps |
| T934 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.478312648 |
|
|
Jan 10 01:56:15 PM PST 24 |
Jan 10 02:02:10 PM PST 24 |
4256457720 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2094885198 |
|
|
Jan 10 02:01:05 PM PST 24 |
Jan 10 02:14:43 PM PST 24 |
5133970594 ps |
| T352 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1941403715 |
|
|
Jan 10 02:04:26 PM PST 24 |
Jan 10 02:09:55 PM PST 24 |
3691784696 ps |
| T935 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.1514762 |
|
|
Jan 10 02:02:03 PM PST 24 |
Jan 10 02:05:34 PM PST 24 |
2633172680 ps |
| T632 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.605717871 |
|
|
Jan 10 01:55:01 PM PST 24 |
Jan 10 02:00:07 PM PST 24 |
2795399500 ps |
| T128 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.988543156 |
|
|
Jan 10 01:58:30 PM PST 24 |
Jan 10 02:06:05 PM PST 24 |
4115481089 ps |
| T936 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.56274909 |
|
|
Jan 10 01:59:06 PM PST 24 |
Jan 10 02:08:28 PM PST 24 |
6132354520 ps |
| T937 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.2487582797 |
|
|
Jan 10 02:02:05 PM PST 24 |
Jan 10 02:06:08 PM PST 24 |
2518598720 ps |
| T112 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3880983532 |
|
|
Jan 10 01:58:52 PM PST 24 |
Jan 10 02:05:36 PM PST 24 |
5310963592 ps |
| T938 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.2949134583 |
|
|
Jan 10 02:01:26 PM PST 24 |
Jan 10 02:29:59 PM PST 24 |
9243570072 ps |
| T613 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444031358 |
|
|
Jan 10 02:03:06 PM PST 24 |
Jan 10 02:09:24 PM PST 24 |
3457770686 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.145887684 |
|
|
Jan 10 01:55:16 PM PST 24 |
Jan 10 02:19:07 PM PST 24 |
6509237240 ps |
| T940 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.1523995763 |
|
|
Jan 10 02:05:30 PM PST 24 |
Jan 10 02:33:27 PM PST 24 |
9297638700 ps |
| T941 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3071087392 |
|
|
Jan 10 01:57:29 PM PST 24 |
Jan 10 02:02:18 PM PST 24 |
2704631587 ps |
| T365 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1169517616 |
|
|
Jan 10 02:02:11 PM PST 24 |
Jan 10 02:07:34 PM PST 24 |
3391066438 ps |
| T942 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2551046564 |
|
|
Jan 10 02:00:58 PM PST 24 |
Jan 10 02:08:50 PM PST 24 |
5935653836 ps |
| T673 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1055757648 |
|
|
Jan 10 01:56:06 PM PST 24 |
Jan 10 02:45:32 PM PST 24 |
20758311519 ps |
| T79 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.792685096 |
|
|
Jan 10 01:59:27 PM PST 24 |
Jan 10 02:18:55 PM PST 24 |
21136777492 ps |
| T943 |
/workspace/coverage/default/1.chip_sw_example_rom.42822993 |
|
|
Jan 10 02:01:35 PM PST 24 |
Jan 10 02:03:26 PM PST 24 |
2010707224 ps |
| T944 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2095862779 |
|
|
Jan 10 01:54:34 PM PST 24 |
Jan 10 01:59:31 PM PST 24 |
2757480846 ps |
| T945 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2808488706 |
|
|
Jan 10 01:55:37 PM PST 24 |
Jan 10 02:40:49 PM PST 24 |
17590408776 ps |
| T946 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3796223930 |
|
|
Jan 10 01:59:03 PM PST 24 |
Jan 10 02:23:19 PM PST 24 |
8165324565 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3955375476 |
|
|
Jan 10 02:02:22 PM PST 24 |
Jan 10 02:22:03 PM PST 24 |
9762068132 ps |
| T312 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.514994066 |
|
|
Jan 10 01:59:28 PM PST 24 |
Jan 10 02:39:26 PM PST 24 |
12168802720 ps |
| T948 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1684970724 |
|
|
Jan 10 01:54:56 PM PST 24 |
Jan 10 02:28:32 PM PST 24 |
22532476696 ps |
| T314 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3255963118 |
|
|
Jan 10 01:57:21 PM PST 24 |
Jan 10 02:03:08 PM PST 24 |
4139498036 ps |
| T949 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.57712229 |
|
|
Jan 10 01:54:20 PM PST 24 |
Jan 10 01:58:43 PM PST 24 |
2863059948 ps |
| T702 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.1902025381 |
|
|
Jan 10 02:02:58 PM PST 24 |
Jan 10 02:12:54 PM PST 24 |
5285258872 ps |
| T71 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1329843326 |
|
|
Jan 10 02:06:13 PM PST 24 |
Jan 10 02:12:35 PM PST 24 |
3595148952 ps |
| T680 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3240565620 |
|
|
Jan 10 02:07:33 PM PST 24 |
Jan 10 02:16:10 PM PST 24 |
4821331030 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2868485908 |
|
|
Jan 10 01:55:53 PM PST 24 |
Jan 10 02:04:44 PM PST 24 |
4639142580 ps |
| T951 |
/workspace/coverage/default/0.chip_sw_example_concurrency.4013982337 |
|
|
Jan 10 01:54:17 PM PST 24 |
Jan 10 01:57:37 PM PST 24 |
2587972844 ps |
| T149 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3237337122 |
|
|
Jan 10 02:05:32 PM PST 24 |
Jan 10 02:15:15 PM PST 24 |
5410041950 ps |
| T952 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.3442046375 |
|
|
Jan 10 01:58:31 PM PST 24 |
Jan 10 02:28:33 PM PST 24 |
8619266536 ps |
| T157 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.902595147 |
|
|
Jan 10 01:56:03 PM PST 24 |
Jan 10 03:19:31 PM PST 24 |
46778696310 ps |
| T953 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.870978780 |
|
|
Jan 10 01:54:55 PM PST 24 |
Jan 10 02:12:38 PM PST 24 |
8153878800 ps |
| T954 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.301702402 |
|
|
Jan 10 02:01:58 PM PST 24 |
Jan 10 02:12:05 PM PST 24 |
3761962692 ps |
| T739 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187959050 |
|
|
Jan 10 02:04:28 PM PST 24 |
Jan 10 02:10:40 PM PST 24 |
4044928240 ps |
| T730 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.666716348 |
|
|
Jan 10 02:04:48 PM PST 24 |
Jan 10 02:09:31 PM PST 24 |
2970858320 ps |
| T298 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2934687152 |
|
|
Jan 10 01:55:35 PM PST 24 |
Jan 10 02:08:52 PM PST 24 |
6293306760 ps |
| T955 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1392101940 |
|
|
Jan 10 02:01:45 PM PST 24 |
Jan 10 02:06:00 PM PST 24 |
2397534616 ps |
| T956 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2023133923 |
|
|
Jan 10 02:04:54 PM PST 24 |
Jan 10 02:52:57 PM PST 24 |
35755764837 ps |
| T749 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2861212765 |
|
|
Jan 10 02:05:42 PM PST 24 |
Jan 10 02:13:46 PM PST 24 |
4281639836 ps |
| T957 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.4072042927 |
|
|
Jan 10 01:59:53 PM PST 24 |
Jan 10 02:03:37 PM PST 24 |
3040070972 ps |
| T958 |
/workspace/coverage/default/0.rom_e2e_static_critical.1396323207 |
|
|
Jan 10 01:58:51 PM PST 24 |
Jan 10 02:34:46 PM PST 24 |
10995039160 ps |
| T959 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1815381207 |
|
|
Jan 10 01:59:14 PM PST 24 |
Jan 10 02:04:42 PM PST 24 |
3290480304 ps |
| T697 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.65794958 |
|
|
Jan 10 02:05:27 PM PST 24 |
Jan 10 02:10:56 PM PST 24 |
3629302200 ps |
| T960 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2166740760 |
|
|
Jan 10 01:54:50 PM PST 24 |
Jan 10 02:14:40 PM PST 24 |
8910516358 ps |
| T961 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3835199054 |
|
|
Jan 10 01:56:50 PM PST 24 |
Jan 10 02:24:05 PM PST 24 |
13206396978 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.263950069 |
|
|
Jan 10 02:04:30 PM PST 24 |
Jan 10 02:30:32 PM PST 24 |
9165509510 ps |
| T963 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1466101056 |
|
|
Jan 10 01:59:55 PM PST 24 |
Jan 10 02:05:55 PM PST 24 |
5590247912 ps |
| T250 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.772024845 |
|
|
Jan 10 02:00:21 PM PST 24 |
Jan 10 02:11:07 PM PST 24 |
4889501164 ps |
| T196 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2199302690 |
|
|
Jan 10 02:02:57 PM PST 24 |
Jan 10 02:13:24 PM PST 24 |
4296067884 ps |
| T964 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2691495251 |
|
|
Jan 10 02:00:30 PM PST 24 |
Jan 10 02:23:59 PM PST 24 |
8850078047 ps |
| T965 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3783641644 |
|
|
Jan 10 02:04:40 PM PST 24 |
Jan 10 02:10:17 PM PST 24 |
2757255701 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_alert_test.1241723213 |
|
|
Jan 10 01:56:13 PM PST 24 |
Jan 10 02:01:07 PM PST 24 |
2276641972 ps |
| T703 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3839402028 |
|
|
Jan 10 02:03:23 PM PST 24 |
Jan 10 02:13:06 PM PST 24 |
6365628326 ps |
| T966 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2923538283 |
|
|
Jan 10 01:59:30 PM PST 24 |
Jan 10 02:05:29 PM PST 24 |
9677840421 ps |
| T761 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2726617107 |
|
|
Jan 10 02:03:06 PM PST 24 |
Jan 10 02:13:32 PM PST 24 |
4984006728 ps |
| T768 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1567276648 |
|
|
Jan 10 02:06:18 PM PST 24 |
Jan 10 02:16:06 PM PST 24 |
5991963224 ps |
| T251 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3130560233 |
|
|
Jan 10 02:05:25 PM PST 24 |
Jan 10 02:13:15 PM PST 24 |
4548262872 ps |
| T268 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.571867397 |
|
|
Jan 10 02:00:16 PM PST 24 |
Jan 10 02:22:47 PM PST 24 |
6810093708 ps |
| T269 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1642020418 |
|
|
Jan 10 01:55:15 PM PST 24 |
Jan 10 02:03:11 PM PST 24 |
5300496604 ps |
| T183 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3866312044 |
|
|
Jan 10 02:00:10 PM PST 24 |
Jan 10 02:24:10 PM PST 24 |
8150163016 ps |
| T270 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4163555562 |
|
|
Jan 10 02:03:03 PM PST 24 |
Jan 10 02:20:58 PM PST 24 |
8622837152 ps |
| T271 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2017504024 |
|
|
Jan 10 02:05:25 PM PST 24 |
Jan 10 02:11:20 PM PST 24 |
3801204940 ps |
| T272 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.1373196247 |
|
|
Jan 10 01:57:06 PM PST 24 |
Jan 10 02:01:05 PM PST 24 |
2867488480 ps |
| T273 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg.4258808010 |
|
|
Jan 10 02:04:21 PM PST 24 |
Jan 10 02:08:13 PM PST 24 |
2721930588 ps |
| T274 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2652793730 |
|
|
Jan 10 01:54:11 PM PST 24 |
Jan 10 02:10:42 PM PST 24 |
6243563760 ps |
| T275 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.3466784572 |
|
|
Jan 10 02:01:00 PM PST 24 |
Jan 10 02:10:56 PM PST 24 |
5552981752 ps |
| T745 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1441410952 |
|
|
Jan 10 02:06:14 PM PST 24 |
Jan 10 02:17:03 PM PST 24 |
5224430152 ps |
| T967 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.781849009 |
|
|
Jan 10 02:04:53 PM PST 24 |
Jan 10 02:14:30 PM PST 24 |
4367890072 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.1538571112 |
|
|
Jan 10 01:54:33 PM PST 24 |
Jan 10 02:03:48 PM PST 24 |
6197659120 ps |
| T969 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1392488017 |
|
|
Jan 10 01:58:41 PM PST 24 |
Jan 10 02:29:55 PM PST 24 |
8514537064 ps |
| T970 |
/workspace/coverage/default/0.chip_sw_example_flash.3255945433 |
|
|
Jan 10 01:54:48 PM PST 24 |
Jan 10 01:57:50 PM PST 24 |
2764211584 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.781579527 |
|
|
Jan 10 01:53:53 PM PST 24 |
Jan 10 01:59:02 PM PST 24 |
3555640600 ps |
| T696 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3271092405 |
|
|
Jan 10 01:54:55 PM PST 24 |
Jan 10 02:01:19 PM PST 24 |
3755932888 ps |
| T191 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1237625889 |
|
|
Jan 10 01:58:25 PM PST 24 |
Jan 10 02:11:50 PM PST 24 |
4541491560 ps |
| T972 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.460163747 |
|
|
Jan 10 01:56:54 PM PST 24 |
Jan 10 02:02:44 PM PST 24 |
3495538993 ps |
| T973 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3386822495 |
|
|
Jan 10 01:55:51 PM PST 24 |
Jan 10 02:03:57 PM PST 24 |
5567495550 ps |
| T974 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.3474618178 |
|
|
Jan 10 02:00:46 PM PST 24 |
Jan 10 02:04:20 PM PST 24 |
2811023214 ps |
| T740 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.532115149 |
|
|
Jan 10 02:01:23 PM PST 24 |
Jan 10 02:08:02 PM PST 24 |
3511731890 ps |
| T975 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1127872303 |
|
|
Jan 10 02:00:40 PM PST 24 |
Jan 10 02:42:44 PM PST 24 |
11562307118 ps |
| T976 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2746336452 |
|
|
Jan 10 02:05:51 PM PST 24 |
Jan 10 02:19:31 PM PST 24 |
6131224806 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.588486874 |
|
|
Jan 10 01:59:54 PM PST 24 |
Jan 10 05:02:23 PM PST 24 |
67185880102 ps |
| T202 |
/workspace/coverage/default/0.chip_sw_hmac_enc.427790192 |
|
|
Jan 10 01:53:57 PM PST 24 |
Jan 10 01:59:15 PM PST 24 |
2485941848 ps |
| T257 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2951528749 |
|
|
Jan 10 02:05:18 PM PST 24 |
Jan 10 02:11:17 PM PST 24 |
4256918680 ps |
| T978 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.848983716 |
|
|
Jan 10 01:59:12 PM PST 24 |
Jan 10 02:23:49 PM PST 24 |
8534631466 ps |
| T188 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.636934115 |
|
|
Jan 10 01:55:52 PM PST 24 |
Jan 10 02:09:43 PM PST 24 |
5660194284 ps |
| T362 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3129520481 |
|
|
Jan 10 02:04:53 PM PST 24 |
Jan 10 02:14:23 PM PST 24 |
5643867903 ps |
| T611 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3994902463 |
|
|
Jan 10 01:59:16 PM PST 24 |
Jan 10 02:07:02 PM PST 24 |
3080123888 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.658525505 |
|
|
Jan 10 02:05:26 PM PST 24 |
Jan 10 02:11:39 PM PST 24 |
3246753846 ps |
| T980 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3697255573 |
|
|
Jan 10 02:05:11 PM PST 24 |
Jan 10 02:15:18 PM PST 24 |
6171939504 ps |
| T245 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1179827962 |
|
|
Jan 10 01:53:57 PM PST 24 |
Jan 10 05:23:30 PM PST 24 |
254808958200 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1574245764 |
|
|
Jan 10 01:56:44 PM PST 24 |
Jan 10 02:30:50 PM PST 24 |
21096705564 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2528116820 |
|
|
Jan 10 01:53:56 PM PST 24 |
Jan 10 01:58:37 PM PST 24 |
2850925300 ps |
| T698 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.508057308 |
|
|
Jan 10 02:05:31 PM PST 24 |
Jan 10 02:11:41 PM PST 24 |
3666105440 ps |
| T674 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1725801346 |
|
|
Jan 10 01:56:41 PM PST 24 |
Jan 10 02:04:52 PM PST 24 |
3880976320 ps |
| T131 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.298863629 |
|
|
Jan 10 01:56:56 PM PST 24 |
Jan 10 02:07:52 PM PST 24 |
3775989668 ps |