| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.69 | 95.42 | 94.23 | 98.00 | 94.87 | 97.93 | 99.69 |
| T2754 | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1686671820 | Jan 10 01:44:00 PM PST 24 | Jan 10 01:45:43 PM PST 24 | 5934978956 ps | ||
| T2755 | /workspace/coverage/cover_reg_top/38.xbar_random.3848670660 | Jan 10 01:40:07 PM PST 24 | Jan 10 01:40:19 PM PST 24 | 98955668 ps | ||
| T2756 | /workspace/coverage/cover_reg_top/6.xbar_same_source.4092235957 | Jan 10 01:36:00 PM PST 24 | Jan 10 01:37:21 PM PST 24 | 2694716775 ps | ||
| T2757 | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1403943141 | Jan 10 01:43:34 PM PST 24 | Jan 10 01:46:37 PM PST 24 | 2675706313 ps | ||
| T2758 | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1596247778 | Jan 10 01:35:51 PM PST 24 | Jan 10 01:47:59 PM PST 24 | 13307486530 ps | ||
| T2759 | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3563327110 | Jan 10 01:43:45 PM PST 24 | Jan 10 01:43:55 PM PST 24 | 48407222 ps | ||
| T2760 | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.2794614504 | Jan 10 01:40:30 PM PST 24 | Jan 10 01:42:36 PM PST 24 | 8006394309 ps | ||
| T2761 | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1185199556 | Jan 10 01:42:42 PM PST 24 | Jan 10 01:44:01 PM PST 24 | 7331918440 ps | ||
| T2762 | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1477968148 | Jan 10 01:36:39 PM PST 24 | Jan 10 01:43:02 PM PST 24 | 9650989554 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1611051059 | Jan 10 01:37:32 PM PST 24 | Jan 10 01:38:15 PM PST 24 | 265120177 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/75.xbar_stress_all.3790378476 | Jan 10 01:43:57 PM PST 24 | Jan 10 01:47:07 PM PST 24 | 4849513944 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1937791427 | Jan 10 01:37:43 PM PST 24 | Jan 10 01:44:00 PM PST 24 | 2487660509 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1059962990 | Jan 10 01:41:25 PM PST 24 | Jan 10 01:42:25 PM PST 24 | 209651134 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.1058183387 | Jan 10 01:43:36 PM PST 24 | Jan 10 02:03:25 PM PST 24 | 67601954323 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.187894090 | Jan 10 01:45:07 PM PST 24 | Jan 10 01:46:16 PM PST 24 | 1600443107 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.641325059 | Jan 10 01:43:49 PM PST 24 | Jan 10 01:45:27 PM PST 24 | 5410494950 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1669393730 | Jan 10 01:41:00 PM PST 24 | Jan 10 01:41:13 PM PST 24 | 52263893 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/56.xbar_random.1638987075 | Jan 10 01:42:14 PM PST 24 | Jan 10 01:43:14 PM PST 24 | 1609837012 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2961344879 | Jan 10 01:38:22 PM PST 24 | Jan 10 01:39:51 PM PST 24 | 4919584324 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/25.xbar_stress_all.1876637481 | Jan 10 01:38:00 PM PST 24 | Jan 10 01:44:05 PM PST 24 | 10442699878 ps | ||
| T551 | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3357634431 | Jan 10 01:38:34 PM PST 24 | Jan 10 01:45:22 PM PST 24 | 7658998761 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.779857368 | Jan 10 01:40:22 PM PST 24 | Jan 10 01:40:59 PM PST 24 | 422982795 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/53.xbar_stress_all.3690386759 | Jan 10 01:42:25 PM PST 24 | Jan 10 01:45:57 PM PST 24 | 5712666324 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/43.xbar_stress_all.3341342327 | Jan 10 01:40:21 PM PST 24 | Jan 10 01:50:24 PM PST 24 | 15059834848 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.2922060718 | Jan 10 01:37:35 PM PST 24 | Jan 10 01:37:56 PM PST 24 | 264489128 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.712303015 | Jan 10 01:46:02 PM PST 24 | Jan 10 01:48:39 PM PST 24 | 1840328958 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3898406428 | Jan 10 01:35:58 PM PST 24 | Jan 10 01:43:15 PM PST 24 | 2725627130 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/96.xbar_random.2362212080 | Jan 10 01:45:57 PM PST 24 | Jan 10 01:46:32 PM PST 24 | 363348333 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1914469081 | Jan 10 01:38:05 PM PST 24 | Jan 10 01:38:16 PM PST 24 | 44909264 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.604153752 | Jan 10 01:43:47 PM PST 24 | Jan 10 01:58:37 PM PST 24 | 51843574516 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.929071168 | Jan 10 01:42:14 PM PST 24 | Jan 10 01:47:54 PM PST 24 | 5164165925 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1913566769 | Jan 10 01:38:35 PM PST 24 | Jan 10 01:38:44 PM PST 24 | 44914079 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2701369616 | Jan 10 01:45:51 PM PST 24 | Jan 10 01:50:09 PM PST 24 | 1891027044 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/32.xbar_same_source.2956429669 | Jan 10 01:38:56 PM PST 24 | Jan 10 01:39:16 PM PST 24 | 205705326 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.78137175 | Jan 10 01:45:03 PM PST 24 | Jan 10 01:45:47 PM PST 24 | 8605977 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/28.xbar_same_source.482311636 | Jan 10 01:38:06 PM PST 24 | Jan 10 01:38:34 PM PST 24 | 820822067 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2211095440 | Jan 10 01:43:04 PM PST 24 | Jan 10 01:45:35 PM PST 24 | 521259563 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.186067939 | Jan 10 01:37:56 PM PST 24 | Jan 10 01:39:29 PM PST 24 | 137253557 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3297906520 | Jan 10 01:41:28 PM PST 24 | Jan 10 01:42:59 PM PST 24 | 8331462799 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.807034116 | Jan 10 01:43:19 PM PST 24 | Jan 10 01:43:30 PM PST 24 | 184482102 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/64.xbar_smoke.4026703106 | Jan 10 01:43:07 PM PST 24 | Jan 10 01:43:16 PM PST 24 | 50654095 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.869349614 | Jan 10 01:42:12 PM PST 24 | Jan 10 01:43:01 PM PST 24 | 575437933 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/19.xbar_stress_all.1835584170 | Jan 10 01:37:33 PM PST 24 | Jan 10 01:41:44 PM PST 24 | 6844934487 ps | ||
| T550 | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.911590787 | Jan 10 01:45:56 PM PST 24 | Jan 10 01:52:01 PM PST 24 | 2378365242 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.81714299 | Jan 10 01:37:35 PM PST 24 | Jan 10 01:43:53 PM PST 24 | 4971092499 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1372448072 | Jan 10 01:40:29 PM PST 24 | Jan 10 01:40:48 PM PST 24 | 137031387 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/95.xbar_error_random.896289222 | Jan 10 01:45:54 PM PST 24 | Jan 10 01:47:18 PM PST 24 | 2315055538 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/16.xbar_error_random.2439024794 | Jan 10 01:37:46 PM PST 24 | Jan 10 01:38:32 PM PST 24 | 557570392 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1044241920 | Jan 10 01:42:33 PM PST 24 | Jan 10 01:43:47 PM PST 24 | 4261962856 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1406096975 | Jan 10 01:36:12 PM PST 24 | Jan 10 01:37:08 PM PST 24 | 741404792 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.547760264 | Jan 10 01:38:01 PM PST 24 | Jan 10 02:16:24 PM PST 24 | 131993871525 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2397281834 | Jan 10 01:36:23 PM PST 24 | Jan 10 01:48:55 PM PST 24 | 82868419355 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.1307688837 | Jan 10 01:42:17 PM PST 24 | Jan 10 01:42:35 PM PST 24 | 141598603 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2445704201 | Jan 10 01:36:38 PM PST 24 | Jan 10 01:37:18 PM PST 24 | 343479454 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/2.chip_tl_errors.2979593722 | Jan 10 01:35:54 PM PST 24 | Jan 10 01:41:52 PM PST 24 | 4994539655 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/38.xbar_smoke.2102110023 | Jan 10 01:40:07 PM PST 24 | Jan 10 01:40:15 PM PST 24 | 159706760 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/40.xbar_random.1255472795 | Jan 10 01:40:29 PM PST 24 | Jan 10 01:40:52 PM PST 24 | 446012747 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/87.xbar_same_source.3785986440 | Jan 10 01:45:09 PM PST 24 | Jan 10 01:45:45 PM PST 24 | 374848553 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.595457880 | Jan 10 01:43:51 PM PST 24 | Jan 10 01:45:11 PM PST 24 | 4909233785 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1004573314 | Jan 10 01:37:32 PM PST 24 | Jan 10 01:37:49 PM PST 24 | 48396348 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2008264864 | Jan 10 01:36:53 PM PST 24 | Jan 10 01:37:09 PM PST 24 | 343810950 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/21.chip_tl_errors.1833463490 | Jan 10 01:37:58 PM PST 24 | Jan 10 01:40:30 PM PST 24 | 2929888530 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3793898169 | Jan 10 01:45:18 PM PST 24 | Jan 10 01:46:37 PM PST 24 | 1586282522 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/68.xbar_error_random.3736014475 | Jan 10 01:43:24 PM PST 24 | Jan 10 01:44:09 PM PST 24 | 528294933 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2207988279 | Jan 10 01:37:53 PM PST 24 | Jan 10 01:42:08 PM PST 24 | 605566972 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.118249848 | Jan 10 01:45:11 PM PST 24 | Jan 10 01:45:52 PM PST 24 | 193359222 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3197720158 | Jan 10 01:38:55 PM PST 24 | Jan 10 01:39:23 PM PST 24 | 302994408 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/56.xbar_stress_all.1182104056 | Jan 10 01:42:26 PM PST 24 | Jan 10 01:49:53 PM PST 24 | 11957095721 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.4180483705 | Jan 10 01:45:07 PM PST 24 | Jan 10 02:13:41 PM PST 24 | 107348325575 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3857699698 | Jan 10 01:42:13 PM PST 24 | Jan 10 01:43:03 PM PST 24 | 2781243615 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3701111839 | Jan 10 01:36:09 PM PST 24 | Jan 10 01:37:08 PM PST 24 | 5149218448 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.4264437012 | Jan 10 01:37:56 PM PST 24 | Jan 10 01:38:15 PM PST 24 | 127865809 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1590578632 | Jan 10 01:35:55 PM PST 24 | Jan 10 01:37:48 PM PST 24 | 1752711367 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.770954455 | Jan 10 01:38:57 PM PST 24 | Jan 10 01:40:37 PM PST 24 | 5795393682 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.372474991 | Jan 10 01:35:56 PM PST 24 | Jan 10 01:55:24 PM PST 24 | 100505689210 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2305368311 | Jan 10 01:43:58 PM PST 24 | Jan 10 01:50:43 PM PST 24 | 22044792359 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.676470029 | Jan 10 01:42:43 PM PST 24 | Jan 10 01:51:22 PM PST 24 | 5942698142 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/13.xbar_stress_all.1719034538 | Jan 10 01:37:17 PM PST 24 | Jan 10 01:41:41 PM PST 24 | 6297095479 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1608702098 | Jan 10 01:43:51 PM PST 24 | Jan 10 01:45:16 PM PST 24 | 5335396127 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.336356586 | Jan 10 01:36:31 PM PST 24 | Jan 10 01:43:46 PM PST 24 | 13668073546 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/24.xbar_same_source.3465070072 | Jan 10 01:38:01 PM PST 24 | Jan 10 01:38:41 PM PST 24 | 509301137 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1717444039 | Jan 10 01:35:57 PM PST 24 | Jan 10 02:07:54 PM PST 24 | 105095232478 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2723600126 | Jan 10 01:40:05 PM PST 24 | Jan 10 01:50:34 PM PST 24 | 5838414199 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1467429522 | Jan 10 01:42:58 PM PST 24 | Jan 10 01:44:31 PM PST 24 | 9076213132 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2123052785 | Jan 10 01:38:57 PM PST 24 | Jan 10 01:39:08 PM PST 24 | 47005527 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/78.xbar_smoke.2462511016 | Jan 10 01:44:40 PM PST 24 | Jan 10 01:44:48 PM PST 24 | 39377661 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/79.xbar_random.903162405 | Jan 10 01:44:26 PM PST 24 | Jan 10 01:45:01 PM PST 24 | 388154648 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.666489091 | Jan 10 01:35:47 PM PST 24 | Jan 10 01:42:17 PM PST 24 | 34901365174 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3533176701 | Jan 10 01:40:26 PM PST 24 | Jan 10 01:40:36 PM PST 24 | 40231782 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.4038079139 | Jan 10 01:40:21 PM PST 24 | Jan 10 01:48:13 PM PST 24 | 4044801042 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2239766741 | Jan 10 01:43:40 PM PST 24 | Jan 10 01:44:54 PM PST 24 | 4222928653 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.2180014801 | Jan 10 01:46:01 PM PST 24 | Jan 10 01:46:25 PM PST 24 | 185377899 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/0.xbar_random.1835499059 | Jan 10 01:35:49 PM PST 24 | Jan 10 01:36:20 PM PST 24 | 183112444 ps | ||
| T670 | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.813987592 | Jan 10 01:35:59 PM PST 24 | Jan 10 01:42:03 PM PST 24 | 5575219601 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.3107103656 | Jan 10 01:45:06 PM PST 24 | Jan 10 01:45:38 PM PST 24 | 256932347 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.322533761 | Jan 10 01:43:28 PM PST 24 | Jan 10 01:44:35 PM PST 24 | 1542499465 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.1428581596 | Jan 10 01:42:45 PM PST 24 | Jan 10 01:44:09 PM PST 24 | 2190184890 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/98.xbar_random.3126819407 | Jan 10 01:46:08 PM PST 24 | Jan 10 01:46:47 PM PST 24 | 156095755 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.4285386125 | Jan 10 01:42:42 PM PST 24 | Jan 10 02:05:56 PM PST 24 | 86994007561 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.737279437 | Jan 10 01:40:06 PM PST 24 | Jan 10 02:06:45 PM PST 24 | 87881283369 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1974157715 | Jan 10 01:35:42 PM PST 24 | Jan 10 01:40:29 PM PST 24 | 5942274665 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/90.xbar_random.2506725039 | Jan 10 01:45:18 PM PST 24 | Jan 10 01:45:50 PM PST 24 | 126129743 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1971091759 | Jan 10 01:41:06 PM PST 24 | Jan 10 01:41:44 PM PST 24 | 481909627 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.3500489413 | Jan 10 01:40:22 PM PST 24 | Jan 10 01:40:57 PM PST 24 | 367773178 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3676664274 | Jan 10 01:43:25 PM PST 24 | Jan 10 01:43:49 PM PST 24 | 129374038 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2210864267 | Jan 10 01:43:34 PM PST 24 | Jan 10 01:43:41 PM PST 24 | 47744996 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3913108826 | Jan 10 01:43:46 PM PST 24 | Jan 10 01:44:17 PM PST 24 | 716965390 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3273085464 | Jan 10 01:38:54 PM PST 24 | Jan 10 01:39:33 PM PST 24 | 149802035 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/30.xbar_smoke.3753765704 | Jan 10 01:38:23 PM PST 24 | Jan 10 01:38:39 PM PST 24 | 192361400 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2684992821 | Jan 10 01:43:01 PM PST 24 | Jan 10 01:44:11 PM PST 24 | 1899580205 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1370677078 | Jan 10 01:42:25 PM PST 24 | Jan 10 01:42:33 PM PST 24 | 47365505 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2793068483 | Jan 10 01:45:57 PM PST 24 | Jan 10 01:47:12 PM PST 24 | 6940777970 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/11.xbar_smoke.785746531 | Jan 10 01:36:42 PM PST 24 | Jan 10 01:36:51 PM PST 24 | 44115832 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/21.xbar_smoke.2627929453 | Jan 10 01:38:03 PM PST 24 | Jan 10 01:38:14 PM PST 24 | 56180933 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.904719099 | Jan 10 01:45:08 PM PST 24 | Jan 10 01:46:10 PM PST 24 | 1000302236 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/93.xbar_same_source.158182324 | Jan 10 01:46:00 PM PST 24 | Jan 10 01:46:37 PM PST 24 | 467700755 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.1399515490 | Jan 10 01:45:04 PM PST 24 | Jan 10 02:04:32 PM PST 24 | 69189689495 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3272779160 | Jan 10 01:40:32 PM PST 24 | Jan 10 01:44:51 PM PST 24 | 5144059832 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4002652412 | Jan 10 01:36:39 PM PST 24 | Jan 10 01:39:09 PM PST 24 | 2291811232 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.577744608 | Jan 10 01:45:04 PM PST 24 | Jan 10 01:49:06 PM PST 24 | 692891319 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.17052828 | Jan 10 01:37:53 PM PST 24 | Jan 10 01:38:59 PM PST 24 | 876812272 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3207197481 | Jan 10 01:40:25 PM PST 24 | Jan 10 01:41:56 PM PST 24 | 1765084638 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2001640419 | Jan 10 01:38:28 PM PST 24 | Jan 10 01:39:52 PM PST 24 | 7752190220 ps |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3041088092 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 31316839837 ps |
| CPU time | 3557.25 seconds |
| Started | Jan 10 01:37:51 PM PST 24 |
| Finished | Jan 10 02:37:13 PM PST 24 |
| Peak memory | 580872 kb |
| Host | smart-872714c3-8681-4e6f-a2f7-ac995247c20a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041088092 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.3041088092 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.313755197 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 8974518772 ps |
| CPU time | 351.96 seconds |
| Started | Jan 10 01:43:23 PM PST 24 |
| Finished | Jan 10 01:49:20 PM PST 24 |
| Peak memory | 555964 kb |
| Host | smart-5f6824cd-8fe1-40a9-8ed0-833bae3595ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313755197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.313755197 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2349278514 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4928339499 ps |
| CPU time | 334.11 seconds |
| Started | Jan 10 01:46:41 PM PST 24 |
| Finished | Jan 10 01:52:21 PM PST 24 |
| Peak memory | 634132 kb |
| Host | smart-34832221-41ab-4eb1-a62e-5bbac698c93b |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349278514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.2349278514 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1504405151 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 145506120822 ps |
| CPU time | 2476.39 seconds |
| Started | Jan 10 01:40:28 PM PST 24 |
| Finished | Jan 10 02:21:49 PM PST 24 |
| Peak memory | 555892 kb |
| Host | smart-dc17eb2a-2b08-4eeb-8677-0292cf90770f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504405151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.1504405151 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.472587330 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 10226092786 ps |
| CPU time | 847.5 seconds |
| Started | Jan 10 01:54:00 PM PST 24 |
| Finished | Jan 10 02:08:10 PM PST 24 |
| Peak memory | 608788 kb |
| Host | smart-49c086bc-c1e0-4c5e-bb01-909cf2c5a337 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=472587330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.472587330 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3088833263 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 152752019737 ps |
| CPU time | 2636 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 02:29:21 PM PST 24 |
| Peak memory | 555980 kb |
| Host | smart-3bafebfd-00bf-440c-a928-80d92a828af8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088833263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.3088833263 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1115202742 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 77107775349 ps |
| CPU time | 1274.79 seconds |
| Started | Jan 10 01:38:04 PM PST 24 |
| Finished | Jan 10 01:59:24 PM PST 24 |
| Peak memory | 555836 kb |
| Host | smart-80f2e904-d24a-4aa5-a3c9-7303182bf7b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115202742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.1115202742 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.2783273539 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 5455719568 ps |
| CPU time | 954.78 seconds |
| Started | Jan 10 01:59:30 PM PST 24 |
| Finished | Jan 10 02:15:26 PM PST 24 |
| Peak memory | 602916 kb |
| Host | smart-19dd9593-f1ca-4083-a77c-d34872714f2b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783273539 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.2783273539 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3603962019 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 126800007230 ps |
| CPU time | 2206.41 seconds |
| Started | Jan 10 01:43:11 PM PST 24 |
| Finished | Jan 10 02:19:59 PM PST 24 |
| Peak memory | 556128 kb |
| Host | smart-e7690d49-03dd-4fed-81ac-60ea4c21d8a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603962019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.3603962019 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.191607960 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 16698169945 ps |
| CPU time | 675.06 seconds |
| Started | Jan 10 01:44:29 PM PST 24 |
| Finished | Jan 10 01:55:47 PM PST 24 |
| Peak memory | 556328 kb |
| Host | smart-ad1109c2-6474-48b9-bbbf-0f0c37e07fd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191607960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.191607960 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1918312888 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 3350148796 ps |
| CPU time | 310.49 seconds |
| Started | Jan 10 01:56:35 PM PST 24 |
| Finished | Jan 10 02:01:58 PM PST 24 |
| Peak memory | 602380 kb |
| Host | smart-71650cb0-7671-48fe-a0be-74ad6a5ab7d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1918312888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1918312888 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1824243094 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3244659608 ps |
| CPU time | 273.46 seconds |
| Started | Jan 10 01:55:05 PM PST 24 |
| Finished | Jan 10 01:59:43 PM PST 24 |
| Peak memory | 603140 kb |
| Host | smart-7bb54c86-2239-4d8a-b9b1-6f4db894d04d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824 243094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1824243094 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.2090176630 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2659685306 ps |
| CPU time | 192.86 seconds |
| Started | Jan 10 01:36:00 PM PST 24 |
| Finished | Jan 10 01:39:24 PM PST 24 |
| Peak memory | 555836 kb |
| Host | smart-9e9610a3-e7e3-4f8b-83d7-f0d73afd8a82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090176630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2090176630 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.120526008 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3952230302 ps |
| CPU time | 507.53 seconds |
| Started | Jan 10 01:54:53 PM PST 24 |
| Finished | Jan 10 02:03:31 PM PST 24 |
| Peak memory | 603016 kb |
| Host | smart-9bd3ed32-7938-4536-87a4-d8fd32ce631f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12 0526008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.120526008 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.3992191382 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 4047924266 ps |
| CPU time | 749.01 seconds |
| Started | Jan 10 01:56:11 PM PST 24 |
| Finished | Jan 10 02:08:42 PM PST 24 |
| Peak memory | 602132 kb |
| Host | smart-fa6022fa-6613-4cda-bdc7-9495d4c9db89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992191382 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.3992191382 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3260394301 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 6260865064 ps |
| CPU time | 538.09 seconds |
| Started | Jan 10 02:00:23 PM PST 24 |
| Finished | Jan 10 02:09:23 PM PST 24 |
| Peak memory | 603252 kb |
| Host | smart-91ce1a4e-1dcf-4bcc-8d69-86f45d8f18e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32603943 01 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3260394301 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.261177697 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4304235408 ps |
| CPU time | 291.42 seconds |
| Started | Jan 10 01:36:47 PM PST 24 |
| Finished | Jan 10 01:41:40 PM PST 24 |
| Peak memory | 580876 kb |
| Host | smart-99873cf3-9067-44ff-a175-6c1c1672cc5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261177697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.261177697 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.236873925 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4778229812 ps |
| CPU time | 767.8 seconds |
| Started | Jan 10 01:56:53 PM PST 24 |
| Finished | Jan 10 02:09:42 PM PST 24 |
| Peak memory | 603188 kb |
| Host | smart-d5aa995d-d1f9-4a9a-9c84-847ffd54c533 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=236873925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.236873925 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.2963413049 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 4374325164 ps |
| CPU time | 485.43 seconds |
| Started | Jan 10 01:59:00 PM PST 24 |
| Finished | Jan 10 02:07:07 PM PST 24 |
| Peak memory | 602908 kb |
| Host | smart-90053370-668c-43d3-a0b9-fadb06332e38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963413049 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.2963413049 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3416886256 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 135080853258 ps |
| CPU time | 2322.97 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 02:17:41 PM PST 24 |
| Peak memory | 556236 kb |
| Host | smart-b557bdf8-9ca2-4d77-9381-39bfac41bcff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416886256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.3416886256 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.4219212512 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 23631520605 ps |
| CPU time | 394.7 seconds |
| Started | Jan 10 01:43:36 PM PST 24 |
| Finished | Jan 10 01:50:13 PM PST 24 |
| Peak memory | 555112 kb |
| Host | smart-a73b5e9f-6420-4818-8b03-c379e83c0c6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219212512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.4219212512 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.3788736566 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 21624500696 ps |
| CPU time | 2464.97 seconds |
| Started | Jan 10 01:47:21 PM PST 24 |
| Finished | Jan 10 02:28:28 PM PST 24 |
| Peak memory | 587840 kb |
| Host | smart-853b20b3-43e2-4fd9-a881-54f4250852b7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788736566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.3788736566 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.658420738 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3867777112 ps |
| CPU time | 282.19 seconds |
| Started | Jan 10 01:57:06 PM PST 24 |
| Finished | Jan 10 02:01:51 PM PST 24 |
| Peak memory | 602488 kb |
| Host | smart-137cf12c-2951-458f-b8b0-7b0213bef011 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658420738 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.658420738 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3383631814 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 30370297412 ps |
| CPU time | 3985.74 seconds |
| Started | Jan 10 01:36:44 PM PST 24 |
| Finished | Jan 10 02:43:12 PM PST 24 |
| Peak memory | 580740 kb |
| Host | smart-123c231d-e588-4c1d-ba02-5529465d4212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383631814 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3383631814 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3247505940 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 5299108892 ps |
| CPU time | 426.1 seconds |
| Started | Jan 10 01:56:31 PM PST 24 |
| Finished | Jan 10 02:03:39 PM PST 24 |
| Peak memory | 602256 kb |
| Host | smart-5423fd7b-04fc-4032-875a-6185570cd93a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32475059 40 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3247505940 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.33556498 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7027624706 ps |
| CPU time | 707.26 seconds |
| Started | Jan 10 02:04:10 PM PST 24 |
| Finished | Jan 10 02:16:00 PM PST 24 |
| Peak memory | 609740 kb |
| Host | smart-ebf7b2a2-6b24-4441-95c5-c43ac220ec91 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=33556498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.33556498 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1400116828 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 47330304458 ps |
| CPU time | 514.13 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:51:25 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-7c7a1bfb-e39d-4c3c-9392-d6c20ed964e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400116828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1400116828 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3015740146 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5959101160 ps |
| CPU time | 540.22 seconds |
| Started | Jan 10 02:00:30 PM PST 24 |
| Finished | Jan 10 02:09:33 PM PST 24 |
| Peak memory | 603820 kb |
| Host | smart-ba6c6702-196c-4a2d-a0a2-56db9caf2f55 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3015740146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3015740146 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2629365821 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 162795894705 ps |
| CPU time | 2834.96 seconds |
| Started | Jan 10 01:45:02 PM PST 24 |
| Finished | Jan 10 02:32:37 PM PST 24 |
| Peak memory | 556284 kb |
| Host | smart-e79ec89f-a210-4740-ab8f-2bcafa7e0362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629365821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.2629365821 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3865455392 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 11870415816 ps |
| CPU time | 1156.7 seconds |
| Started | Jan 10 01:54:43 PM PST 24 |
| Finished | Jan 10 02:14:01 PM PST 24 |
| Peak memory | 603604 kb |
| Host | smart-cde57028-7dd5-442d-8e60-173f962364dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865455392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.3865455392 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.3223094929 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4036202260 ps |
| CPU time | 499.08 seconds |
| Started | Jan 10 02:07:29 PM PST 24 |
| Finished | Jan 10 02:16:02 PM PST 24 |
| Peak memory | 608664 kb |
| Host | smart-3ca6545b-5606-4eba-9711-0195e32b391b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3223094929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3223094929 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.230442759 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 4284615857 ps |
| CPU time | 371.59 seconds |
| Started | Jan 10 01:37:44 PM PST 24 |
| Finished | Jan 10 01:44:00 PM PST 24 |
| Peak memory | 580820 kb |
| Host | smart-674e2aea-b682-42c1-ac9a-7d48b5d62cbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230442759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.230442759 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1060084682 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 8595644992 ps |
| CPU time | 401.53 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:43:21 PM PST 24 |
| Peak memory | 559608 kb |
| Host | smart-18e6631a-3592-433b-84bd-2c77ae211660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060084682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.1060084682 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.559643965 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2472875527 ps |
| CPU time | 218.23 seconds |
| Started | Jan 10 01:57:19 PM PST 24 |
| Finished | Jan 10 02:00:58 PM PST 24 |
| Peak memory | 602800 kb |
| Host | smart-788906f3-8fc9-4d08-95bb-a29820ba2b2f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5596 43965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.559643965 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1857507718 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 7471481744 ps |
| CPU time | 702.7 seconds |
| Started | Jan 10 01:55:11 PM PST 24 |
| Finished | Jan 10 02:06:54 PM PST 24 |
| Peak memory | 603748 kb |
| Host | smart-03313f4a-91ab-4962-ac91-682a06f93b1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857507718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.1857507718 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1348139901 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4489035120 ps |
| CPU time | 307.2 seconds |
| Started | Jan 10 01:55:37 PM PST 24 |
| Finished | Jan 10 02:00:45 PM PST 24 |
| Peak memory | 603132 kb |
| Host | smart-ffb1f66b-c1c6-4b38-ae41-dba631c0076f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348139901 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.1348139901 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3994685001 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 24238010924 ps |
| CPU time | 1580.75 seconds |
| Started | Jan 10 01:56:24 PM PST 24 |
| Finished | Jan 10 02:22:46 PM PST 24 |
| Peak memory | 603708 kb |
| Host | smart-0bd511d1-80a1-43e3-b69a-754a7b54c17f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3994685001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3994685001 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.1859867802 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 16159610372 ps |
| CPU time | 1518.39 seconds |
| Started | Jan 10 01:56:05 PM PST 24 |
| Finished | Jan 10 02:21:24 PM PST 24 |
| Peak memory | 608792 kb |
| Host | smart-816df9e6-7cb6-44ba-a00e-eac6f989a024 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1859867802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.1859867802 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3882474806 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4133871952 ps |
| CPU time | 392.47 seconds |
| Started | Jan 10 01:58:00 PM PST 24 |
| Finished | Jan 10 02:04:47 PM PST 24 |
| Peak memory | 610512 kb |
| Host | smart-69d42d11-49cb-4391-bb97-f4b6b50e25e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3882474806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3882474806 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.662194498 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2991131807 ps |
| CPU time | 252.12 seconds |
| Started | Jan 10 02:00:11 PM PST 24 |
| Finished | Jan 10 02:04:30 PM PST 24 |
| Peak memory | 602532 kb |
| Host | smart-e9f9b224-efdb-433f-8828-47e4d54eee76 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6621 94498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.662194498 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.4178509702 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 8642992375 ps |
| CPU time | 1142.67 seconds |
| Started | Jan 10 01:59:29 PM PST 24 |
| Finished | Jan 10 02:18:33 PM PST 24 |
| Peak memory | 602584 kb |
| Host | smart-9e6a50a9-f768-489f-a77f-f624eb80f12e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178509702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _csrng_edn_concurrency_reduced_freq.4178509702 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.3865660949 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 4160976388 ps |
| CPU time | 289.08 seconds |
| Started | Jan 10 01:38:24 PM PST 24 |
| Finished | Jan 10 01:43:21 PM PST 24 |
| Peak memory | 580728 kb |
| Host | smart-fbb70803-ce89-4424-a00c-fe6ed0e42c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865660949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.3865660949 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2744235679 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 7850503166 ps |
| CPU time | 1105.96 seconds |
| Started | Jan 10 01:56:57 PM PST 24 |
| Finished | Jan 10 02:15:24 PM PST 24 |
| Peak memory | 591280 kb |
| Host | smart-096cd8b8-b8c8-4df5-aa20-f28aee311b91 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744235679 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.2744235679 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.3848664148 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5496225036 ps |
| CPU time | 515.13 seconds |
| Started | Jan 10 02:04:25 PM PST 24 |
| Finished | Jan 10 02:13:04 PM PST 24 |
| Peak memory | 630344 kb |
| Host | smart-cdd7bf3b-ddaf-4341-bfd8-517fe052bddd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3848664148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.3848664148 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3488052792 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3206794644 ps |
| CPU time | 372.96 seconds |
| Started | Jan 10 02:06:43 PM PST 24 |
| Finished | Jan 10 02:12:59 PM PST 24 |
| Peak memory | 633308 kb |
| Host | smart-3fcd0866-d1d1-4d29-9d4f-869ae360abcb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488052792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3488052792 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.103873213 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 5248628320 ps |
| CPU time | 571.35 seconds |
| Started | Jan 10 02:06:48 PM PST 24 |
| Finished | Jan 10 02:16:24 PM PST 24 |
| Peak memory | 635328 kb |
| Host | smart-6302b3f5-6b80-4950-8e74-eb67e36e2d98 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 103873213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.103873213 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.138825366 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 5097925588 ps |
| CPU time | 551.72 seconds |
| Started | Jan 10 02:01:38 PM PST 24 |
| Finished | Jan 10 02:10:52 PM PST 24 |
| Peak memory | 634980 kb |
| Host | smart-fc5c3274-d559-4bf6-960d-0bd3a0c7b15a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 138825366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.138825366 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.4009096611 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 5857182592 ps |
| CPU time | 544.29 seconds |
| Started | Jan 10 02:05:10 PM PST 24 |
| Finished | Jan 10 02:14:16 PM PST 24 |
| Peak memory | 634724 kb |
| Host | smart-41900039-2f37-4bc6-b4be-5981dd146be6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4009096611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.4009096611 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.320893614 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3480549061 ps |
| CPU time | 395.65 seconds |
| Started | Jan 10 01:53:50 PM PST 24 |
| Finished | Jan 10 02:00:27 PM PST 24 |
| Peak memory | 602780 kb |
| Host | smart-8c6101c3-4b5a-4051-b03f-164f7bfc4878 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320893614 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_gpio.320893614 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1714340717 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5338579789 ps |
| CPU time | 266.96 seconds |
| Started | Jan 10 01:47:08 PM PST 24 |
| Finished | Jan 10 01:51:37 PM PST 24 |
| Peak memory | 634256 kb |
| Host | smart-9e138dba-4819-4ab9-b4b6-e1333e5a22cf |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714340717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.1714340717 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2584177 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5450678602 ps |
| CPU time | 888.69 seconds |
| Started | Jan 10 02:05:58 PM PST 24 |
| Finished | Jan 10 02:20:51 PM PST 24 |
| Peak memory | 603876 kb |
| Host | smart-cf2d889a-6299-4f88-a405-2c523fabfc88 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2584177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2584177 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3209214035 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3155807561 ps |
| CPU time | 135.57 seconds |
| Started | Jan 10 01:53:40 PM PST 24 |
| Finished | Jan 10 01:55:57 PM PST 24 |
| Peak memory | 603360 kb |
| Host | smart-a68b0fd4-dedf-48a9-9c01-05cbbe99e18b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209214035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.3209214035 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3449654245 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 23478982108 ps |
| CPU time | 1167.42 seconds |
| Started | Jan 10 01:37:31 PM PST 24 |
| Finished | Jan 10 01:57:10 PM PST 24 |
| Peak memory | 568104 kb |
| Host | smart-1d106681-fdac-4d12-a2b1-71229aa2b6e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449654245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.3449654245 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.4218699364 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 6089327750 ps |
| CPU time | 1060.73 seconds |
| Started | Jan 10 01:56:48 PM PST 24 |
| Finished | Jan 10 02:14:34 PM PST 24 |
| Peak memory | 602808 kb |
| Host | smart-79b0a866-9ecf-4a9a-a49e-b25d509cc849 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218699364 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.4218699364 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2377362077 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2818411980 ps |
| CPU time | 305.29 seconds |
| Started | Jan 10 02:00:18 PM PST 24 |
| Finished | Jan 10 02:05:26 PM PST 24 |
| Peak memory | 602832 kb |
| Host | smart-6db9b9e8-b963-4763-b262-1d8b7f81f071 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377362077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.2377362077 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.1960557793 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4936295861 ps |
| CPU time | 360.31 seconds |
| Started | Jan 10 01:55:43 PM PST 24 |
| Finished | Jan 10 02:01:45 PM PST 24 |
| Peak memory | 614304 kb |
| Host | smart-c4e0d244-e953-4991-8647-6056bf8be1e9 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960557793 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.1960557793 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.513524587 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 4480953472 ps |
| CPU time | 352.65 seconds |
| Started | Jan 10 01:37:45 PM PST 24 |
| Finished | Jan 10 01:43:42 PM PST 24 |
| Peak memory | 580828 kb |
| Host | smart-6390c18e-1a39-47cf-a453-e46962e5ef3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513524587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.513524587 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.902595147 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 46778696310 ps |
| CPU time | 5006.13 seconds |
| Started | Jan 10 01:56:03 PM PST 24 |
| Finished | Jan 10 03:19:31 PM PST 24 |
| Peak memory | 609092 kb |
| Host | smart-01126501-e746-4794-a094-4d6b69ccf5bc |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902595147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.902595147 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3733385793 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2885659331 ps |
| CPU time | 405.65 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:44:30 PM PST 24 |
| Peak memory | 560056 kb |
| Host | smart-2a94e579-0ed9-4a76-a02d-e7517f398d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733385793 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3733385793 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.560722315 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 72284061160 ps |
| CPU time | 11714.6 seconds |
| Started | Jan 10 01:58:00 PM PST 24 |
| Finished | Jan 10 05:13:30 PM PST 24 |
| Peak memory | 611892 kb |
| Host | smart-60d0bdb5-3265-4fef-9110-738216d4604c |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=560722315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.560722315 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3815398942 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 5600136397 ps |
| CPU time | 364.78 seconds |
| Started | Jan 10 01:35:44 PM PST 24 |
| Finished | Jan 10 01:42:07 PM PST 24 |
| Peak memory | 639992 kb |
| Host | smart-e62c2e58-3265-4f0c-ba0a-123e2288d4b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815398942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.3815398942 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2934687152 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 6293306760 ps |
| CPU time | 796.82 seconds |
| Started | Jan 10 01:55:35 PM PST 24 |
| Finished | Jan 10 02:08:52 PM PST 24 |
| Peak memory | 603316 kb |
| Host | smart-64451685-e95a-44ea-869a-7b6c6fa997d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29346871 52 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2934687152 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.835542947 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 13771572432 ps |
| CPU time | 1426.62 seconds |
| Started | Jan 10 01:58:05 PM PST 24 |
| Finished | Jan 10 02:22:01 PM PST 24 |
| Peak memory | 603772 kb |
| Host | smart-69153a7e-6825-44ff-a895-4437ce685bbd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=835542947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.835542947 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2193033683 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 11247332135 ps |
| CPU time | 744.57 seconds |
| Started | Jan 10 01:58:45 PM PST 24 |
| Finished | Jan 10 02:11:19 PM PST 24 |
| Peak memory | 603496 kb |
| Host | smart-c616d09a-bf7e-4456-8068-50cb717f4408 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193033683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.2193033683 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1371968673 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 4547473427 ps |
| CPU time | 275.98 seconds |
| Started | Jan 10 01:38:18 PM PST 24 |
| Finished | Jan 10 01:42:58 PM PST 24 |
| Peak memory | 558584 kb |
| Host | smart-daa36ca0-5220-48e3-b112-865740c0d20f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371968673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.1371968673 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.1479867508 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 4482129355 ps |
| CPU time | 300.71 seconds |
| Started | Jan 10 01:37:53 PM PST 24 |
| Finished | Jan 10 01:42:58 PM PST 24 |
| Peak memory | 580852 kb |
| Host | smart-aec5d94c-f2d2-4b0e-a3cd-d7eeaab9bbe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479867508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1479867508 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.449086468 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 3856739144 ps |
| CPU time | 575.86 seconds |
| Started | Jan 10 02:00:05 PM PST 24 |
| Finished | Jan 10 02:09:49 PM PST 24 |
| Peak memory | 602428 kb |
| Host | smart-62c848c7-3d6d-41fa-940e-45b6b6ecae03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449086468 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_20.449086468 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2880239488 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5132126092 ps |
| CPU time | 448.02 seconds |
| Started | Jan 10 01:56:43 PM PST 24 |
| Finished | Jan 10 02:04:16 PM PST 24 |
| Peak memory | 603600 kb |
| Host | smart-68f936f6-c371-4db7-8555-e5d95d2aa579 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880239488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.2880239488 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.2702948143 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5554449640 ps |
| CPU time | 1057.98 seconds |
| Started | Jan 10 01:54:33 PM PST 24 |
| Finished | Jan 10 02:12:12 PM PST 24 |
| Peak memory | 602816 kb |
| Host | smart-f5e6d52b-bd37-4a1e-a6ca-f4416420411a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702948143 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.2702948143 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3771312198 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 31637878200 ps |
| CPU time | 6243.82 seconds |
| Started | Jan 10 01:57:07 PM PST 24 |
| Finished | Jan 10 03:41:13 PM PST 24 |
| Peak memory | 602496 kb |
| Host | smart-537c1228-1c3a-455a-8e80-053f120292af |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3771312198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.3771312198 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.297618714 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 12190990251 ps |
| CPU time | 2297.72 seconds |
| Started | Jan 10 01:59:25 PM PST 24 |
| Finished | Jan 10 02:37:45 PM PST 24 |
| Peak memory | 590544 kb |
| Host | smart-9ac20ab9-d7a9-4811-bf38-483e2560cb76 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_dev_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_dev_key_0:new_rules,otp_img_sigve rify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297618714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_alw ays_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_si gverify_always_a_bad_b_bad_dev.297618714 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.2420659670 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 7151336314 ps |
| CPU time | 627.39 seconds |
| Started | Jan 10 01:54:15 PM PST 24 |
| Finished | Jan 10 02:04:43 PM PST 24 |
| Peak memory | 618276 kb |
| Host | smart-c1908d67-022e-4cc3-a711-5b4e686436d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420659670 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.2420659670 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3582238435 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3441787798 ps |
| CPU time | 352.81 seconds |
| Started | Jan 10 01:38:12 PM PST 24 |
| Finished | Jan 10 01:44:10 PM PST 24 |
| Peak memory | 558528 kb |
| Host | smart-16986a00-7f97-400a-9af1-bce03b4165e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582238435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.3582238435 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.481708061 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 6380941155 ps |
| CPU time | 936.12 seconds |
| Started | Jan 10 01:56:41 PM PST 24 |
| Finished | Jan 10 02:12:24 PM PST 24 |
| Peak memory | 602876 kb |
| Host | smart-df10f304-90d8-4086-92be-d912ce2ccc37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=481708061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.481708061 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.444322223 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12345088871 ps |
| CPU time | 469.8 seconds |
| Started | Jan 10 01:36:45 PM PST 24 |
| Finished | Jan 10 01:44:36 PM PST 24 |
| Peak memory | 556232 kb |
| Host | smart-6ed0bf6f-1c74-46ad-8e7f-ac603bf1a5c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444322223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.444322223 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.1908921488 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 875321871 ps |
| CPU time | 249.58 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:44:39 PM PST 24 |
| Peak memory | 559904 kb |
| Host | smart-abb896dc-aa0a-4563-b6cf-15e8a5e8b453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908921488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.1908921488 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1236353597 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2353558141 ps |
| CPU time | 95.47 seconds |
| Started | Jan 10 02:03:11 PM PST 24 |
| Finished | Jan 10 02:05:15 PM PST 24 |
| Peak memory | 599000 kb |
| Host | smart-3a060c3e-0c9a-41af-a5fa-5e5f9eed20a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236353597 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1236353597 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.298863629 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3775989668 ps |
| CPU time | 654.63 seconds |
| Started | Jan 10 01:56:56 PM PST 24 |
| Finished | Jan 10 02:07:52 PM PST 24 |
| Peak memory | 590388 kb |
| Host | smart-88c71055-d197-4875-a2fe-4e2503a47430 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298863629 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.298863629 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2127371464 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5006293830 ps |
| CPU time | 701.73 seconds |
| Started | Jan 10 02:01:37 PM PST 24 |
| Finished | Jan 10 02:13:21 PM PST 24 |
| Peak memory | 599128 kb |
| Host | smart-693cd899-a3ce-4384-ba7c-db1fc86f388b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2127371464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2127371464 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2164231485 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7258412310 ps |
| CPU time | 367.22 seconds |
| Started | Jan 10 01:36:22 PM PST 24 |
| Finished | Jan 10 01:42:35 PM PST 24 |
| Peak memory | 615380 kb |
| Host | smart-888fa49e-9624-4a40-9239-dc4a0eceee96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164231485 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.2164231485 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2167133312 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 11423885745 ps |
| CPU time | 599.1 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:46:09 PM PST 24 |
| Peak memory | 558560 kb |
| Host | smart-6c4d54a9-c5db-4d71-afb5-e82e37fa8196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167133312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.2167133312 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1284889271 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2844060544 ps |
| CPU time | 260.09 seconds |
| Started | Jan 10 01:53:53 PM PST 24 |
| Finished | Jan 10 01:58:15 PM PST 24 |
| Peak memory | 602568 kb |
| Host | smart-9eb52d6d-d668-4dd5-965a-5b99a7a5a7a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284889271 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1284889271 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.223956681 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 18941352997 ps |
| CPU time | 2070.71 seconds |
| Started | Jan 10 01:54:18 PM PST 24 |
| Finished | Jan 10 02:28:50 PM PST 24 |
| Peak memory | 603948 kb |
| Host | smart-ce601b86-2a5d-4674-8278-1c614b7a4e0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=223956681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.223956681 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1176272106 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4104332438 ps |
| CPU time | 505.93 seconds |
| Started | Jan 10 01:53:49 PM PST 24 |
| Finished | Jan 10 02:02:17 PM PST 24 |
| Peak memory | 595404 kb |
| Host | smart-1d7532c6-7c7e-43b0-9253-107d340aa771 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176272106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1176272106 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.315096468 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 23664147220 ps |
| CPU time | 1708.37 seconds |
| Started | Jan 10 01:55:33 PM PST 24 |
| Finished | Jan 10 02:24:04 PM PST 24 |
| Peak memory | 603360 kb |
| Host | smart-dce6de53-7bc7-4912-9036-a5922152eba4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=315096468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.315096468 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.3569420132 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3713957404 ps |
| CPU time | 272.99 seconds |
| Started | Jan 10 01:37:34 PM PST 24 |
| Finished | Jan 10 01:42:17 PM PST 24 |
| Peak memory | 580076 kb |
| Host | smart-a15db325-6633-4bf3-8855-ce45f8ff03f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569420132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3569420132 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.1241723213 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2276641972 ps |
| CPU time | 292.16 seconds |
| Started | Jan 10 01:56:13 PM PST 24 |
| Finished | Jan 10 02:01:07 PM PST 24 |
| Peak memory | 602748 kb |
| Host | smart-f6f84b36-af24-49f6-880e-c5335ab26cdc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241723213 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.1241723213 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1117324120 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2415920948 ps |
| CPU time | 229.17 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:41:34 PM PST 24 |
| Peak memory | 558908 kb |
| Host | smart-c41ea0ff-7f1a-4029-8b63-a70b1a09c7d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117324120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.1117324120 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3837064032 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 528969638 ps |
| CPU time | 211.36 seconds |
| Started | Jan 10 01:38:25 PM PST 24 |
| Finished | Jan 10 01:42:03 PM PST 24 |
| Peak memory | 559720 kb |
| Host | smart-c357fb71-25e7-45fb-861a-d9ba35326ca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837064032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.3837064032 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.1928388121 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 4239296312 ps |
| CPU time | 655.09 seconds |
| Started | Jan 10 01:56:44 PM PST 24 |
| Finished | Jan 10 02:07:43 PM PST 24 |
| Peak memory | 602516 kb |
| Host | smart-2504d572-cacb-48a4-aa99-7b8c49fe8dc9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928388121 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.1928388121 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3696733799 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4122103444 ps |
| CPU time | 394.33 seconds |
| Started | Jan 10 01:56:45 PM PST 24 |
| Finished | Jan 10 02:03:23 PM PST 24 |
| Peak memory | 616544 kb |
| Host | smart-7746b19d-ba66-4033-b8a3-63846b15a46f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696733799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3696733799 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2773039671 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 7898397470 ps |
| CPU time | 680.77 seconds |
| Started | Jan 10 02:00:31 PM PST 24 |
| Finished | Jan 10 02:11:55 PM PST 24 |
| Peak memory | 604732 kb |
| Host | smart-c1732691-72af-4f06-8fb3-19ce5ce19d74 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2773039671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2773039671 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1773561987 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5966568456 ps |
| CPU time | 961.56 seconds |
| Started | Jan 10 01:55:47 PM PST 24 |
| Finished | Jan 10 02:11:50 PM PST 24 |
| Peak memory | 602896 kb |
| Host | smart-1892f8eb-b497-442b-ab71-beac4f5c312a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1773561987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.1773561987 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4201034518 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3192091835 ps |
| CPU time | 212.61 seconds |
| Started | Jan 10 01:53:44 PM PST 24 |
| Finished | Jan 10 01:57:18 PM PST 24 |
| Peak memory | 599592 kb |
| Host | smart-eb21ee89-e167-4f43-ba99-eb83702782e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201034518 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.4201034518 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.2645585805 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2666286880 ps |
| CPU time | 237.34 seconds |
| Started | Jan 10 01:57:00 PM PST 24 |
| Finished | Jan 10 02:00:59 PM PST 24 |
| Peak memory | 590632 kb |
| Host | smart-3e544003-5f05-4e67-adcd-2018359a9f84 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645585805 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2645585805 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2258694410 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4305388524 ps |
| CPU time | 365.57 seconds |
| Started | Jan 10 01:53:40 PM PST 24 |
| Finished | Jan 10 01:59:47 PM PST 24 |
| Peak memory | 608552 kb |
| Host | smart-3f6c83df-0f5d-4b2e-ad08-158bfbe26e40 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2258694410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2258694410 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4164511158 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 432838148 ps |
| CPU time | 110.37 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:38:35 PM PST 24 |
| Peak memory | 555928 kb |
| Host | smart-41acd544-4593-4390-ac62-3921e0d6b54f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164511158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.4164511158 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3357634431 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 7658998761 ps |
| CPU time | 404.14 seconds |
| Started | Jan 10 01:38:34 PM PST 24 |
| Finished | Jan 10 01:45:22 PM PST 24 |
| Peak memory | 559916 kb |
| Host | smart-1b4b6c44-8af1-461b-84a8-df21e96ffc56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357634431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.3357634431 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.15862876 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 26241854990 ps |
| CPU time | 1717.93 seconds |
| Started | Jan 10 02:00:23 PM PST 24 |
| Finished | Jan 10 02:29:03 PM PST 24 |
| Peak memory | 603156 kb |
| Host | smart-af1df9a7-c7ae-43e8-9138-e46eb69b51cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=15862876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.15862876 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2304435000 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 27446757845 ps |
| CPU time | 2878.88 seconds |
| Started | Jan 10 01:36:35 PM PST 24 |
| Finished | Jan 10 02:24:37 PM PST 24 |
| Peak memory | 580840 kb |
| Host | smart-bb9193c1-9c87-4201-b683-e930f8b61377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304435000 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.2304435000 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.3595939808 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 11764212930 ps |
| CPU time | 1350.35 seconds |
| Started | Jan 10 01:52:08 PM PST 24 |
| Finished | Jan 10 02:14:41 PM PST 24 |
| Peak memory | 596540 kb |
| Host | smart-0f781362-2bc2-40b1-aaa2-37a70892f0a0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595939808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.3595939808 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2072350738 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2550205410 ps |
| CPU time | 310.95 seconds |
| Started | Jan 10 01:56:26 PM PST 24 |
| Finished | Jan 10 02:01:38 PM PST 24 |
| Peak memory | 602912 kb |
| Host | smart-e17ff98c-e28f-4a89-8383-9049895ea0cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072350 738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2072350738 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3989169589 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5267119816 ps |
| CPU time | 746.27 seconds |
| Started | Jan 10 01:53:30 PM PST 24 |
| Finished | Jan 10 02:05:58 PM PST 24 |
| Peak memory | 602868 kb |
| Host | smart-46e66e67-b673-497d-a262-33acddace6e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3989169589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3989169589 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1788207522 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 485577119 ps |
| CPU time | 173.6 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:39:36 PM PST 24 |
| Peak memory | 559560 kb |
| Host | smart-2eb1f65a-c267-45b0-9dd9-d46d463d296e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788207522 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1788207522 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.1540628183 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 5461669765 ps |
| CPU time | 185.39 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:41:21 PM PST 24 |
| Peak memory | 555908 kb |
| Host | smart-e20011fe-124d-41b3-b6c1-9853166b0c5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540628183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1540628183 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.1083265084 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3064544096 ps |
| CPU time | 161.83 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:40:57 PM PST 24 |
| Peak memory | 580728 kb |
| Host | smart-b29976b0-7c67-4998-b709-f1fa374df65c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083265084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.1083265084 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3549112406 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 8678732056 ps |
| CPU time | 373.32 seconds |
| Started | Jan 10 01:38:13 PM PST 24 |
| Finished | Jan 10 01:44:32 PM PST 24 |
| Peak memory | 559776 kb |
| Host | smart-f5c656ec-e1b3-41ef-bc3b-fb523587a007 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549112406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.3549112406 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.987053806 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 4229184468 ps |
| CPU time | 408.57 seconds |
| Started | Jan 10 01:55:30 PM PST 24 |
| Finished | Jan 10 02:02:23 PM PST 24 |
| Peak memory | 633388 kb |
| Host | smart-a269f026-2b82-42ef-a184-b8134d81ec8d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987053806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _alert_handler_lpg_sleep_mode_alerts.987053806 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.3494593777 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 6231032856 ps |
| CPU time | 621.68 seconds |
| Started | Jan 10 01:56:10 PM PST 24 |
| Finished | Jan 10 02:06:33 PM PST 24 |
| Peak memory | 635168 kb |
| Host | smart-be1a9b60-061e-4588-af76-3f5192201199 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3494593777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3494593777 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.2726617107 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 4984006728 ps |
| CPU time | 602.81 seconds |
| Started | Jan 10 02:03:06 PM PST 24 |
| Finished | Jan 10 02:13:32 PM PST 24 |
| Peak memory | 634712 kb |
| Host | smart-81e82b1a-eb30-4594-bfe1-cb6933a93c51 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2726617107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.2726617107 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.315595874 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 3860665232 ps |
| CPU time | 278.22 seconds |
| Started | Jan 10 02:01:17 PM PST 24 |
| Finished | Jan 10 02:06:04 PM PST 24 |
| Peak memory | 633624 kb |
| Host | smart-4814d60c-7912-4cdf-babb-0c538e6317ca |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315595874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_s w_alert_handler_lpg_sleep_mode_alerts.315595874 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2267349555 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3610172440 ps |
| CPU time | 405.1 seconds |
| Started | Jan 10 02:04:29 PM PST 24 |
| Finished | Jan 10 02:11:18 PM PST 24 |
| Peak memory | 633384 kb |
| Host | smart-bffd9a3e-bbea-4e09-9557-644d26f9fd23 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267349555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2267349555 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.4146935959 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 5904671586 ps |
| CPU time | 599.77 seconds |
| Started | Jan 10 02:01:25 PM PST 24 |
| Finished | Jan 10 02:11:33 PM PST 24 |
| Peak memory | 634908 kb |
| Host | smart-f851249c-c469-4b1a-8f1f-8a38163c616a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4146935959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.4146935959 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2547776347 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3870951856 ps |
| CPU time | 411.21 seconds |
| Started | Jan 10 02:02:00 PM PST 24 |
| Finished | Jan 10 02:08:54 PM PST 24 |
| Peak memory | 633424 kb |
| Host | smart-a2ffa5f6-f25e-4795-9a42-34f285aeed99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547776347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2547776347 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3180497948 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4975901688 ps |
| CPU time | 565.87 seconds |
| Started | Jan 10 02:02:43 PM PST 24 |
| Finished | Jan 10 02:12:50 PM PST 24 |
| Peak memory | 634904 kb |
| Host | smart-9ed7c836-4964-419c-95e0-0bb367419baf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3180497948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3180497948 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1715343511 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3726962070 ps |
| CPU time | 337.43 seconds |
| Started | Jan 10 02:01:31 PM PST 24 |
| Finished | Jan 10 02:07:13 PM PST 24 |
| Peak memory | 633460 kb |
| Host | smart-2ddd0d2b-b58e-40d4-84be-5e5ff11c1d25 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715343511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1715343511 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.2666862943 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 5637186318 ps |
| CPU time | 556.87 seconds |
| Started | Jan 10 02:01:47 PM PST 24 |
| Finished | Jan 10 02:11:06 PM PST 24 |
| Peak memory | 634792 kb |
| Host | smart-22323d5d-6167-4651-a203-1081f4758262 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2666862943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2666862943 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.85215465 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3853756894 ps |
| CPU time | 366.5 seconds |
| Started | Jan 10 02:00:54 PM PST 24 |
| Finished | Jan 10 02:07:02 PM PST 24 |
| Peak memory | 632992 kb |
| Host | smart-f0b84149-37c3-4633-b5dc-364148cd1975 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85215465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw _alert_handler_lpg_sleep_mode_alerts.85215465 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.1962978142 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5532893664 ps |
| CPU time | 647.15 seconds |
| Started | Jan 10 02:01:32 PM PST 24 |
| Finished | Jan 10 02:12:22 PM PST 24 |
| Peak memory | 634796 kb |
| Host | smart-f8820f7a-6e24-42c4-9169-bb99e0fd8f03 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1962978142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1962978142 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1521329766 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3967665000 ps |
| CPU time | 492.48 seconds |
| Started | Jan 10 02:01:50 PM PST 24 |
| Finished | Jan 10 02:10:05 PM PST 24 |
| Peak memory | 633448 kb |
| Host | smart-69790db5-e5f2-42fc-ad73-ae487589608a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521329766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1521329766 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.932958134 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 5228649944 ps |
| CPU time | 515.1 seconds |
| Started | Jan 10 02:02:07 PM PST 24 |
| Finished | Jan 10 02:10:53 PM PST 24 |
| Peak memory | 634728 kb |
| Host | smart-cf84a4a5-24fd-4a36-88ab-ab9fdd644fd3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 932958134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.932958134 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.3466784572 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 5552981752 ps |
| CPU time | 593.73 seconds |
| Started | Jan 10 02:01:00 PM PST 24 |
| Finished | Jan 10 02:10:56 PM PST 24 |
| Peak memory | 630324 kb |
| Host | smart-edd51215-02bd-4c69-96c4-c24b054bffdc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3466784572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.3466784572 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2076807283 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3751975250 ps |
| CPU time | 323.65 seconds |
| Started | Jan 10 02:02:36 PM PST 24 |
| Finished | Jan 10 02:08:48 PM PST 24 |
| Peak memory | 633112 kb |
| Host | smart-efc3383a-de6c-4a7c-9156-bacfdef4608f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076807283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2076807283 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.2363331322 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 6394429970 ps |
| CPU time | 640.37 seconds |
| Started | Jan 10 02:01:31 PM PST 24 |
| Finished | Jan 10 02:12:16 PM PST 24 |
| Peak memory | 635032 kb |
| Host | smart-3382572b-1644-4276-ab08-a593fe84dc51 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2363331322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2363331322 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1574439695 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 3967508876 ps |
| CPU time | 427.14 seconds |
| Started | Jan 10 02:06:39 PM PST 24 |
| Finished | Jan 10 02:13:48 PM PST 24 |
| Peak memory | 633136 kb |
| Host | smart-8de58f76-4905-420d-9e47-2b199b66c455 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574439695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1574439695 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.3198161492 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 4438836908 ps |
| CPU time | 625.53 seconds |
| Started | Jan 10 02:06:18 PM PST 24 |
| Finished | Jan 10 02:16:45 PM PST 24 |
| Peak memory | 630384 kb |
| Host | smart-1d69eb36-46ea-4f89-921d-bc55c01c52e9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3198161492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.3198161492 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.165438680 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3498212352 ps |
| CPU time | 312.64 seconds |
| Started | Jan 10 01:59:30 PM PST 24 |
| Finished | Jan 10 02:04:44 PM PST 24 |
| Peak memory | 633412 kb |
| Host | smart-3c9fb5b5-8329-42a1-af84-884ed6fa884a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165438680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.165438680 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3980645318 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3979725892 ps |
| CPU time | 393.17 seconds |
| Started | Jan 10 02:07:28 PM PST 24 |
| Finished | Jan 10 02:14:16 PM PST 24 |
| Peak memory | 633396 kb |
| Host | smart-15d2846b-95bd-4427-81de-508ae49e1776 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980645318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3980645318 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2386371521 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3587410774 ps |
| CPU time | 342.87 seconds |
| Started | Jan 10 02:02:59 PM PST 24 |
| Finished | Jan 10 02:09:05 PM PST 24 |
| Peak memory | 633460 kb |
| Host | smart-02d84b94-1d26-4443-b79f-eb759830e645 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386371521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2386371521 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.1902025381 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 5285258872 ps |
| CPU time | 567.67 seconds |
| Started | Jan 10 02:02:58 PM PST 24 |
| Finished | Jan 10 02:12:54 PM PST 24 |
| Peak memory | 634864 kb |
| Host | smart-2c00b17b-e781-4632-818c-a97312b60527 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1902025381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1902025381 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.532115149 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3511731890 ps |
| CPU time | 390.18 seconds |
| Started | Jan 10 02:01:23 PM PST 24 |
| Finished | Jan 10 02:08:02 PM PST 24 |
| Peak memory | 633428 kb |
| Host | smart-11d88888-37b8-49c1-9434-50439644b6f7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532115149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_s w_alert_handler_lpg_sleep_mode_alerts.532115149 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1479494026 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3780696248 ps |
| CPU time | 336.11 seconds |
| Started | Jan 10 02:02:14 PM PST 24 |
| Finished | Jan 10 02:08:00 PM PST 24 |
| Peak memory | 633132 kb |
| Host | smart-6c9c0ba1-5620-4d02-9e2f-f0972f94c9ff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479494026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1479494026 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.3202743103 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 4476581850 ps |
| CPU time | 579.82 seconds |
| Started | Jan 10 02:09:29 PM PST 24 |
| Finished | Jan 10 02:19:12 PM PST 24 |
| Peak memory | 634656 kb |
| Host | smart-01bf17fd-8d9b-41de-ae12-d529a4c80852 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3202743103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.3202743103 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4176703194 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3420994968 ps |
| CPU time | 358.23 seconds |
| Started | Jan 10 02:04:57 PM PST 24 |
| Finished | Jan 10 02:11:01 PM PST 24 |
| Peak memory | 633416 kb |
| Host | smart-1a88171b-fb0f-4fc7-9d5a-5a4c29e55a66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176703194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4176703194 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.3208882009 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4501668424 ps |
| CPU time | 481.01 seconds |
| Started | Jan 10 02:02:38 PM PST 24 |
| Finished | Jan 10 02:11:22 PM PST 24 |
| Peak memory | 634816 kb |
| Host | smart-3a02abf2-9311-4236-a39b-7802f2f1e078 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3208882009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.3208882009 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1546743156 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4265889014 ps |
| CPU time | 352.49 seconds |
| Started | Jan 10 02:04:26 PM PST 24 |
| Finished | Jan 10 02:10:21 PM PST 24 |
| Peak memory | 633392 kb |
| Host | smart-aae7c2af-a0b5-45b2-a376-9040fec9b1db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546743156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1546743156 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.302660264 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3325967378 ps |
| CPU time | 322.05 seconds |
| Started | Jan 10 02:02:07 PM PST 24 |
| Finished | Jan 10 02:07:40 PM PST 24 |
| Peak memory | 633036 kb |
| Host | smart-e46cc7e7-38d6-4f83-8c09-059aec804a73 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302660264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_s w_alert_handler_lpg_sleep_mode_alerts.302660264 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607524107 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3771661680 ps |
| CPU time | 394.29 seconds |
| Started | Jan 10 02:01:50 PM PST 24 |
| Finished | Jan 10 02:08:26 PM PST 24 |
| Peak memory | 633536 kb |
| Host | smart-5eef4029-8ba0-416e-9020-8b13381080d7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607524107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2607524107 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.1505819286 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 6060623932 ps |
| CPU time | 670.83 seconds |
| Started | Jan 10 02:03:10 PM PST 24 |
| Finished | Jan 10 02:14:44 PM PST 24 |
| Peak memory | 634872 kb |
| Host | smart-3ed46bf2-c979-4dcf-ba87-7eac7fddb722 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1505819286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.1505819286 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.499713755 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4951272840 ps |
| CPU time | 685.11 seconds |
| Started | Jan 10 02:04:40 PM PST 24 |
| Finished | Jan 10 02:16:09 PM PST 24 |
| Peak memory | 634796 kb |
| Host | smart-f9fdba80-00d4-482b-9ac9-0589b36acdd5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 499713755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.499713755 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1983254087 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3021175278 ps |
| CPU time | 375.24 seconds |
| Started | Jan 10 02:03:06 PM PST 24 |
| Finished | Jan 10 02:09:43 PM PST 24 |
| Peak memory | 633372 kb |
| Host | smart-4dc6a667-fb9a-4ef5-8183-15cdd4e7b52e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983254087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1983254087 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.2187694829 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 4936775970 ps |
| CPU time | 575.99 seconds |
| Started | Jan 10 02:10:34 PM PST 24 |
| Finished | Jan 10 02:20:11 PM PST 24 |
| Peak memory | 634732 kb |
| Host | smart-44e441ee-22c0-4c36-aa47-d86ac9538fe1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2187694829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.2187694829 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.1431248284 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 5814417320 ps |
| CPU time | 546.44 seconds |
| Started | Jan 10 02:03:02 PM PST 24 |
| Finished | Jan 10 02:12:29 PM PST 24 |
| Peak memory | 634928 kb |
| Host | smart-623a9767-2ebe-4136-8310-8ee158ab76ef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1431248284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.1431248284 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.300856584 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 4682632964 ps |
| CPU time | 632.78 seconds |
| Started | Jan 10 02:10:06 PM PST 24 |
| Finished | Jan 10 02:20:46 PM PST 24 |
| Peak memory | 634828 kb |
| Host | smart-3cd8b69f-f622-403f-a842-6c1520429ab7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 300856584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.300856584 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.3281037074 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 6304688440 ps |
| CPU time | 549.62 seconds |
| Started | Jan 10 02:09:59 PM PST 24 |
| Finished | Jan 10 02:19:11 PM PST 24 |
| Peak memory | 634728 kb |
| Host | smart-473085b4-67e7-4fce-ac59-52ba9df527e5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3281037074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.3281037074 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1251258751 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3650477274 ps |
| CPU time | 309.2 seconds |
| Started | Jan 10 02:10:33 PM PST 24 |
| Finished | Jan 10 02:15:44 PM PST 24 |
| Peak memory | 633488 kb |
| Host | smart-55b8e17f-52be-4cb3-b057-4255a23af404 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251258751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1251258751 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.531595031 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5385283928 ps |
| CPU time | 566.48 seconds |
| Started | Jan 10 02:02:19 PM PST 24 |
| Finished | Jan 10 02:11:57 PM PST 24 |
| Peak memory | 634976 kb |
| Host | smart-e43b0292-a7b8-4011-8c6d-1fe0e089dd30 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 531595031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.531595031 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2007988778 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 4305841266 ps |
| CPU time | 411.3 seconds |
| Started | Jan 10 02:10:17 PM PST 24 |
| Finished | Jan 10 02:17:12 PM PST 24 |
| Peak memory | 629108 kb |
| Host | smart-0aa3502e-04f5-45db-98cf-ad4970adb8f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007988778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2007988778 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.383405371 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 4314923042 ps |
| CPU time | 464.07 seconds |
| Started | Jan 10 02:04:22 PM PST 24 |
| Finished | Jan 10 02:12:08 PM PST 24 |
| Peak memory | 634696 kb |
| Host | smart-d3b41c83-5854-4320-b53a-057c85f0eec0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 383405371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.383405371 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238642103 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3352187082 ps |
| CPU time | 334.04 seconds |
| Started | Jan 10 02:01:34 PM PST 24 |
| Finished | Jan 10 02:07:11 PM PST 24 |
| Peak memory | 633216 kb |
| Host | smart-528acaff-20e7-4255-9160-201f6fd43a03 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238642103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2238642103 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.640227614 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4988135960 ps |
| CPU time | 633.17 seconds |
| Started | Jan 10 02:03:07 PM PST 24 |
| Finished | Jan 10 02:14:04 PM PST 24 |
| Peak memory | 630284 kb |
| Host | smart-9974518a-005f-4114-b0c6-053a47327091 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 640227614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.640227614 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.981994609 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5176714424 ps |
| CPU time | 406.98 seconds |
| Started | Jan 10 02:05:40 PM PST 24 |
| Finished | Jan 10 02:12:29 PM PST 24 |
| Peak memory | 630404 kb |
| Host | smart-83dbee99-aab3-4b3e-b353-923c06584cba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 981994609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.981994609 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2317923867 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 3803947500 ps |
| CPU time | 510.71 seconds |
| Started | Jan 10 02:05:03 PM PST 24 |
| Finished | Jan 10 02:13:39 PM PST 24 |
| Peak memory | 628912 kb |
| Host | smart-87b0d6cf-77d3-4e20-a635-9b8ae90bdf0a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317923867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2317923867 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.3483458703 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 5969089848 ps |
| CPU time | 739.1 seconds |
| Started | Jan 10 02:05:48 PM PST 24 |
| Finished | Jan 10 02:18:11 PM PST 24 |
| Peak memory | 634512 kb |
| Host | smart-c0c086fa-c3db-41f7-946e-5a28375d6919 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3483458703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3483458703 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.3130560233 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 4548262872 ps |
| CPU time | 466.84 seconds |
| Started | Jan 10 02:05:25 PM PST 24 |
| Finished | Jan 10 02:13:15 PM PST 24 |
| Peak memory | 635036 kb |
| Host | smart-de973fb2-5437-4a9e-8145-6505d3ad4b62 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3130560233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.3130560233 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3230805629 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3496972630 ps |
| CPU time | 280.81 seconds |
| Started | Jan 10 02:06:00 PM PST 24 |
| Finished | Jan 10 02:10:45 PM PST 24 |
| Peak memory | 633044 kb |
| Host | smart-047aa795-3991-416f-a5e1-3b20f76201e1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230805629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3230805629 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.2351909884 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4470452040 ps |
| CPU time | 485.36 seconds |
| Started | Jan 10 02:05:00 PM PST 24 |
| Finished | Jan 10 02:13:13 PM PST 24 |
| Peak memory | 634828 kb |
| Host | smart-d7d1f5e3-079b-46a8-bdac-f71b4698d1c0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2351909884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.2351909884 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.203817393 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 3966330208 ps |
| CPU time | 391.6 seconds |
| Started | Jan 10 02:05:51 PM PST 24 |
| Finished | Jan 10 02:12:28 PM PST 24 |
| Peak memory | 633380 kb |
| Host | smart-5d2ac3ba-d94f-4559-bb62-8c2ffa6b86ea |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203817393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.203817393 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.849675278 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 4971745768 ps |
| CPU time | 624.96 seconds |
| Started | Jan 10 02:06:13 PM PST 24 |
| Finished | Jan 10 02:16:41 PM PST 24 |
| Peak memory | 634860 kb |
| Host | smart-b98ffcb9-b1e5-4201-a5b1-8e9dce995944 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 849675278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.849675278 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2574720140 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3529472936 ps |
| CPU time | 293.56 seconds |
| Started | Jan 10 02:06:05 PM PST 24 |
| Finished | Jan 10 02:11:01 PM PST 24 |
| Peak memory | 629480 kb |
| Host | smart-4a7ecc94-f0e8-4f53-9db4-e3372cff3610 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574720140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2574720140 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.3275182748 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 5073618188 ps |
| CPU time | 572.78 seconds |
| Started | Jan 10 02:06:27 PM PST 24 |
| Finished | Jan 10 02:16:03 PM PST 24 |
| Peak memory | 634768 kb |
| Host | smart-d4cbcf77-f9df-4029-b62e-93e3b4d45f05 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3275182748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3275182748 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.115250673 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 5367673128 ps |
| CPU time | 553.96 seconds |
| Started | Jan 10 02:05:42 PM PST 24 |
| Finished | Jan 10 02:14:59 PM PST 24 |
| Peak memory | 634448 kb |
| Host | smart-efb4bf23-1e37-45b5-877e-ee7325aa4a45 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 115250673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.115250673 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3424854318 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3371542040 ps |
| CPU time | 313.39 seconds |
| Started | Jan 10 02:07:07 PM PST 24 |
| Finished | Jan 10 02:12:29 PM PST 24 |
| Peak memory | 633456 kb |
| Host | smart-f0770846-09fb-4657-95f6-55cec719efa2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424854318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3424854318 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.1877262397 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 5073317230 ps |
| CPU time | 461.94 seconds |
| Started | Jan 10 02:06:03 PM PST 24 |
| Finished | Jan 10 02:13:49 PM PST 24 |
| Peak memory | 634728 kb |
| Host | smart-c0608865-def7-4e48-a340-03b9410e2eaf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1877262397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1877262397 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3311572911 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3424953960 ps |
| CPU time | 368.09 seconds |
| Started | Jan 10 02:07:19 PM PST 24 |
| Finished | Jan 10 02:13:37 PM PST 24 |
| Peak memory | 633312 kb |
| Host | smart-b8268de1-7e85-4a0d-8e0f-f44e34f43674 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311572911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3311572911 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.2831019015 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4871518066 ps |
| CPU time | 507.44 seconds |
| Started | Jan 10 02:05:29 PM PST 24 |
| Finished | Jan 10 02:14:00 PM PST 24 |
| Peak memory | 634528 kb |
| Host | smart-340ad0c9-2c39-4dcb-aa50-a86faf81503d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2831019015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2831019015 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.962024143 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4216469552 ps |
| CPU time | 347.83 seconds |
| Started | Jan 10 02:06:02 PM PST 24 |
| Finished | Jan 10 02:11:53 PM PST 24 |
| Peak memory | 633480 kb |
| Host | smart-59ea4009-5ca7-4111-a71e-94d3a0dbc9b7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962024143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_s w_alert_handler_lpg_sleep_mode_alerts.962024143 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.2861212765 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 4281639836 ps |
| CPU time | 481.99 seconds |
| Started | Jan 10 02:05:42 PM PST 24 |
| Finished | Jan 10 02:13:46 PM PST 24 |
| Peak memory | 634124 kb |
| Host | smart-aac8eafb-f326-4753-b260-61a3309c0eb4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2861212765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2861212765 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2050587787 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 3112198580 ps |
| CPU time | 360.69 seconds |
| Started | Jan 10 02:06:33 PM PST 24 |
| Finished | Jan 10 02:12:38 PM PST 24 |
| Peak memory | 633364 kb |
| Host | smart-5984dc16-05cc-48f1-95c2-0cafa472bd29 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050587787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2050587787 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.3411341340 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 5092296184 ps |
| CPU time | 547.57 seconds |
| Started | Jan 10 02:06:04 PM PST 24 |
| Finished | Jan 10 02:15:14 PM PST 24 |
| Peak memory | 634612 kb |
| Host | smart-83bca9e9-5fd3-4373-883e-eae5d4bf88c4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3411341340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3411341340 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1169517616 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3391066438 ps |
| CPU time | 314.96 seconds |
| Started | Jan 10 02:02:11 PM PST 24 |
| Finished | Jan 10 02:07:34 PM PST 24 |
| Peak memory | 629928 kb |
| Host | smart-df00ebe3-680b-4a4a-9b51-bce798dee70e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169517616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.1169517616 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.724755247 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 5671350900 ps |
| CPU time | 513.74 seconds |
| Started | Jan 10 02:05:54 PM PST 24 |
| Finished | Jan 10 02:14:32 PM PST 24 |
| Peak memory | 634792 kb |
| Host | smart-84cfe7c1-0860-4daf-bcdb-0c666de2f154 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 724755247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.724755247 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2610095080 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3978326456 ps |
| CPU time | 307.84 seconds |
| Started | Jan 10 02:06:17 PM PST 24 |
| Finished | Jan 10 02:11:26 PM PST 24 |
| Peak memory | 633396 kb |
| Host | smart-23e5daa1-36ca-4e08-b543-f601ab5b808d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610095080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2610095080 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.1567276648 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 5991963224 ps |
| CPU time | 585.45 seconds |
| Started | Jan 10 02:06:18 PM PST 24 |
| Finished | Jan 10 02:16:06 PM PST 24 |
| Peak memory | 634832 kb |
| Host | smart-80ec2dd0-f437-4929-a95a-81ddf2da2f00 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1567276648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1567276648 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.3906314976 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5704559132 ps |
| CPU time | 602.6 seconds |
| Started | Jan 10 02:06:20 PM PST 24 |
| Finished | Jan 10 02:16:24 PM PST 24 |
| Peak memory | 634556 kb |
| Host | smart-f2b81e2a-1ff1-4540-bd25-4ad7f0fffdd1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3906314976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.3906314976 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1329843326 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3595148952 ps |
| CPU time | 379.07 seconds |
| Started | Jan 10 02:06:13 PM PST 24 |
| Finished | Jan 10 02:12:35 PM PST 24 |
| Peak memory | 633632 kb |
| Host | smart-d33df91b-3d67-4169-a11f-974258827305 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329843326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1329843326 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.847569902 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4420938744 ps |
| CPU time | 469.48 seconds |
| Started | Jan 10 02:06:17 PM PST 24 |
| Finished | Jan 10 02:14:08 PM PST 24 |
| Peak memory | 634892 kb |
| Host | smart-2c56c3b8-e9e0-4ac6-9756-c301e3d3ae2c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 847569902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.847569902 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.2410702427 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5652803928 ps |
| CPU time | 487.99 seconds |
| Started | Jan 10 02:06:57 PM PST 24 |
| Finished | Jan 10 02:15:07 PM PST 24 |
| Peak memory | 634520 kb |
| Host | smart-c347fb03-c22c-476b-9038-a3ff39a62017 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2410702427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2410702427 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.3240565620 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 4821331030 ps |
| CPU time | 502.29 seconds |
| Started | Jan 10 02:07:33 PM PST 24 |
| Finished | Jan 10 02:16:10 PM PST 24 |
| Peak memory | 634216 kb |
| Host | smart-6aeaedda-9cef-41d6-a3a7-f337e2689f0d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3240565620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3240565620 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.2646591213 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 6334167092 ps |
| CPU time | 632.18 seconds |
| Started | Jan 10 02:06:38 PM PST 24 |
| Finished | Jan 10 02:17:13 PM PST 24 |
| Peak memory | 592528 kb |
| Host | smart-e4c67476-476c-48d0-829b-67d68b3068a2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2646591213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2646591213 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.604955947 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2497996870 ps |
| CPU time | 136.72 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:38:57 PM PST 24 |
| Peak memory | 580416 kb |
| Host | smart-c25799fa-c1d9-41a8-b60e-bd59e58ec2ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604955947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.604955947 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.118165475 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3380971447 ps |
| CPU time | 202.51 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:41:29 PM PST 24 |
| Peak memory | 580860 kb |
| Host | smart-017c5213-4bcc-4253-9664-1ba6c12ed81c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118165475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.118165475 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4091426588 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5055121800 ps |
| CPU time | 593.27 seconds |
| Started | Jan 10 02:01:37 PM PST 24 |
| Finished | Jan 10 02:11:33 PM PST 24 |
| Peak memory | 599624 kb |
| Host | smart-3f22f327-fad4-4a28-9ef8-dd6fe2b45de9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4091426588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.4091426588 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.4172033869 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4277972132 ps |
| CPU time | 221.39 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:39:50 PM PST 24 |
| Peak memory | 643268 kb |
| Host | smart-d41770ea-d8ed-4625-809e-cb236a7f15b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172033869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.4172033869 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.85094425 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 7104370762 ps |
| CPU time | 692.81 seconds |
| Started | Jan 10 01:54:40 PM PST 24 |
| Finished | Jan 10 02:06:14 PM PST 24 |
| Peak memory | 603308 kb |
| Host | smart-44e58f22-3d82-4c49-9705-70861b78f6eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85094425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_s ram_ret_contents_scramble.85094425 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1832828920 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 6007032825 ps |
| CPU time | 536.9 seconds |
| Started | Jan 10 01:56:39 PM PST 24 |
| Finished | Jan 10 02:05:45 PM PST 24 |
| Peak memory | 617248 kb |
| Host | smart-14edfbab-e2ef-460e-92d6-48a542db5296 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832828920 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.1832828920 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.3624171000 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 14593454468 ps |
| CPU time | 1175.5 seconds |
| Started | Jan 10 01:54:42 PM PST 24 |
| Finished | Jan 10 02:14:18 PM PST 24 |
| Peak memory | 601904 kb |
| Host | smart-ffb2c655-9219-46f6-bcfd-f95f76a51541 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3624171000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3624171000 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1484761787 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 19859579636 ps |
| CPU time | 600.92 seconds |
| Started | Jan 10 01:56:32 PM PST 24 |
| Finished | Jan 10 02:06:35 PM PST 24 |
| Peak memory | 599912 kb |
| Host | smart-af33d24c-b86d-44e6-9812-89312c1335ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1484761787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1484761787 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.1758757362 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 3450132696 ps |
| CPU time | 225.33 seconds |
| Started | Jan 10 01:37:30 PM PST 24 |
| Finished | Jan 10 01:41:27 PM PST 24 |
| Peak memory | 580640 kb |
| Host | smart-75a71fe6-cade-4e38-a6b6-e03dff9978f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758757362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.1758757362 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.91853521 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 4744082056 ps |
| CPU time | 543.51 seconds |
| Started | Jan 10 01:55:15 PM PST 24 |
| Finished | Jan 10 02:04:19 PM PST 24 |
| Peak memory | 602864 kb |
| Host | smart-16dcac61-c265-4d5c-9845-7ec25a63ebf3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91853521 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_plic_all_irqs_10.91853521 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.75047412 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 11036508384 ps |
| CPU time | 1356.23 seconds |
| Started | Jan 10 01:53:19 PM PST 24 |
| Finished | Jan 10 02:15:57 PM PST 24 |
| Peak memory | 603752 kb |
| Host | smart-053a314c-64dd-46e7-aa55-e2e10d5362d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=75047412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.75047412 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1083836468 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 22669906816 ps |
| CPU time | 4111.44 seconds |
| Started | Jan 10 01:56:28 PM PST 24 |
| Finished | Jan 10 03:05:01 PM PST 24 |
| Peak memory | 598224 kb |
| Host | smart-f204a522-2189-486e-8c20-75b75acf5f81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1083836468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1083836468 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3566433380 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 6005428872 ps |
| CPU time | 1034.74 seconds |
| Started | Jan 10 02:01:04 PM PST 24 |
| Finished | Jan 10 02:18:20 PM PST 24 |
| Peak memory | 602624 kb |
| Host | smart-83ec4799-87a7-429b-ad42-9cbdfce07a05 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566433380 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.3566433380 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2094885198 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 5133970594 ps |
| CPU time | 816.99 seconds |
| Started | Jan 10 02:01:05 PM PST 24 |
| Finished | Jan 10 02:14:43 PM PST 24 |
| Peak memory | 602592 kb |
| Host | smart-8e62283f-af80-4284-a1fc-b81e019c6022 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094885198 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.2094885198 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1237625889 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4541491560 ps |
| CPU time | 802.56 seconds |
| Started | Jan 10 01:58:25 PM PST 24 |
| Finished | Jan 10 02:11:50 PM PST 24 |
| Peak memory | 602884 kb |
| Host | smart-011e4f24-edfb-4abb-9dec-63949a65451c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237625889 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1237625889 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1957740213 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2707406966 ps |
| CPU time | 631.79 seconds |
| Started | Jan 10 01:55:20 PM PST 24 |
| Finished | Jan 10 02:05:57 PM PST 24 |
| Peak memory | 602388 kb |
| Host | smart-9776779a-54d6-448b-930e-d679b683cae0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957740213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.1957740213 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.51664237 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 5779325046 ps |
| CPU time | 471.46 seconds |
| Started | Jan 10 01:56:11 PM PST 24 |
| Finished | Jan 10 02:04:04 PM PST 24 |
| Peak memory | 616984 kb |
| Host | smart-0973c30d-d757-4f76-9447-32b753add0fa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=51664237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.51664237 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1443165523 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 3878499690 ps |
| CPU time | 357.78 seconds |
| Started | Jan 10 01:55:33 PM PST 24 |
| Finished | Jan 10 02:01:33 PM PST 24 |
| Peak memory | 609416 kb |
| Host | smart-9eb9c2b4-88a8-45da-a209-4e2f9969e570 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1443165523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.1443165523 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1049087909 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 2803622504 ps |
| CPU time | 95.71 seconds |
| Started | Jan 10 01:54:18 PM PST 24 |
| Finished | Jan 10 01:55:55 PM PST 24 |
| Peak memory | 599116 kb |
| Host | smart-eb4fbf5e-2fd7-443c-89ca-ed504a0eab21 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049087909 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1049087909 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3908046668 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 15086503176 ps |
| CPU time | 545.38 seconds |
| Started | Jan 10 01:35:41 PM PST 24 |
| Finished | Jan 10 01:45:06 PM PST 24 |
| Peak memory | 556080 kb |
| Host | smart-0463fcc4-9a96-48bf-a5d6-fa1194fb0538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908046668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3908046668 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.62746630 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 6072174922 ps |
| CPU time | 384.09 seconds |
| Started | Jan 10 01:35:41 PM PST 24 |
| Finished | Jan 10 01:42:24 PM PST 24 |
| Peak memory | 559952 kb |
| Host | smart-7eaae1f9-d791-4875-b291-cda34b8c4098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62746630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w ith_reset_error.62746630 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.1688071958 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 4131395108 ps |
| CPU time | 286.35 seconds |
| Started | Jan 10 01:36:43 PM PST 24 |
| Finished | Jan 10 01:41:31 PM PST 24 |
| Peak memory | 580768 kb |
| Host | smart-986a81fd-cf28-4ebe-99ab-4f44596f2c40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688071958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.1688071958 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2058728861 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 53243030560 ps |
| CPU time | 907.34 seconds |
| Started | Jan 10 01:37:46 PM PST 24 |
| Finished | Jan 10 01:52:57 PM PST 24 |
| Peak memory | 554852 kb |
| Host | smart-482f6b75-3937-48fc-980f-7a78c0bd3afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058728861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2058728861 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3235055723 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 3753807160 ps |
| CPU time | 256.81 seconds |
| Started | Jan 10 01:37:53 PM PST 24 |
| Finished | Jan 10 01:42:14 PM PST 24 |
| Peak memory | 580736 kb |
| Host | smart-6517b992-5bfc-4019-8bea-eb01f9478e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235055723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3235055723 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1911796149 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 3472571972 ps |
| CPU time | 257.79 seconds |
| Started | Jan 10 01:39:51 PM PST 24 |
| Finished | Jan 10 01:44:09 PM PST 24 |
| Peak memory | 556332 kb |
| Host | smart-900acd4e-a146-4ad5-a4b4-857c5dc80cf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911796149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1911796149 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.567893599 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3100619004 ps |
| CPU time | 103.04 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:42:11 PM PST 24 |
| Peak memory | 555872 kb |
| Host | smart-20fa0961-5094-4f67-8c59-29c4b47e44c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567893599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.567893599 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.2582012676 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3751199774 ps |
| CPU time | 263.94 seconds |
| Started | Jan 10 01:35:50 PM PST 24 |
| Finished | Jan 10 01:40:29 PM PST 24 |
| Peak memory | 555932 kb |
| Host | smart-767135a5-d425-40a8-a384-0cbb5499f576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582012676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2582012676 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.4233407863 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 5768650116 ps |
| CPU time | 628.4 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:52:00 PM PST 24 |
| Peak memory | 559920 kb |
| Host | smart-9d0ec944-6fbc-4650-a2a1-05b431ef4ba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233407863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.4233407863 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1789836580 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 13753485332 ps |
| CPU time | 459.6 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 01:51:37 PM PST 24 |
| Peak memory | 556316 kb |
| Host | smart-632a9e53-2181-4da4-94ed-83c4d3bbf5c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789836580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1789836580 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.911590787 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2378365242 ps |
| CPU time | 361.94 seconds |
| Started | Jan 10 01:45:56 PM PST 24 |
| Finished | Jan 10 01:52:01 PM PST 24 |
| Peak memory | 559772 kb |
| Host | smart-ed352417-46bd-4178-bd2f-58ae20db2eb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911590787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_reset_error.911590787 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.1751911439 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 1923903577 ps |
| CPU time | 64.64 seconds |
| Started | Jan 10 01:45:57 PM PST 24 |
| Finished | Jan 10 01:47:04 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-7d498a3f-9e18-4bb1-8503-3c59cfef8f39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751911439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.1751911439 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.3123330799 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4192362624 ps |
| CPU time | 459.71 seconds |
| Started | Jan 10 01:54:44 PM PST 24 |
| Finished | Jan 10 02:02:25 PM PST 24 |
| Peak memory | 602620 kb |
| Host | smart-4d081af6-084a-461d-9f46-47518130eb8a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3123330799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.3123330799 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.2421982732 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3069988046 ps |
| CPU time | 185.81 seconds |
| Started | Jan 10 01:56:31 PM PST 24 |
| Finished | Jan 10 01:59:39 PM PST 24 |
| Peak memory | 590872 kb |
| Host | smart-0f643d56-ffc0-4382-a6ea-095a2d11cff9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421982732 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2421982732 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1310449132 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4519659900 ps |
| CPU time | 695.42 seconds |
| Started | Jan 10 01:55:32 PM PST 24 |
| Finished | Jan 10 02:07:10 PM PST 24 |
| Peak memory | 602712 kb |
| Host | smart-eaed6afd-32d9-4b9c-97fb-7fb81df4ee67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13104 49132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1310449132 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2073064310 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4309431255 ps |
| CPU time | 580.42 seconds |
| Started | Jan 10 01:55:19 PM PST 24 |
| Finished | Jan 10 02:05:03 PM PST 24 |
| Peak memory | 593044 kb |
| Host | smart-c4855fa1-54df-4f21-a5f7-1741641da733 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073064310 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.2073064310 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.2601000931 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 5368108040 ps |
| CPU time | 899.33 seconds |
| Started | Jan 10 01:56:56 PM PST 24 |
| Finished | Jan 10 02:11:56 PM PST 24 |
| Peak memory | 599112 kb |
| Host | smart-2de322c2-48ab-4a6b-b0fc-b61a4b795bb2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601000931 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.2601000931 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2565340040 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 10452348417 ps |
| CPU time | 697.74 seconds |
| Started | Jan 10 02:01:03 PM PST 24 |
| Finished | Jan 10 02:12:43 PM PST 24 |
| Peak memory | 603736 kb |
| Host | smart-75d88449-61cf-4070-9398-63b51e55f69b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565340040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2565340040 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.651668047 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3363676387 ps |
| CPU time | 442.37 seconds |
| Started | Jan 10 01:57:30 PM PST 24 |
| Finished | Jan 10 02:04:53 PM PST 24 |
| Peak memory | 602344 kb |
| Host | smart-a7ed41cf-76b7-4584-b7cc-da738237971a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651668047 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.651668047 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1954866387 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 19993843153 ps |
| CPU time | 2899.4 seconds |
| Started | Jan 10 01:55:02 PM PST 24 |
| Finished | Jan 10 02:43:29 PM PST 24 |
| Peak memory | 603332 kb |
| Host | smart-5a129d83-95f7-4da1-9657-00856dcdfd7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954866387 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.1954866387 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2293641596 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5641779215 ps |
| CPU time | 232.91 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 01:39:59 PM PST 24 |
| Peak memory | 639184 kb |
| Host | smart-63fab637-f91a-4c5f-a344-5704da778f70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293641596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.2293641596 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.264558167 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 8196952600 ps |
| CPU time | 1819.51 seconds |
| Started | Jan 10 01:57:13 PM PST 24 |
| Finished | Jan 10 02:27:35 PM PST 24 |
| Peak memory | 602968 kb |
| Host | smart-78b60f14-7736-4b12-9cd1-4953e4ddbd09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264558167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a uto_mode.264558167 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1667390900 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 5478446102 ps |
| CPU time | 1174.77 seconds |
| Started | Jan 10 01:54:44 PM PST 24 |
| Finished | Jan 10 02:14:20 PM PST 24 |
| Peak memory | 603196 kb |
| Host | smart-a59fa909-50fc-430e-b23f-f1e9a18239b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667390900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.1667390900 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.384883123 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 4239060556 ps |
| CPU time | 507.89 seconds |
| Started | Jan 10 01:54:22 PM PST 24 |
| Finished | Jan 10 02:02:51 PM PST 24 |
| Peak memory | 603740 kb |
| Host | smart-941e03a8-f042-4044-960b-012fc448262c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384883 123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.384883123 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2885808607 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 16135325800 ps |
| CPU time | 3583.08 seconds |
| Started | Jan 10 01:54:57 PM PST 24 |
| Finished | Jan 10 02:54:48 PM PST 24 |
| Peak memory | 603264 kb |
| Host | smart-eb841b70-5a9b-43fe-a9aa-a639c28c5b5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858 08607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2885808607 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3065518026 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2472309800 ps |
| CPU time | 192.34 seconds |
| Started | Jan 10 02:01:21 PM PST 24 |
| Finished | Jan 10 02:04:39 PM PST 24 |
| Peak memory | 631160 kb |
| Host | smart-752871f0-8139-4189-afee-972b04d824f8 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065518026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.3065518026 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1542346163 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 24386759885 ps |
| CPU time | 3077.46 seconds |
| Started | Jan 10 02:05:01 PM PST 24 |
| Finished | Jan 10 02:56:26 PM PST 24 |
| Peak memory | 602924 kb |
| Host | smart-0fa7f995-2867-4963-8a3e-8f75969890ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542346163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1542346163 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.514994066 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 12168802720 ps |
| CPU time | 2397.26 seconds |
| Started | Jan 10 01:59:28 PM PST 24 |
| Finished | Jan 10 02:39:26 PM PST 24 |
| Peak memory | 602456 kb |
| Host | smart-f98454a0-74de-4438-b5bf-723091e1780a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_dev:4,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514994066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.514994066 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1958573668 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 28223684656 ps |
| CPU time | 4499.45 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 02:51:07 PM PST 24 |
| Peak memory | 580828 kb |
| Host | smart-8ca0670d-e94d-475b-8c66-86c1e8c331dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958573668 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.1958573668 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.101969899 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 13975950842 ps |
| CPU time | 1838.36 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 02:06:45 PM PST 24 |
| Peak memory | 580364 kb |
| Host | smart-74fbdb5b-500e-455a-a9ba-d3a0ff7b411a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101969899 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.101969899 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.583651497 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 4769370264 ps |
| CPU time | 203.39 seconds |
| Started | Jan 10 01:35:44 PM PST 24 |
| Finished | Jan 10 01:39:25 PM PST 24 |
| Peak memory | 614160 kb |
| Host | smart-dffb7caa-c9a1-49bf-97a5-b131d5008cf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583651497 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.583651497 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.94561387 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 4246077456 ps |
| CPU time | 350.09 seconds |
| Started | Jan 10 01:35:44 PM PST 24 |
| Finished | Jan 10 01:41:52 PM PST 24 |
| Peak memory | 580728 kb |
| Host | smart-b8c2eddd-d585-43b3-8315-7ee722f43a8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94561387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.94561387 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1733430755 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 13249815379 ps |
| CPU time | 500.52 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:44:30 PM PST 24 |
| Peak memory | 576444 kb |
| Host | smart-f62dd3ab-7920-4d21-9b01-e8190c85a279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733430755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1733430755 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3461924596 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 11682754408 ps |
| CPU time | 408.41 seconds |
| Started | Jan 10 01:35:45 PM PST 24 |
| Finished | Jan 10 01:42:50 PM PST 24 |
| Peak memory | 578280 kb |
| Host | smart-26f69e14-d126-4616-8274-7fdba5acd596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461924596 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.3461924596 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1401130899 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 14060372588 ps |
| CPU time | 1984.9 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 02:09:15 PM PST 24 |
| Peak memory | 580840 kb |
| Host | smart-debd86db-fdad-4761-b6fd-1086d0cccaae |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401130899 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1401130899 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.1050073114 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3019699200 ps |
| CPU time | 152.01 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 01:38:39 PM PST 24 |
| Peak memory | 580724 kb |
| Host | smart-3e6cbe45-2a04-4da9-99d4-9a154ab9738e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050073114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1050073114 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.874748902 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 935290362 ps |
| CPU time | 70.2 seconds |
| Started | Jan 10 01:35:59 PM PST 24 |
| Finished | Jan 10 01:37:21 PM PST 24 |
| Peak memory | 554800 kb |
| Host | smart-f7849789-cd63-4a9e-94de-df2fd558427a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874748902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.874748902 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2591009575 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 115668736296 ps |
| CPU time | 2225.65 seconds |
| Started | Jan 10 01:35:43 PM PST 24 |
| Finished | Jan 10 02:13:07 PM PST 24 |
| Peak memory | 556236 kb |
| Host | smart-08d7fe13-e706-4d47-a236-e5f0719b1be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591009575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.2591009575 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1836790817 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 108172571 ps |
| CPU time | 12.63 seconds |
| Started | Jan 10 01:35:47 PM PST 24 |
| Finished | Jan 10 01:36:16 PM PST 24 |
| Peak memory | 553784 kb |
| Host | smart-762b930b-d54c-4e5d-a976-7e1b0c47108c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836790817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .1836790817 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.2209108059 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 2469283607 ps |
| CPU time | 72.71 seconds |
| Started | Jan 10 01:35:46 PM PST 24 |
| Finished | Jan 10 01:37:16 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-2bc4db14-7e80-4555-bc2a-5db6c51165a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209108059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2209108059 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.1835499059 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 183112444 ps |
| CPU time | 15.15 seconds |
| Started | Jan 10 01:35:49 PM PST 24 |
| Finished | Jan 10 01:36:20 PM PST 24 |
| Peak memory | 554932 kb |
| Host | smart-879de8e4-b620-416b-bece-8fa457313533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835499059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.1835499059 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.666489091 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 34901365174 ps |
| CPU time | 372.83 seconds |
| Started | Jan 10 01:35:47 PM PST 24 |
| Finished | Jan 10 01:42:17 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-487024cc-b338-4a37-b5a9-5480379471e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666489091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.666489091 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.548791026 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 41286264432 ps |
| CPU time | 693.5 seconds |
| Started | Jan 10 01:35:47 PM PST 24 |
| Finished | Jan 10 01:47:37 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-88ea14dd-ae5d-4124-8a6f-36e693c07e63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548791026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.548791026 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1347215363 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 36159168 ps |
| CPU time | 5.83 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:36:11 PM PST 24 |
| Peak memory | 552652 kb |
| Host | smart-31919c54-fd36-4aff-ae1b-19aa57bf4f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347215363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.1347215363 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.1083955856 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1728377130 ps |
| CPU time | 50.61 seconds |
| Started | Jan 10 01:35:46 PM PST 24 |
| Finished | Jan 10 01:36:53 PM PST 24 |
| Peak memory | 555052 kb |
| Host | smart-d8c576ba-3524-4a20-8167-c53e9b18d107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083955856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1083955856 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.663517820 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 198365989 ps |
| CPU time | 8.45 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:36:17 PM PST 24 |
| Peak memory | 552916 kb |
| Host | smart-98fdb53a-9c34-4e41-beeb-2a05c4a064b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663517820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.663517820 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2404357183 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 6368765220 ps |
| CPU time | 68.16 seconds |
| Started | Jan 10 01:35:55 PM PST 24 |
| Finished | Jan 10 01:37:16 PM PST 24 |
| Peak memory | 552704 kb |
| Host | smart-e84d43d8-76a1-48d4-9b2c-b0d050fa00f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404357183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2404357183 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1421462013 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 3744847246 ps |
| CPU time | 61.38 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:37:07 PM PST 24 |
| Peak memory | 552676 kb |
| Host | smart-85283645-ab9a-49df-b928-be5606892415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421462013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.1421462013 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2528390167 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 44814192 ps |
| CPU time | 5.95 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 01:36:13 PM PST 24 |
| Peak memory | 552660 kb |
| Host | smart-1040814a-5bfc-4185-b496-400b48fbf80c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528390167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .2528390167 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1472605789 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 13955284951 ps |
| CPU time | 606.05 seconds |
| Started | Jan 10 01:35:45 PM PST 24 |
| Finished | Jan 10 01:46:08 PM PST 24 |
| Peak memory | 556248 kb |
| Host | smart-c5ba0903-fefd-4dce-a31b-200a05cc27f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472605789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1472605789 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1798935898 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 285374475 ps |
| CPU time | 118.51 seconds |
| Started | Jan 10 01:35:41 PM PST 24 |
| Finished | Jan 10 01:37:59 PM PST 24 |
| Peak memory | 555968 kb |
| Host | smart-0d89041a-be5e-4a95-8d47-5f11ffb0da4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798935898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.1798935898 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2389786135 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 603818150 ps |
| CPU time | 26.64 seconds |
| Started | Jan 10 01:35:45 PM PST 24 |
| Finished | Jan 10 01:36:29 PM PST 24 |
| Peak memory | 554948 kb |
| Host | smart-83870198-eb64-4628-b483-89840b73ff77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389786135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2389786135 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2088473384 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 27962247768 ps |
| CPU time | 4115.32 seconds |
| Started | Jan 10 01:35:42 PM PST 24 |
| Finished | Jan 10 02:44:36 PM PST 24 |
| Peak memory | 580812 kb |
| Host | smart-e7fe49cf-7843-4f97-b4b6-a0c6bdaba782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088473384 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.2088473384 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2246685530 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 5353935839 ps |
| CPU time | 502 seconds |
| Started | Jan 10 01:35:44 PM PST 24 |
| Finished | Jan 10 01:44:24 PM PST 24 |
| Peak memory | 580784 kb |
| Host | smart-072145c6-6a06-4290-80c5-7ca584bdeb60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246685530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2246685530 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3387155714 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 6812963162 ps |
| CPU time | 381.17 seconds |
| Started | Jan 10 01:35:42 PM PST 24 |
| Finished | Jan 10 01:42:22 PM PST 24 |
| Peak memory | 633204 kb |
| Host | smart-c9295f05-a353-4341-90a5-94c0cea8fcb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387155714 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.3387155714 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.2066663200 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 3961420264 ps |
| CPU time | 311.63 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 01:41:18 PM PST 24 |
| Peak memory | 580872 kb |
| Host | smart-2101dfbe-0a88-474b-9866-64480243e298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066663200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.2066663200 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3547697188 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 6789448486 ps |
| CPU time | 207.64 seconds |
| Started | Jan 10 01:35:45 PM PST 24 |
| Finished | Jan 10 01:39:30 PM PST 24 |
| Peak memory | 576760 kb |
| Host | smart-869063c1-9ed4-422e-b7df-1bd468b1e988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547697188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.3547697188 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1974157715 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 5942274665 ps |
| CPU time | 268.29 seconds |
| Started | Jan 10 01:35:42 PM PST 24 |
| Finished | Jan 10 01:40:29 PM PST 24 |
| Peak memory | 578164 kb |
| Host | smart-c42f7502-154f-4393-b7f6-ada10f885aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974157715 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.1974157715 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1214767550 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 15887192656 ps |
| CPU time | 2115.15 seconds |
| Started | Jan 10 01:35:44 PM PST 24 |
| Finished | Jan 10 02:11:17 PM PST 24 |
| Peak memory | 580860 kb |
| Host | smart-90b69fde-e5b0-4290-81dc-264535292ef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214767550 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.1214767550 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.1053305557 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 3477314250 ps |
| CPU time | 187.2 seconds |
| Started | Jan 10 01:35:46 PM PST 24 |
| Finished | Jan 10 01:39:10 PM PST 24 |
| Peak memory | 580784 kb |
| Host | smart-6c01aeb0-9488-4dd1-af1f-f99d9c80ed8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053305557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.1053305557 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.2586636420 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 584156150 ps |
| CPU time | 26.24 seconds |
| Started | Jan 10 01:35:47 PM PST 24 |
| Finished | Jan 10 01:36:30 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-54a65439-326f-423e-b7ea-c039ab43dcc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586636420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 2586636420 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.576906982 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 60238539892 ps |
| CPU time | 1093.71 seconds |
| Started | Jan 10 01:35:47 PM PST 24 |
| Finished | Jan 10 01:54:17 PM PST 24 |
| Peak memory | 554852 kb |
| Host | smart-ce1eb658-4ca0-42db-867d-fc3fe09f1a0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576906982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_de vice_slow_rsp.576906982 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2982541234 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 195009410 ps |
| CPU time | 20.28 seconds |
| Started | Jan 10 01:35:48 PM PST 24 |
| Finished | Jan 10 01:36:24 PM PST 24 |
| Peak memory | 554696 kb |
| Host | smart-be83e921-def5-4db3-8f8a-d39c0e45c2b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982541234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .2982541234 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.3647460213 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 153092091 ps |
| CPU time | 8.32 seconds |
| Started | Jan 10 01:35:48 PM PST 24 |
| Finished | Jan 10 01:36:12 PM PST 24 |
| Peak memory | 552644 kb |
| Host | smart-b286e807-840c-4a2e-a250-adbdeec53faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647460213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3647460213 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.1086342056 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2486523320 ps |
| CPU time | 88.59 seconds |
| Started | Jan 10 01:35:43 PM PST 24 |
| Finished | Jan 10 01:37:30 PM PST 24 |
| Peak memory | 554852 kb |
| Host | smart-c06d4b7f-f7c8-4928-8644-9d1e8e39b3f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086342056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1086342056 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3780032667 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 22875293297 ps |
| CPU time | 231.52 seconds |
| Started | Jan 10 01:35:45 PM PST 24 |
| Finished | Jan 10 01:39:53 PM PST 24 |
| Peak memory | 554824 kb |
| Host | smart-12c75efb-91b0-4173-9837-7ab97815c5bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780032667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3780032667 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2929063268 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 11247558591 ps |
| CPU time | 201.13 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:39:27 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-6a819212-1fcd-499f-b899-2983449ef934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929063268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2929063268 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2430282390 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 61606457 ps |
| CPU time | 7.76 seconds |
| Started | Jan 10 01:35:46 PM PST 24 |
| Finished | Jan 10 01:36:11 PM PST 24 |
| Peak memory | 552744 kb |
| Host | smart-48d80818-c85f-4f56-a5c8-7121e75b43f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430282390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.2430282390 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.931046444 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 1448360454 ps |
| CPU time | 44.02 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:36:49 PM PST 24 |
| Peak memory | 554784 kb |
| Host | smart-72576957-64c4-4014-b33e-9a511d7d8b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931046444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.931046444 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.3425409019 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 215196108 ps |
| CPU time | 8.65 seconds |
| Started | Jan 10 01:35:46 PM PST 24 |
| Finished | Jan 10 01:36:11 PM PST 24 |
| Peak memory | 552724 kb |
| Host | smart-b49ef139-d6bf-480e-8493-9f76351b7cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425409019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3425409019 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2576618907 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 8712366935 ps |
| CPU time | 88.37 seconds |
| Started | Jan 10 01:35:45 PM PST 24 |
| Finished | Jan 10 01:37:30 PM PST 24 |
| Peak memory | 552524 kb |
| Host | smart-942c3eee-9bb6-4268-adee-168cf8159eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576618907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2576618907 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2902729155 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 5662794971 ps |
| CPU time | 99.07 seconds |
| Started | Jan 10 01:35:45 PM PST 24 |
| Finished | Jan 10 01:37:41 PM PST 24 |
| Peak memory | 553048 kb |
| Host | smart-c1185d4b-a180-4a53-80d3-c0b8b640897f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902729155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.2902729155 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.345336143 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 57810877 ps |
| CPU time | 6.44 seconds |
| Started | Jan 10 01:35:46 PM PST 24 |
| Finished | Jan 10 01:36:10 PM PST 24 |
| Peak memory | 552984 kb |
| Host | smart-d0ea0721-1703-4bc5-9b6a-3f177d4bdad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345336143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 345336143 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.1225654822 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 6145570867 ps |
| CPU time | 188.33 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:39:14 PM PST 24 |
| Peak memory | 555260 kb |
| Host | smart-b510d508-55d0-4299-8ea1-250707449ac5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225654822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.1225654822 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.387515548 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 1533273085 ps |
| CPU time | 106.17 seconds |
| Started | Jan 10 01:35:48 PM PST 24 |
| Finished | Jan 10 01:37:50 PM PST 24 |
| Peak memory | 555816 kb |
| Host | smart-4e4a34dd-16fa-4ed5-9060-d3c2b1820d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387515548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.387515548 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2845668217 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 300592976 ps |
| CPU time | 104.15 seconds |
| Started | Jan 10 01:35:49 PM PST 24 |
| Finished | Jan 10 01:37:49 PM PST 24 |
| Peak memory | 555608 kb |
| Host | smart-a6e052ae-70ff-441a-8dff-7577f9351506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845668217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2845668217 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3404932859 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 10523281079 ps |
| CPU time | 481.28 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 01:44:08 PM PST 24 |
| Peak memory | 558864 kb |
| Host | smart-3dea27eb-0af8-473a-8f60-4b575cb62c4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404932859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.3404932859 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1656600056 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 345532901 ps |
| CPU time | 15.76 seconds |
| Started | Jan 10 01:35:46 PM PST 24 |
| Finished | Jan 10 01:36:19 PM PST 24 |
| Peak memory | 554760 kb |
| Host | smart-75fb9c9f-61c0-4705-80ae-cd39e18beeb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656600056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1656600056 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1477968148 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 9650989554 ps |
| CPU time | 379.76 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:43:02 PM PST 24 |
| Peak memory | 630024 kb |
| Host | smart-2bfb2a78-d425-4917-96b9-a4e6df5bb907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477968148 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.1477968148 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2089393754 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 4363023784 ps |
| CPU time | 292.02 seconds |
| Started | Jan 10 01:36:40 PM PST 24 |
| Finished | Jan 10 01:41:35 PM PST 24 |
| Peak memory | 580892 kb |
| Host | smart-4b1cbde8-e606-4dfb-94b2-fc3f92206847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089393754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2089393754 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1036620150 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 2185563077 ps |
| CPU time | 85.06 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:38:09 PM PST 24 |
| Peak memory | 555136 kb |
| Host | smart-173c0783-3b98-4dc1-910e-bb4b504ffd84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036620150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1036620150 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1863061210 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 137818517154 ps |
| CPU time | 2268.98 seconds |
| Started | Jan 10 01:36:43 PM PST 24 |
| Finished | Jan 10 02:14:35 PM PST 24 |
| Peak memory | 555904 kb |
| Host | smart-15ed9b92-651b-4a60-8d5a-0595f190d48d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863061210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.1863061210 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3607598840 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 121805810 ps |
| CPU time | 12.95 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:36:56 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-de9b5ae6-a9ad-43df-9351-8457dc85e171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607598840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.3607598840 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.2529932015 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 100396901 ps |
| CPU time | 10.06 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:36:52 PM PST 24 |
| Peak memory | 553852 kb |
| Host | smart-2688386d-2030-450f-add3-3927426b894f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529932015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2529932015 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.1034284323 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 570379123 ps |
| CPU time | 49.86 seconds |
| Started | Jan 10 01:36:36 PM PST 24 |
| Finished | Jan 10 01:37:28 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-7b1f5e2d-dce4-4fcb-990f-a757749b3fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034284323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1034284323 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1528564664 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 74254469143 ps |
| CPU time | 770.34 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:49:30 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-baaaa303-8b21-4ac1-a936-d875f6abb005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528564664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1528564664 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1599588865 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 64070723991 ps |
| CPU time | 1119.99 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:55:23 PM PST 24 |
| Peak memory | 555132 kb |
| Host | smart-708fce34-e585-45d0-b945-23b5338a9dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599588865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1599588865 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4050560892 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 153193630 ps |
| CPU time | 15.92 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:36:56 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-ddd8f1dc-9c95-435a-908e-e627b4f76734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050560892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.4050560892 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.2021096674 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 487063072 ps |
| CPU time | 35.09 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:37:18 PM PST 24 |
| Peak memory | 554776 kb |
| Host | smart-92b0b1f3-e4bd-4065-88b4-32e33718cc59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021096674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2021096674 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.566562402 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 187472284 ps |
| CPU time | 7.79 seconds |
| Started | Jan 10 01:36:35 PM PST 24 |
| Finished | Jan 10 01:36:45 PM PST 24 |
| Peak memory | 552704 kb |
| Host | smart-94a8e1da-2162-466e-baaf-1a47b6686563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566562402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.566562402 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.155537242 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 9083693966 ps |
| CPU time | 94 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:38:13 PM PST 24 |
| Peak memory | 552944 kb |
| Host | smart-d288fd62-6a33-4683-a1e0-a3918017e618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155537242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.155537242 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2259297840 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 5935410053 ps |
| CPU time | 97.11 seconds |
| Started | Jan 10 01:36:37 PM PST 24 |
| Finished | Jan 10 01:38:15 PM PST 24 |
| Peak memory | 552696 kb |
| Host | smart-c506a7e8-8491-4e41-80af-609e5987a6ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259297840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2259297840 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.4246528454 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 43867119 ps |
| CPU time | 5.6 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:36:47 PM PST 24 |
| Peak memory | 552584 kb |
| Host | smart-36ecd500-73f9-4fe0-9164-486ff62aec84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246528454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.4246528454 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.364103211 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 734281177 ps |
| CPU time | 47.15 seconds |
| Started | Jan 10 01:36:43 PM PST 24 |
| Finished | Jan 10 01:37:33 PM PST 24 |
| Peak memory | 555900 kb |
| Host | smart-2e097d96-9ba8-48fe-a5c6-14a53f95052a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364103211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.364103211 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2612536673 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 2996454631 ps |
| CPU time | 90.23 seconds |
| Started | Jan 10 01:36:43 PM PST 24 |
| Finished | Jan 10 01:38:16 PM PST 24 |
| Peak memory | 556148 kb |
| Host | smart-2985bb67-4ed8-4366-b7f3-65bf28acf92a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612536673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2612536673 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.237664509 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 54465138 ps |
| CPU time | 8.57 seconds |
| Started | Jan 10 01:36:41 PM PST 24 |
| Finished | Jan 10 01:36:52 PM PST 24 |
| Peak memory | 552908 kb |
| Host | smart-6c8e700c-6d75-4ac8-8851-e7b726b1140c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237664509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.237664509 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2862120319 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 7630081012 ps |
| CPU time | 324.25 seconds |
| Started | Jan 10 01:36:50 PM PST 24 |
| Finished | Jan 10 01:42:16 PM PST 24 |
| Peak memory | 627764 kb |
| Host | smart-a81ad047-af77-4be6-9312-0e0e5ead9893 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862120319 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.2862120319 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.3009573196 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2891811080 ps |
| CPU time | 185.25 seconds |
| Started | Jan 10 01:36:41 PM PST 24 |
| Finished | Jan 10 01:39:49 PM PST 24 |
| Peak memory | 580572 kb |
| Host | smart-782e896f-990c-4814-a1f2-17f08ae77407 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009573196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.3009573196 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.700320542 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 789346144 ps |
| CPU time | 49.02 seconds |
| Started | Jan 10 01:36:49 PM PST 24 |
| Finished | Jan 10 01:37:39 PM PST 24 |
| Peak memory | 555092 kb |
| Host | smart-4180596c-b4e2-4e5a-a443-787f29e8ed2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700320542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device. 700320542 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.337835076 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 18324738941 ps |
| CPU time | 314.34 seconds |
| Started | Jan 10 01:36:43 PM PST 24 |
| Finished | Jan 10 01:42:00 PM PST 24 |
| Peak memory | 555856 kb |
| Host | smart-07464da8-18e0-4905-bd4a-6de2e0bbbba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337835076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_d evice_slow_rsp.337835076 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3167392272 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 23025118 ps |
| CPU time | 4.82 seconds |
| Started | Jan 10 01:36:46 PM PST 24 |
| Finished | Jan 10 01:36:52 PM PST 24 |
| Peak memory | 552564 kb |
| Host | smart-c066b312-ca77-4321-81da-8c06f7ccbde5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167392272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3167392272 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.81772390 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 2299430027 ps |
| CPU time | 69.22 seconds |
| Started | Jan 10 01:36:41 PM PST 24 |
| Finished | Jan 10 01:37:53 PM PST 24 |
| Peak memory | 554708 kb |
| Host | smart-7b984f19-2a87-499b-b22c-bed2736cfb0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81772390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.81772390 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.3915847686 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 2464510583 ps |
| CPU time | 84.04 seconds |
| Started | Jan 10 01:36:41 PM PST 24 |
| Finished | Jan 10 01:38:07 PM PST 24 |
| Peak memory | 554860 kb |
| Host | smart-15ba9a87-8795-4832-b56d-cc5f530f1359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915847686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.3915847686 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2868954675 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 72202912272 ps |
| CPU time | 778.04 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:49:40 PM PST 24 |
| Peak memory | 553960 kb |
| Host | smart-560fd387-30b6-4b0a-8fc6-e278b707280a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868954675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2868954675 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.614230882 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 19914176026 ps |
| CPU time | 303.49 seconds |
| Started | Jan 10 01:36:43 PM PST 24 |
| Finished | Jan 10 01:41:49 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-fd623467-206b-4cba-917c-12c348f07b73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614230882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.614230882 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3955376080 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 538749956 ps |
| CPU time | 47.43 seconds |
| Started | Jan 10 01:36:40 PM PST 24 |
| Finished | Jan 10 01:37:30 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-f6fc074d-6208-4532-9021-1ffeed9a5079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955376080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.3955376080 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.1086171885 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 444837729 ps |
| CPU time | 30.43 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:37:15 PM PST 24 |
| Peak memory | 554820 kb |
| Host | smart-46a60a95-8c5a-4dc9-9493-a7b4554c42ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086171885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1086171885 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.785746531 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 44115832 ps |
| CPU time | 6.21 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:36:51 PM PST 24 |
| Peak memory | 552956 kb |
| Host | smart-ba52e4f2-9e0f-45b2-b0d7-bb397bccfcbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785746531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.785746531 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3276838655 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 9765926620 ps |
| CPU time | 94.08 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:38:19 PM PST 24 |
| Peak memory | 552708 kb |
| Host | smart-dfaefdce-359a-4995-9620-1b385544846d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276838655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3276838655 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2229618048 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 3435980452 ps |
| CPU time | 53.42 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:37:34 PM PST 24 |
| Peak memory | 553000 kb |
| Host | smart-db675667-8fb3-4ec1-b9f1-905e0d0dcf6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229618048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.2229618048 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3759302092 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 45811952 ps |
| CPU time | 5.91 seconds |
| Started | Jan 10 01:36:43 PM PST 24 |
| Finished | Jan 10 01:36:51 PM PST 24 |
| Peak memory | 552712 kb |
| Host | smart-d7184bc9-7f42-4f82-aef0-ee840ff68e64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759302092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.3759302092 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.395436468 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 6613832067 ps |
| CPU time | 225.3 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:40:30 PM PST 24 |
| Peak memory | 556228 kb |
| Host | smart-180eeb6f-43b8-463a-bf0d-58244f874179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395436468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.395436468 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2952107394 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 2053914117 ps |
| CPU time | 68.27 seconds |
| Started | Jan 10 01:36:41 PM PST 24 |
| Finished | Jan 10 01:37:52 PM PST 24 |
| Peak memory | 556060 kb |
| Host | smart-ac7d023e-9d96-44ef-b979-60ae02cf7aca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952107394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2952107394 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1548683023 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 272751621 ps |
| CPU time | 87.85 seconds |
| Started | Jan 10 01:36:47 PM PST 24 |
| Finished | Jan 10 01:38:16 PM PST 24 |
| Peak memory | 555120 kb |
| Host | smart-c4645542-42db-4cb2-b1e5-909a52a04d13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548683023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.1548683023 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.208809675 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 336005770 ps |
| CPU time | 34.24 seconds |
| Started | Jan 10 01:36:41 PM PST 24 |
| Finished | Jan 10 01:37:18 PM PST 24 |
| Peak memory | 554704 kb |
| Host | smart-2bbb9d77-8294-42de-a1b7-cd1b78663c9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208809675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.208809675 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.4264341156 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 5478918880 ps |
| CPU time | 237.72 seconds |
| Started | Jan 10 01:36:45 PM PST 24 |
| Finished | Jan 10 01:40:45 PM PST 24 |
| Peak memory | 622464 kb |
| Host | smart-5fd25740-27e9-4c5c-99c9-6c64dce5fe3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264341156 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.4264341156 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.4093662328 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 5933476848 ps |
| CPU time | 559.11 seconds |
| Started | Jan 10 01:36:45 PM PST 24 |
| Finished | Jan 10 01:46:06 PM PST 24 |
| Peak memory | 580788 kb |
| Host | smart-ff4810af-ae32-4400-9458-349b9587c8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093662328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.4093662328 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.695851111 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 16009728568 ps |
| CPU time | 1646.84 seconds |
| Started | Jan 10 01:36:41 PM PST 24 |
| Finished | Jan 10 02:04:11 PM PST 24 |
| Peak memory | 580824 kb |
| Host | smart-1ef4dfbe-3864-4fc6-9ef5-f4cc71309699 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695851111 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.chip_same_csr_outstanding.695851111 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.3407747586 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1017942784 ps |
| CPU time | 41.08 seconds |
| Started | Jan 10 01:36:46 PM PST 24 |
| Finished | Jan 10 01:37:28 PM PST 24 |
| Peak memory | 554784 kb |
| Host | smart-61d73fb5-9936-40f3-b2f9-c1dbf4550e0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407747586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .3407747586 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1548312582 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 3211625041 ps |
| CPU time | 52.06 seconds |
| Started | Jan 10 01:36:50 PM PST 24 |
| Finished | Jan 10 01:37:44 PM PST 24 |
| Peak memory | 554072 kb |
| Host | smart-ac185b0f-0e5a-4503-983d-65976d3129f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548312582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.1548312582 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2908347394 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 989814711 ps |
| CPU time | 40.08 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:37:25 PM PST 24 |
| Peak memory | 553816 kb |
| Host | smart-7171d0f5-64eb-447e-bef5-b57caf7ce2c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908347394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.2908347394 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.2689429705 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 249255056 ps |
| CPU time | 11.42 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:36:56 PM PST 24 |
| Peak memory | 552880 kb |
| Host | smart-d89d54d1-4e63-49b1-87cc-d16690e94de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689429705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2689429705 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.824302316 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 944243614 ps |
| CPU time | 30.02 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:37:15 PM PST 24 |
| Peak memory | 555004 kb |
| Host | smart-1d4e05ce-a6af-4d7e-912f-b5f6747f8a74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824302316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.824302316 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3481023775 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 103007868719 ps |
| CPU time | 1053 seconds |
| Started | Jan 10 01:36:41 PM PST 24 |
| Finished | Jan 10 01:54:17 PM PST 24 |
| Peak memory | 555188 kb |
| Host | smart-a40c8403-f290-4951-a93c-ce4eb4f389dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481023775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3481023775 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3255802402 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 59940644751 ps |
| CPU time | 1093.74 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:54:55 PM PST 24 |
| Peak memory | 554824 kb |
| Host | smart-fa6caaa0-d539-44ff-bf39-6cb6540861b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255802402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.3255802402 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2025027846 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 578939412 ps |
| CPU time | 48.81 seconds |
| Started | Jan 10 01:36:45 PM PST 24 |
| Finished | Jan 10 01:37:35 PM PST 24 |
| Peak memory | 554680 kb |
| Host | smart-46276c16-0859-401d-bca6-6dcf5b7fb879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025027846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.2025027846 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.3165587788 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 636643312 ps |
| CPU time | 22.3 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:37:05 PM PST 24 |
| Peak memory | 554756 kb |
| Host | smart-1d179d7d-eab4-43e0-9035-953200497ec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165587788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3165587788 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.2485852107 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 206417230 ps |
| CPU time | 8.66 seconds |
| Started | Jan 10 01:36:50 PM PST 24 |
| Finished | Jan 10 01:37:00 PM PST 24 |
| Peak memory | 552988 kb |
| Host | smart-83d8571a-a500-4d75-a8d4-524dffccdfc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485852107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.2485852107 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3323590072 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 8241680849 ps |
| CPU time | 87.9 seconds |
| Started | Jan 10 01:36:50 PM PST 24 |
| Finished | Jan 10 01:38:20 PM PST 24 |
| Peak memory | 552768 kb |
| Host | smart-ddc7745f-31a8-4d45-b889-b48faa343ddc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323590072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3323590072 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2884328969 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 4426707457 ps |
| CPU time | 73.91 seconds |
| Started | Jan 10 01:36:45 PM PST 24 |
| Finished | Jan 10 01:38:01 PM PST 24 |
| Peak memory | 552684 kb |
| Host | smart-c02537a9-7660-406d-ac89-ff4efdf8cf67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884328969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2884328969 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.4152797284 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 43258190 ps |
| CPU time | 5.8 seconds |
| Started | Jan 10 01:36:47 PM PST 24 |
| Finished | Jan 10 01:36:54 PM PST 24 |
| Peak memory | 551452 kb |
| Host | smart-e8011011-1468-4756-a68b-5939c14a20c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152797284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.4152797284 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4002652412 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 2291811232 ps |
| CPU time | 146.56 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:39:09 PM PST 24 |
| Peak memory | 556328 kb |
| Host | smart-83451c41-cf19-4634-a0e9-996cb1d7118c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002652412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.4002652412 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4022390558 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 158186199 ps |
| CPU time | 47.94 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:37:31 PM PST 24 |
| Peak memory | 555404 kb |
| Host | smart-fa8d037a-926f-478d-8004-b17bb9813b97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022390558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.4022390558 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1775924285 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 645050505 ps |
| CPU time | 88.82 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:38:13 PM PST 24 |
| Peak memory | 556192 kb |
| Host | smart-358e17d6-c2fc-4d07-9dd2-9f82ab9b6c6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775924285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1775924285 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2374353190 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 345210572 ps |
| CPU time | 36.56 seconds |
| Started | Jan 10 01:36:41 PM PST 24 |
| Finished | Jan 10 01:37:21 PM PST 24 |
| Peak memory | 555060 kb |
| Host | smart-81e31ac0-e24f-47df-9cb7-6dcadbbf66df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374353190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2374353190 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.878325676 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 6140999075 ps |
| CPU time | 197.23 seconds |
| Started | Jan 10 01:37:15 PM PST 24 |
| Finished | Jan 10 01:40:51 PM PST 24 |
| Peak memory | 613488 kb |
| Host | smart-f4ca42c6-696d-4a23-a0e3-d6cfd1227938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878325676 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.878325676 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.2872200311 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 5397728849 ps |
| CPU time | 555.48 seconds |
| Started | Jan 10 01:37:31 PM PST 24 |
| Finished | Jan 10 01:46:58 PM PST 24 |
| Peak memory | 580800 kb |
| Host | smart-e5a67836-31ad-4ffa-a177-236b7cb7029b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872200311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2872200311 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.24590086 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 15401337192 ps |
| CPU time | 2131.71 seconds |
| Started | Jan 10 01:36:47 PM PST 24 |
| Finished | Jan 10 02:12:20 PM PST 24 |
| Peak memory | 580808 kb |
| Host | smart-1aac0b09-892d-4baa-b9ee-b692df2202ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24590086 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.chip_same_csr_outstanding.24590086 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2492863021 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 3076143867 ps |
| CPU time | 180.04 seconds |
| Started | Jan 10 01:36:49 PM PST 24 |
| Finished | Jan 10 01:39:50 PM PST 24 |
| Peak memory | 580848 kb |
| Host | smart-a73ac4ac-04fb-41a3-a940-aa890a2f4465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492863021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.2492863021 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2008264864 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 343810950 ps |
| CPU time | 14.5 seconds |
| Started | Jan 10 01:36:53 PM PST 24 |
| Finished | Jan 10 01:37:09 PM PST 24 |
| Peak memory | 553760 kb |
| Host | smart-ab666137-c672-4c61-ad3d-f2797211c2ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008264864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .2008264864 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2836132934 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 150364139995 ps |
| CPU time | 2440.17 seconds |
| Started | Jan 10 01:36:51 PM PST 24 |
| Finished | Jan 10 02:17:33 PM PST 24 |
| Peak memory | 555888 kb |
| Host | smart-8ed82350-e8bc-4f84-a5ef-e3c67a9d4c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836132934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.2836132934 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3685703248 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 222370702 ps |
| CPU time | 23.64 seconds |
| Started | Jan 10 01:37:18 PM PST 24 |
| Finished | Jan 10 01:37:59 PM PST 24 |
| Peak memory | 554760 kb |
| Host | smart-19966ce5-e6a5-43fe-a871-dcfbddef3ea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685703248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.3685703248 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.645484110 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 2562053769 ps |
| CPU time | 89.58 seconds |
| Started | Jan 10 01:36:52 PM PST 24 |
| Finished | Jan 10 01:38:23 PM PST 24 |
| Peak memory | 554724 kb |
| Host | smart-8d37f47c-d305-4e4f-9545-e53adfea07a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645484110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.645484110 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.2957716724 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 2397360018 ps |
| CPU time | 76.46 seconds |
| Started | Jan 10 01:36:45 PM PST 24 |
| Finished | Jan 10 01:38:03 PM PST 24 |
| Peak memory | 554828 kb |
| Host | smart-1cacd90a-8ffc-40aa-9a65-58fcdc194822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957716724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.2957716724 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1128745369 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 81918802650 ps |
| CPU time | 854.06 seconds |
| Started | Jan 10 01:36:50 PM PST 24 |
| Finished | Jan 10 01:51:05 PM PST 24 |
| Peak memory | 555136 kb |
| Host | smart-cb7f2b55-b3a6-4cd2-b72c-5ac9edf9e48b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128745369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1128745369 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1856352275 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 31333414889 ps |
| CPU time | 534.5 seconds |
| Started | Jan 10 01:36:50 PM PST 24 |
| Finished | Jan 10 01:45:47 PM PST 24 |
| Peak memory | 555120 kb |
| Host | smart-cd68d5f5-5605-4be6-800e-5a86f876fec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856352275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1856352275 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.337780661 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 583564159 ps |
| CPU time | 47.97 seconds |
| Started | Jan 10 01:36:51 PM PST 24 |
| Finished | Jan 10 01:37:41 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-b6c24c2c-4181-4bae-ba14-d96aa81f7c98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337780661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_dela ys.337780661 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.3139231694 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 1216689470 ps |
| CPU time | 35.03 seconds |
| Started | Jan 10 01:36:50 PM PST 24 |
| Finished | Jan 10 01:37:26 PM PST 24 |
| Peak memory | 554752 kb |
| Host | smart-6d60c167-1e7b-4c2d-bebc-cbbb24714253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139231694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3139231694 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.2877813596 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 149794570 ps |
| CPU time | 7.06 seconds |
| Started | Jan 10 01:36:47 PM PST 24 |
| Finished | Jan 10 01:36:55 PM PST 24 |
| Peak memory | 552684 kb |
| Host | smart-f4f463fc-bd7f-4c79-8742-f9eeb588d1b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877813596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.2877813596 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3699575504 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 7646961758 ps |
| CPU time | 82.62 seconds |
| Started | Jan 10 01:36:48 PM PST 24 |
| Finished | Jan 10 01:38:12 PM PST 24 |
| Peak memory | 552828 kb |
| Host | smart-aef16c41-8877-4afb-877c-76fe87cf5b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699575504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3699575504 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3113474198 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 3943707355 ps |
| CPU time | 62.23 seconds |
| Started | Jan 10 01:36:51 PM PST 24 |
| Finished | Jan 10 01:37:55 PM PST 24 |
| Peak memory | 552944 kb |
| Host | smart-9b2c3fcb-c8e6-4c01-bc31-0de135ffe3bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113474198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.3113474198 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1639851897 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 42033876 ps |
| CPU time | 5.46 seconds |
| Started | Jan 10 01:36:50 PM PST 24 |
| Finished | Jan 10 01:36:56 PM PST 24 |
| Peak memory | 552956 kb |
| Host | smart-6c2be0af-d7f4-425a-96f6-77e00e40b988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639851897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.1639851897 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.1719034538 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 6297095479 ps |
| CPU time | 245.62 seconds |
| Started | Jan 10 01:37:17 PM PST 24 |
| Finished | Jan 10 01:41:41 PM PST 24 |
| Peak memory | 556236 kb |
| Host | smart-1860ca9c-c09b-461e-8e1e-2ed605f0f06f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719034538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1719034538 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1762545351 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 2480153232 ps |
| CPU time | 78.91 seconds |
| Started | Jan 10 01:37:28 PM PST 24 |
| Finished | Jan 10 01:38:59 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-14d2889d-33cd-4c63-827a-6b58de8a7ba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762545351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1762545351 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.81714299 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 4971092499 ps |
| CPU time | 368.62 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:43:53 PM PST 24 |
| Peak memory | 558376 kb |
| Host | smart-a4710a81-3c8a-465a-a0c8-781938ddc4c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81714299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_w ith_rand_reset.81714299 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1484546433 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 229597881 ps |
| CPU time | 56.36 seconds |
| Started | Jan 10 01:37:58 PM PST 24 |
| Finished | Jan 10 01:39:00 PM PST 24 |
| Peak memory | 555812 kb |
| Host | smart-8cc80ee9-b224-43cc-8b6b-30a40d71cb7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484546433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.1484546433 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1611051059 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 265120177 ps |
| CPU time | 32.51 seconds |
| Started | Jan 10 01:37:32 PM PST 24 |
| Finished | Jan 10 01:38:15 PM PST 24 |
| Peak memory | 554740 kb |
| Host | smart-09e82d27-34b2-4857-b5e1-ee09f4f62cbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611051059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1611051059 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2174280029 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 4870354466 ps |
| CPU time | 229.26 seconds |
| Started | Jan 10 01:37:46 PM PST 24 |
| Finished | Jan 10 01:41:39 PM PST 24 |
| Peak memory | 613572 kb |
| Host | smart-3fd64adf-41d8-4a70-bc0d-380e6a9e89a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174280029 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.2174280029 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.539089344 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 4581279360 ps |
| CPU time | 348.33 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:43:55 PM PST 24 |
| Peak memory | 580816 kb |
| Host | smart-8a651892-4030-46cc-a372-442a228c8f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539089344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.539089344 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.759798068 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 16289720562 ps |
| CPU time | 2104.07 seconds |
| Started | Jan 10 01:37:16 PM PST 24 |
| Finished | Jan 10 02:12:39 PM PST 24 |
| Peak memory | 580864 kb |
| Host | smart-79ede018-dd3b-45ec-890d-042a6d53c897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759798068 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.chip_same_csr_outstanding.759798068 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2624666305 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 1782694053 ps |
| CPU time | 80.36 seconds |
| Started | Jan 10 01:37:58 PM PST 24 |
| Finished | Jan 10 01:39:23 PM PST 24 |
| Peak memory | 556076 kb |
| Host | smart-1e2b0629-4675-411e-9a9d-96c0484965e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624666305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .2624666305 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3026618442 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3160854704 ps |
| CPU time | 50.98 seconds |
| Started | Jan 10 01:37:51 PM PST 24 |
| Finished | Jan 10 01:38:47 PM PST 24 |
| Peak memory | 552772 kb |
| Host | smart-ecdbb522-abfd-4ae7-b7ae-a0a4b9078725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026618442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3026618442 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3003666056 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 74224627 ps |
| CPU time | 9.78 seconds |
| Started | Jan 10 01:37:16 PM PST 24 |
| Finished | Jan 10 01:37:44 PM PST 24 |
| Peak memory | 554964 kb |
| Host | smart-b8fa311e-57fe-478e-826e-33badefccb81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003666056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.3003666056 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.4256369688 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 221269805 ps |
| CPU time | 18.3 seconds |
| Started | Jan 10 01:37:55 PM PST 24 |
| Finished | Jan 10 01:38:18 PM PST 24 |
| Peak memory | 554972 kb |
| Host | smart-18101758-8982-4c4d-8f11-ec4a1806a845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256369688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.4256369688 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.312571785 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 425885683 ps |
| CPU time | 32.18 seconds |
| Started | Jan 10 01:37:45 PM PST 24 |
| Finished | Jan 10 01:38:21 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-4c9d0054-d44d-4136-99f4-10e850ff867b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312571785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.312571785 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.938145637 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 101484506647 ps |
| CPU time | 1093.9 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:56:21 PM PST 24 |
| Peak memory | 554832 kb |
| Host | smart-4b1874c7-8d67-4dc5-8401-a9a1b15616b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938145637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.938145637 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3165562240 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 56998369516 ps |
| CPU time | 878.55 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:52:30 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-1996c889-f997-40fe-bc6f-2c48378e9d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165562240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3165562240 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1222812859 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 478647443 ps |
| CPU time | 34.04 seconds |
| Started | Jan 10 01:37:56 PM PST 24 |
| Finished | Jan 10 01:38:35 PM PST 24 |
| Peak memory | 554784 kb |
| Host | smart-3b5900c4-fbde-4e1e-a4f1-c843f2fe55e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222812859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.1222812859 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.767672911 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 2327281829 ps |
| CPU time | 62.64 seconds |
| Started | Jan 10 01:37:57 PM PST 24 |
| Finished | Jan 10 01:39:06 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-7473abbd-e0cd-440c-b12b-de9173d422f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767672911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.767672911 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.3716768845 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 213810130 ps |
| CPU time | 9.05 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:37:54 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-216c7b97-8fef-4dd3-ba7e-9a47fd709b0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716768845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3716768845 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.1491278405 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 9131320241 ps |
| CPU time | 100.61 seconds |
| Started | Jan 10 01:38:03 PM PST 24 |
| Finished | Jan 10 01:39:49 PM PST 24 |
| Peak memory | 552636 kb |
| Host | smart-8c53eada-f066-4a98-9ac2-37ad492b45bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491278405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1491278405 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1148367590 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 4858883008 ps |
| CPU time | 83.85 seconds |
| Started | Jan 10 01:37:46 PM PST 24 |
| Finished | Jan 10 01:39:14 PM PST 24 |
| Peak memory | 552724 kb |
| Host | smart-e0f9bb75-9617-4179-847a-0978df11fda6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148367590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1148367590 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1004573314 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 48396348 ps |
| CPU time | 6.31 seconds |
| Started | Jan 10 01:37:32 PM PST 24 |
| Finished | Jan 10 01:37:49 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-8d86d7a5-0dde-4803-8123-a2608e4f7327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004573314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.1004573314 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.1043545026 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2828511606 ps |
| CPU time | 213.86 seconds |
| Started | Jan 10 01:37:55 PM PST 24 |
| Finished | Jan 10 01:41:34 PM PST 24 |
| Peak memory | 556220 kb |
| Host | smart-817d2900-714d-423b-9ada-db6f64c6c9fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043545026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1043545026 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2316311804 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 11129389302 ps |
| CPU time | 424.3 seconds |
| Started | Jan 10 01:37:58 PM PST 24 |
| Finished | Jan 10 01:45:08 PM PST 24 |
| Peak memory | 555864 kb |
| Host | smart-454f5c5f-04ec-4370-a450-d753e0718b6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316311804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2316311804 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2430232282 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 604231050 ps |
| CPU time | 238.96 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:42:06 PM PST 24 |
| Peak memory | 556972 kb |
| Host | smart-9d08f15e-6cd0-4e00-9084-7132fc1d7e14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430232282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.2430232282 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.915084909 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 651252824 ps |
| CPU time | 152.11 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:40:38 PM PST 24 |
| Peak memory | 559028 kb |
| Host | smart-b483aa86-d866-4150-9b20-fea6395a2c3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915084909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_reset_error.915084909 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1468520304 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 93738589 ps |
| CPU time | 12.66 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:38:18 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-a96cdad9-a274-4ee1-83ba-530d51b40cc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468520304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1468520304 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3711782944 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 9560232582 ps |
| CPU time | 347.21 seconds |
| Started | Jan 10 01:37:30 PM PST 24 |
| Finished | Jan 10 01:43:29 PM PST 24 |
| Peak memory | 630004 kb |
| Host | smart-4e013553-4ada-441c-a8a5-9995cfafa433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711782944 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.3711782944 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.2716669362 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 4732850880 ps |
| CPU time | 295.37 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:42:48 PM PST 24 |
| Peak memory | 580784 kb |
| Host | smart-c2fef410-d44d-49d3-a384-ea2546a51b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716669362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.2716669362 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2596304642 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 14385135495 ps |
| CPU time | 2010.84 seconds |
| Started | Jan 10 01:38:05 PM PST 24 |
| Finished | Jan 10 02:11:41 PM PST 24 |
| Peak memory | 580752 kb |
| Host | smart-cb2fb1d2-968d-485b-b527-af3ddd708d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596304642 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.2596304642 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.2940512093 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2607857987 ps |
| CPU time | 112.64 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:40:08 PM PST 24 |
| Peak memory | 553952 kb |
| Host | smart-57588d13-e9d1-41ad-ac58-8da4931ff853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940512093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .2940512093 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1169197970 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 96801035609 ps |
| CPU time | 1535.28 seconds |
| Started | Jan 10 01:38:09 PM PST 24 |
| Finished | Jan 10 02:03:49 PM PST 24 |
| Peak memory | 555868 kb |
| Host | smart-c2a29711-3b6c-4511-8aa8-e64f35b49ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169197970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.1169197970 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1422062394 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 831387218 ps |
| CPU time | 33.66 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:38:50 PM PST 24 |
| Peak memory | 554740 kb |
| Host | smart-12a60bb5-39a8-43cf-85cf-de08b5c8d882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422062394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.1422062394 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.1702099240 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 796787702 ps |
| CPU time | 26.07 seconds |
| Started | Jan 10 01:38:16 PM PST 24 |
| Finished | Jan 10 01:38:48 PM PST 24 |
| Peak memory | 553884 kb |
| Host | smart-15e4d18e-02b4-4bb7-bbbe-e400aba0d7c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702099240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1702099240 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.2133982802 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 66601907 ps |
| CPU time | 8.53 seconds |
| Started | Jan 10 01:38:08 PM PST 24 |
| Finished | Jan 10 01:38:21 PM PST 24 |
| Peak memory | 552688 kb |
| Host | smart-9e0a2be0-540c-41e2-a7c0-8887c72a9886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133982802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.2133982802 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2835231610 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 52122205271 ps |
| CPU time | 545.9 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:47:12 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-8e9bec8a-e900-4eb1-a9ca-cd59d9ea9cd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835231610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2835231610 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1914469081 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 44909264 ps |
| CPU time | 6.31 seconds |
| Started | Jan 10 01:38:05 PM PST 24 |
| Finished | Jan 10 01:38:16 PM PST 24 |
| Peak memory | 552884 kb |
| Host | smart-1ec0987d-4098-4551-a16a-d82b8816091b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914469081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1914469081 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.3871607378 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 497759409 ps |
| CPU time | 32.58 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:38:47 PM PST 24 |
| Peak memory | 554708 kb |
| Host | smart-3177d934-f058-495f-a408-7cc901d52743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871607378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3871607378 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.2975506458 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 244211181 ps |
| CPU time | 9.85 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:38:16 PM PST 24 |
| Peak memory | 552948 kb |
| Host | smart-8b97d57a-455c-4888-aa75-3b1a3b25b1e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975506458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2975506458 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.364985447 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 6604067637 ps |
| CPU time | 68.29 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:39:14 PM PST 24 |
| Peak memory | 552772 kb |
| Host | smart-5197421f-1758-48b4-9238-1983ef9521a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364985447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.364985447 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3112109398 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 5744090241 ps |
| CPU time | 96.17 seconds |
| Started | Jan 10 01:38:03 PM PST 24 |
| Finished | Jan 10 01:39:44 PM PST 24 |
| Peak memory | 552580 kb |
| Host | smart-ca7839c5-c104-4421-921a-b0caf70ffb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112109398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3112109398 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2089187657 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 48635525 ps |
| CPU time | 5.97 seconds |
| Started | Jan 10 01:38:08 PM PST 24 |
| Finished | Jan 10 01:38:18 PM PST 24 |
| Peak memory | 552968 kb |
| Host | smart-cdf49b8d-f599-4f7d-8779-53b84043667f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089187657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.2089187657 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.3996795294 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 1053465273 ps |
| CPU time | 82.28 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:39:39 PM PST 24 |
| Peak memory | 555936 kb |
| Host | smart-efa6c410-4fe1-47a1-abd7-4185e488068a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996795294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3996795294 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.139861956 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 2013666026 ps |
| CPU time | 136.49 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:40:33 PM PST 24 |
| Peak memory | 555872 kb |
| Host | smart-816603de-8d4e-4049-951d-3eb03cfdb93d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139861956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_ with_rand_reset.139861956 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3882125573 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1387993665 ps |
| CPU time | 51.99 seconds |
| Started | Jan 10 01:38:16 PM PST 24 |
| Finished | Jan 10 01:39:14 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-df8c92f6-d7f4-43f6-a51c-40cf59afc3c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882125573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3882125573 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.2647793506 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 9026601521 ps |
| CPU time | 349.94 seconds |
| Started | Jan 10 01:37:46 PM PST 24 |
| Finished | Jan 10 01:43:40 PM PST 24 |
| Peak memory | 628100 kb |
| Host | smart-0297144b-5bb3-42bc-a51c-d2e3775c4c7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647793506 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.2647793506 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.777025838 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 5261882540 ps |
| CPU time | 525.73 seconds |
| Started | Jan 10 01:38:04 PM PST 24 |
| Finished | Jan 10 01:46:55 PM PST 24 |
| Peak memory | 580800 kb |
| Host | smart-2350efc2-41eb-4412-a559-d11eccdfc1b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777025838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.777025838 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2560407562 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 29860331236 ps |
| CPU time | 3108.85 seconds |
| Started | Jan 10 01:38:15 PM PST 24 |
| Finished | Jan 10 02:30:10 PM PST 24 |
| Peak memory | 580752 kb |
| Host | smart-b85d509e-da00-4a5e-b0b2-4ae842b15fa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560407562 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.2560407562 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.3775875925 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 2545720532 ps |
| CPU time | 98.08 seconds |
| Started | Jan 10 01:37:42 PM PST 24 |
| Finished | Jan 10 01:39:25 PM PST 24 |
| Peak memory | 554800 kb |
| Host | smart-33a7c4ae-5ada-4e0e-a6a7-346b7e179db3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775875925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .3775875925 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2934435804 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 41312090257 ps |
| CPU time | 653.11 seconds |
| Started | Jan 10 01:37:37 PM PST 24 |
| Finished | Jan 10 01:48:38 PM PST 24 |
| Peak memory | 554800 kb |
| Host | smart-3e5192d4-4491-41f7-bb14-88814d26e80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934435804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.2934435804 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1528869771 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 858196590 ps |
| CPU time | 31.29 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:38:22 PM PST 24 |
| Peak memory | 554976 kb |
| Host | smart-0ca0c0f6-9086-4c0b-9e3c-a599604b352e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528869771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.1528869771 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.2439024794 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 557570392 ps |
| CPU time | 41.85 seconds |
| Started | Jan 10 01:37:46 PM PST 24 |
| Finished | Jan 10 01:38:32 PM PST 24 |
| Peak memory | 554960 kb |
| Host | smart-664f4600-4e77-444f-b829-02735ab95e16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439024794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2439024794 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.1825375223 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 334064927 ps |
| CPU time | 30.38 seconds |
| Started | Jan 10 01:37:50 PM PST 24 |
| Finished | Jan 10 01:38:25 PM PST 24 |
| Peak memory | 555040 kb |
| Host | smart-373f5aa9-54d1-4600-8657-4f498a5a4f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825375223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1825375223 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2292090600 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 14722859419 ps |
| CPU time | 159.59 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:40:45 PM PST 24 |
| Peak memory | 554724 kb |
| Host | smart-0e11f3f8-8449-4f57-9029-d2b676ee5032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292090600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2292090600 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1637254513 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 34129412560 ps |
| CPU time | 527.9 seconds |
| Started | Jan 10 01:37:40 PM PST 24 |
| Finished | Jan 10 01:46:35 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-aaec0ae5-9b81-4fab-ae38-af14f1c0a671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637254513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1637254513 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1171692168 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 302322245 ps |
| CPU time | 23.93 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:38:08 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-c73f224a-9c34-437b-bcd3-64a27dde63d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171692168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.1171692168 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.1593472480 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 63257800 ps |
| CPU time | 6.82 seconds |
| Started | Jan 10 01:37:51 PM PST 24 |
| Finished | Jan 10 01:38:02 PM PST 24 |
| Peak memory | 553764 kb |
| Host | smart-33258d42-6e1c-495a-ab74-b0acca10f9e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593472480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1593472480 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.3072360854 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 197541615 ps |
| CPU time | 8.24 seconds |
| Started | Jan 10 01:37:34 PM PST 24 |
| Finished | Jan 10 01:37:52 PM PST 24 |
| Peak memory | 552964 kb |
| Host | smart-dd16c909-8e54-4469-a9a1-bc0050519940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072360854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3072360854 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.3694484135 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 10780738167 ps |
| CPU time | 106.71 seconds |
| Started | Jan 10 01:37:30 PM PST 24 |
| Finished | Jan 10 01:39:28 PM PST 24 |
| Peak memory | 553040 kb |
| Host | smart-f3ebd201-d13d-40b6-ae1d-7b5c26318548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694484135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3694484135 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1766589629 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 5015708011 ps |
| CPU time | 85.19 seconds |
| Started | Jan 10 01:37:15 PM PST 24 |
| Finished | Jan 10 01:38:59 PM PST 24 |
| Peak memory | 553008 kb |
| Host | smart-6f32cfe7-d433-4d74-a98c-48c4a7a91034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766589629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1766589629 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2243383541 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 44526121 ps |
| CPU time | 5.95 seconds |
| Started | Jan 10 01:37:17 PM PST 24 |
| Finished | Jan 10 01:37:41 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-8464efdf-4d3c-4943-829a-4e1d2a6bc476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243383541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2243383541 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.375973417 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1564413479 ps |
| CPU time | 103.67 seconds |
| Started | Jan 10 01:36:53 PM PST 24 |
| Finished | Jan 10 01:38:37 PM PST 24 |
| Peak memory | 555920 kb |
| Host | smart-d042e280-1db4-4f0c-801c-d8443d169b3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375973417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.375973417 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1523940722 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 11635140786 ps |
| CPU time | 365.24 seconds |
| Started | Jan 10 01:37:54 PM PST 24 |
| Finished | Jan 10 01:44:04 PM PST 24 |
| Peak memory | 555952 kb |
| Host | smart-40e7aab4-de69-4f87-a0ac-0bb2de68182d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523940722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1523940722 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2207988279 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 605566972 ps |
| CPU time | 251.24 seconds |
| Started | Jan 10 01:37:53 PM PST 24 |
| Finished | Jan 10 01:42:08 PM PST 24 |
| Peak memory | 558176 kb |
| Host | smart-65b915b2-0eae-4566-bf8c-62dc813b6027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207988279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.2207988279 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1937791427 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 2487660509 ps |
| CPU time | 371.55 seconds |
| Started | Jan 10 01:37:43 PM PST 24 |
| Finished | Jan 10 01:44:00 PM PST 24 |
| Peak memory | 559928 kb |
| Host | smart-c1aa4cfc-a933-40d7-81e0-548161c06b9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937791427 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1937791427 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.2922060718 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 264489128 ps |
| CPU time | 12.52 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:37:56 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-61fea58c-c438-46aa-84b6-659736892b56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922060718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.2922060718 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.2856442365 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 8289020758 ps |
| CPU time | 331.3 seconds |
| Started | Jan 10 01:38:13 PM PST 24 |
| Finished | Jan 10 01:43:50 PM PST 24 |
| Peak memory | 629424 kb |
| Host | smart-edb5ced7-91ec-4441-a2ce-d2b767d09b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856442365 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.2856442365 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.3065617933 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 5591768748 ps |
| CPU time | 587.61 seconds |
| Started | Jan 10 01:38:16 PM PST 24 |
| Finished | Jan 10 01:48:09 PM PST 24 |
| Peak memory | 580852 kb |
| Host | smart-2c95b178-106f-4ff1-932a-bb68435f5712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065617933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3065617933 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2170107806 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 28567590726 ps |
| CPU time | 3236.65 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 02:32:04 PM PST 24 |
| Peak memory | 580832 kb |
| Host | smart-e696e47a-9308-4da1-9e73-ae1ca793b3c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170107806 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.2170107806 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3941245218 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 2563306610 ps |
| CPU time | 100.96 seconds |
| Started | Jan 10 01:37:58 PM PST 24 |
| Finished | Jan 10 01:39:45 PM PST 24 |
| Peak memory | 553972 kb |
| Host | smart-3a14a459-3fce-48f3-85c3-bb8509c5a366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941245218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3941245218 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.329255394 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 35105552848 ps |
| CPU time | 572.04 seconds |
| Started | Jan 10 01:37:58 PM PST 24 |
| Finished | Jan 10 01:47:36 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-82a8bf64-2969-4f84-894c-d6d62f6ccc43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329255394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_d evice_slow_rsp.329255394 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1240180319 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 433872719 ps |
| CPU time | 18.77 seconds |
| Started | Jan 10 01:38:07 PM PST 24 |
| Finished | Jan 10 01:38:30 PM PST 24 |
| Peak memory | 554620 kb |
| Host | smart-642941ec-229a-4143-9fbb-88a0cb1a99f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240180319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.1240180319 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3728494071 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 258567116 ps |
| CPU time | 21.61 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:38:38 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-95389a68-c320-4aeb-a5f5-859449de2ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728494071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3728494071 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.805766560 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1837259198 ps |
| CPU time | 62.88 seconds |
| Started | Jan 10 01:37:59 PM PST 24 |
| Finished | Jan 10 01:39:08 PM PST 24 |
| Peak memory | 554756 kb |
| Host | smart-b59cc5f8-b747-49dc-ac2a-483d3037f029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805766560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.805766560 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.161822969 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 95389232845 ps |
| CPU time | 1100.28 seconds |
| Started | Jan 10 01:37:52 PM PST 24 |
| Finished | Jan 10 01:56:17 PM PST 24 |
| Peak memory | 554844 kb |
| Host | smart-585cabef-5cd1-4b97-8b5b-db153079b1b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161822969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.161822969 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2098357665 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 4639274642 ps |
| CPU time | 68.18 seconds |
| Started | Jan 10 01:38:05 PM PST 24 |
| Finished | Jan 10 01:39:18 PM PST 24 |
| Peak memory | 552712 kb |
| Host | smart-675fa098-c992-4cd5-b719-86802d2511c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098357665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2098357665 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3353546008 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 548110309 ps |
| CPU time | 46.32 seconds |
| Started | Jan 10 01:37:59 PM PST 24 |
| Finished | Jan 10 01:38:51 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-5efaa8ef-978b-4afe-ace0-fcca76f328b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353546008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.3353546008 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.213481804 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 295224522 ps |
| CPU time | 11.25 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:38:18 PM PST 24 |
| Peak memory | 554040 kb |
| Host | smart-85750fb0-7f08-412e-9e6b-7e9fbc5687a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213481804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.213481804 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.510504656 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 46388068 ps |
| CPU time | 5.69 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:38:11 PM PST 24 |
| Peak memory | 552652 kb |
| Host | smart-a8225d3b-ea73-405c-a919-ba69d8a73826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510504656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.510504656 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.4100031174 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 8431640799 ps |
| CPU time | 80.49 seconds |
| Started | Jan 10 01:37:51 PM PST 24 |
| Finished | Jan 10 01:39:16 PM PST 24 |
| Peak memory | 552784 kb |
| Host | smart-a11c37bd-e69f-485c-8d5b-0be7b6dab31a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100031174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.4100031174 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1493192139 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 6236771330 ps |
| CPU time | 96.65 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:39:42 PM PST 24 |
| Peak memory | 552588 kb |
| Host | smart-cd007e73-46b1-41ce-aeea-1fb2c40290aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493192139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1493192139 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1560804875 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 51045543 ps |
| CPU time | 6.22 seconds |
| Started | Jan 10 01:37:54 PM PST 24 |
| Finished | Jan 10 01:38:05 PM PST 24 |
| Peak memory | 552960 kb |
| Host | smart-3f5c661a-6e6c-4c2e-ac3c-541fd80b6061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560804875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.1560804875 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.4111911229 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 6295973436 ps |
| CPU time | 223.79 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:41:59 PM PST 24 |
| Peak memory | 556064 kb |
| Host | smart-17a9228d-0063-4c31-be40-00754361a193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111911229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.4111911229 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.4284198768 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 12075275526 ps |
| CPU time | 402.46 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:44:58 PM PST 24 |
| Peak memory | 556364 kb |
| Host | smart-fa3e49bf-d254-41a2-84fd-c03864a0c669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284198768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.4284198768 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3951679596 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 7232378632 ps |
| CPU time | 412.16 seconds |
| Started | Jan 10 01:38:13 PM PST 24 |
| Finished | Jan 10 01:45:11 PM PST 24 |
| Peak memory | 557236 kb |
| Host | smart-73e6e17c-0ae9-4c7e-b5c2-7264644c3305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951679596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.3951679596 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.3866293417 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 103205198 ps |
| CPU time | 18.08 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:38:33 PM PST 24 |
| Peak memory | 554092 kb |
| Host | smart-dc28d3ad-1fd1-4678-b331-a7d3f41ff97e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866293417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.3866293417 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.4159242868 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 31037028 ps |
| CPU time | 6.32 seconds |
| Started | Jan 10 01:38:09 PM PST 24 |
| Finished | Jan 10 01:38:20 PM PST 24 |
| Peak memory | 552596 kb |
| Host | smart-7436d4f6-9c64-4482-a4c4-97dfc7ee69ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159242868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.4159242868 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.3357270556 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 10182362607 ps |
| CPU time | 397.19 seconds |
| Started | Jan 10 01:37:39 PM PST 24 |
| Finished | Jan 10 01:44:23 PM PST 24 |
| Peak memory | 616636 kb |
| Host | smart-598f1ae7-a45c-4869-8626-58d20421d1c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357270556 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.3357270556 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.359823101 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4344595453 ps |
| CPU time | 329.72 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:43:21 PM PST 24 |
| Peak memory | 580904 kb |
| Host | smart-1c7179c6-36fb-482a-b73c-c73785972c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359823101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.359823101 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.187177588 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 15735392298 ps |
| CPU time | 1858.62 seconds |
| Started | Jan 10 01:38:12 PM PST 24 |
| Finished | Jan 10 02:09:16 PM PST 24 |
| Peak memory | 580768 kb |
| Host | smart-ace23bcb-7214-4c6e-b94d-ce6ef74e6b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187177588 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.chip_same_csr_outstanding.187177588 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.2457220410 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 3413284264 ps |
| CPU time | 172.05 seconds |
| Started | Jan 10 01:38:14 PM PST 24 |
| Finished | Jan 10 01:41:11 PM PST 24 |
| Peak memory | 580880 kb |
| Host | smart-e89dbeae-0480-4ecf-9491-bc0cbb253d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457220410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.2457220410 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.2427856379 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 1194761518 ps |
| CPU time | 44.02 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:38:35 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-132b6355-7c73-4ba9-8972-2e928e7ada61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427856379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .2427856379 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3110606229 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 64275628518 ps |
| CPU time | 1078.25 seconds |
| Started | Jan 10 01:37:18 PM PST 24 |
| Finished | Jan 10 01:55:34 PM PST 24 |
| Peak memory | 554876 kb |
| Host | smart-f2e1b7f5-610e-4c8a-afd7-a711b759ab47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110606229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.3110606229 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3135437835 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 36806232 ps |
| CPU time | 6.59 seconds |
| Started | Jan 10 01:37:54 PM PST 24 |
| Finished | Jan 10 01:38:06 PM PST 24 |
| Peak memory | 552664 kb |
| Host | smart-39408b4c-f1bf-448a-ab0e-96d8bd4440c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135437835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.3135437835 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.3633596647 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 498449507 ps |
| CPU time | 41.44 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:38:26 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-3d87ea44-6574-44f1-9375-73fd8ec87e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633596647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3633596647 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.1574568273 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 612295396 ps |
| CPU time | 52.52 seconds |
| Started | Jan 10 01:37:16 PM PST 24 |
| Finished | Jan 10 01:38:28 PM PST 24 |
| Peak memory | 555044 kb |
| Host | smart-9869774a-68e7-431a-a6ab-de3d81c2bb7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574568273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.1574568273 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.3753963760 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 17578806966 ps |
| CPU time | 183.5 seconds |
| Started | Jan 10 01:37:17 PM PST 24 |
| Finished | Jan 10 01:40:39 PM PST 24 |
| Peak memory | 554784 kb |
| Host | smart-e2621c91-01b1-4d30-b377-258beefc96b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753963760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3753963760 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1028722148 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 9458109240 ps |
| CPU time | 168.2 seconds |
| Started | Jan 10 01:37:29 PM PST 24 |
| Finished | Jan 10 01:40:29 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-ab1e9772-6bc9-4ed3-a7b3-3865c2cc9bb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028722148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1028722148 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.500374839 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 316684414 ps |
| CPU time | 28.97 seconds |
| Started | Jan 10 01:37:17 PM PST 24 |
| Finished | Jan 10 01:38:04 PM PST 24 |
| Peak memory | 553948 kb |
| Host | smart-5e90a831-e033-4128-89ca-894a16491b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500374839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_dela ys.500374839 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.51493868 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 2314658484 ps |
| CPU time | 65.09 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:38:58 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-e8e07419-9d01-4e2a-8e09-4e0f64009074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51493868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.51493868 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.934117918 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 237621074 ps |
| CPU time | 9.23 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:38:25 PM PST 24 |
| Peak memory | 552724 kb |
| Host | smart-6b91e773-90ac-4a30-9040-a3ab0a4493fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934117918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.934117918 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1447723245 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 8873659050 ps |
| CPU time | 100.08 seconds |
| Started | Jan 10 01:37:18 PM PST 24 |
| Finished | Jan 10 01:39:16 PM PST 24 |
| Peak memory | 553048 kb |
| Host | smart-7e1809b4-cd47-44eb-ad96-52aa2bb83802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447723245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.1447723245 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.664837015 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 5581541790 ps |
| CPU time | 88.83 seconds |
| Started | Jan 10 01:37:37 PM PST 24 |
| Finished | Jan 10 01:39:14 PM PST 24 |
| Peak memory | 552916 kb |
| Host | smart-d76d440f-e6d9-4d5a-b1ab-3c8f9ebcad50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664837015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.664837015 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2239162189 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 53301128 ps |
| CPU time | 6.17 seconds |
| Started | Jan 10 01:38:15 PM PST 24 |
| Finished | Jan 10 01:38:27 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-23499bc2-5088-4d79-b737-796bacce3b9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239162189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.2239162189 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.74009067 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2511345771 ps |
| CPU time | 178.91 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:40:44 PM PST 24 |
| Peak memory | 556284 kb |
| Host | smart-d68d420b-6a18-4f93-9ae3-16d2e7c5c010 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74009067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.74009067 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1368199081 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 9978885367 ps |
| CPU time | 329.17 seconds |
| Started | Jan 10 01:37:56 PM PST 24 |
| Finished | Jan 10 01:43:31 PM PST 24 |
| Peak memory | 557292 kb |
| Host | smart-98ec00fa-ae0f-4459-8934-450f44511352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368199081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1368199081 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.159811863 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 17453284656 ps |
| CPU time | 827.44 seconds |
| Started | Jan 10 01:37:33 PM PST 24 |
| Finished | Jan 10 01:51:30 PM PST 24 |
| Peak memory | 559976 kb |
| Host | smart-d859df09-7025-4afd-b64a-7e192eb14f7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159811863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_ with_rand_reset.159811863 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1246447897 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 239693077 ps |
| CPU time | 27.33 seconds |
| Started | Jan 10 01:37:37 PM PST 24 |
| Finished | Jan 10 01:38:13 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-bddea34d-9ab4-46f4-b14e-133801848418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246447897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1246447897 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.1632309121 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6504802275 ps |
| CPU time | 234.83 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:41:47 PM PST 24 |
| Peak memory | 614708 kb |
| Host | smart-dd32d08c-c491-4559-822d-b999a56e1f5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632309121 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.1632309121 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.4238190735 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 5825425858 ps |
| CPU time | 558.61 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:47:12 PM PST 24 |
| Peak memory | 581252 kb |
| Host | smart-711edd3a-f258-4840-b7d8-4c742d320892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238190735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.4238190735 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.1319888454 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 1202713898 ps |
| CPU time | 46.04 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:38:30 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-981bf18c-06ea-42dc-863e-bb6d8c03b9fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319888454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .1319888454 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1541876762 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 165139031101 ps |
| CPU time | 2749.24 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 02:23:41 PM PST 24 |
| Peak memory | 555936 kb |
| Host | smart-c351d8c3-e396-43f5-913e-27003ea009cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541876762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.1541876762 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.422541993 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 435598511 ps |
| CPU time | 16.77 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:38:01 PM PST 24 |
| Peak memory | 555020 kb |
| Host | smart-de28283b-b0ca-4ee0-903c-9d4e5796e88c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422541993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr .422541993 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.975183859 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 214629505 ps |
| CPU time | 17.69 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:38:09 PM PST 24 |
| Peak memory | 554724 kb |
| Host | smart-963b0ea1-8b58-4a0f-895a-949cc8f33b58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975183859 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.975183859 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.3736637480 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 1545701635 ps |
| CPU time | 57.98 seconds |
| Started | Jan 10 01:37:29 PM PST 24 |
| Finished | Jan 10 01:38:39 PM PST 24 |
| Peak memory | 554760 kb |
| Host | smart-903aab7f-039c-4958-acab-c7a22615b451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736637480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.3736637480 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.1101857113 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 38214725424 ps |
| CPU time | 378.09 seconds |
| Started | Jan 10 01:37:43 PM PST 24 |
| Finished | Jan 10 01:44:06 PM PST 24 |
| Peak memory | 554824 kb |
| Host | smart-5e7b069b-95d7-4937-a9a9-042b2f997776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101857113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1101857113 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.3054477350 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 28091572059 ps |
| CPU time | 436.96 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:45:09 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-d0e0b44c-1f9c-4364-87dc-5b0122836f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054477350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.3054477350 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.144532638 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 160112817 ps |
| CPU time | 14.98 seconds |
| Started | Jan 10 01:37:32 PM PST 24 |
| Finished | Jan 10 01:37:57 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-dc6a49d9-a1d4-420b-b27a-c33cde8e4d27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144532638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_dela ys.144532638 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.2133099180 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 399574032 ps |
| CPU time | 28.69 seconds |
| Started | Jan 10 01:37:37 PM PST 24 |
| Finished | Jan 10 01:38:14 PM PST 24 |
| Peak memory | 554736 kb |
| Host | smart-ffb54a9f-b0e5-4a92-87ee-5db3fdddc224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133099180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2133099180 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.2949533315 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 49344271 ps |
| CPU time | 6.1 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:37:51 PM PST 24 |
| Peak memory | 552952 kb |
| Host | smart-d9bbb154-0c27-40cd-ac79-5eb81fc1a6dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949533315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2949533315 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.1621257758 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 6402853460 ps |
| CPU time | 64.63 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:38:49 PM PST 24 |
| Peak memory | 552572 kb |
| Host | smart-2e21fb52-14eb-41bd-a6d9-d78cf126ae5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621257758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1621257758 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3077670554 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 4403028703 ps |
| CPU time | 75.63 seconds |
| Started | Jan 10 01:37:32 PM PST 24 |
| Finished | Jan 10 01:38:58 PM PST 24 |
| Peak memory | 552724 kb |
| Host | smart-18800adb-f656-458a-8b72-eebe6a06715d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077670554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3077670554 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3943480618 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 45819428 ps |
| CPU time | 6.12 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:37:51 PM PST 24 |
| Peak memory | 553056 kb |
| Host | smart-6cb71a64-3005-4433-b651-fe61a42d7a41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943480618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.3943480618 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.1835584170 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 6844934487 ps |
| CPU time | 241.21 seconds |
| Started | Jan 10 01:37:33 PM PST 24 |
| Finished | Jan 10 01:41:44 PM PST 24 |
| Peak memory | 556168 kb |
| Host | smart-8e9d8422-06a1-467a-a009-dddedca2ef3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835584170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1835584170 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.1773717922 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1108880546 ps |
| CPU time | 86.23 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:39:19 PM PST 24 |
| Peak memory | 556112 kb |
| Host | smart-4e87c2dd-7d38-489a-8924-2e2e31a43890 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773717922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1773717922 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.4259800855 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 8604283102 ps |
| CPU time | 536.95 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:46:41 PM PST 24 |
| Peak memory | 558720 kb |
| Host | smart-4bdc972b-9b4d-4b5b-9c15-a57b823fb134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259800855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.4259800855 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2558538894 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 339693197 ps |
| CPU time | 67.83 seconds |
| Started | Jan 10 01:37:44 PM PST 24 |
| Finished | Jan 10 01:38:57 PM PST 24 |
| Peak memory | 556332 kb |
| Host | smart-ddf9737c-d5ab-48d9-8ca8-0edf06505923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558538894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.2558538894 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.4221314482 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 1209475296 ps |
| CPU time | 50.22 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:38:41 PM PST 24 |
| Peak memory | 553884 kb |
| Host | smart-8ae5f9d6-73d9-4b28-996e-7622b9feea16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221314482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.4221314482 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.626736145 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 57943792177 ps |
| CPU time | 9798.53 seconds |
| Started | Jan 10 01:35:43 PM PST 24 |
| Finished | Jan 10 04:19:21 PM PST 24 |
| Peak memory | 618192 kb |
| Host | smart-0bf50230-db69-4fae-b9e7-fc86385aa39a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626736145 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.chip_csr_aliasing.626736145 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1764046537 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 10023818610 ps |
| CPU time | 1232.22 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 01:56:39 PM PST 24 |
| Peak memory | 580824 kb |
| Host | smart-c0e26ae7-c8db-4d64-9502-2492accd196b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764046537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.1764046537 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2604112572 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4351462312 ps |
| CPU time | 180.51 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 01:39:07 PM PST 24 |
| Peak memory | 642996 kb |
| Host | smart-afdedfbb-6f03-459f-85f9-dcc3b026d466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604112572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.2604112572 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3555530576 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5040631314 ps |
| CPU time | 213.63 seconds |
| Started | Jan 10 01:36:02 PM PST 24 |
| Finished | Jan 10 01:39:46 PM PST 24 |
| Peak memory | 622152 kb |
| Host | smart-c49ba08f-19d6-415e-8a6a-917ad0678a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555530576 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.3555530576 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.263533272 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 6393844166 ps |
| CPU time | 704.58 seconds |
| Started | Jan 10 01:35:52 PM PST 24 |
| Finished | Jan 10 01:47:51 PM PST 24 |
| Peak memory | 580808 kb |
| Host | smart-0c91a543-a326-4927-afab-c0b53087f1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263533272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.263533272 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.4255170556 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 4719416141 ps |
| CPU time | 126.9 seconds |
| Started | Jan 10 01:35:44 PM PST 24 |
| Finished | Jan 10 01:38:08 PM PST 24 |
| Peak memory | 576700 kb |
| Host | smart-4f8577f3-a367-46ce-a4b3-9f8c0c9186da |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255170556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.4255170556 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3291207797 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 8947937213 ps |
| CPU time | 266.85 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:40:35 PM PST 24 |
| Peak memory | 578148 kb |
| Host | smart-e21463aa-9745-4947-b58b-5d068595718d |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291207797 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3291207797 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.620682458 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 15982193630 ps |
| CPU time | 1919.2 seconds |
| Started | Jan 10 01:35:55 PM PST 24 |
| Finished | Jan 10 02:08:07 PM PST 24 |
| Peak memory | 580736 kb |
| Host | smart-f0be04c6-9030-447b-997f-3e93542eff30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620682458 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.chip_same_csr_outstanding.620682458 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.2979593722 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 4994539655 ps |
| CPU time | 344.57 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 01:41:52 PM PST 24 |
| Peak memory | 579404 kb |
| Host | smart-3c06f2e4-31d6-41a1-b814-927e68cbbba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979593722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.2979593722 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.426463354 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 2990257842 ps |
| CPU time | 114.31 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 01:38:01 PM PST 24 |
| Peak memory | 555112 kb |
| Host | smart-04b2ea1a-4ff7-4a9e-a886-e998da5dcb63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426463354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.426463354 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2507701966 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 65640366920 ps |
| CPU time | 1123.39 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:54:54 PM PST 24 |
| Peak memory | 553964 kb |
| Host | smart-9674ac4f-7515-421e-9a03-b6922257f58c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507701966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2507701966 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.918201204 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 283086170 ps |
| CPU time | 13.53 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 01:36:20 PM PST 24 |
| Peak memory | 553612 kb |
| Host | smart-bc64bf21-ab24-406c-8388-59b630013f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918201204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr. 918201204 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.2541001599 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 1225437696 ps |
| CPU time | 37.51 seconds |
| Started | Jan 10 01:35:55 PM PST 24 |
| Finished | Jan 10 01:36:45 PM PST 24 |
| Peak memory | 554620 kb |
| Host | smart-37f417fc-fe5f-4a15-899e-967ecdf760d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541001599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2541001599 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.3589847133 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 333280824 ps |
| CPU time | 12.67 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:36:21 PM PST 24 |
| Peak memory | 553812 kb |
| Host | smart-b2ed7003-90df-4980-a407-e35ee3977e59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589847133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.3589847133 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.372474991 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 100505689210 ps |
| CPU time | 1155.51 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:55:24 PM PST 24 |
| Peak memory | 554780 kb |
| Host | smart-b39ccf33-2ba8-43e6-9f3f-5389a73b438d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372474991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.372474991 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1446706844 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 22145421031 ps |
| CPU time | 358.86 seconds |
| Started | Jan 10 01:35:49 PM PST 24 |
| Finished | Jan 10 01:42:03 PM PST 24 |
| Peak memory | 554820 kb |
| Host | smart-5a64b0b9-69ee-4b7c-9c3a-3e5caa2d27d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446706844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1446706844 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.1071255867 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 450101497 ps |
| CPU time | 39.74 seconds |
| Started | Jan 10 01:35:57 PM PST 24 |
| Finished | Jan 10 01:36:49 PM PST 24 |
| Peak memory | 555020 kb |
| Host | smart-91bd3694-0f3c-49a2-a9f2-dd7dd83d3410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071255867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.1071255867 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.165114905 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 558581018 ps |
| CPU time | 35.59 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 01:36:43 PM PST 24 |
| Peak memory | 553728 kb |
| Host | smart-b01cbbbe-c7e7-461b-b3a2-ba2d36b2a184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165114905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.165114905 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.2902760685 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 45282244 ps |
| CPU time | 5.93 seconds |
| Started | Jan 10 01:35:52 PM PST 24 |
| Finished | Jan 10 01:36:12 PM PST 24 |
| Peak memory | 552544 kb |
| Host | smart-fe564e7b-e8ea-45e8-9fde-3eedea1465eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902760685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2902760685 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.2239999396 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 10405065884 ps |
| CPU time | 111.05 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:37:57 PM PST 24 |
| Peak memory | 552724 kb |
| Host | smart-b9b67972-5e08-4f24-aadb-2ef16e1b91a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239999396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2239999396 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2554863657 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 5115679460 ps |
| CPU time | 83.82 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:37:32 PM PST 24 |
| Peak memory | 552892 kb |
| Host | smart-b1a6fe5b-8dce-4fac-ac44-a2c46c7d3194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554863657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2554863657 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.502382921 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 48362275 ps |
| CPU time | 5.87 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:36:12 PM PST 24 |
| Peak memory | 552944 kb |
| Host | smart-8a1763c8-3846-4455-a0c3-941da490daf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502382921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays. 502382921 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.36388782 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 1083560167 ps |
| CPU time | 71.19 seconds |
| Started | Jan 10 01:35:57 PM PST 24 |
| Finished | Jan 10 01:37:20 PM PST 24 |
| Peak memory | 556928 kb |
| Host | smart-23577d4a-9dc0-4a6c-86f2-1189f9f0896a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.36388782 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.4211972853 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 9623775091 ps |
| CPU time | 337.97 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:41:48 PM PST 24 |
| Peak memory | 556996 kb |
| Host | smart-383fe278-26a9-425c-9da6-df77488e257c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211972853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.4211972853 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3501822671 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 885918651 ps |
| CPU time | 147.69 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:38:33 PM PST 24 |
| Peak memory | 557332 kb |
| Host | smart-91b71608-e788-4ad9-8d6b-460b83ef3a5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501822671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.3501822671 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.1590578632 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 1752711367 ps |
| CPU time | 99.74 seconds |
| Started | Jan 10 01:35:55 PM PST 24 |
| Finished | Jan 10 01:37:48 PM PST 24 |
| Peak memory | 556184 kb |
| Host | smart-1ec962b5-80ae-4ead-a995-6275e26dc484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590578632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.1590578632 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.2359896825 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 1334824575 ps |
| CPU time | 52.55 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:37:02 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-3e575934-d77d-4731-a267-937d982dfca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359896825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2359896825 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.1014804782 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 4053723789 ps |
| CPU time | 321.71 seconds |
| Started | Jan 10 01:37:51 PM PST 24 |
| Finished | Jan 10 01:43:17 PM PST 24 |
| Peak memory | 580860 kb |
| Host | smart-88b06f39-cfc6-4a1c-8514-3eb4229b98d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014804782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.1014804782 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.759185132 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 2826491952 ps |
| CPU time | 108.26 seconds |
| Started | Jan 10 01:37:31 PM PST 24 |
| Finished | Jan 10 01:39:30 PM PST 24 |
| Peak memory | 554872 kb |
| Host | smart-e70816f4-b11b-4166-8cc0-51797bdb36ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759185132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device. 759185132 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.559018446 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 150381130810 ps |
| CPU time | 2412.43 seconds |
| Started | Jan 10 01:37:50 PM PST 24 |
| Finished | Jan 10 02:18:08 PM PST 24 |
| Peak memory | 555848 kb |
| Host | smart-a33339d6-4e21-4a49-a37c-f45d94da0079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559018446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_d evice_slow_rsp.559018446 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.304673538 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 23053815 ps |
| CPU time | 5.33 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:37:57 PM PST 24 |
| Peak memory | 552632 kb |
| Host | smart-e6e00e8e-7f91-4f0f-bdd3-7f64be42d94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304673538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr .304673538 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.3275057111 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 418133051 ps |
| CPU time | 15 seconds |
| Started | Jan 10 01:37:29 PM PST 24 |
| Finished | Jan 10 01:37:56 PM PST 24 |
| Peak memory | 554712 kb |
| Host | smart-c2197c72-013f-4aeb-99a1-f5e727499a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275057111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3275057111 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.2561097046 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 353827652 ps |
| CPU time | 15.88 seconds |
| Started | Jan 10 01:37:42 PM PST 24 |
| Finished | Jan 10 01:38:03 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-b79045d8-f8f0-42fa-ba5d-8942a0580342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561097046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2561097046 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.2174305921 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 35391951391 ps |
| CPU time | 397.81 seconds |
| Started | Jan 10 01:37:38 PM PST 24 |
| Finished | Jan 10 01:44:23 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-cbd81a02-a61d-41e8-9bdb-93de1ee560af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174305921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.2174305921 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3490700228 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 71564404085 ps |
| CPU time | 1377.94 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 02:00:49 PM PST 24 |
| Peak memory | 555104 kb |
| Host | smart-8a7879bd-2856-404c-b684-681b055f764d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490700228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3490700228 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.4199461241 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 427626842 ps |
| CPU time | 35.46 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:38:26 PM PST 24 |
| Peak memory | 554892 kb |
| Host | smart-ab6d4529-a5cb-46fa-ac91-d693bd3ccc93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199461241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.4199461241 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.2136681186 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 1998057089 ps |
| CPU time | 55.9 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:38:41 PM PST 24 |
| Peak memory | 554732 kb |
| Host | smart-c5d06628-5460-4a00-ac04-97e54fb69af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136681186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2136681186 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.3714099431 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 197333113 ps |
| CPU time | 8.45 seconds |
| Started | Jan 10 01:37:34 PM PST 24 |
| Finished | Jan 10 01:37:52 PM PST 24 |
| Peak memory | 552676 kb |
| Host | smart-9fba7b0b-9247-4c42-862d-8c7d346297a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714099431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3714099431 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1233421825 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 9796741064 ps |
| CPU time | 97.08 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:39:30 PM PST 24 |
| Peak memory | 552968 kb |
| Host | smart-37b73813-4261-472d-a6c6-ff0ff5ba4354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233421825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1233421825 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2646045177 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 4746958852 ps |
| CPU time | 69.71 seconds |
| Started | Jan 10 01:37:37 PM PST 24 |
| Finished | Jan 10 01:38:55 PM PST 24 |
| Peak memory | 552688 kb |
| Host | smart-b6b61444-5d11-4213-9fa6-37fd7a3c5aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646045177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2646045177 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.24702454 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 39531487 ps |
| CPU time | 5.87 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:37:51 PM PST 24 |
| Peak memory | 552684 kb |
| Host | smart-33274a55-eb93-4c95-bdd6-f32e4430000e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24702454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.24702454 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.2262573619 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 1643040779 ps |
| CPU time | 115.09 seconds |
| Started | Jan 10 01:37:56 PM PST 24 |
| Finished | Jan 10 01:39:57 PM PST 24 |
| Peak memory | 555864 kb |
| Host | smart-516a5f94-cbc8-49d6-9a2e-5e5f0a8315d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262573619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2262573619 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.782046669 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 10386161271 ps |
| CPU time | 353.51 seconds |
| Started | Jan 10 01:37:50 PM PST 24 |
| Finished | Jan 10 01:43:48 PM PST 24 |
| Peak memory | 556012 kb |
| Host | smart-6cba77e1-a512-4bfd-a544-cbbf857faf34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782046669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.782046669 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.186067939 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 137253557 ps |
| CPU time | 88.02 seconds |
| Started | Jan 10 01:37:56 PM PST 24 |
| Finished | Jan 10 01:39:29 PM PST 24 |
| Peak memory | 556776 kb |
| Host | smart-053ad077-2e99-47ab-9f5d-641116051c28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186067939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_ with_rand_reset.186067939 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.734683417 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 3776087520 ps |
| CPU time | 463.89 seconds |
| Started | Jan 10 01:37:56 PM PST 24 |
| Finished | Jan 10 01:45:46 PM PST 24 |
| Peak memory | 559916 kb |
| Host | smart-cb9df6fc-b76a-441f-85ca-64be182936e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734683417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_reset_error.734683417 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.2178170660 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 1051552479 ps |
| CPU time | 40.12 seconds |
| Started | Jan 10 01:37:50 PM PST 24 |
| Finished | Jan 10 01:38:35 PM PST 24 |
| Peak memory | 555076 kb |
| Host | smart-e8084598-4d7c-47b9-a45e-b64082851da5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178170660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2178170660 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.1833463490 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 2929888530 ps |
| CPU time | 146.82 seconds |
| Started | Jan 10 01:37:58 PM PST 24 |
| Finished | Jan 10 01:40:30 PM PST 24 |
| Peak memory | 580796 kb |
| Host | smart-d9a17b31-652c-41b4-ab3d-50c78ff34f8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833463490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1833463490 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.17052828 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 876812272 ps |
| CPU time | 62.46 seconds |
| Started | Jan 10 01:37:53 PM PST 24 |
| Finished | Jan 10 01:38:59 PM PST 24 |
| Peak memory | 556104 kb |
| Host | smart-cfbd5617-adaa-4c5b-899d-198147aad6f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17052828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.17052828 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3621132439 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 17514364569 ps |
| CPU time | 265.21 seconds |
| Started | Jan 10 01:37:51 PM PST 24 |
| Finished | Jan 10 01:42:21 PM PST 24 |
| Peak memory | 556108 kb |
| Host | smart-7e0dabb0-693e-450a-af2f-5dcf919a59b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621132439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.3621132439 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2279827577 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 36382942 ps |
| CPU time | 6.27 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:37:57 PM PST 24 |
| Peak memory | 552912 kb |
| Host | smart-71f31b16-2069-4b7d-ba39-2bd08a76183a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279827577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.2279827577 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.1446054621 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 514407144 ps |
| CPU time | 39.69 seconds |
| Started | Jan 10 01:37:44 PM PST 24 |
| Finished | Jan 10 01:38:28 PM PST 24 |
| Peak memory | 554600 kb |
| Host | smart-25d9e690-662e-4175-968c-6c060a09c46e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446054621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1446054621 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.3373082131 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 2166401248 ps |
| CPU time | 73.9 seconds |
| Started | Jan 10 01:38:02 PM PST 24 |
| Finished | Jan 10 01:39:21 PM PST 24 |
| Peak memory | 555128 kb |
| Host | smart-bc9555b3-416c-4391-978e-bed251ffedc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373082131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3373082131 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1475189045 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 49247026612 ps |
| CPU time | 497.09 seconds |
| Started | Jan 10 01:37:51 PM PST 24 |
| Finished | Jan 10 01:46:13 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-0f7aab93-8445-45cb-9f84-d3e5ad91cdb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475189045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1475189045 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.4060406785 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 8167496528 ps |
| CPU time | 131.97 seconds |
| Started | Jan 10 01:38:05 PM PST 24 |
| Finished | Jan 10 01:40:22 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-0f579964-10a1-49c9-9a3a-eaf0ea178ecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060406785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.4060406785 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.1239104044 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 101071714 ps |
| CPU time | 10.68 seconds |
| Started | Jan 10 01:38:03 PM PST 24 |
| Finished | Jan 10 01:38:19 PM PST 24 |
| Peak memory | 553960 kb |
| Host | smart-70fc5a9b-7285-456a-98e3-f2a86b3ff5af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239104044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.1239104044 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.2101520169 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 166393344 ps |
| CPU time | 13.94 seconds |
| Started | Jan 10 01:37:32 PM PST 24 |
| Finished | Jan 10 01:37:56 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-47382509-24b9-481b-8ae3-6a185cdf404a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101520169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2101520169 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.2627929453 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 56180933 ps |
| CPU time | 6.42 seconds |
| Started | Jan 10 01:38:03 PM PST 24 |
| Finished | Jan 10 01:38:14 PM PST 24 |
| Peak memory | 552892 kb |
| Host | smart-6ed178ce-7e81-46d0-8d5d-82c60dba2ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627929453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2627929453 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3553311421 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 10940917695 ps |
| CPU time | 109.12 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:39:56 PM PST 24 |
| Peak memory | 552736 kb |
| Host | smart-4c7844d5-5fb5-4c23-9452-820e655f00f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553311421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3553311421 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3918634447 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 5980693072 ps |
| CPU time | 98.63 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:39:45 PM PST 24 |
| Peak memory | 552760 kb |
| Host | smart-a5a0b960-048b-403b-940e-565a7d978492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918634447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3918634447 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1885332148 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 43089298 ps |
| CPU time | 5.83 seconds |
| Started | Jan 10 01:37:54 PM PST 24 |
| Finished | Jan 10 01:38:03 PM PST 24 |
| Peak memory | 552672 kb |
| Host | smart-7ed3b209-ed37-4b31-b9c8-9284f3a22d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885332148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.1885332148 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.4104486937 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 1199426925 ps |
| CPU time | 100.56 seconds |
| Started | Jan 10 01:37:34 PM PST 24 |
| Finished | Jan 10 01:39:24 PM PST 24 |
| Peak memory | 556264 kb |
| Host | smart-f84d51b0-f31b-412f-b119-afce22428afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104486937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4104486937 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3368389966 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 2687180156 ps |
| CPU time | 77.04 seconds |
| Started | Jan 10 01:37:58 PM PST 24 |
| Finished | Jan 10 01:39:20 PM PST 24 |
| Peak memory | 555828 kb |
| Host | smart-233f3d2a-ee6b-4e6a-a735-286a3d799933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368389966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3368389966 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1315364316 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 4556521301 ps |
| CPU time | 611.69 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:48:03 PM PST 24 |
| Peak memory | 559928 kb |
| Host | smart-a5c30723-4107-46f4-9ebf-8b40827ac9db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315364316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.1315364316 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.901366526 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 633275944 ps |
| CPU time | 169.6 seconds |
| Started | Jan 10 01:37:42 PM PST 24 |
| Finished | Jan 10 01:40:37 PM PST 24 |
| Peak memory | 559320 kb |
| Host | smart-c41af89a-dd6a-41b2-93d6-8ca37bb7dfae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901366526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_reset_error.901366526 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.4178235736 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 128213625 ps |
| CPU time | 15.95 seconds |
| Started | Jan 10 01:37:37 PM PST 24 |
| Finished | Jan 10 01:38:01 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-d5ce041f-53f9-47dc-8a47-b1572878808e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178235736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.4178235736 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.3729256204 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 805092087 ps |
| CPU time | 63.97 seconds |
| Started | Jan 10 01:37:37 PM PST 24 |
| Finished | Jan 10 01:38:49 PM PST 24 |
| Peak memory | 554832 kb |
| Host | smart-8956dd71-6ed6-4d29-8763-1f159a33011b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729256204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .3729256204 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1154298401 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 31674078053 ps |
| CPU time | 496.12 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:46:00 PM PST 24 |
| Peak memory | 554780 kb |
| Host | smart-184a1144-438b-4453-81e1-962820574001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154298401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.1154298401 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.60007420 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 102003453 ps |
| CPU time | 11.91 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:38:18 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-bbe9fe88-c32a-4bff-853d-58205d9d4c46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60007420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.60007420 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.3728527446 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 624230609 ps |
| CPU time | 23.05 seconds |
| Started | Jan 10 01:37:37 PM PST 24 |
| Finished | Jan 10 01:38:08 PM PST 24 |
| Peak memory | 554988 kb |
| Host | smart-3666b14a-b228-4a5a-b113-75303a725085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728527446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3728527446 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.1280443704 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 284674159 ps |
| CPU time | 11.68 seconds |
| Started | Jan 10 01:37:43 PM PST 24 |
| Finished | Jan 10 01:38:00 PM PST 24 |
| Peak memory | 553732 kb |
| Host | smart-fd3d2e5f-2c20-462e-bb43-3b25a2d6339e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280443704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.1280443704 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2512079090 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 11585754266 ps |
| CPU time | 119.68 seconds |
| Started | Jan 10 01:37:42 PM PST 24 |
| Finished | Jan 10 01:39:47 PM PST 24 |
| Peak memory | 553012 kb |
| Host | smart-975646d8-95be-484b-93d6-ab0d000c32aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512079090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2512079090 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.3261313494 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 36372309015 ps |
| CPU time | 599.57 seconds |
| Started | Jan 10 01:37:46 PM PST 24 |
| Finished | Jan 10 01:47:49 PM PST 24 |
| Peak memory | 555088 kb |
| Host | smart-544f1b9e-696a-45df-872b-5de07ed7e4ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261313494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3261313494 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.2105993272 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 146884140 ps |
| CPU time | 13.58 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:38:05 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-c7e8a03c-2c1f-42b4-b576-8081fcae0c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105993272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.2105993272 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.1798997270 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 497371822 ps |
| CPU time | 16.04 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:38:00 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-11da4060-6f19-4dad-a511-88eb95310c71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798997270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1798997270 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.1156918374 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 168692036 ps |
| CPU time | 7.54 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:37:51 PM PST 24 |
| Peak memory | 552468 kb |
| Host | smart-c206cb67-7eb8-4095-9c9e-e288ccc7909d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156918374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1156918374 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.1505103645 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 7889629832 ps |
| CPU time | 84.82 seconds |
| Started | Jan 10 01:37:46 PM PST 24 |
| Finished | Jan 10 01:39:15 PM PST 24 |
| Peak memory | 552664 kb |
| Host | smart-a032dbdb-24d5-49b3-96a4-402c953030be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505103645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1505103645 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3671463761 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 4706465480 ps |
| CPU time | 80.1 seconds |
| Started | Jan 10 01:37:31 PM PST 24 |
| Finished | Jan 10 01:39:02 PM PST 24 |
| Peak memory | 552560 kb |
| Host | smart-7d06dd8c-efa7-4565-860d-40a70ab6f725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671463761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3671463761 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4016913904 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 49368606 ps |
| CPU time | 6.1 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:37:57 PM PST 24 |
| Peak memory | 553072 kb |
| Host | smart-aba3b814-b661-40f3-9ab5-c6802b6d65be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016913904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.4016913904 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.3583043397 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 271070794 ps |
| CPU time | 19.29 seconds |
| Started | Jan 10 01:37:27 PM PST 24 |
| Finished | Jan 10 01:37:59 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-40ccf5b3-235d-4c11-8113-dc5f8eb9767e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583043397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3583043397 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.155813649 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 144188116 ps |
| CPU time | 10.74 seconds |
| Started | Jan 10 01:37:37 PM PST 24 |
| Finished | Jan 10 01:37:56 PM PST 24 |
| Peak memory | 553804 kb |
| Host | smart-261f8f15-daae-4c8e-800e-43799185d707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155813649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.155813649 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1257563506 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 13586874883 ps |
| CPU time | 579.86 seconds |
| Started | Jan 10 01:37:35 PM PST 24 |
| Finished | Jan 10 01:47:24 PM PST 24 |
| Peak memory | 559916 kb |
| Host | smart-ce891ba1-88a5-40f0-b9d0-bd9f381931a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257563506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.1257563506 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.670005035 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 477984693 ps |
| CPU time | 20.82 seconds |
| Started | Jan 10 01:37:51 PM PST 24 |
| Finished | Jan 10 01:38:16 PM PST 24 |
| Peak memory | 553960 kb |
| Host | smart-596edb0b-15c8-4adb-82c7-41e244a8a034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670005035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.670005035 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.1704343318 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 4721867689 ps |
| CPU time | 311.33 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:43:02 PM PST 24 |
| Peak memory | 580788 kb |
| Host | smart-3f7cdbbd-5fc9-4be2-8a19-fd41119e7ef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704343318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1704343318 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.2918651068 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 710914611 ps |
| CPU time | 55.38 seconds |
| Started | Jan 10 01:37:56 PM PST 24 |
| Finished | Jan 10 01:38:57 PM PST 24 |
| Peak memory | 555088 kb |
| Host | smart-1897bf65-cc0a-4e2b-a0d2-dd5a7a8adcc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918651068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .2918651068 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.547760264 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 131993871525 ps |
| CPU time | 2297.07 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 02:16:24 PM PST 24 |
| Peak memory | 555960 kb |
| Host | smart-8a895650-56be-4701-b971-61be8968c4cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547760264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_d evice_slow_rsp.547760264 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.4080427492 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 152081984 ps |
| CPU time | 17.06 seconds |
| Started | Jan 10 01:37:33 PM PST 24 |
| Finished | Jan 10 01:38:00 PM PST 24 |
| Peak memory | 554628 kb |
| Host | smart-395f4404-deac-4f5b-bf49-5d05f855a2a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080427492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.4080427492 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.3942110206 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 830972784 ps |
| CPU time | 33.12 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:38:26 PM PST 24 |
| Peak memory | 554632 kb |
| Host | smart-664b9aab-89c2-4f2a-924e-83f73c4daae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942110206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3942110206 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.4051351953 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 1095439142 ps |
| CPU time | 41.62 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:38:34 PM PST 24 |
| Peak memory | 555012 kb |
| Host | smart-31eea831-14f6-434d-85f7-33b4ba862a5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051351953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.4051351953 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2393319457 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 119323835626 ps |
| CPU time | 1231.46 seconds |
| Started | Jan 10 01:37:36 PM PST 24 |
| Finished | Jan 10 01:58:17 PM PST 24 |
| Peak memory | 554888 kb |
| Host | smart-a5899fd0-8989-434c-96c6-5e83c086d983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393319457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2393319457 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3753465592 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 28555903079 ps |
| CPU time | 485.87 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:45:56 PM PST 24 |
| Peak memory | 555128 kb |
| Host | smart-45618116-ab89-4d27-923e-e0606ececc5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753465592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3753465592 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.4264437012 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 127865809 ps |
| CPU time | 13.56 seconds |
| Started | Jan 10 01:37:56 PM PST 24 |
| Finished | Jan 10 01:38:15 PM PST 24 |
| Peak memory | 554924 kb |
| Host | smart-65fce4ed-6201-4240-b20a-11857b73cae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264437012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.4264437012 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.2858219333 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 2113923696 ps |
| CPU time | 58.1 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:38:50 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-92012add-2d0e-467b-8fdb-9cef2039ec66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858219333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2858219333 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.1220581788 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 45485519 ps |
| CPU time | 6.45 seconds |
| Started | Jan 10 01:37:50 PM PST 24 |
| Finished | Jan 10 01:38:02 PM PST 24 |
| Peak memory | 552696 kb |
| Host | smart-03b869c8-54ce-4c5c-ab3a-f9c06b440e5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220581788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1220581788 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.3807081937 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 11216227495 ps |
| CPU time | 109.2 seconds |
| Started | Jan 10 01:37:44 PM PST 24 |
| Finished | Jan 10 01:39:38 PM PST 24 |
| Peak memory | 552764 kb |
| Host | smart-921d88b9-2917-4794-a006-f5a06caa0a09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807081937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3807081937 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3667150586 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 5866455541 ps |
| CPU time | 103.75 seconds |
| Started | Jan 10 01:37:29 PM PST 24 |
| Finished | Jan 10 01:39:25 PM PST 24 |
| Peak memory | 553048 kb |
| Host | smart-ac63282d-270c-4047-b20a-8445051c40ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667150586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3667150586 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.393693370 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 46790483 ps |
| CPU time | 6.23 seconds |
| Started | Jan 10 01:37:42 PM PST 24 |
| Finished | Jan 10 01:37:54 PM PST 24 |
| Peak memory | 552908 kb |
| Host | smart-7c213e65-058a-4d33-b682-3c44fc4fabd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393693370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays .393693370 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.1746659935 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2049138917 ps |
| CPU time | 162.73 seconds |
| Started | Jan 10 01:37:48 PM PST 24 |
| Finished | Jan 10 01:40:35 PM PST 24 |
| Peak memory | 556136 kb |
| Host | smart-366db0e9-88fb-48f4-8b4e-89fb25e6352d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746659935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1746659935 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2678115365 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 7276585828 ps |
| CPU time | 257.84 seconds |
| Started | Jan 10 01:37:47 PM PST 24 |
| Finished | Jan 10 01:42:08 PM PST 24 |
| Peak memory | 557264 kb |
| Host | smart-b7e6b86f-6390-460d-9645-1d23869438a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678115365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2678115365 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3439629071 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 5485185033 ps |
| CPU time | 300.26 seconds |
| Started | Jan 10 01:37:31 PM PST 24 |
| Finished | Jan 10 01:42:42 PM PST 24 |
| Peak memory | 556640 kb |
| Host | smart-2e43ca55-17d8-404d-b984-9e3aa306a898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439629071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.3439629071 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2192628475 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 14258361456 ps |
| CPU time | 558.33 seconds |
| Started | Jan 10 01:37:54 PM PST 24 |
| Finished | Jan 10 01:47:17 PM PST 24 |
| Peak memory | 559912 kb |
| Host | smart-b236b6e6-ccc9-4d88-8d63-486ed331ba37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192628475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.2192628475 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.244934381 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 1008322602 ps |
| CPU time | 37.63 seconds |
| Started | Jan 10 01:37:41 PM PST 24 |
| Finished | Jan 10 01:38:25 PM PST 24 |
| Peak memory | 554704 kb |
| Host | smart-8346ae31-30da-4bc9-855e-29b3354117f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244934381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.244934381 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.239020267 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 2056732859 ps |
| CPU time | 74.97 seconds |
| Started | Jan 10 01:37:59 PM PST 24 |
| Finished | Jan 10 01:39:20 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-5f6923c4-66dc-41e1-94ef-a33b2c8a2009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239020267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device. 239020267 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1274629983 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 25758738166 ps |
| CPU time | 432.76 seconds |
| Started | Jan 10 01:38:03 PM PST 24 |
| Finished | Jan 10 01:45:21 PM PST 24 |
| Peak memory | 554832 kb |
| Host | smart-50dc89e2-204b-473c-a405-5b0f3cc01f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274629983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.1274629983 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2580589192 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 908712121 ps |
| CPU time | 35.56 seconds |
| Started | Jan 10 01:38:02 PM PST 24 |
| Finished | Jan 10 01:38:43 PM PST 24 |
| Peak memory | 554672 kb |
| Host | smart-67232549-168d-4520-9831-7aeb2a6f2f20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580589192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.2580589192 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.1559618381 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 117777413 ps |
| CPU time | 10.5 seconds |
| Started | Jan 10 01:38:09 PM PST 24 |
| Finished | Jan 10 01:38:24 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-f659f491-b0ee-43d6-b821-3bb5f22a1480 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559618381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1559618381 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.2551140024 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 1402568472 ps |
| CPU time | 47.18 seconds |
| Started | Jan 10 01:37:50 PM PST 24 |
| Finished | Jan 10 01:38:42 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-f8a62be3-f875-4290-928b-6938da6188fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551140024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.2551140024 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1235056295 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 66532464015 ps |
| CPU time | 792.9 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:51:19 PM PST 24 |
| Peak memory | 555112 kb |
| Host | smart-dc72da38-37bc-4245-bfd1-8379288ddad8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235056295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1235056295 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.146160503 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 6790805647 ps |
| CPU time | 118.07 seconds |
| Started | Jan 10 01:37:46 PM PST 24 |
| Finished | Jan 10 01:39:48 PM PST 24 |
| Peak memory | 552848 kb |
| Host | smart-5ad1010f-f996-4184-bf03-fae0b4e8a0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146160503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.146160503 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.332810069 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 434543500 ps |
| CPU time | 38.48 seconds |
| Started | Jan 10 01:38:04 PM PST 24 |
| Finished | Jan 10 01:38:48 PM PST 24 |
| Peak memory | 555044 kb |
| Host | smart-c2f70714-9856-4ea8-afc6-6c7f5caf8b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332810069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_dela ys.332810069 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.3465070072 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 509301137 ps |
| CPU time | 34.21 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:38:41 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-95a68fd6-2d6a-4a89-a129-3915c1e13b73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465070072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3465070072 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.2801819375 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 51500192 ps |
| CPU time | 6.1 seconds |
| Started | Jan 10 01:37:51 PM PST 24 |
| Finished | Jan 10 01:38:02 PM PST 24 |
| Peak memory | 552940 kb |
| Host | smart-eaaf26ae-fc36-44df-9f84-7d716e6f300c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801819375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2801819375 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3592098012 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 6488199655 ps |
| CPU time | 67.79 seconds |
| Started | Jan 10 01:37:59 PM PST 24 |
| Finished | Jan 10 01:39:13 PM PST 24 |
| Peak memory | 552700 kb |
| Host | smart-ae0c2463-c3c7-4e2a-bf3d-67d4e76c653c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592098012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3592098012 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.360059829 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 4538038636 ps |
| CPU time | 74.95 seconds |
| Started | Jan 10 01:37:53 PM PST 24 |
| Finished | Jan 10 01:39:11 PM PST 24 |
| Peak memory | 552572 kb |
| Host | smart-10e7028f-e04a-4526-880e-adf32b9a1b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360059829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.360059829 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.262990805 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 47567813 ps |
| CPU time | 6.02 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:38:11 PM PST 24 |
| Peak memory | 552704 kb |
| Host | smart-f6ef3338-6d23-4f1c-ae09-0d1421aa525c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262990805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .262990805 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1664738396 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 1207863702 ps |
| CPU time | 103.51 seconds |
| Started | Jan 10 01:38:07 PM PST 24 |
| Finished | Jan 10 01:39:55 PM PST 24 |
| Peak memory | 555880 kb |
| Host | smart-166265e9-5bf8-4790-8d08-380cb9f50ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664738396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1664738396 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2100903210 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 11956486702 ps |
| CPU time | 401.19 seconds |
| Started | Jan 10 01:38:14 PM PST 24 |
| Finished | Jan 10 01:45:01 PM PST 24 |
| Peak memory | 556476 kb |
| Host | smart-97411563-0273-4211-9453-e35977615ec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100903210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2100903210 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.239553639 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 16854012143 ps |
| CPU time | 784.22 seconds |
| Started | Jan 10 01:38:03 PM PST 24 |
| Finished | Jan 10 01:51:13 PM PST 24 |
| Peak memory | 559904 kb |
| Host | smart-b605e611-605a-4665-80ec-190464ddd280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239553639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_rand_reset.239553639 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.138503428 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 8998063630 ps |
| CPU time | 480.81 seconds |
| Started | Jan 10 01:38:13 PM PST 24 |
| Finished | Jan 10 01:46:19 PM PST 24 |
| Peak memory | 559852 kb |
| Host | smart-6e13a479-0f58-4721-bd4d-f16cc2c405a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138503428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_reset_error.138503428 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.815272435 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1364273415 ps |
| CPU time | 51.96 seconds |
| Started | Jan 10 01:37:52 PM PST 24 |
| Finished | Jan 10 01:38:48 PM PST 24 |
| Peak memory | 555044 kb |
| Host | smart-ca448d6b-b6ff-4117-b783-571b3093cef1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815272435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.815272435 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.3225125488 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 4673374878 ps |
| CPU time | 534.94 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:47:01 PM PST 24 |
| Peak memory | 580912 kb |
| Host | smart-8f8638ba-81d3-4787-81cf-f17246ded902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225125488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.3225125488 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.902231729 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 798020102 ps |
| CPU time | 31.64 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:38:48 PM PST 24 |
| Peak memory | 554904 kb |
| Host | smart-dea0966e-c9bc-4474-a787-83378055d3d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902231729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device. 902231729 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.614835951 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 122595452 ps |
| CPU time | 14.54 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:38:30 PM PST 24 |
| Peak memory | 555020 kb |
| Host | smart-a4761678-02f2-4d9b-bca0-c48616be1eae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614835951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr .614835951 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.2191706766 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 1057192768 ps |
| CPU time | 32.27 seconds |
| Started | Jan 10 01:38:13 PM PST 24 |
| Finished | Jan 10 01:38:51 PM PST 24 |
| Peak memory | 554636 kb |
| Host | smart-fedfb0aa-a38f-43d4-8ec5-a7615f226544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191706766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2191706766 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.971841480 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 368296849 ps |
| CPU time | 14.5 seconds |
| Started | Jan 10 01:38:04 PM PST 24 |
| Finished | Jan 10 01:38:24 PM PST 24 |
| Peak memory | 554948 kb |
| Host | smart-8bf6f36a-0f68-4c73-ac78-856edf1e9f98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971841480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.971841480 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1324428008 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 67648626453 ps |
| CPU time | 700.45 seconds |
| Started | Jan 10 01:38:04 PM PST 24 |
| Finished | Jan 10 01:49:50 PM PST 24 |
| Peak memory | 554836 kb |
| Host | smart-34acc1f6-e23f-476c-84e8-3a0e1522c882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324428008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1324428008 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.2036249875 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 50137165182 ps |
| CPU time | 904.51 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:53:11 PM PST 24 |
| Peak memory | 554844 kb |
| Host | smart-7fc9a983-0c2c-4622-a0be-98e58f57140c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036249875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2036249875 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.610567229 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 602280639 ps |
| CPU time | 42.98 seconds |
| Started | Jan 10 01:38:09 PM PST 24 |
| Finished | Jan 10 01:38:57 PM PST 24 |
| Peak memory | 554924 kb |
| Host | smart-cdfbea69-f7cd-40f0-8ffb-38e9e769ae41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610567229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela ys.610567229 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.2574072066 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 856019348 ps |
| CPU time | 24.79 seconds |
| Started | Jan 10 01:37:58 PM PST 24 |
| Finished | Jan 10 01:38:28 PM PST 24 |
| Peak memory | 554716 kb |
| Host | smart-0e74b853-adde-439a-8338-227b2aed77e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574072066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2574072066 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.3192056951 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 201930412 ps |
| CPU time | 8.61 seconds |
| Started | Jan 10 01:38:15 PM PST 24 |
| Finished | Jan 10 01:38:29 PM PST 24 |
| Peak memory | 553096 kb |
| Host | smart-dde03bc9-116f-49a8-8755-9fbc5acc7782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192056951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3192056951 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.2246766109 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 7678441894 ps |
| CPU time | 78.08 seconds |
| Started | Jan 10 01:38:01 PM PST 24 |
| Finished | Jan 10 01:39:25 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-bce65c19-75fc-4b54-b43b-0e0bab7a37c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246766109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2246766109 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2801520583 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 5461112726 ps |
| CPU time | 81.91 seconds |
| Started | Jan 10 01:38:08 PM PST 24 |
| Finished | Jan 10 01:39:34 PM PST 24 |
| Peak memory | 552628 kb |
| Host | smart-25828de2-4728-49c6-ad5f-8e4f72795d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801520583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2801520583 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.463618497 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 50202712 ps |
| CPU time | 6.38 seconds |
| Started | Jan 10 01:37:57 PM PST 24 |
| Finished | Jan 10 01:38:09 PM PST 24 |
| Peak memory | 552892 kb |
| Host | smart-11909bf9-8838-4c6d-9698-8e59e7867caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463618497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays .463618497 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.1876637481 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 10442699878 ps |
| CPU time | 359.33 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:44:05 PM PST 24 |
| Peak memory | 556160 kb |
| Host | smart-7f582d31-7f9a-4095-a481-46868b2d2e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876637481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1876637481 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.3324281132 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 4233420081 ps |
| CPU time | 139.12 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:40:33 PM PST 24 |
| Peak memory | 556376 kb |
| Host | smart-0907f915-d7ba-45a4-9c9c-f889e7ab7cc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324281132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.3324281132 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.348825930 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 1115258387 ps |
| CPU time | 41.65 seconds |
| Started | Jan 10 01:38:04 PM PST 24 |
| Finished | Jan 10 01:38:51 PM PST 24 |
| Peak memory | 556104 kb |
| Host | smart-4e22277e-b135-4dcf-9fe8-ef5d2cea6d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348825930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_reset_error.348825930 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.545948423 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 696139190 ps |
| CPU time | 28.16 seconds |
| Started | Jan 10 01:38:12 PM PST 24 |
| Finished | Jan 10 01:38:46 PM PST 24 |
| Peak memory | 554812 kb |
| Host | smart-20cde776-2f80-40d8-b698-6e155c1ca37b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545948423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.545948423 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3718770885 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 97864083 ps |
| CPU time | 7.34 seconds |
| Started | Jan 10 01:38:09 PM PST 24 |
| Finished | Jan 10 01:38:21 PM PST 24 |
| Peak memory | 552612 kb |
| Host | smart-5b0df17c-a3d9-48cd-8f00-238e70f4f70c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718770885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .3718770885 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.161179842 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 93844080492 ps |
| CPU time | 1464.02 seconds |
| Started | Jan 10 01:38:06 PM PST 24 |
| Finished | Jan 10 02:02:35 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-e538f57c-acc9-4a04-b78f-e14c2b2c617b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161179842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_d evice_slow_rsp.161179842 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2357745980 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 593731407 ps |
| CPU time | 23.78 seconds |
| Started | Jan 10 01:38:02 PM PST 24 |
| Finished | Jan 10 01:38:32 PM PST 24 |
| Peak memory | 554712 kb |
| Host | smart-ef8f5989-244c-4f38-b322-1f8743e414d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357745980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.2357745980 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.1330576738 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 2298005025 ps |
| CPU time | 74.22 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:39:19 PM PST 24 |
| Peak memory | 555088 kb |
| Host | smart-c60c995e-e576-4316-9a14-821f78c4dd16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330576738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1330576738 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.1256545531 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 310725624 ps |
| CPU time | 26.32 seconds |
| Started | Jan 10 01:38:03 PM PST 24 |
| Finished | Jan 10 01:38:34 PM PST 24 |
| Peak memory | 553824 kb |
| Host | smart-7a0ded65-2686-4671-ab7d-6e2c3858e366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256545531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1256545531 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.4094373481 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 59789630486 ps |
| CPU time | 620.82 seconds |
| Started | Jan 10 01:38:03 PM PST 24 |
| Finished | Jan 10 01:48:29 PM PST 24 |
| Peak memory | 555148 kb |
| Host | smart-9e4f041b-89b1-49db-b0ed-af5c4cc6d06e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094373481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.4094373481 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.3053786380 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 46610355406 ps |
| CPU time | 716.24 seconds |
| Started | Jan 10 01:38:02 PM PST 24 |
| Finished | Jan 10 01:50:03 PM PST 24 |
| Peak memory | 554776 kb |
| Host | smart-0ed38c82-27ab-4a05-ae1a-445b4ed2c4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053786380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3053786380 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.2462576495 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 154394525 ps |
| CPU time | 14.51 seconds |
| Started | Jan 10 01:38:09 PM PST 24 |
| Finished | Jan 10 01:38:27 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-a9db6543-1cdf-4072-9657-7f99b88a340d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462576495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.2462576495 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.3112658263 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1334781874 ps |
| CPU time | 36.44 seconds |
| Started | Jan 10 01:38:09 PM PST 24 |
| Finished | Jan 10 01:38:50 PM PST 24 |
| Peak memory | 554716 kb |
| Host | smart-20d6ae27-7060-46b5-b178-53156e3c7573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112658263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3112658263 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.232162128 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 54905519 ps |
| CPU time | 6.36 seconds |
| Started | Jan 10 01:38:06 PM PST 24 |
| Finished | Jan 10 01:38:17 PM PST 24 |
| Peak memory | 552864 kb |
| Host | smart-cbff664d-fd76-4575-9ee2-d33ab525fd0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232162128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.232162128 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.3156027229 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 6192838668 ps |
| CPU time | 59.46 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:39:16 PM PST 24 |
| Peak memory | 552960 kb |
| Host | smart-fb107d2f-9d31-4eaf-a948-dc961571a15a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156027229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3156027229 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.4286889772 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 5219991320 ps |
| CPU time | 88.39 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:39:45 PM PST 24 |
| Peak memory | 552764 kb |
| Host | smart-ea7c3b89-fae7-4257-be79-2a087bd3ed61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286889772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.4286889772 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.1784614464 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 43138279 ps |
| CPU time | 5.58 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:38:21 PM PST 24 |
| Peak memory | 553068 kb |
| Host | smart-bcbb4fc2-4af4-4e9c-8acc-c0a794d7cbe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784614464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.1784614464 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3979041794 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 4285523278 ps |
| CPU time | 298.46 seconds |
| Started | Jan 10 01:38:16 PM PST 24 |
| Finished | Jan 10 01:43:20 PM PST 24 |
| Peak memory | 556604 kb |
| Host | smart-92ef7690-80b7-4982-a5da-c99cff1ceb11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979041794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3979041794 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3431145380 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 2550704202 ps |
| CPU time | 168.67 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:41:04 PM PST 24 |
| Peak memory | 555932 kb |
| Host | smart-b8454034-cede-4ffe-9baa-902325f77a18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431145380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3431145380 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3274940550 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 1242775949 ps |
| CPU time | 370.52 seconds |
| Started | Jan 10 01:38:12 PM PST 24 |
| Finished | Jan 10 01:44:28 PM PST 24 |
| Peak memory | 559528 kb |
| Host | smart-7ae2bcd2-ec27-4d36-92df-9aae1b50287e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274940550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.3274940550 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.4108694913 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 928771876 ps |
| CPU time | 38.35 seconds |
| Started | Jan 10 01:38:09 PM PST 24 |
| Finished | Jan 10 01:38:51 PM PST 24 |
| Peak memory | 555104 kb |
| Host | smart-bb09eb85-7971-4f22-90d0-7df71eb6be72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108694913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4108694913 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.3785020768 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 3930027295 ps |
| CPU time | 314.28 seconds |
| Started | Jan 10 01:38:02 PM PST 24 |
| Finished | Jan 10 01:43:22 PM PST 24 |
| Peak memory | 580832 kb |
| Host | smart-3695ac89-43f7-420c-8a4d-ca38b702386b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785020768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.3785020768 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.2116941409 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 2375538181 ps |
| CPU time | 86.31 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:39:54 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-b55c9894-9f80-4f13-84bd-5bb2d02a1cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116941409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .2116941409 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1288636364 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 21746369962 ps |
| CPU time | 331.14 seconds |
| Started | Jan 10 01:38:13 PM PST 24 |
| Finished | Jan 10 01:43:50 PM PST 24 |
| Peak memory | 554736 kb |
| Host | smart-cc1f5f24-6577-4314-9ca3-fd2afc195f63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288636364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.1288636364 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2520693626 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 16284114 ps |
| CPU time | 4.91 seconds |
| Started | Jan 10 01:38:19 PM PST 24 |
| Finished | Jan 10 01:38:28 PM PST 24 |
| Peak memory | 552596 kb |
| Host | smart-957672bc-dedc-4004-9688-f994e7e50f5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520693626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2520693626 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2993455440 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 706785288 ps |
| CPU time | 21.97 seconds |
| Started | Jan 10 01:38:17 PM PST 24 |
| Finished | Jan 10 01:38:44 PM PST 24 |
| Peak memory | 554884 kb |
| Host | smart-48f8f9fe-8fa0-4064-b55b-140b25fd8d2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993455440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2993455440 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.1772163411 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 1439132151 ps |
| CPU time | 48.64 seconds |
| Started | Jan 10 01:38:07 PM PST 24 |
| Finished | Jan 10 01:38:59 PM PST 24 |
| Peak memory | 554748 kb |
| Host | smart-9c917cbb-cbf0-401b-b247-2c979c4d001d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772163411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1772163411 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.4041427538 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 9681494822 ps |
| CPU time | 108.94 seconds |
| Started | Jan 10 01:38:07 PM PST 24 |
| Finished | Jan 10 01:40:00 PM PST 24 |
| Peak memory | 552792 kb |
| Host | smart-285e0bdd-8670-447e-9a15-cfc951078b79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041427538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.4041427538 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.3982390340 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 13070343917 ps |
| CPU time | 198.89 seconds |
| Started | Jan 10 01:38:14 PM PST 24 |
| Finished | Jan 10 01:41:38 PM PST 24 |
| Peak memory | 554708 kb |
| Host | smart-de4c2438-63ab-4c59-bef5-48ffa3ee2861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982390340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3982390340 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.2032291763 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 660321515 ps |
| CPU time | 51.8 seconds |
| Started | Jan 10 01:38:25 PM PST 24 |
| Finished | Jan 10 01:39:24 PM PST 24 |
| Peak memory | 554636 kb |
| Host | smart-26efeac1-10fc-4c60-a690-197eb863c7ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032291763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.2032291763 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.3234644294 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 474736420 ps |
| CPU time | 32.51 seconds |
| Started | Jan 10 01:38:25 PM PST 24 |
| Finished | Jan 10 01:39:05 PM PST 24 |
| Peak memory | 554644 kb |
| Host | smart-db9e3258-a23c-44b9-b028-80a619c0b610 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234644294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3234644294 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.3179532790 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 192516953 ps |
| CPU time | 8.18 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:38:23 PM PST 24 |
| Peak memory | 552952 kb |
| Host | smart-1063d3ed-1a38-4200-bcf8-e25c6069b44b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179532790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3179532790 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2612218165 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 8202680438 ps |
| CPU time | 81.27 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:39:36 PM PST 24 |
| Peak memory | 552596 kb |
| Host | smart-438f8f54-497a-4890-9be1-76ef1ae57129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612218165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2612218165 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.392968946 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 4791599770 ps |
| CPU time | 78.24 seconds |
| Started | Jan 10 01:38:13 PM PST 24 |
| Finished | Jan 10 01:39:37 PM PST 24 |
| Peak memory | 552628 kb |
| Host | smart-73dc2afe-726d-44ec-94ad-392c8e93afe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392968946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.392968946 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.76021583 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 40861896 ps |
| CPU time | 5.75 seconds |
| Started | Jan 10 01:38:12 PM PST 24 |
| Finished | Jan 10 01:38:23 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-1c33d749-c041-4413-9b93-e3a529b9929e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76021583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.76021583 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.107771888 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 6612651858 ps |
| CPU time | 215.31 seconds |
| Started | Jan 10 01:38:13 PM PST 24 |
| Finished | Jan 10 01:41:54 PM PST 24 |
| Peak memory | 555272 kb |
| Host | smart-f0a1edbe-9c66-4cdc-9c18-9e75e5c480aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107771888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.107771888 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.392467614 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 2520742464 ps |
| CPU time | 181.34 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:41:30 PM PST 24 |
| Peak memory | 555876 kb |
| Host | smart-91a07659-ad64-44d8-a55b-10021df52be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392467614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.392467614 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1574314155 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 5741604329 ps |
| CPU time | 335.5 seconds |
| Started | Jan 10 01:38:04 PM PST 24 |
| Finished | Jan 10 01:43:45 PM PST 24 |
| Peak memory | 557524 kb |
| Host | smart-ebdb3963-718f-493b-abcd-020e2994f664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574314155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.1574314155 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2421832630 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 1342076672 ps |
| CPU time | 52.81 seconds |
| Started | Jan 10 01:38:02 PM PST 24 |
| Finished | Jan 10 01:39:01 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-d5cbaa5d-2bdd-445b-af2d-24de33da8ba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421832630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2421832630 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.4168625816 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 816496457 ps |
| CPU time | 48.62 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:39:17 PM PST 24 |
| Peak memory | 553988 kb |
| Host | smart-8e98414f-e9fb-4b88-93d7-2b443495fb73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168625816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .4168625816 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3650237609 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 39225452515 ps |
| CPU time | 648.26 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:49:17 PM PST 24 |
| Peak memory | 554864 kb |
| Host | smart-c8e189e1-8bfb-4fe4-bdf1-c4b138bdd988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650237609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.3650237609 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1621692623 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 274319670 ps |
| CPU time | 25.76 seconds |
| Started | Jan 10 01:38:08 PM PST 24 |
| Finished | Jan 10 01:38:37 PM PST 24 |
| Peak memory | 553888 kb |
| Host | smart-bf5d5382-b9c5-4bfc-ba02-dff224bb49fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621692623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.1621692623 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.2674542749 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 1261006685 ps |
| CPU time | 42.93 seconds |
| Started | Jan 10 01:38:06 PM PST 24 |
| Finished | Jan 10 01:38:53 PM PST 24 |
| Peak memory | 553896 kb |
| Host | smart-aaeda51d-8e09-4931-9993-022ffacf40f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674542749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2674542749 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.1296597680 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 106525275 ps |
| CPU time | 11.15 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:38:39 PM PST 24 |
| Peak memory | 555080 kb |
| Host | smart-c0ed04a5-1768-416d-8c77-9749dfa874b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296597680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1296597680 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2607101959 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 77826868695 ps |
| CPU time | 797.68 seconds |
| Started | Jan 10 01:38:16 PM PST 24 |
| Finished | Jan 10 01:51:39 PM PST 24 |
| Peak memory | 554844 kb |
| Host | smart-a159f13a-63d8-40c0-a380-507e14f1d977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607101959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2607101959 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.964934569 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 12699467724 ps |
| CPU time | 205.81 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:41:55 PM PST 24 |
| Peak memory | 555156 kb |
| Host | smart-3e98e7c4-9c80-44cb-bf95-a5fa17a1b8ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964934569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.964934569 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.677795774 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 516508741 ps |
| CPU time | 37.31 seconds |
| Started | Jan 10 01:38:18 PM PST 24 |
| Finished | Jan 10 01:39:00 PM PST 24 |
| Peak memory | 553920 kb |
| Host | smart-866435ea-8265-4026-a96b-6310f7772df2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677795774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_dela ys.677795774 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.482311636 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 820822067 ps |
| CPU time | 23.38 seconds |
| Started | Jan 10 01:38:06 PM PST 24 |
| Finished | Jan 10 01:38:34 PM PST 24 |
| Peak memory | 554776 kb |
| Host | smart-b831ebd5-468a-4dfe-8111-95186867d07d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482311636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.482311636 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.3882126200 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 39420450 ps |
| CPU time | 5.8 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:38:34 PM PST 24 |
| Peak memory | 552980 kb |
| Host | smart-3cb5206c-a155-47fa-a81d-5b7547e03f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882126200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3882126200 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.4281669913 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 9096532540 ps |
| CPU time | 86.6 seconds |
| Started | Jan 10 01:38:16 PM PST 24 |
| Finished | Jan 10 01:39:48 PM PST 24 |
| Peak memory | 553020 kb |
| Host | smart-dbcfb8c8-7e5a-452e-ae20-1afde6444091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281669913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4281669913 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3507031936 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 5673949157 ps |
| CPU time | 88.68 seconds |
| Started | Jan 10 01:38:16 PM PST 24 |
| Finished | Jan 10 01:39:50 PM PST 24 |
| Peak memory | 552740 kb |
| Host | smart-5b707c84-6d4a-4d16-b911-22a03a2cbb7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507031936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3507031936 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1593236984 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 46855859 ps |
| CPU time | 6.11 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:38:35 PM PST 24 |
| Peak memory | 552976 kb |
| Host | smart-073f848b-1595-4086-82ae-2ab16d927995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593236984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.1593236984 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.2270778742 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 4455717771 ps |
| CPU time | 180.69 seconds |
| Started | Jan 10 01:38:19 PM PST 24 |
| Finished | Jan 10 01:41:24 PM PST 24 |
| Peak memory | 556236 kb |
| Host | smart-46c4b778-d3ed-4339-b80e-ef68640b027b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270778742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.2270778742 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.169906456 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 13844644325 ps |
| CPU time | 453.09 seconds |
| Started | Jan 10 01:38:18 PM PST 24 |
| Finished | Jan 10 01:45:55 PM PST 24 |
| Peak memory | 555956 kb |
| Host | smart-f0bb373a-a3dc-4e34-8b8f-e55b6071eef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169906456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.169906456 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.267293804 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 1143938910 ps |
| CPU time | 51.39 seconds |
| Started | Jan 10 01:38:20 PM PST 24 |
| Finished | Jan 10 01:39:15 PM PST 24 |
| Peak memory | 556200 kb |
| Host | smart-6514ca2d-61d5-469c-8071-2319e16248f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267293804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_ with_rand_reset.267293804 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1946496666 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 168657461 ps |
| CPU time | 21.21 seconds |
| Started | Jan 10 01:38:17 PM PST 24 |
| Finished | Jan 10 01:38:43 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-48900bd2-2d7b-4941-bd6d-246fcb340a62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946496666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1946496666 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.3701873036 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 4378609239 ps |
| CPU time | 250.46 seconds |
| Started | Jan 10 01:38:08 PM PST 24 |
| Finished | Jan 10 01:42:23 PM PST 24 |
| Peak memory | 580856 kb |
| Host | smart-067ad414-2bcd-47cc-859b-e08fe9aab35a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701873036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3701873036 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3914238423 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 2427862007 ps |
| CPU time | 89.46 seconds |
| Started | Jan 10 01:38:12 PM PST 24 |
| Finished | Jan 10 01:39:46 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-e3491d88-536b-4213-ab3d-0712af99e4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914238423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .3914238423 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1730766573 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 75791777177 ps |
| CPU time | 1337.06 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 02:00:33 PM PST 24 |
| Peak memory | 555956 kb |
| Host | smart-e2414237-cf66-434b-a28c-dc982c3ed559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730766573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.1730766573 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1463718440 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 38231215 ps |
| CPU time | 6.71 seconds |
| Started | Jan 10 01:38:13 PM PST 24 |
| Finished | Jan 10 01:38:25 PM PST 24 |
| Peak memory | 552432 kb |
| Host | smart-f76b3241-b147-4330-bb6e-6858c0b720af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463718440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.1463718440 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.644131716 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 206363144 ps |
| CPU time | 17.3 seconds |
| Started | Jan 10 01:38:11 PM PST 24 |
| Finished | Jan 10 01:38:33 PM PST 24 |
| Peak memory | 554748 kb |
| Host | smart-afc3b1cb-86c6-496a-82ab-27a9a11e0e66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644131716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.644131716 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.4179417749 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 1281351493 ps |
| CPU time | 41.61 seconds |
| Started | Jan 10 01:38:09 PM PST 24 |
| Finished | Jan 10 01:38:55 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-facfc5f8-7252-4801-8767-dfe470859a08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179417749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.4179417749 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.3914571559 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 62689123028 ps |
| CPU time | 641.01 seconds |
| Started | Jan 10 01:37:59 PM PST 24 |
| Finished | Jan 10 01:48:45 PM PST 24 |
| Peak memory | 554880 kb |
| Host | smart-109655c8-5117-4cf2-a207-cd98aea4236a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914571559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3914571559 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3186043982 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 44858385607 ps |
| CPU time | 775.37 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:51:02 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-68b8d4ed-6513-4630-b553-0806cbae0bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186043982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3186043982 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.433474377 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 253845968 ps |
| CPU time | 21.17 seconds |
| Started | Jan 10 01:38:18 PM PST 24 |
| Finished | Jan 10 01:38:43 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-bf8717cb-4eab-4e3a-89d3-c161e6a8801c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433474377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_dela ys.433474377 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.4037988112 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 266969788 ps |
| CPU time | 9.95 seconds |
| Started | Jan 10 01:38:04 PM PST 24 |
| Finished | Jan 10 01:38:20 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-ffa4ad11-a5ed-4f45-85e2-aba00a274f6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037988112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4037988112 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.4179862207 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 205131227 ps |
| CPU time | 8.31 seconds |
| Started | Jan 10 01:38:08 PM PST 24 |
| Finished | Jan 10 01:38:20 PM PST 24 |
| Peak memory | 552596 kb |
| Host | smart-f3ba9193-2e9e-4fc9-98ef-fc6ea42ad097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179862207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.4179862207 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1046627457 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 8069185943 ps |
| CPU time | 81.29 seconds |
| Started | Jan 10 01:38:12 PM PST 24 |
| Finished | Jan 10 01:39:38 PM PST 24 |
| Peak memory | 553016 kb |
| Host | smart-c975aa95-685a-4ee9-8410-959f68c4fedd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046627457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1046627457 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1259871692 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 4876519810 ps |
| CPU time | 79.8 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:39:34 PM PST 24 |
| Peak memory | 552796 kb |
| Host | smart-738a7dc7-89a7-46ec-91d9-103205579ee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259871692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1259871692 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3302826536 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 51959277 ps |
| CPU time | 6.25 seconds |
| Started | Jan 10 01:38:08 PM PST 24 |
| Finished | Jan 10 01:38:18 PM PST 24 |
| Peak memory | 552408 kb |
| Host | smart-32b30b12-6a35-4204-a7d4-5076dff510f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302826536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.3302826536 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.185934790 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 2985428435 ps |
| CPU time | 83.28 seconds |
| Started | Jan 10 01:38:04 PM PST 24 |
| Finished | Jan 10 01:39:32 PM PST 24 |
| Peak memory | 555172 kb |
| Host | smart-3e375be0-99aa-4142-b96d-25884313fe4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185934790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.185934790 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.190298050 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 221134988 ps |
| CPU time | 10.8 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:38:40 PM PST 24 |
| Peak memory | 553740 kb |
| Host | smart-865109f8-6e6a-48d3-8d16-9aa25006a479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190298050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.190298050 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.3018849116 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 106689481 ps |
| CPU time | 34.73 seconds |
| Started | Jan 10 01:38:10 PM PST 24 |
| Finished | Jan 10 01:38:49 PM PST 24 |
| Peak memory | 554976 kb |
| Host | smart-b2201bb7-0805-49ec-ba5e-137f6fd06c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018849116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.3018849116 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2973518931 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 10702143 ps |
| CPU time | 4.72 seconds |
| Started | Jan 10 01:38:25 PM PST 24 |
| Finished | Jan 10 01:38:37 PM PST 24 |
| Peak memory | 552960 kb |
| Host | smart-cc1beba2-f716-4069-9ac1-b9f90c41b5e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973518931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2973518931 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.3449010652 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1026389480 ps |
| CPU time | 42.28 seconds |
| Started | Jan 10 01:38:00 PM PST 24 |
| Finished | Jan 10 01:38:47 PM PST 24 |
| Peak memory | 555112 kb |
| Host | smart-82f4aff7-fdab-4277-8b99-2e27a752706a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449010652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3449010652 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.1163211042 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 56130083805 ps |
| CPU time | 8105.32 seconds |
| Started | Jan 10 01:36:01 PM PST 24 |
| Finished | Jan 10 03:51:18 PM PST 24 |
| Peak memory | 624700 kb |
| Host | smart-fb0913cf-3c84-4088-a51f-857e96ff93de |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163211042 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.1163211042 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.1250338356 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 14036735750 ps |
| CPU time | 1736 seconds |
| Started | Jan 10 01:35:47 PM PST 24 |
| Finished | Jan 10 02:05:00 PM PST 24 |
| Peak memory | 579428 kb |
| Host | smart-84beb8ed-4a99-4f1e-a6c1-d4065b2b21fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250338356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.1250338356 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1332446966 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 6963164176 ps |
| CPU time | 273.38 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:40:42 PM PST 24 |
| Peak memory | 614580 kb |
| Host | smart-56b3e5f8-91f2-4dcd-821c-a726b5656176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332446966 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.1332446966 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.2390565398 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 6819527425 ps |
| CPU time | 568.81 seconds |
| Started | Jan 10 01:35:55 PM PST 24 |
| Finished | Jan 10 01:45:37 PM PST 24 |
| Peak memory | 580980 kb |
| Host | smart-63ceed27-ec50-4f44-b3de-41fc5f9515d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390565398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2390565398 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1242117550 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 14178729601 ps |
| CPU time | 1684.32 seconds |
| Started | Jan 10 01:35:49 PM PST 24 |
| Finished | Jan 10 02:04:09 PM PST 24 |
| Peak memory | 580856 kb |
| Host | smart-24cd9c57-35b2-47d7-8b2a-4cc1642a8611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242117550 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1242117550 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.3276074539 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2549497248 ps |
| CPU time | 94.17 seconds |
| Started | Jan 10 01:35:50 PM PST 24 |
| Finished | Jan 10 01:37:39 PM PST 24 |
| Peak memory | 580784 kb |
| Host | smart-b3d903f0-ebb7-424e-87c1-0a2bacb324e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276074539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.3276074539 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.1425769545 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 2764107862 ps |
| CPU time | 94.9 seconds |
| Started | Jan 10 01:35:52 PM PST 24 |
| Finished | Jan 10 01:37:41 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-a3ccb1a1-a134-44b6-a380-1123a7c6ba78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425769545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 1425769545 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1717444039 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 105095232478 ps |
| CPU time | 1904.23 seconds |
| Started | Jan 10 01:35:57 PM PST 24 |
| Finished | Jan 10 02:07:54 PM PST 24 |
| Peak memory | 556208 kb |
| Host | smart-3abbf973-de1e-4b77-b847-0b82c03dd1ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717444039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.1717444039 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.433062379 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 103595666 ps |
| CPU time | 12.16 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:36:21 PM PST 24 |
| Peak memory | 554648 kb |
| Host | smart-f5514d0f-ef77-4a94-aa8a-bab6b7aa1432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433062379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr. 433062379 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.2043529132 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 1885028128 ps |
| CPU time | 68.21 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 01:37:15 PM PST 24 |
| Peak memory | 554728 kb |
| Host | smart-8d0a2f91-fd50-4b78-a55e-255974f4f2f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043529132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2043529132 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.3754134307 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 1155854877 ps |
| CPU time | 38.26 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:36:44 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-53f03d3a-a070-4f2a-bd61-cb1fc924335f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754134307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.3754134307 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.197477594 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 18153243220 ps |
| CPU time | 198.61 seconds |
| Started | Jan 10 01:35:48 PM PST 24 |
| Finished | Jan 10 01:39:23 PM PST 24 |
| Peak memory | 554820 kb |
| Host | smart-42a073d1-4878-4b93-8e56-428b2df5c07c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197477594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.197477594 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.662806331 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 59599979542 ps |
| CPU time | 1060.25 seconds |
| Started | Jan 10 01:35:50 PM PST 24 |
| Finished | Jan 10 01:53:45 PM PST 24 |
| Peak memory | 554828 kb |
| Host | smart-9b24ff2c-1d38-4668-badb-c18fd1926d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662806331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.662806331 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.2160823150 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 231288408 ps |
| CPU time | 21.32 seconds |
| Started | Jan 10 01:35:52 PM PST 24 |
| Finished | Jan 10 01:36:27 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-223e3d18-13f2-4231-ac29-8015b346b9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160823150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.2160823150 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.1062631837 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 161092769 ps |
| CPU time | 12.78 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:36:21 PM PST 24 |
| Peak memory | 554680 kb |
| Host | smart-a6f59e9e-c22a-4d2f-a8ec-ab123738181f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062631837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1062631837 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.2812425019 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 225802975 ps |
| CPU time | 9.39 seconds |
| Started | Jan 10 01:35:50 PM PST 24 |
| Finished | Jan 10 01:36:14 PM PST 24 |
| Peak memory | 552964 kb |
| Host | smart-8e9b962a-823b-4200-97c1-233e7da10d12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812425019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2812425019 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.4108438645 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 7686409881 ps |
| CPU time | 86.44 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:37:35 PM PST 24 |
| Peak memory | 552728 kb |
| Host | smart-8c28c907-0107-47a4-b6f0-6285dc1b2689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108438645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.4108438645 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.63433943 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 5306019578 ps |
| CPU time | 84.15 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:37:33 PM PST 24 |
| Peak memory | 552980 kb |
| Host | smart-0a725a69-7bdb-40b7-a1a1-1738f7b2d7ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63433943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.63433943 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1804604463 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 44808024 ps |
| CPU time | 5.75 seconds |
| Started | Jan 10 01:35:49 PM PST 24 |
| Finished | Jan 10 01:36:10 PM PST 24 |
| Peak memory | 552676 kb |
| Host | smart-0b8cd4f3-c185-45fa-bf0e-c2eb9df858fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804604463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .1804604463 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.2394579030 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 6825958407 ps |
| CPU time | 244 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:40:14 PM PST 24 |
| Peak memory | 555216 kb |
| Host | smart-ecb80914-5c97-4275-a483-d3a83dea15ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394579030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2394579030 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2367135344 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 1138032851 ps |
| CPU time | 83.19 seconds |
| Started | Jan 10 01:35:55 PM PST 24 |
| Finished | Jan 10 01:37:31 PM PST 24 |
| Peak memory | 554752 kb |
| Host | smart-42c86f28-17f5-4414-ac88-21d519c2f17b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367135344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2367135344 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2308846180 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 1317522246 ps |
| CPU time | 146.85 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:38:33 PM PST 24 |
| Peak memory | 555964 kb |
| Host | smart-b8081d29-a42b-44d1-be31-60265a7d6631 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308846180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.2308846180 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1596247778 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 13307486530 ps |
| CPU time | 712.8 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:47:59 PM PST 24 |
| Peak memory | 559976 kb |
| Host | smart-a74c542a-acd7-4606-91eb-c2d74373652f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596247778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.1596247778 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.451325611 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 129015937 ps |
| CPU time | 8.97 seconds |
| Started | Jan 10 01:35:44 PM PST 24 |
| Finished | Jan 10 01:36:10 PM PST 24 |
| Peak memory | 552976 kb |
| Host | smart-24a8cfd3-694d-4c2d-b274-92d0a01b348b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451325611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.451325611 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.3333567737 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 918557183 ps |
| CPU time | 65.3 seconds |
| Started | Jan 10 01:38:24 PM PST 24 |
| Finished | Jan 10 01:39:36 PM PST 24 |
| Peak memory | 554820 kb |
| Host | smart-d4988f17-3800-47a7-8abd-637d5a1edf3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333567737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .3333567737 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1627726438 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 41313180650 ps |
| CPU time | 712.25 seconds |
| Started | Jan 10 01:38:21 PM PST 24 |
| Finished | Jan 10 01:50:18 PM PST 24 |
| Peak memory | 555040 kb |
| Host | smart-ec90e0cd-c14b-455c-a367-4480626a3eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627726438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.1627726438 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.266321181 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 278495595 ps |
| CPU time | 27.6 seconds |
| Started | Jan 10 01:38:35 PM PST 24 |
| Finished | Jan 10 01:39:06 PM PST 24 |
| Peak memory | 554716 kb |
| Host | smart-6dd2268b-2a40-4d45-9371-8e5399b4a824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266321181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr .266321181 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.1215257496 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 1501483864 ps |
| CPU time | 50.92 seconds |
| Started | Jan 10 01:38:19 PM PST 24 |
| Finished | Jan 10 01:39:14 PM PST 24 |
| Peak memory | 554708 kb |
| Host | smart-d2856bd9-7a09-42e9-a18b-62cca12c63ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215257496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.1215257496 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.2477417307 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 449283628 ps |
| CPU time | 41.08 seconds |
| Started | Jan 10 01:38:20 PM PST 24 |
| Finished | Jan 10 01:39:06 PM PST 24 |
| Peak memory | 555052 kb |
| Host | smart-db054794-8d09-421a-a10c-ecf1fdbbd05b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477417307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.2477417307 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2640083544 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 63950891305 ps |
| CPU time | 645.05 seconds |
| Started | Jan 10 01:38:35 PM PST 24 |
| Finished | Jan 10 01:49:24 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-415ac7d0-e346-4192-9363-6dd54de3ed87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640083544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2640083544 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.4153687976 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 51987460104 ps |
| CPU time | 936.56 seconds |
| Started | Jan 10 01:38:25 PM PST 24 |
| Finished | Jan 10 01:54:09 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-b7baf07b-6f13-437f-94d2-b1c10455f9e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153687976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.4153687976 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.201881462 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 204217122 ps |
| CPU time | 19.1 seconds |
| Started | Jan 10 01:38:19 PM PST 24 |
| Finished | Jan 10 01:38:42 PM PST 24 |
| Peak memory | 554972 kb |
| Host | smart-9a5fa039-651e-4ebf-ab5c-e03136f2c6c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201881462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_dela ys.201881462 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.662962156 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 1980995420 ps |
| CPU time | 54.01 seconds |
| Started | Jan 10 01:38:24 PM PST 24 |
| Finished | Jan 10 01:39:25 PM PST 24 |
| Peak memory | 554744 kb |
| Host | smart-f3822d94-5efd-48c7-9178-c5ceef32db8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662962156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.662962156 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.3753765704 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 192361400 ps |
| CPU time | 8.69 seconds |
| Started | Jan 10 01:38:23 PM PST 24 |
| Finished | Jan 10 01:38:39 PM PST 24 |
| Peak memory | 552668 kb |
| Host | smart-6ba5821d-c7f4-4838-9e5e-25e64d86608b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753765704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3753765704 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.698351265 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 8932328426 ps |
| CPU time | 92.16 seconds |
| Started | Jan 10 01:38:24 PM PST 24 |
| Finished | Jan 10 01:40:03 PM PST 24 |
| Peak memory | 553012 kb |
| Host | smart-a4d1497d-db79-4841-bdd8-de6c5cd7436b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698351265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.698351265 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.2961344879 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 4919584324 ps |
| CPU time | 81.93 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:39:51 PM PST 24 |
| Peak memory | 553008 kb |
| Host | smart-957807e5-75a7-43cd-bac1-138f928db949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961344879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2961344879 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.494884142 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 53367762 ps |
| CPU time | 6.56 seconds |
| Started | Jan 10 01:38:26 PM PST 24 |
| Finished | Jan 10 01:38:39 PM PST 24 |
| Peak memory | 552680 kb |
| Host | smart-bbe73beb-4b84-4424-a47a-39e9fd3a9296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494884142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays .494884142 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.705522517 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 5448631376 ps |
| CPU time | 201.13 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:41:49 PM PST 24 |
| Peak memory | 556208 kb |
| Host | smart-a149b491-81b1-47d6-82fc-3c2bf57b3919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705522517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.705522517 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1485274312 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 12072405603 ps |
| CPU time | 410.31 seconds |
| Started | Jan 10 01:38:22 PM PST 24 |
| Finished | Jan 10 01:45:19 PM PST 24 |
| Peak memory | 555964 kb |
| Host | smart-5cb75dc7-eaef-494f-8de6-d47758101772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485274312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1485274312 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.4270207090 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2940519314 ps |
| CPU time | 338.96 seconds |
| Started | Jan 10 01:38:21 PM PST 24 |
| Finished | Jan 10 01:44:06 PM PST 24 |
| Peak memory | 558340 kb |
| Host | smart-d38bf8ec-0f2c-46df-a033-d26b4e222ca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270207090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.4270207090 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2109457430 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 1499431921 ps |
| CPU time | 55.91 seconds |
| Started | Jan 10 01:38:39 PM PST 24 |
| Finished | Jan 10 01:39:39 PM PST 24 |
| Peak memory | 553916 kb |
| Host | smart-e7dab12b-b6b7-4959-8ff6-d18156517677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109457430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2109457430 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.3660589638 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 709231722 ps |
| CPU time | 26.56 seconds |
| Started | Jan 10 01:38:34 PM PST 24 |
| Finished | Jan 10 01:39:04 PM PST 24 |
| Peak memory | 555008 kb |
| Host | smart-db1c19fa-c700-4a35-8ec3-5bd206febcce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660589638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .3660589638 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.3608224909 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 56637356869 ps |
| CPU time | 918.05 seconds |
| Started | Jan 10 01:38:23 PM PST 24 |
| Finished | Jan 10 01:53:49 PM PST 24 |
| Peak memory | 555136 kb |
| Host | smart-4f5fdffc-84a3-40f7-9f3a-66773561e014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608224909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.3608224909 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1033035748 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 37313726 ps |
| CPU time | 6.96 seconds |
| Started | Jan 10 01:38:40 PM PST 24 |
| Finished | Jan 10 01:38:51 PM PST 24 |
| Peak memory | 552936 kb |
| Host | smart-8ac413ce-051c-4aeb-8161-37e08ad647d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033035748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.1033035748 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.3204530609 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 1681610122 ps |
| CPU time | 53.38 seconds |
| Started | Jan 10 01:38:40 PM PST 24 |
| Finished | Jan 10 01:39:37 PM PST 24 |
| Peak memory | 554712 kb |
| Host | smart-900f2e79-fd61-4414-b45b-28a67846aff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204530609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3204530609 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.2377238062 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 2268904011 ps |
| CPU time | 75.6 seconds |
| Started | Jan 10 01:38:24 PM PST 24 |
| Finished | Jan 10 01:39:47 PM PST 24 |
| Peak memory | 554844 kb |
| Host | smart-27014a46-bc90-433a-85cb-99574cd848b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377238062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.2377238062 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2528461470 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 5142369023 ps |
| CPU time | 51.88 seconds |
| Started | Jan 10 01:38:38 PM PST 24 |
| Finished | Jan 10 01:39:34 PM PST 24 |
| Peak memory | 553000 kb |
| Host | smart-77df3ee8-f51a-4572-b34a-c12a98193c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528461470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2528461470 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2020667301 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 63226555136 ps |
| CPU time | 1117.12 seconds |
| Started | Jan 10 01:38:26 PM PST 24 |
| Finished | Jan 10 01:57:10 PM PST 24 |
| Peak memory | 554796 kb |
| Host | smart-f61a234a-3ca4-477e-be67-63340dc55b5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020667301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2020667301 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.2346018195 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 127625627 ps |
| CPU time | 12.36 seconds |
| Started | Jan 10 01:38:25 PM PST 24 |
| Finished | Jan 10 01:38:45 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-726631a0-adc9-45ae-beb6-bdb2123bd736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346018195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.2346018195 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.2109004615 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 571392187 ps |
| CPU time | 35.33 seconds |
| Started | Jan 10 01:38:24 PM PST 24 |
| Finished | Jan 10 01:39:07 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-11b88da3-11ba-489a-816d-9da63f3bf21e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109004615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2109004615 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.824283766 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 140296374 ps |
| CPU time | 7.34 seconds |
| Started | Jan 10 01:38:19 PM PST 24 |
| Finished | Jan 10 01:38:31 PM PST 24 |
| Peak memory | 552536 kb |
| Host | smart-9b541593-e130-4bbe-99a9-9dafc6c345c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824283766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.824283766 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.1721861466 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 9379727613 ps |
| CPU time | 93.6 seconds |
| Started | Jan 10 01:38:40 PM PST 24 |
| Finished | Jan 10 01:40:17 PM PST 24 |
| Peak memory | 552572 kb |
| Host | smart-512d9271-b91f-44a1-9a7c-edba9c5bbaf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721861466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.1721861466 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1611216648 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 5686873466 ps |
| CPU time | 88.96 seconds |
| Started | Jan 10 01:38:23 PM PST 24 |
| Finished | Jan 10 01:39:59 PM PST 24 |
| Peak memory | 552748 kb |
| Host | smart-a86492eb-5760-4189-ab10-c551ef03b2f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611216648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1611216648 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1913566769 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 44914079 ps |
| CPU time | 5.94 seconds |
| Started | Jan 10 01:38:35 PM PST 24 |
| Finished | Jan 10 01:38:44 PM PST 24 |
| Peak memory | 552472 kb |
| Host | smart-3a5d4f4f-0652-4072-bb33-38b21748605b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913566769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.1913566769 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.3376884598 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 240698278 ps |
| CPU time | 22.22 seconds |
| Started | Jan 10 01:38:39 PM PST 24 |
| Finished | Jan 10 01:39:05 PM PST 24 |
| Peak memory | 554004 kb |
| Host | smart-aab3ec61-d90b-4220-83a6-229601ca73b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376884598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3376884598 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.2469301382 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 1620903854 ps |
| CPU time | 51.65 seconds |
| Started | Jan 10 01:38:40 PM PST 24 |
| Finished | Jan 10 01:39:35 PM PST 24 |
| Peak memory | 556052 kb |
| Host | smart-4edabd20-e487-491d-b744-f7027c8317ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469301382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.2469301382 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.3052409058 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 245027761 ps |
| CPU time | 51.48 seconds |
| Started | Jan 10 01:38:20 PM PST 24 |
| Finished | Jan 10 01:39:15 PM PST 24 |
| Peak memory | 555996 kb |
| Host | smart-96e92f1d-882d-440c-8ce5-62e5ed1c52b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052409058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.3052409058 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1042888920 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 4361109693 ps |
| CPU time | 407.21 seconds |
| Started | Jan 10 01:38:26 PM PST 24 |
| Finished | Jan 10 01:45:20 PM PST 24 |
| Peak memory | 559104 kb |
| Host | smart-4e1510bd-db1c-49da-9cd1-11d594549d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042888920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.1042888920 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.4085580596 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 82508876 ps |
| CPU time | 6.12 seconds |
| Started | Jan 10 01:38:38 PM PST 24 |
| Finished | Jan 10 01:38:49 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-8ab573a8-c286-4ada-8813-d49adc1123c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085580596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4085580596 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3806876868 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 134836537 ps |
| CPU time | 8.48 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:39:07 PM PST 24 |
| Peak memory | 552564 kb |
| Host | smart-f53e0169-5d76-4181-9bd0-c0c69723bbcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806876868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3806876868 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.959780227 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 62592339243 ps |
| CPU time | 1140.95 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:57:59 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-c9d2006e-35ca-4294-8767-ceeedf76beca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959780227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d evice_slow_rsp.959780227 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3331314031 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 180694099 ps |
| CPU time | 19.25 seconds |
| Started | Jan 10 01:38:53 PM PST 24 |
| Finished | Jan 10 01:39:14 PM PST 24 |
| Peak memory | 555104 kb |
| Host | smart-e6b8ebe4-bbf4-4793-82fc-b59b4dbe3fd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331314031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.3331314031 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.2025842808 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 533318389 ps |
| CPU time | 50.33 seconds |
| Started | Jan 10 01:38:54 PM PST 24 |
| Finished | Jan 10 01:39:47 PM PST 24 |
| Peak memory | 554668 kb |
| Host | smart-63534f2b-9af7-4831-a771-ae7260203c05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025842808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2025842808 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.582922427 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 408822616 ps |
| CPU time | 32.35 seconds |
| Started | Jan 10 01:38:31 PM PST 24 |
| Finished | Jan 10 01:39:07 PM PST 24 |
| Peak memory | 554920 kb |
| Host | smart-0bcd9850-97cb-4271-8f68-a4c44955d42f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582922427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.582922427 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3381023641 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 12927153640 ps |
| CPU time | 130.5 seconds |
| Started | Jan 10 01:38:28 PM PST 24 |
| Finished | Jan 10 01:40:44 PM PST 24 |
| Peak memory | 553960 kb |
| Host | smart-4793022b-63d6-4967-93fd-bcf6964ac886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381023641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3381023641 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2784039440 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 63944965756 ps |
| CPU time | 1167.89 seconds |
| Started | Jan 10 01:38:23 PM PST 24 |
| Finished | Jan 10 01:57:58 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-e708f9bf-b906-4736-a547-a176fb3b2038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784039440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2784039440 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.2059120951 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 71955516 ps |
| CPU time | 7.81 seconds |
| Started | Jan 10 01:38:24 PM PST 24 |
| Finished | Jan 10 01:38:39 PM PST 24 |
| Peak memory | 553988 kb |
| Host | smart-ff18c8b5-2091-4380-ad23-2036e693435c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059120951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.2059120951 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.2956429669 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 205705326 ps |
| CPU time | 15.81 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:39:16 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-a8e4eda8-46ec-4ff8-ac32-7d1a3dbf3705 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956429669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2956429669 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.3950579567 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 167422743 ps |
| CPU time | 8.11 seconds |
| Started | Jan 10 01:38:34 PM PST 24 |
| Finished | Jan 10 01:38:45 PM PST 24 |
| Peak memory | 552628 kb |
| Host | smart-fc196e95-255a-4b50-a840-1b261a59a966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950579567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3950579567 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2001640419 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 7752190220 ps |
| CPU time | 79.21 seconds |
| Started | Jan 10 01:38:28 PM PST 24 |
| Finished | Jan 10 01:39:52 PM PST 24 |
| Peak memory | 552896 kb |
| Host | smart-a9ad51fc-c666-47ab-a413-bcfd0cfb040d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001640419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2001640419 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.921029314 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 4256426134 ps |
| CPU time | 71.27 seconds |
| Started | Jan 10 01:38:27 PM PST 24 |
| Finished | Jan 10 01:39:44 PM PST 24 |
| Peak memory | 552744 kb |
| Host | smart-5ab292a3-e611-407f-88f0-aa664b01106f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921029314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.921029314 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3567341582 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 52281650 ps |
| CPU time | 5.85 seconds |
| Started | Jan 10 01:38:31 PM PST 24 |
| Finished | Jan 10 01:38:41 PM PST 24 |
| Peak memory | 552832 kb |
| Host | smart-37931eef-abdd-40d5-8622-b3efe624f484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567341582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3567341582 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.2154797160 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 406589287 ps |
| CPU time | 31.66 seconds |
| Started | Jan 10 01:38:54 PM PST 24 |
| Finished | Jan 10 01:39:28 PM PST 24 |
| Peak memory | 553980 kb |
| Host | smart-c1cf4f8d-5950-4685-9d74-d114f917d151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154797160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2154797160 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.3135413539 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 13267217086 ps |
| CPU time | 475.93 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:46:53 PM PST 24 |
| Peak memory | 556244 kb |
| Host | smart-b3fc51e1-c621-4b99-8543-e3ea297bd382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135413539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.3135413539 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1120621765 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 973369287 ps |
| CPU time | 358.81 seconds |
| Started | Jan 10 01:38:54 PM PST 24 |
| Finished | Jan 10 01:44:54 PM PST 24 |
| Peak memory | 559268 kb |
| Host | smart-b3e5211d-5e8f-475b-90f1-6e3ba5f8bd78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120621765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.1120621765 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2115225460 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 3701392429 ps |
| CPU time | 373.72 seconds |
| Started | Jan 10 01:38:53 PM PST 24 |
| Finished | Jan 10 01:45:09 PM PST 24 |
| Peak memory | 557756 kb |
| Host | smart-bf609695-0828-48b7-8e53-39cbbf3c2657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115225460 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.2115225460 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1970375892 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 636227199 ps |
| CPU time | 25.41 seconds |
| Started | Jan 10 01:38:54 PM PST 24 |
| Finished | Jan 10 01:39:22 PM PST 24 |
| Peak memory | 553972 kb |
| Host | smart-d4669b61-a27f-4b5a-8b75-a4f5f8f25039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970375892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1970375892 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.1676265026 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 974296219 ps |
| CPU time | 71.65 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:40:13 PM PST 24 |
| Peak memory | 555804 kb |
| Host | smart-cc9459c2-d34b-493c-bb95-eac0fa215d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676265026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .1676265026 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1222109931 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 40842750474 ps |
| CPU time | 698.59 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:50:41 PM PST 24 |
| Peak memory | 556124 kb |
| Host | smart-22048cb2-e606-4424-b29e-19feeb0e1850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222109931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1222109931 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1123177826 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 155977862 ps |
| CPU time | 16.85 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:39:18 PM PST 24 |
| Peak memory | 553920 kb |
| Host | smart-3bbd7c72-0798-4ae3-8c7e-d07609675a4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123177826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.1123177826 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.3412476070 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 477415422 ps |
| CPU time | 40.4 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:39:40 PM PST 24 |
| Peak memory | 554956 kb |
| Host | smart-d13f61ae-04aa-42bc-8853-079abc95bcd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412476070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3412476070 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.3331515332 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 1431181502 ps |
| CPU time | 47.97 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:39:49 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-9a667f81-6c7a-4319-b70f-01238a72a190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331515332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.3331515332 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3689308746 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 66716531126 ps |
| CPU time | 713.22 seconds |
| Started | Jan 10 01:38:58 PM PST 24 |
| Finished | Jan 10 01:50:56 PM PST 24 |
| Peak memory | 554796 kb |
| Host | smart-80c23ee0-26e7-412a-8d8a-0ef97f4edcc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689308746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3689308746 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1182177499 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 4019452574 ps |
| CPU time | 69.31 seconds |
| Started | Jan 10 01:39:00 PM PST 24 |
| Finished | Jan 10 01:40:13 PM PST 24 |
| Peak memory | 553076 kb |
| Host | smart-a1286b5d-3bb9-4def-84e1-93d90e5ebdad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182177499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1182177499 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3197720158 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 302994408 ps |
| CPU time | 26.1 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:39:23 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-ebf607fc-9e8e-4a75-a5c5-c9076e09232a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197720158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3197720158 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.3665569474 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 782206498 ps |
| CPU time | 24.6 seconds |
| Started | Jan 10 01:39:03 PM PST 24 |
| Finished | Jan 10 01:39:30 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-30267e2f-9c85-4cc6-8903-1f9a4c1d0932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665569474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3665569474 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.2841287525 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 53786797 ps |
| CPU time | 6.81 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:39:04 PM PST 24 |
| Peak memory | 552988 kb |
| Host | smart-87d42a05-0176-4daa-be10-a8e0706d7ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841287525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2841287525 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3534314593 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 8411040506 ps |
| CPU time | 86.13 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:40:25 PM PST 24 |
| Peak memory | 552768 kb |
| Host | smart-87b2ee41-ce44-4760-bccc-1cd20e116f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534314593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3534314593 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3645689636 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 5150979548 ps |
| CPU time | 90.3 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:40:27 PM PST 24 |
| Peak memory | 552748 kb |
| Host | smart-5d4df6af-5039-42cf-9941-6f0fbe059ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645689636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3645689636 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1411809494 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 44418478 ps |
| CPU time | 6.23 seconds |
| Started | Jan 10 01:38:54 PM PST 24 |
| Finished | Jan 10 01:39:02 PM PST 24 |
| Peak memory | 552992 kb |
| Host | smart-4dd9336a-6088-45c2-b6ad-2515726c189a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411809494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.1411809494 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.901778461 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 613002257 ps |
| CPU time | 50.12 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:39:52 PM PST 24 |
| Peak memory | 556160 kb |
| Host | smart-02e2583b-0ca8-4d6a-b0ea-cf49a9559fa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901778461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.901778461 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3507208568 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 16045231722 ps |
| CPU time | 562.51 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:48:20 PM PST 24 |
| Peak memory | 557408 kb |
| Host | smart-91bd71a6-1c37-4077-b4ba-d81f8b9d79d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507208568 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3507208568 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.1996737924 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 36862515 ps |
| CPU time | 50.26 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:39:50 PM PST 24 |
| Peak memory | 556044 kb |
| Host | smart-f6a1fdf0-6298-4b4a-aa21-2fb8f29b0da1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996737924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.1996737924 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2500381375 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 10907921527 ps |
| CPU time | 557.16 seconds |
| Started | Jan 10 01:38:58 PM PST 24 |
| Finished | Jan 10 01:48:19 PM PST 24 |
| Peak memory | 559900 kb |
| Host | smart-02cf4f29-e218-498d-a938-ce933cd1de00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500381375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.2500381375 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.1156686049 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 198142407 ps |
| CPU time | 23.99 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:39:22 PM PST 24 |
| Peak memory | 553916 kb |
| Host | smart-91beb454-1f35-4639-99fb-ced6edde1c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156686049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.1156686049 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.3661534036 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 3477561937 ps |
| CPU time | 138.02 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:41:19 PM PST 24 |
| Peak memory | 555892 kb |
| Host | smart-177460a0-da02-4e6c-b25c-23ef175098f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661534036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .3661534036 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2060818126 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 55010378308 ps |
| CPU time | 989.66 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:55:29 PM PST 24 |
| Peak memory | 555112 kb |
| Host | smart-97c7e5fe-ce80-47f1-b6e4-c5472ef2bddc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060818126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.2060818126 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3691269656 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 294358129 ps |
| CPU time | 27.81 seconds |
| Started | Jan 10 01:38:59 PM PST 24 |
| Finished | Jan 10 01:39:31 PM PST 24 |
| Peak memory | 554904 kb |
| Host | smart-9d89d40a-de34-4a42-aa64-68492f360192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691269656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.3691269656 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.1778337629 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 81234369 ps |
| CPU time | 9.53 seconds |
| Started | Jan 10 01:39:00 PM PST 24 |
| Finished | Jan 10 01:39:13 PM PST 24 |
| Peak memory | 554976 kb |
| Host | smart-c104599d-e4c8-4b3e-8463-83e8a44c4497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778337629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.1778337629 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.3485824570 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 738475010 ps |
| CPU time | 25.64 seconds |
| Started | Jan 10 01:39:00 PM PST 24 |
| Finished | Jan 10 01:39:29 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-3473c393-9239-4078-b343-07671e7e31b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485824570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3485824570 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.3663419039 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 74634013159 ps |
| CPU time | 849.83 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:53:08 PM PST 24 |
| Peak memory | 555000 kb |
| Host | smart-c7ff4d8f-e13d-4eed-8e07-331007637b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663419039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3663419039 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2804307357 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 17805039004 ps |
| CPU time | 302.04 seconds |
| Started | Jan 10 01:39:01 PM PST 24 |
| Finished | Jan 10 01:44:07 PM PST 24 |
| Peak memory | 554852 kb |
| Host | smart-1ef952b9-75d5-4db1-a623-3d535fdd3494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804307357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2804307357 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.515714322 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 589156840 ps |
| CPU time | 49.17 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:39:47 PM PST 24 |
| Peak memory | 554976 kb |
| Host | smart-c3ed965d-0684-4e2c-ad52-539eca7d8500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515714322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_dela ys.515714322 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.3434462120 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 441516318 ps |
| CPU time | 29.87 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:39:29 PM PST 24 |
| Peak memory | 554796 kb |
| Host | smart-d9bc1bdf-c9b2-4e47-9169-4fa54031eb3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434462120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3434462120 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.4280404987 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 110425343 ps |
| CPU time | 6.51 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:39:04 PM PST 24 |
| Peak memory | 552928 kb |
| Host | smart-3d36a6b1-d653-4e1f-98bd-4e9ea2bc3f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280404987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4280404987 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.4157430577 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 8944775651 ps |
| CPU time | 86.68 seconds |
| Started | Jan 10 01:39:03 PM PST 24 |
| Finished | Jan 10 01:40:33 PM PST 24 |
| Peak memory | 553052 kb |
| Host | smart-5aa7f4b8-2969-425f-9c4e-7c16e4a53097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157430577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.4157430577 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3263861560 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 4693889028 ps |
| CPU time | 79.13 seconds |
| Started | Jan 10 01:39:00 PM PST 24 |
| Finished | Jan 10 01:40:23 PM PST 24 |
| Peak memory | 553000 kb |
| Host | smart-18419e10-c3a8-48da-a067-f8345545db7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263861560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3263861560 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.128799761 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 41231875 ps |
| CPU time | 5.76 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:39:05 PM PST 24 |
| Peak memory | 552888 kb |
| Host | smart-eb813f38-1c91-4d6f-ba4e-cb4a7b7fa7aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128799761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays .128799761 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1347507862 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 1368450787 ps |
| CPU time | 105.19 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:40:43 PM PST 24 |
| Peak memory | 556160 kb |
| Host | smart-f1de00f7-e07a-4c74-8034-d663e2f19033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347507862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1347507862 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1712226363 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 12320156483 ps |
| CPU time | 471.41 seconds |
| Started | Jan 10 01:38:55 PM PST 24 |
| Finished | Jan 10 01:46:48 PM PST 24 |
| Peak memory | 556956 kb |
| Host | smart-6c469a04-085e-4cfc-89b1-6a0d6304ffce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712226363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1712226363 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2945904824 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 5321154122 ps |
| CPU time | 699.87 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:50:42 PM PST 24 |
| Peak memory | 568148 kb |
| Host | smart-a7fb9d23-4780-4313-9a55-e15c5b783791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945904824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.2945904824 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.3273085464 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 149802035 ps |
| CPU time | 37.14 seconds |
| Started | Jan 10 01:38:54 PM PST 24 |
| Finished | Jan 10 01:39:33 PM PST 24 |
| Peak memory | 554060 kb |
| Host | smart-40d4b3d3-baea-4f2f-90e9-d9f079d77445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273085464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.3273085464 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.205268851 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 1217205496 ps |
| CPU time | 49.55 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:39:48 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-2949c5a3-79ae-4632-b5b7-5353685850ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205268851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.205268851 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3416126714 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 595993569 ps |
| CPU time | 43.86 seconds |
| Started | Jan 10 01:38:59 PM PST 24 |
| Finished | Jan 10 01:39:47 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-b0460896-3e10-42e5-b6b1-14dbd9fe90ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416126714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3416126714 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2550216724 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 305029426 ps |
| CPU time | 14.57 seconds |
| Started | Jan 10 01:39:52 PM PST 24 |
| Finished | Jan 10 01:40:08 PM PST 24 |
| Peak memory | 554976 kb |
| Host | smart-f09b398e-33d8-4ed0-a523-b7d75aaea1ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550216724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.2550216724 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.4102851202 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 827847051 ps |
| CPU time | 30.21 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:40:35 PM PST 24 |
| Peak memory | 555012 kb |
| Host | smart-c9eecd7d-3760-4708-bea9-67ebaccaa1a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102851202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.4102851202 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.3824755745 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 721598355 ps |
| CPU time | 25.68 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:39:27 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-741958ea-aebc-4df6-91fb-c1989ac5879e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824755745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.3824755745 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.240632483 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 6965775109 ps |
| CPU time | 76.82 seconds |
| Started | Jan 10 01:38:58 PM PST 24 |
| Finished | Jan 10 01:40:19 PM PST 24 |
| Peak memory | 552784 kb |
| Host | smart-3d754a91-c506-42df-8f5b-71f39de7b1f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240632483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.240632483 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.2599457336 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 17964079738 ps |
| CPU time | 336.68 seconds |
| Started | Jan 10 01:38:59 PM PST 24 |
| Finished | Jan 10 01:44:40 PM PST 24 |
| Peak memory | 555044 kb |
| Host | smart-269f6cb0-c2b6-42e4-b2f9-de9b0bfe1dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599457336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2599457336 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.689337178 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 91168735 ps |
| CPU time | 10.21 seconds |
| Started | Jan 10 01:38:58 PM PST 24 |
| Finished | Jan 10 01:39:12 PM PST 24 |
| Peak memory | 553828 kb |
| Host | smart-bdb15e9a-254c-4cf3-965e-87778de8b83c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689337178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela ys.689337178 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.4181815929 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 242736273 ps |
| CPU time | 18.57 seconds |
| Started | Jan 10 01:39:54 PM PST 24 |
| Finished | Jan 10 01:40:13 PM PST 24 |
| Peak memory | 554984 kb |
| Host | smart-15fc6033-782c-41ec-8c47-06075f914dc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181815929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4181815929 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.4201722090 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 39765625 ps |
| CPU time | 5.67 seconds |
| Started | Jan 10 01:38:56 PM PST 24 |
| Finished | Jan 10 01:39:04 PM PST 24 |
| Peak memory | 552700 kb |
| Host | smart-081e99b9-fd33-4f3b-9ad4-dd5f21372cea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201722090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.4201722090 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.3202278318 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 8174034874 ps |
| CPU time | 86.77 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:40:28 PM PST 24 |
| Peak memory | 553056 kb |
| Host | smart-6ba41b05-498f-40eb-addc-ac324f1898de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202278318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3202278318 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.770954455 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 5795393682 ps |
| CPU time | 95.96 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:40:37 PM PST 24 |
| Peak memory | 552996 kb |
| Host | smart-6f1e1fe2-f018-4751-9a16-ae785ea5fc5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770954455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.770954455 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2123052785 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 47005527 ps |
| CPU time | 6.78 seconds |
| Started | Jan 10 01:38:57 PM PST 24 |
| Finished | Jan 10 01:39:08 PM PST 24 |
| Peak memory | 552640 kb |
| Host | smart-3e1003b1-a9e5-4d13-a14c-481719c29954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123052785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.2123052785 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.2241081106 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1682399612 ps |
| CPU time | 70.06 seconds |
| Started | Jan 10 01:40:05 PM PST 24 |
| Finished | Jan 10 01:41:16 PM PST 24 |
| Peak memory | 554696 kb |
| Host | smart-6cf67483-4578-46b5-9428-a402ad616344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241081106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2241081106 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.875563282 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6589780935 ps |
| CPU time | 320.15 seconds |
| Started | Jan 10 01:40:16 PM PST 24 |
| Finished | Jan 10 01:45:36 PM PST 24 |
| Peak memory | 556724 kb |
| Host | smart-99809293-c61f-4c40-a7cb-5fb57462469f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875563282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_ with_rand_reset.875563282 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3418756477 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 4403575210 ps |
| CPU time | 364.52 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:46:09 PM PST 24 |
| Peak memory | 559964 kb |
| Host | smart-a9bef131-7e77-4605-920e-6e1fc81a9c5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418756477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.3418756477 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.2033205503 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 277769659 ps |
| CPU time | 15.46 seconds |
| Started | Jan 10 01:40:08 PM PST 24 |
| Finished | Jan 10 01:40:25 PM PST 24 |
| Peak memory | 555024 kb |
| Host | smart-0ec17d36-3cb4-4cd3-961e-f343d3d8285d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033205503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2033205503 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.3953695132 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 892464396 ps |
| CPU time | 50.09 seconds |
| Started | Jan 10 01:39:57 PM PST 24 |
| Finished | Jan 10 01:40:48 PM PST 24 |
| Peak memory | 554816 kb |
| Host | smart-2e8b2347-1329-4c9f-a1f1-f0f4441e4c39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953695132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .3953695132 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.202391249 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 124770522259 ps |
| CPU time | 2254.95 seconds |
| Started | Jan 10 01:39:53 PM PST 24 |
| Finished | Jan 10 02:17:29 PM PST 24 |
| Peak memory | 555888 kb |
| Host | smart-79df2a7b-4788-455f-aefa-ef6765b43037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202391249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_d evice_slow_rsp.202391249 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1970416586 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 238768167 ps |
| CPU time | 24.91 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:40:29 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-86cfa1f7-446c-4f7b-909b-e46fba2348f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970416586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.1970416586 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.3166347716 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 918973436 ps |
| CPU time | 32.5 seconds |
| Started | Jan 10 01:40:01 PM PST 24 |
| Finished | Jan 10 01:40:35 PM PST 24 |
| Peak memory | 554748 kb |
| Host | smart-7abb600f-c625-4db0-a48a-c75834d3ff63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166347716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3166347716 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.1030520895 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 374648698 ps |
| CPU time | 30.03 seconds |
| Started | Jan 10 01:40:05 PM PST 24 |
| Finished | Jan 10 01:40:35 PM PST 24 |
| Peak memory | 555088 kb |
| Host | smart-156b3780-45ef-4956-8b08-59298ffb58ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030520895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1030520895 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1321355432 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 23752769760 ps |
| CPU time | 252.42 seconds |
| Started | Jan 10 01:40:06 PM PST 24 |
| Finished | Jan 10 01:44:19 PM PST 24 |
| Peak memory | 555100 kb |
| Host | smart-672671b2-3c44-4e82-831d-9ba5a19e6619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321355432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1321355432 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3492314012 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 44435894651 ps |
| CPU time | 841.68 seconds |
| Started | Jan 10 01:40:04 PM PST 24 |
| Finished | Jan 10 01:54:07 PM PST 24 |
| Peak memory | 555148 kb |
| Host | smart-b723209a-a4a1-4c3b-86ab-916fa790fcf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492314012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3492314012 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.1854210342 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 329290264 ps |
| CPU time | 27.55 seconds |
| Started | Jan 10 01:40:05 PM PST 24 |
| Finished | Jan 10 01:40:33 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-fe6d2318-29d5-49e1-9438-90bd23495f61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854210342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.1854210342 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.3111271785 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 264258617 ps |
| CPU time | 17.85 seconds |
| Started | Jan 10 01:39:53 PM PST 24 |
| Finished | Jan 10 01:40:12 PM PST 24 |
| Peak memory | 554828 kb |
| Host | smart-0ee02a11-5f27-4ab5-88ff-48a40566ed01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111271785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3111271785 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.359436371 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 207700947 ps |
| CPU time | 8.22 seconds |
| Started | Jan 10 01:39:53 PM PST 24 |
| Finished | Jan 10 01:40:02 PM PST 24 |
| Peak memory | 552912 kb |
| Host | smart-4aa7a016-ed6e-49ca-8bcd-3ac3f7741da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359436371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.359436371 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1167940045 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 10495094808 ps |
| CPU time | 107.71 seconds |
| Started | Jan 10 01:40:02 PM PST 24 |
| Finished | Jan 10 01:41:51 PM PST 24 |
| Peak memory | 552688 kb |
| Host | smart-f5f6ea44-2990-4f1a-abd3-349429e7e937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167940045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1167940045 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1915421503 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 4095382398 ps |
| CPU time | 72.54 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:41:17 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-04ca1cd8-dce9-4118-aa91-0870be7d4c24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915421503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1915421503 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1283799834 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 52060048 ps |
| CPU time | 6.16 seconds |
| Started | Jan 10 01:40:05 PM PST 24 |
| Finished | Jan 10 01:40:12 PM PST 24 |
| Peak memory | 552960 kb |
| Host | smart-f04b502a-b0cb-4fe8-a055-c97876faf063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283799834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.1283799834 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.3449953385 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 9754314548 ps |
| CPU time | 423.07 seconds |
| Started | Jan 10 01:40:05 PM PST 24 |
| Finished | Jan 10 01:47:08 PM PST 24 |
| Peak memory | 557404 kb |
| Host | smart-d75fa9a7-647d-4070-94dc-97a99a50e8cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449953385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3449953385 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.748027057 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 3468885496 ps |
| CPU time | 277.8 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:44:42 PM PST 24 |
| Peak memory | 557956 kb |
| Host | smart-1b47fd1f-1fcf-40d6-b881-332991377f52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748027057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.748027057 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.120031501 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 109471746 ps |
| CPU time | 43.47 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:40:48 PM PST 24 |
| Peak memory | 555244 kb |
| Host | smart-ea4dc5d3-5f41-40cd-90a5-aecbe1d93341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120031501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_ with_rand_reset.120031501 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3567844783 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 3246599743 ps |
| CPU time | 507.1 seconds |
| Started | Jan 10 01:39:57 PM PST 24 |
| Finished | Jan 10 01:48:25 PM PST 24 |
| Peak memory | 568128 kb |
| Host | smart-0c02186a-4960-4790-b35f-5012521164fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567844783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.3567844783 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.1686795562 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 31352118 ps |
| CPU time | 6.69 seconds |
| Started | Jan 10 01:39:52 PM PST 24 |
| Finished | Jan 10 01:40:00 PM PST 24 |
| Peak memory | 552520 kb |
| Host | smart-81c05ffd-3699-45d1-81bd-98e6f78721fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686795562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1686795562 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3205245765 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 3657691112 ps |
| CPU time | 137.57 seconds |
| Started | Jan 10 01:39:52 PM PST 24 |
| Finished | Jan 10 01:42:11 PM PST 24 |
| Peak memory | 554820 kb |
| Host | smart-66df840e-a4e4-4166-8ae5-58d1764b5af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205245765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .3205245765 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.737279437 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 87881283369 ps |
| CPU time | 1597.66 seconds |
| Started | Jan 10 01:40:06 PM PST 24 |
| Finished | Jan 10 02:06:45 PM PST 24 |
| Peak memory | 555196 kb |
| Host | smart-8ecc8962-594a-45a1-a938-fce3103bf09e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737279437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_d evice_slow_rsp.737279437 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.2800187449 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 179060406 ps |
| CPU time | 20.05 seconds |
| Started | Jan 10 01:39:57 PM PST 24 |
| Finished | Jan 10 01:40:18 PM PST 24 |
| Peak memory | 555044 kb |
| Host | smart-29e87eb8-8556-4134-982f-6a298722530e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800187449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.2800187449 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.3233297206 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 95657615 ps |
| CPU time | 10.12 seconds |
| Started | Jan 10 01:39:52 PM PST 24 |
| Finished | Jan 10 01:40:03 PM PST 24 |
| Peak memory | 554932 kb |
| Host | smart-85efa8fd-b724-491f-a824-01678201c7f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233297206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3233297206 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.73673294 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 366942994 ps |
| CPU time | 15.23 seconds |
| Started | Jan 10 01:39:52 PM PST 24 |
| Finished | Jan 10 01:40:08 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-1b73b61b-da6b-4b3b-8fe0-5cba8f16d6bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73673294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.73673294 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3279815036 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 37382630249 ps |
| CPU time | 432.55 seconds |
| Started | Jan 10 01:39:52 PM PST 24 |
| Finished | Jan 10 01:47:05 PM PST 24 |
| Peak memory | 554832 kb |
| Host | smart-77ffeaa5-bc82-4bab-9093-678a065933d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279815036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3279815036 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1415991352 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 39932637011 ps |
| CPU time | 652.11 seconds |
| Started | Jan 10 01:40:07 PM PST 24 |
| Finished | Jan 10 01:51:00 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-ddf63d2a-bff1-42bd-93d0-e4f889b20553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415991352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1415991352 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3835536890 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 543051236 ps |
| CPU time | 42.34 seconds |
| Started | Jan 10 01:39:51 PM PST 24 |
| Finished | Jan 10 01:40:34 PM PST 24 |
| Peak memory | 555012 kb |
| Host | smart-18615b6c-48d2-40a5-977b-271de934b6d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835536890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.3835536890 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.3504864557 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 521934624 ps |
| CPU time | 37.69 seconds |
| Started | Jan 10 01:40:08 PM PST 24 |
| Finished | Jan 10 01:40:47 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-b9b1fde0-bce6-4b84-9e8d-f2cad3c5579b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504864557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3504864557 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2970958744 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 52399317 ps |
| CPU time | 6.28 seconds |
| Started | Jan 10 01:39:52 PM PST 24 |
| Finished | Jan 10 01:40:00 PM PST 24 |
| Peak memory | 552640 kb |
| Host | smart-2cd6130f-d17f-420d-8c79-09cf69338d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970958744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2970958744 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1102634438 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 8232471172 ps |
| CPU time | 81.49 seconds |
| Started | Jan 10 01:40:07 PM PST 24 |
| Finished | Jan 10 01:41:30 PM PST 24 |
| Peak memory | 552720 kb |
| Host | smart-ccd3f5b9-2aef-40af-b041-310cab0124d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102634438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1102634438 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.357921064 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 5061860570 ps |
| CPU time | 89.32 seconds |
| Started | Jan 10 01:39:54 PM PST 24 |
| Finished | Jan 10 01:41:24 PM PST 24 |
| Peak memory | 553032 kb |
| Host | smart-6fbf50d6-3ac7-4626-8621-8d2b93b4cecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357921064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.357921064 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2517595436 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 49083179 ps |
| CPU time | 6.17 seconds |
| Started | Jan 10 01:40:01 PM PST 24 |
| Finished | Jan 10 01:40:08 PM PST 24 |
| Peak memory | 552660 kb |
| Host | smart-a0d79733-aa97-4d0b-979a-d4c6c3da8707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517595436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2517595436 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.2185831550 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 770869016 ps |
| CPU time | 56.58 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:41:01 PM PST 24 |
| Peak memory | 555932 kb |
| Host | smart-611eacd3-baa1-4d76-a3b2-8b63b7a49a1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185831550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.2185831550 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.650902756 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 1288521524 ps |
| CPU time | 90.42 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:41:35 PM PST 24 |
| Peak memory | 557092 kb |
| Host | smart-2616ba4c-9c71-4e2a-9abb-aea9b7f4514e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650902756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.650902756 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3105038647 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1850150348 ps |
| CPU time | 266.57 seconds |
| Started | Jan 10 01:39:52 PM PST 24 |
| Finished | Jan 10 01:44:20 PM PST 24 |
| Peak memory | 556388 kb |
| Host | smart-cd40ae3c-0a45-425f-9957-2002998ae75e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105038647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.3105038647 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2723600126 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 5838414199 ps |
| CPU time | 628.22 seconds |
| Started | Jan 10 01:40:05 PM PST 24 |
| Finished | Jan 10 01:50:34 PM PST 24 |
| Peak memory | 568136 kb |
| Host | smart-f1bcb3cf-a41d-4c64-9f55-194a480d4c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723600126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.2723600126 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.3336388138 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 145265335 ps |
| CPU time | 17.81 seconds |
| Started | Jan 10 01:40:01 PM PST 24 |
| Finished | Jan 10 01:40:20 PM PST 24 |
| Peak memory | 554688 kb |
| Host | smart-7418c170-3816-4d41-9af5-d943577d7916 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336388138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3336388138 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2658645789 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 1894470676 ps |
| CPU time | 93.3 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:41:38 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-7a7a05d7-f7ba-4fef-a307-47a38a33f07f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658645789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .2658645789 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3495823074 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 61897311627 ps |
| CPU time | 1115.94 seconds |
| Started | Jan 10 01:40:03 PM PST 24 |
| Finished | Jan 10 01:58:40 PM PST 24 |
| Peak memory | 556136 kb |
| Host | smart-1cf07eb4-3ec3-48fd-9991-b4688732a967 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495823074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.3495823074 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2763154474 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 783969800 ps |
| CPU time | 29.27 seconds |
| Started | Jan 10 01:40:16 PM PST 24 |
| Finished | Jan 10 01:40:46 PM PST 24 |
| Peak memory | 554960 kb |
| Host | smart-138ba788-c25e-4afb-a35b-e9b1a4ed4e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763154474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.2763154474 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.83359623 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 1586626438 ps |
| CPU time | 54.96 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:41:17 PM PST 24 |
| Peak memory | 554908 kb |
| Host | smart-a5069028-eb89-4ec9-b435-9d4ba6380d63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83359623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.83359623 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.3848670660 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 98955668 ps |
| CPU time | 10.73 seconds |
| Started | Jan 10 01:40:07 PM PST 24 |
| Finished | Jan 10 01:40:19 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-8da3ef4f-dc9c-490f-93a4-23154e9e167d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848670660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.3848670660 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3712000145 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 61879493046 ps |
| CPU time | 558.12 seconds |
| Started | Jan 10 01:40:05 PM PST 24 |
| Finished | Jan 10 01:49:23 PM PST 24 |
| Peak memory | 554832 kb |
| Host | smart-866ab523-aea4-4e7f-bac4-c8270c74cde8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712000145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3712000145 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.1565504566 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 6662292209 ps |
| CPU time | 113.32 seconds |
| Started | Jan 10 01:40:08 PM PST 24 |
| Finished | Jan 10 01:42:02 PM PST 24 |
| Peak memory | 552568 kb |
| Host | smart-0f17fe9f-90d7-4598-8db3-3743c6161265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565504566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1565504566 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.887321825 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 322839973 ps |
| CPU time | 33.54 seconds |
| Started | Jan 10 01:40:01 PM PST 24 |
| Finished | Jan 10 01:40:36 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-d264f98a-d23e-49fd-9d8e-4c9052577e71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887321825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_dela ys.887321825 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.1082005049 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 1829459515 ps |
| CPU time | 54.05 seconds |
| Started | Jan 10 01:40:16 PM PST 24 |
| Finished | Jan 10 01:41:11 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-a251dfcc-7aa7-4dc9-9d22-98af51cac4d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082005049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1082005049 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.2102110023 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 159706760 ps |
| CPU time | 7.32 seconds |
| Started | Jan 10 01:40:07 PM PST 24 |
| Finished | Jan 10 01:40:15 PM PST 24 |
| Peak memory | 552708 kb |
| Host | smart-6e2848e9-7835-461c-8e1c-d596680d13ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102110023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2102110023 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2326846374 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 7735165391 ps |
| CPU time | 77.74 seconds |
| Started | Jan 10 01:40:04 PM PST 24 |
| Finished | Jan 10 01:41:22 PM PST 24 |
| Peak memory | 552580 kb |
| Host | smart-72e780fd-2fc7-43c5-929e-f391d461cb14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326846374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2326846374 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1253358182 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 5137258081 ps |
| CPU time | 91.61 seconds |
| Started | Jan 10 01:40:02 PM PST 24 |
| Finished | Jan 10 01:41:35 PM PST 24 |
| Peak memory | 552796 kb |
| Host | smart-9c58615a-9ba6-4eb0-b3e8-aed08928fe6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253358182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1253358182 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1992582254 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 50324586 ps |
| CPU time | 6.05 seconds |
| Started | Jan 10 01:39:51 PM PST 24 |
| Finished | Jan 10 01:39:58 PM PST 24 |
| Peak memory | 552644 kb |
| Host | smart-def9064e-7d0c-4029-9e12-48ddf88e126e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992582254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1992582254 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.3178528070 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 3761770167 ps |
| CPU time | 132.32 seconds |
| Started | Jan 10 01:40:05 PM PST 24 |
| Finished | Jan 10 01:42:18 PM PST 24 |
| Peak memory | 556232 kb |
| Host | smart-21c8e929-c551-4059-8f3e-cb874490297a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178528070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.3178528070 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.4130556732 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 3416462420 ps |
| CPU time | 113.18 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:42:16 PM PST 24 |
| Peak memory | 553968 kb |
| Host | smart-b4f2339a-2de5-46ef-b289-d66b55e088af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130556732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.4130556732 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.4055383647 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 519486535 ps |
| CPU time | 213.29 seconds |
| Started | Jan 10 01:40:15 PM PST 24 |
| Finished | Jan 10 01:43:49 PM PST 24 |
| Peak memory | 557268 kb |
| Host | smart-c8461bf8-3ddf-44d5-85ce-8326781680ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055383647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.4055383647 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3158141293 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 534330050 ps |
| CPU time | 207.52 seconds |
| Started | Jan 10 01:40:20 PM PST 24 |
| Finished | Jan 10 01:43:49 PM PST 24 |
| Peak memory | 559856 kb |
| Host | smart-b8525719-c99d-409b-bc4a-027b7fd945fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158141293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.3158141293 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.2924067020 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 166933323 ps |
| CPU time | 10.3 seconds |
| Started | Jan 10 01:40:08 PM PST 24 |
| Finished | Jan 10 01:40:19 PM PST 24 |
| Peak memory | 553032 kb |
| Host | smart-6ac7cc7c-5298-4ff6-8a10-e7bc23274950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924067020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2924067020 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.4226601106 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 736771285 ps |
| CPU time | 35.26 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:41:04 PM PST 24 |
| Peak memory | 553720 kb |
| Host | smart-b310652c-f3ef-40ea-8823-ce41f56b3720 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226601106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .4226601106 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.2355653796 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 93496582090 ps |
| CPU time | 1483.99 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 02:05:13 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-0120b1b0-c0ee-4a58-bbd5-be697665f29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355653796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.2355653796 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.4152415561 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 293946074 ps |
| CPU time | 14.27 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:40:43 PM PST 24 |
| Peak memory | 554780 kb |
| Host | smart-59c60a2f-0b76-4e2a-9a64-d014cc7053b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152415561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.4152415561 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.4132956036 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 372566902 ps |
| CPU time | 28.53 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:40:57 PM PST 24 |
| Peak memory | 554640 kb |
| Host | smart-5aa43bc0-b9c5-4edc-9eab-f993857c90eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132956036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.4132956036 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.437657647 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 2037775905 ps |
| CPU time | 65.91 seconds |
| Started | Jan 10 01:40:19 PM PST 24 |
| Finished | Jan 10 01:41:25 PM PST 24 |
| Peak memory | 554952 kb |
| Host | smart-b75d1f61-1e85-4d7c-aea4-8908c0185c58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437657647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.437657647 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3219800472 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 14773288533 ps |
| CPU time | 173.83 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:43:21 PM PST 24 |
| Peak memory | 555092 kb |
| Host | smart-f4b0249e-c31f-4b3c-8d9e-f07ed8b286b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219800472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3219800472 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.956551733 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 13225445527 ps |
| CPU time | 236.78 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:44:21 PM PST 24 |
| Peak memory | 555104 kb |
| Host | smart-f58ebb1c-2979-4f9b-af04-23566b646514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956551733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.956551733 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.779857368 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 422982795 ps |
| CPU time | 35.01 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:40:59 PM PST 24 |
| Peak memory | 554984 kb |
| Host | smart-a71cf12c-5154-4a91-86ae-34b015b10854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779857368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.779857368 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.2691813021 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 796621061 ps |
| CPU time | 26.33 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:40:49 PM PST 24 |
| Peak memory | 553904 kb |
| Host | smart-e7e04a70-ad4d-413f-832a-5df77a2082ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691813021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.2691813021 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.3719657380 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 238113647 ps |
| CPU time | 9.59 seconds |
| Started | Jan 10 01:40:17 PM PST 24 |
| Finished | Jan 10 01:40:27 PM PST 24 |
| Peak memory | 552968 kb |
| Host | smart-6f70bbe0-78f3-4493-962c-b95e9bf54658 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719657380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3719657380 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2825379602 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 9184711581 ps |
| CPU time | 97.1 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:42:05 PM PST 24 |
| Peak memory | 553028 kb |
| Host | smart-4a7a2413-7887-4874-af50-89f12f49d403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825379602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2825379602 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.277748421 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 5617924140 ps |
| CPU time | 92.56 seconds |
| Started | Jan 10 01:40:18 PM PST 24 |
| Finished | Jan 10 01:41:51 PM PST 24 |
| Peak memory | 552956 kb |
| Host | smart-046e21ae-c3c7-4f90-a011-861c9e687339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277748421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.277748421 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2509734518 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 38817708 ps |
| CPU time | 5.68 seconds |
| Started | Jan 10 01:40:05 PM PST 24 |
| Finished | Jan 10 01:40:12 PM PST 24 |
| Peak memory | 552868 kb |
| Host | smart-aa6836f9-5bdb-402f-955e-7a52c76d6c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509734518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.2509734518 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.4187380569 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 3523654874 ps |
| CPU time | 267.77 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:44:56 PM PST 24 |
| Peak memory | 555816 kb |
| Host | smart-36d73589-bf63-4f8d-99c2-fee8766a9bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187380569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4187380569 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.762714704 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2643123900 ps |
| CPU time | 283.36 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:45:13 PM PST 24 |
| Peak memory | 559084 kb |
| Host | smart-32b310c0-3275-4449-b8f5-a54d4c1ed5c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762714704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_ with_rand_reset.762714704 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2630816502 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 1114065719 ps |
| CPU time | 213.8 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:44:03 PM PST 24 |
| Peak memory | 559796 kb |
| Host | smart-143cbfd4-1263-474b-946f-ce6ad29704e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630816502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.2630816502 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1281110655 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 38469710 ps |
| CPU time | 6.61 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:40:34 PM PST 24 |
| Peak memory | 552940 kb |
| Host | smart-4fc82e2f-0cf7-494a-a286-3f4fbcef0b42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281110655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1281110655 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.38619737 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 37183599142 ps |
| CPU time | 5177.32 seconds |
| Started | Jan 10 01:36:04 PM PST 24 |
| Finished | Jan 10 03:02:31 PM PST 24 |
| Peak memory | 580852 kb |
| Host | smart-cd62936a-1f02-48eb-8ede-d2fbc02a95cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38619737 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.chip_csr_aliasing.38619737 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3428271931 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 5905927624 ps |
| CPU time | 541.31 seconds |
| Started | Jan 10 01:35:47 PM PST 24 |
| Finished | Jan 10 01:45:05 PM PST 24 |
| Peak memory | 579352 kb |
| Host | smart-48da71f2-03cb-46fe-8898-d342b8102c62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428271931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.3428271931 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.813987592 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 5575219601 ps |
| CPU time | 352.01 seconds |
| Started | Jan 10 01:35:59 PM PST 24 |
| Finished | Jan 10 01:42:03 PM PST 24 |
| Peak memory | 641704 kb |
| Host | smart-fef1c14d-278d-454f-b863-60a69e0d76d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813987592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_re set.813987592 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1479032539 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 7827492200 ps |
| CPU time | 313.22 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 01:41:20 PM PST 24 |
| Peak memory | 625924 kb |
| Host | smart-421d0c31-5037-415f-b238-8d322253b26f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479032539 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.1479032539 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.552409964 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 5931488770 ps |
| CPU time | 555.83 seconds |
| Started | Jan 10 01:36:12 PM PST 24 |
| Finished | Jan 10 01:45:33 PM PST 24 |
| Peak memory | 580792 kb |
| Host | smart-fd7cd086-acf9-4474-afd0-41ba35e006e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552409964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.552409964 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.3576223687 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 31442297812 ps |
| CPU time | 4102.52 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 02:44:33 PM PST 24 |
| Peak memory | 580772 kb |
| Host | smart-2ce6f019-9323-48f0-aea3-ac9a2b01a868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576223687 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.3576223687 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.2871009655 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 3371165246 ps |
| CPU time | 219.75 seconds |
| Started | Jan 10 01:36:05 PM PST 24 |
| Finished | Jan 10 01:39:53 PM PST 24 |
| Peak memory | 580832 kb |
| Host | smart-3ccce12f-f66b-4010-850d-23284c868667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871009655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2871009655 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1406096975 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 741404792 ps |
| CPU time | 49.89 seconds |
| Started | Jan 10 01:36:12 PM PST 24 |
| Finished | Jan 10 01:37:08 PM PST 24 |
| Peak memory | 554796 kb |
| Host | smart-c4a1765a-2852-4081-8a47-ad9a7fe55e1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406096975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 1406096975 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2477766554 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 80436870760 ps |
| CPU time | 1441.72 seconds |
| Started | Jan 10 01:36:00 PM PST 24 |
| Finished | Jan 10 02:00:13 PM PST 24 |
| Peak memory | 556104 kb |
| Host | smart-46d45e90-7e19-4701-9bde-5f955f1959a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477766554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.2477766554 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2141783390 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 190174806 ps |
| CPU time | 9.72 seconds |
| Started | Jan 10 01:36:07 PM PST 24 |
| Finished | Jan 10 01:36:24 PM PST 24 |
| Peak memory | 552964 kb |
| Host | smart-1b0f6d02-1fec-4049-8f76-e974d276f9ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141783390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .2141783390 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.1646875118 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 259542337 ps |
| CPU time | 20.81 seconds |
| Started | Jan 10 01:36:04 PM PST 24 |
| Finished | Jan 10 01:36:34 PM PST 24 |
| Peak memory | 554984 kb |
| Host | smart-eab18bb4-6236-4b1b-bb5c-1fc74cb6214f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646875118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1646875118 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.3064305416 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 528248269 ps |
| CPU time | 44.79 seconds |
| Started | Jan 10 01:36:11 PM PST 24 |
| Finished | Jan 10 01:37:02 PM PST 24 |
| Peak memory | 554780 kb |
| Host | smart-491401e6-dc1f-40e6-b7ff-f87461bcc9ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064305416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.3064305416 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.434513012 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 85411907628 ps |
| CPU time | 1017.03 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 01:53:04 PM PST 24 |
| Peak memory | 554876 kb |
| Host | smart-58034b1b-3d99-4f43-96b0-84e8bf05d3f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434513012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.434513012 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1996838057 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 27229674388 ps |
| CPU time | 449.06 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:43:35 PM PST 24 |
| Peak memory | 555104 kb |
| Host | smart-840e7b60-f842-4afe-8ec0-716d9029611e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996838057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.1996838057 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.818752071 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 281544537 ps |
| CPU time | 23.23 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 01:36:30 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-4e99cdfb-3f9e-4d7a-b913-4c7eab67a13e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818752071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delay s.818752071 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.3874788544 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 1573706283 ps |
| CPU time | 42.8 seconds |
| Started | Jan 10 01:35:55 PM PST 24 |
| Finished | Jan 10 01:36:51 PM PST 24 |
| Peak memory | 554968 kb |
| Host | smart-c2d2475c-a967-412e-adbb-9f835122a70a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874788544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3874788544 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.2823104097 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 177236333 ps |
| CPU time | 7.71 seconds |
| Started | Jan 10 01:36:11 PM PST 24 |
| Finished | Jan 10 01:36:24 PM PST 24 |
| Peak memory | 552700 kb |
| Host | smart-2bedac29-9fee-4992-b618-1e75ee17100d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823104097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2823104097 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.933313191 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 8723135373 ps |
| CPU time | 91.82 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 01:37:38 PM PST 24 |
| Peak memory | 553048 kb |
| Host | smart-305718fd-bdd7-47c2-97e5-c02ccc6ace5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933313191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.933313191 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.611573550 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 5400467745 ps |
| CPU time | 92.95 seconds |
| Started | Jan 10 01:35:59 PM PST 24 |
| Finished | Jan 10 01:37:44 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-7dc61e15-f4b9-4582-b7d1-db50e5842b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611573550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.611573550 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.653828305 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 47571225 ps |
| CPU time | 5.8 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:36:14 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-93b4cfc3-b8e9-43fb-86e7-553752b1707e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653828305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays. 653828305 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.3497036855 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 615689416 ps |
| CPU time | 24.27 seconds |
| Started | Jan 10 01:36:11 PM PST 24 |
| Finished | Jan 10 01:36:41 PM PST 24 |
| Peak memory | 555120 kb |
| Host | smart-070b5baa-daf1-4540-bd2c-b14f92cf1663 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497036855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3497036855 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1158159580 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 4931637299 ps |
| CPU time | 331.31 seconds |
| Started | Jan 10 01:35:55 PM PST 24 |
| Finished | Jan 10 01:41:39 PM PST 24 |
| Peak memory | 557744 kb |
| Host | smart-f2d8ebc7-c85e-49fe-b0d2-2d9e5d46d8ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158159580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.1158159580 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1242225441 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 16107230542 ps |
| CPU time | 761.06 seconds |
| Started | Jan 10 01:35:52 PM PST 24 |
| Finished | Jan 10 01:48:47 PM PST 24 |
| Peak memory | 568144 kb |
| Host | smart-8d5518e4-ba73-4ba8-8c22-73502f17b936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242225441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1242225441 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.1638631741 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 165045664 ps |
| CPU time | 19.05 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:36:29 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-2ac9db96-0836-45d7-9a1d-a047bc941097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638631741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1638631741 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.1005797006 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1037793925 ps |
| CPU time | 75.99 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:41:49 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-343424bd-220f-4ffa-8fdb-71ba085df245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005797006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .1005797006 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3817925192 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 131147540959 ps |
| CPU time | 2243.12 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 02:17:54 PM PST 24 |
| Peak memory | 554964 kb |
| Host | smart-3423e38d-b695-41c2-8a9d-14fe06fa90c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817925192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3817925192 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.3164273247 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 37975579 ps |
| CPU time | 6.56 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:40:41 PM PST 24 |
| Peak memory | 552884 kb |
| Host | smart-9748ce8d-5c4c-45c9-85a0-1304a0d456aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164273247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.3164273247 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.2469124995 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 353043815 ps |
| CPU time | 26.94 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:40:58 PM PST 24 |
| Peak memory | 554700 kb |
| Host | smart-b981d634-ef43-440e-8992-4737a66e9297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469124995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2469124995 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.1255472795 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 446012747 ps |
| CPU time | 17.39 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:40:52 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-047d817f-8fa9-4541-89d2-7c977267d58f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255472795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.1255472795 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.4223707340 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 36783299991 ps |
| CPU time | 424.98 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:47:36 PM PST 24 |
| Peak memory | 554980 kb |
| Host | smart-e7e029f0-5682-4d96-8187-3d9a0f087b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223707340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4223707340 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2365767241 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 58450322376 ps |
| CPU time | 970.45 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:56:44 PM PST 24 |
| Peak memory | 555128 kb |
| Host | smart-2b45ed2a-5c0a-455a-b44e-f0848c6bb8df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365767241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2365767241 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1609774843 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 89693235 ps |
| CPU time | 10.29 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:40:44 PM PST 24 |
| Peak memory | 554968 kb |
| Host | smart-a42f01e2-f20b-42d1-8fa5-58c4ec4f2d18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609774843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1609774843 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.15831986 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 2708410539 ps |
| CPU time | 83.83 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:41:55 PM PST 24 |
| Peak memory | 553956 kb |
| Host | smart-d372d17b-dca6-4861-9e06-bc6e01d0271e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15831986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.15831986 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.2439513189 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 222328336 ps |
| CPU time | 9.16 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:40:37 PM PST 24 |
| Peak memory | 553004 kb |
| Host | smart-64186dbc-27fe-46ad-a9dd-08a6554d224f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439513189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2439513189 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.975075872 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 6858906286 ps |
| CPU time | 70.43 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:41:41 PM PST 24 |
| Peak memory | 552856 kb |
| Host | smart-6f1a8442-2299-4f4c-9b08-0499a76d52d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975075872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.975075872 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.1201764243 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 5026567543 ps |
| CPU time | 81.17 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:41:54 PM PST 24 |
| Peak memory | 552768 kb |
| Host | smart-1fc12890-7edc-4dd3-ba39-1e91465cddf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201764243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.1201764243 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.698479535 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 53966270 ps |
| CPU time | 6.4 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:40:37 PM PST 24 |
| Peak memory | 552696 kb |
| Host | smart-9be8530b-0866-432e-8604-db509fca52bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698479535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays .698479535 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3926339759 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 542719466 ps |
| CPU time | 50.58 seconds |
| Started | Jan 10 01:40:06 PM PST 24 |
| Finished | Jan 10 01:40:58 PM PST 24 |
| Peak memory | 554040 kb |
| Host | smart-5de35e2f-239c-4186-be49-639c7b7af19a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926339759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3926339759 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1632498139 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 9786530712 ps |
| CPU time | 314.78 seconds |
| Started | Jan 10 01:40:23 PM PST 24 |
| Finished | Jan 10 01:45:42 PM PST 24 |
| Peak memory | 556268 kb |
| Host | smart-337c92cc-71af-43fa-a377-19aca0f5c8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632498139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1632498139 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.3601212903 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 7800139444 ps |
| CPU time | 361.79 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:46:31 PM PST 24 |
| Peak memory | 556912 kb |
| Host | smart-0f04ea9f-be3b-483e-a77e-85d36cd84a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601212903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.3601212903 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3544234967 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 804292883 ps |
| CPU time | 327.68 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:45:51 PM PST 24 |
| Peak memory | 568008 kb |
| Host | smart-eb01afa9-388c-4c85-bd48-e144d152da99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544234967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3544234967 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.2244089888 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 637908572 ps |
| CPU time | 27.04 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:41:01 PM PST 24 |
| Peak memory | 555080 kb |
| Host | smart-15606e80-87ed-4c07-94e2-9d6e378b865f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244089888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2244089888 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3207197481 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 1765084638 ps |
| CPU time | 87.94 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:41:56 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-5f81d892-2dab-435a-a0e7-7a0875944ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207197481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .3207197481 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.4091272510 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 2884607876 ps |
| CPU time | 52.07 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:41:21 PM PST 24 |
| Peak memory | 552752 kb |
| Host | smart-93415f46-fc3a-4524-ba24-8e7446447e0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091272510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.4091272510 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.183795957 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 245969304 ps |
| CPU time | 12.5 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:40:41 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-7eacb7a4-3cd9-4978-bc3a-7df109f38a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183795957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr .183795957 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.2351743358 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 146654790 ps |
| CPU time | 13.32 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:40:43 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-168b4d6b-ffd6-41e3-a12f-def6dcfcb279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351743358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2351743358 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.2251401778 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 161929532 ps |
| CPU time | 16.27 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:40:41 PM PST 24 |
| Peak memory | 555140 kb |
| Host | smart-19ef7a3d-560c-49aa-b602-7b51d4bc0812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251401778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.2251401778 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.359670953 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 80035143070 ps |
| CPU time | 821.76 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:54:12 PM PST 24 |
| Peak memory | 555024 kb |
| Host | smart-e3ac6972-fd30-4296-a4da-2ddc37910ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359670953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.359670953 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.404485025 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 27471594350 ps |
| CPU time | 479.25 seconds |
| Started | Jan 10 01:40:19 PM PST 24 |
| Finished | Jan 10 01:48:19 PM PST 24 |
| Peak memory | 554856 kb |
| Host | smart-c62295cb-ca7d-4596-bb5f-81a94c0e3d39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404485025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.404485025 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.3897317288 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 404919005 ps |
| CPU time | 32.04 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:40:56 PM PST 24 |
| Peak memory | 554736 kb |
| Host | smart-54492fba-dc78-4cfc-8edd-34d73f9b96c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897317288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.3897317288 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.1998121604 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 111994007 ps |
| CPU time | 10.63 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:40:40 PM PST 24 |
| Peak memory | 555044 kb |
| Host | smart-b4310110-88be-4f7f-833b-76fb3735990f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998121604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1998121604 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.158742989 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 38877302 ps |
| CPU time | 5.86 seconds |
| Started | Jan 10 01:40:23 PM PST 24 |
| Finished | Jan 10 01:40:32 PM PST 24 |
| Peak memory | 552868 kb |
| Host | smart-341b4d69-5c70-44b9-aa5f-933e072eb4a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158742989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.158742989 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3456344955 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 6191797053 ps |
| CPU time | 66.49 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:41:29 PM PST 24 |
| Peak memory | 552996 kb |
| Host | smart-397518bc-7517-42d5-932b-6d097771617c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456344955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3456344955 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.3312988431 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 5717275742 ps |
| CPU time | 99.21 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:42:02 PM PST 24 |
| Peak memory | 552876 kb |
| Host | smart-b9794263-6d10-49e1-89c6-5460bcc6d361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312988431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3312988431 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2286326491 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 37159026 ps |
| CPU time | 5.55 seconds |
| Started | Jan 10 01:40:20 PM PST 24 |
| Finished | Jan 10 01:40:27 PM PST 24 |
| Peak memory | 552908 kb |
| Host | smart-69f4879c-dfe1-4389-bae5-2e87d62c68fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286326491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.2286326491 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.1494438652 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 1315855161 ps |
| CPU time | 117.81 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:42:22 PM PST 24 |
| Peak memory | 557016 kb |
| Host | smart-8f93963e-92d6-4529-a17d-5af88084f04a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494438652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1494438652 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3250869250 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 5082859763 ps |
| CPU time | 188.4 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:43:37 PM PST 24 |
| Peak memory | 556292 kb |
| Host | smart-83873cc1-b3fd-4dfb-8c86-de16bc9b50d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250869250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3250869250 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.4138116075 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 7994706782 ps |
| CPU time | 943.08 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:56:13 PM PST 24 |
| Peak memory | 561464 kb |
| Host | smart-8bb4061f-7417-4c7e-944f-d94ed40d4a8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138116075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.4138116075 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.2487041421 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 86274292 ps |
| CPU time | 6.54 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:40:36 PM PST 24 |
| Peak memory | 552988 kb |
| Host | smart-db779da7-55ed-40af-900c-477f7743ff83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487041421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2487041421 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.2684871801 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2470227146 ps |
| CPU time | 97.71 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:42:13 PM PST 24 |
| Peak memory | 555140 kb |
| Host | smart-fc3f3e80-ef38-4c1c-9d2e-bd2c09ad7204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684871801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .2684871801 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.353706912 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 82362952127 ps |
| CPU time | 1481.03 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 02:05:16 PM PST 24 |
| Peak memory | 554908 kb |
| Host | smart-2cf7f88d-9563-455d-906b-27f6a4414812 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353706912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.353706912 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2856714695 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 243500211 ps |
| CPU time | 11.81 seconds |
| Started | Jan 10 01:40:32 PM PST 24 |
| Finished | Jan 10 01:40:50 PM PST 24 |
| Peak memory | 554988 kb |
| Host | smart-ab165624-724d-4064-80ef-4b7411018fa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856714695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.2856714695 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.3727691146 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 923384877 ps |
| CPU time | 30.9 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:41:06 PM PST 24 |
| Peak memory | 553848 kb |
| Host | smart-f699654d-0fee-453b-afc8-1ecdd819bbce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727691146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3727691146 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.1303008989 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 377768082 ps |
| CPU time | 37.04 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:41:10 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-a3f996e7-e5a4-418f-a9a3-f891dbdae942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303008989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.1303008989 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3813132777 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 57564656670 ps |
| CPU time | 607.64 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:50:40 PM PST 24 |
| Peak memory | 554720 kb |
| Host | smart-ad0efaa1-7da7-4a91-846e-121b59fd5fea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813132777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3813132777 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.3467301997 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 2210338771 ps |
| CPU time | 37.83 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:41:05 PM PST 24 |
| Peak memory | 553008 kb |
| Host | smart-8a22483f-ee01-44b2-ae1c-cba0684c6dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467301997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.3467301997 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.3263869193 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 281848450 ps |
| CPU time | 25.41 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:41:01 PM PST 24 |
| Peak memory | 555060 kb |
| Host | smart-3476b61b-8830-411f-a495-b3b1f01f777e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263869193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.3263869193 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.2777919786 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 453027016 ps |
| CPU time | 30.53 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:41:03 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-7bfa77da-665b-42e8-a0ae-d38fe3f52791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777919786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2777919786 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.2452292785 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 45763922 ps |
| CPU time | 5.85 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:40:39 PM PST 24 |
| Peak memory | 552648 kb |
| Host | smart-ea7856f7-0a14-429d-abb7-cca07b2e26e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452292785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2452292785 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1426905542 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 5741638199 ps |
| CPU time | 58.69 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:41:33 PM PST 24 |
| Peak memory | 552732 kb |
| Host | smart-c80846fb-d5b3-4c7a-a416-4277f35ff286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426905542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1426905542 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1031918150 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 5787778028 ps |
| CPU time | 102.25 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:42:16 PM PST 24 |
| Peak memory | 552756 kb |
| Host | smart-26d6d77a-6636-49cc-bbd1-5faad865e7ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031918150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1031918150 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.141373013 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 48508312 ps |
| CPU time | 6.02 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:40:40 PM PST 24 |
| Peak memory | 552616 kb |
| Host | smart-43834b9f-35ee-46f9-a232-c6033eb2e65c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141373013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .141373013 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.3255067353 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 5243138036 ps |
| CPU time | 188.66 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:43:42 PM PST 24 |
| Peak memory | 555916 kb |
| Host | smart-1d780d09-01e5-41ae-8eea-69b9bf7477d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255067353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3255067353 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.455414865 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 16551131520 ps |
| CPU time | 520.33 seconds |
| Started | Jan 10 01:40:33 PM PST 24 |
| Finished | Jan 10 01:49:19 PM PST 24 |
| Peak memory | 556280 kb |
| Host | smart-061d52e6-47f1-4eb5-a1ce-05686b01dc5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455414865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.455414865 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1232480275 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 168704414 ps |
| CPU time | 53.07 seconds |
| Started | Jan 10 01:40:31 PM PST 24 |
| Finished | Jan 10 01:41:30 PM PST 24 |
| Peak memory | 555932 kb |
| Host | smart-b7e3b7d1-1f07-43cc-bbc5-f5a3e5a482c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232480275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.1232480275 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1459421082 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 311926074 ps |
| CPU time | 83.85 seconds |
| Started | Jan 10 01:40:32 PM PST 24 |
| Finished | Jan 10 01:42:02 PM PST 24 |
| Peak memory | 556208 kb |
| Host | smart-221bd4c2-48a7-4046-a5fc-a6bb8b01e46e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459421082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.1459421082 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.2217770382 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 782649340 ps |
| CPU time | 34.03 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:41:03 PM PST 24 |
| Peak memory | 553912 kb |
| Host | smart-8224073d-4fdd-484a-ba0c-2a4cecea067a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217770382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2217770382 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.442543453 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 834681067 ps |
| CPU time | 56.65 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:41:27 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-1a1ca369-a3ce-4bdf-88bd-873325966bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442543453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 442543453 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.307825827 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 107146377513 ps |
| CPU time | 1907.82 seconds |
| Started | Jan 10 01:40:32 PM PST 24 |
| Finished | Jan 10 02:12:27 PM PST 24 |
| Peak memory | 556204 kb |
| Host | smart-9140bbf6-b5b5-4114-bbe6-e2bb54750506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307825827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_d evice_slow_rsp.307825827 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3449940588 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 211115749 ps |
| CPU time | 10.16 seconds |
| Started | Jan 10 01:40:23 PM PST 24 |
| Finished | Jan 10 01:40:36 PM PST 24 |
| Peak memory | 553964 kb |
| Host | smart-2824d7e2-49e2-41c2-ae2f-66c22155ccee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449940588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.3449940588 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.2432140746 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 1757450886 ps |
| CPU time | 60.73 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:41:28 PM PST 24 |
| Peak memory | 554652 kb |
| Host | smart-70ae07a5-ac48-48ce-9e2d-b21fffce179e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432140746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2432140746 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.1284910376 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2354512087 ps |
| CPU time | 81.61 seconds |
| Started | Jan 10 01:40:37 PM PST 24 |
| Finished | Jan 10 01:42:03 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-6b1f93aa-2520-4348-bfa3-af2161bfea7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284910376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1284910376 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3214319635 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 99798262559 ps |
| CPU time | 1053.23 seconds |
| Started | Jan 10 01:40:33 PM PST 24 |
| Finished | Jan 10 01:58:13 PM PST 24 |
| Peak memory | 554828 kb |
| Host | smart-122c4426-edbb-4c7c-a314-8fc4049f271a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214319635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3214319635 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.2395431512 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 18736219968 ps |
| CPU time | 313.17 seconds |
| Started | Jan 10 01:40:34 PM PST 24 |
| Finished | Jan 10 01:45:53 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-8f74c32d-16da-47ec-ac58-49b2d61d39de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395431512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2395431512 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.2424835067 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 566267913 ps |
| CPU time | 45.74 seconds |
| Started | Jan 10 01:40:36 PM PST 24 |
| Finished | Jan 10 01:41:27 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-54f3f7b9-0cc7-4c2b-9b2a-b62fd4f21bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424835067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.2424835067 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.308565826 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 1079866523 ps |
| CPU time | 30.99 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:40:59 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-2367c85a-e29b-430a-8f76-414a5e9c8aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308565826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.308565826 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.3744956962 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 201357593 ps |
| CPU time | 9.01 seconds |
| Started | Jan 10 01:40:32 PM PST 24 |
| Finished | Jan 10 01:40:47 PM PST 24 |
| Peak memory | 552688 kb |
| Host | smart-e9745bc7-849c-49e8-a7cc-dc629d08c10e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744956962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3744956962 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.475610122 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 8189508036 ps |
| CPU time | 87.6 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:41:57 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-b9ee1c5a-1b5a-461a-b988-47c05406b3f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475610122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.475610122 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.187469493 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 5265700659 ps |
| CPU time | 86.3 seconds |
| Started | Jan 10 01:40:31 PM PST 24 |
| Finished | Jan 10 01:42:04 PM PST 24 |
| Peak memory | 552756 kb |
| Host | smart-9d6b337c-224e-43f0-bc71-9e8f65ce2cf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187469493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.187469493 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1999576168 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 52314697 ps |
| CPU time | 6.13 seconds |
| Started | Jan 10 01:40:37 PM PST 24 |
| Finished | Jan 10 01:40:48 PM PST 24 |
| Peak memory | 552656 kb |
| Host | smart-a1204a9d-ad4c-474a-b1f9-921d83ad6ae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999576168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.1999576168 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.3341342327 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 15059834848 ps |
| CPU time | 600.55 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:50:24 PM PST 24 |
| Peak memory | 556184 kb |
| Host | smart-1518f337-5bb3-4352-b8b6-93bc8808a7e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341342327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3341342327 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1133279580 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 4699634261 ps |
| CPU time | 157.64 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:43:01 PM PST 24 |
| Peak memory | 555864 kb |
| Host | smart-7351b322-cef8-4a53-9386-9d8b6a64902c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133279580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1133279580 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2625863076 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 157910218 ps |
| CPU time | 70.91 seconds |
| Started | Jan 10 01:40:34 PM PST 24 |
| Finished | Jan 10 01:41:50 PM PST 24 |
| Peak memory | 555932 kb |
| Host | smart-d27b6b1f-b595-4ff6-8305-92eba6657c96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625863076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2625863076 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3317062320 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 40374318 ps |
| CPU time | 37.29 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:41:00 PM PST 24 |
| Peak memory | 555128 kb |
| Host | smart-780f8fc7-f6e5-4ace-aae6-993074bca81a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317062320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.3317062320 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.363439264 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 1044608919 ps |
| CPU time | 42.57 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:41:06 PM PST 24 |
| Peak memory | 554836 kb |
| Host | smart-3f7cd375-808f-497b-a4ac-41495a1b2570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363439264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.363439264 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.4002237467 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 2671915383 ps |
| CPU time | 116.07 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:42:26 PM PST 24 |
| Peak memory | 555140 kb |
| Host | smart-96cd89ad-e392-4ff5-87fa-85ef9ee573b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002237467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .4002237467 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2794294247 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 54611530198 ps |
| CPU time | 981.18 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:56:50 PM PST 24 |
| Peak memory | 556188 kb |
| Host | smart-3afbe2de-a139-42a9-92e1-7f76b364c28f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794294247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.2794294247 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.3217171724 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 818305151 ps |
| CPU time | 32.06 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:41:02 PM PST 24 |
| Peak memory | 554748 kb |
| Host | smart-742bbe09-c97c-4514-b9e6-6f80d47ed548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217171724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.3217171724 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.2938379141 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 559623875 ps |
| CPU time | 42.3 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:41:10 PM PST 24 |
| Peak memory | 554956 kb |
| Host | smart-5579572a-f1e2-461a-80ce-6b6205fe2ab4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938379141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2938379141 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.2609531885 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 571855144 ps |
| CPU time | 49.12 seconds |
| Started | Jan 10 01:40:23 PM PST 24 |
| Finished | Jan 10 01:41:15 PM PST 24 |
| Peak memory | 553900 kb |
| Host | smart-e30fa688-e6e6-4f14-bbf0-c401b272e205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609531885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.2609531885 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.3932474221 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 29992087479 ps |
| CPU time | 291.63 seconds |
| Started | Jan 10 01:40:20 PM PST 24 |
| Finished | Jan 10 01:45:13 PM PST 24 |
| Peak memory | 554836 kb |
| Host | smart-0c896f97-3211-4359-a4d3-8c2309cddf4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932474221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3932474221 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.4210033734 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 38390968536 ps |
| CPU time | 665.98 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:51:35 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-402cff99-8d5d-4828-87b2-534c24afaf84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210033734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4210033734 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.2629274091 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 40574935 ps |
| CPU time | 6.76 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:40:36 PM PST 24 |
| Peak memory | 552492 kb |
| Host | smart-55f348d1-ca9d-43af-b6a8-843476142e3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629274091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.2629274091 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.1723313327 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 557576379 ps |
| CPU time | 36.78 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:41:05 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-292f1f74-da59-4995-9f65-ce4ed08f988c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723313327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1723313327 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.1653855621 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 39757828 ps |
| CPU time | 5.91 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:40:34 PM PST 24 |
| Peak memory | 552904 kb |
| Host | smart-25f93919-b226-48a1-b85f-c18329249ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653855621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1653855621 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.165524072 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 10269513771 ps |
| CPU time | 98.91 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:42:03 PM PST 24 |
| Peak memory | 553088 kb |
| Host | smart-391a2d6c-e22a-46e4-b2c7-ab3e2b45a1df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165524072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.165524072 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2662798775 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 4623427628 ps |
| CPU time | 81.03 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:41:45 PM PST 24 |
| Peak memory | 553020 kb |
| Host | smart-55a0078c-d2f8-46e3-8b7c-db6416de7c21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662798775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2662798775 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.2343558782 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 39557966 ps |
| CPU time | 5.73 seconds |
| Started | Jan 10 01:40:20 PM PST 24 |
| Finished | Jan 10 01:40:27 PM PST 24 |
| Peak memory | 552564 kb |
| Host | smart-a4c00ff5-3455-44e9-824d-80d663d84810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343558782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.2343558782 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.284179478 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1660900685 ps |
| CPU time | 127.86 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:42:40 PM PST 24 |
| Peak memory | 555968 kb |
| Host | smart-0b5d1164-8fb2-4c56-bd98-2bb54f7011c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284179478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.284179478 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.4202251406 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 11395375059 ps |
| CPU time | 381.18 seconds |
| Started | Jan 10 01:40:28 PM PST 24 |
| Finished | Jan 10 01:46:54 PM PST 24 |
| Peak memory | 556988 kb |
| Host | smart-4afc78ee-4482-4630-ae65-4ebecaa4ec78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202251406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.4202251406 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.2327716547 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2342679262 ps |
| CPU time | 322.08 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:45:56 PM PST 24 |
| Peak memory | 557684 kb |
| Host | smart-d8b853bc-1346-4775-99fe-a00085fabe0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327716547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.2327716547 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1968518821 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 291300217 ps |
| CPU time | 79.66 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:41:51 PM PST 24 |
| Peak memory | 556096 kb |
| Host | smart-49d77b3c-882c-41e8-9f2e-5e926714a4c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968518821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.1968518821 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2241668582 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 274300494 ps |
| CPU time | 30.4 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:40:59 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-93d2b7c4-d71f-4674-a4fd-3e574a3c1061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241668582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2241668582 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3084037629 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 1310638424 ps |
| CPU time | 51.95 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:41:26 PM PST 24 |
| Peak memory | 554720 kb |
| Host | smart-a3be90fb-ccca-4901-85d8-fb7c6865c389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084037629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3084037629 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2233270260 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 2704576963 ps |
| CPU time | 45.28 seconds |
| Started | Jan 10 01:40:31 PM PST 24 |
| Finished | Jan 10 01:41:23 PM PST 24 |
| Peak memory | 552736 kb |
| Host | smart-f4ecbfb0-16cf-4bdf-801b-71830a6c905c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233270260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.2233270260 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.364618157 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 97043297 ps |
| CPU time | 6.99 seconds |
| Started | Jan 10 01:40:32 PM PST 24 |
| Finished | Jan 10 01:40:45 PM PST 24 |
| Peak memory | 552604 kb |
| Host | smart-095a0203-afc3-4fd3-aa51-0b5adcc93ffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364618157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr .364618157 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.1480408983 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 1500491370 ps |
| CPU time | 48.1 seconds |
| Started | Jan 10 01:40:32 PM PST 24 |
| Finished | Jan 10 01:41:27 PM PST 24 |
| Peak memory | 555024 kb |
| Host | smart-db5beedf-ab01-4cf9-9a14-4fe5dc02dcee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480408983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1480408983 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.4255460107 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 462912850 ps |
| CPU time | 17.16 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:40:48 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-a762e2da-ac69-4d4f-bdc0-49b60c6b4606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255460107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.4255460107 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2230997612 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 66410814193 ps |
| CPU time | 707.49 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:52:23 PM PST 24 |
| Peak memory | 554832 kb |
| Host | smart-f1d36d37-f979-4276-b735-438de1b5a5d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230997612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2230997612 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.2794614504 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 8006394309 ps |
| CPU time | 121.37 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:42:36 PM PST 24 |
| Peak memory | 553984 kb |
| Host | smart-d18518e5-c0a0-4918-9ae9-5af3d29829a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794614504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2794614504 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2173164949 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 38739538 ps |
| CPU time | 5.97 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:40:41 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-98f21d45-4552-4f44-9fa0-7895467d7c96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173164949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.2173164949 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.4191657377 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 80878062 ps |
| CPU time | 8.69 seconds |
| Started | Jan 10 01:40:33 PM PST 24 |
| Finished | Jan 10 01:40:48 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-b37667e0-1725-48fe-9487-88d10554a2c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191657377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.4191657377 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.2011938437 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 161808391 ps |
| CPU time | 7.29 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:40:36 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-ed3c1dc6-4841-4071-b91c-4eeae4d87ef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011938437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2011938437 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.744118466 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 8495059864 ps |
| CPU time | 88.37 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:42:00 PM PST 24 |
| Peak memory | 552992 kb |
| Host | smart-77fb44c9-4876-4768-a949-6a37087cba75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744118466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.744118466 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.3114545660 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 4320619844 ps |
| CPU time | 67.21 seconds |
| Started | Jan 10 01:40:28 PM PST 24 |
| Finished | Jan 10 01:41:40 PM PST 24 |
| Peak memory | 552916 kb |
| Host | smart-12c45415-7054-4231-b122-c2d5f3367c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114545660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3114545660 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.3533176701 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 40231782 ps |
| CPU time | 5.8 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:40:36 PM PST 24 |
| Peak memory | 552948 kb |
| Host | smart-a599e521-b5b4-4b7d-8a02-5abdd36bd302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533176701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.3533176701 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3606660737 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 8272164334 ps |
| CPU time | 268.08 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:45:04 PM PST 24 |
| Peak memory | 556288 kb |
| Host | smart-b349f9d2-96d3-4237-a230-e71f146225c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606660737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3606660737 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.2305963321 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 2956219275 ps |
| CPU time | 95.8 seconds |
| Started | Jan 10 01:40:32 PM PST 24 |
| Finished | Jan 10 01:42:14 PM PST 24 |
| Peak memory | 556216 kb |
| Host | smart-2d72eb24-e5b5-4589-a3be-93823110ab95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305963321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.2305963321 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1014471577 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 347611809 ps |
| CPU time | 126.62 seconds |
| Started | Jan 10 01:40:32 PM PST 24 |
| Finished | Jan 10 01:42:45 PM PST 24 |
| Peak memory | 557196 kb |
| Host | smart-a42292bd-6e11-4013-ac4f-fac40d768d8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014471577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1014471577 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3272779160 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 5144059832 ps |
| CPU time | 252.04 seconds |
| Started | Jan 10 01:40:32 PM PST 24 |
| Finished | Jan 10 01:44:51 PM PST 24 |
| Peak memory | 558428 kb |
| Host | smart-67de8f1d-6b59-4f25-9172-4787d9ce7120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272779160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.3272779160 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.1833539651 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 344257029 ps |
| CPU time | 16.63 seconds |
| Started | Jan 10 01:40:33 PM PST 24 |
| Finished | Jan 10 01:40:56 PM PST 24 |
| Peak memory | 555120 kb |
| Host | smart-00240ce2-e508-482c-a668-e16fd872c690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833539651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.1833539651 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.3733398674 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 254346977 ps |
| CPU time | 11.26 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:40:33 PM PST 24 |
| Peak memory | 553012 kb |
| Host | smart-fd71a85d-493d-4312-8b4c-3e5bc9381f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733398674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .3733398674 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.742234293 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 89923236045 ps |
| CPU time | 1541.92 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 02:06:06 PM PST 24 |
| Peak memory | 556024 kb |
| Host | smart-cb4253aa-3a34-4433-93a6-4f46402b9cfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742234293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d evice_slow_rsp.742234293 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.2755422595 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 1192053156 ps |
| CPU time | 43.13 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:41:07 PM PST 24 |
| Peak memory | 553824 kb |
| Host | smart-ce1223a0-f6f2-4e4b-96d7-c5e87f55b758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755422595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.2755422595 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.1044366395 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 562330903 ps |
| CPU time | 44.03 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:41:07 PM PST 24 |
| Peak memory | 554964 kb |
| Host | smart-af537d8e-1967-496d-abcf-e5856315a4ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044366395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1044366395 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.3990687338 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2509965610 ps |
| CPU time | 89.67 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:41:58 PM PST 24 |
| Peak memory | 555148 kb |
| Host | smart-49d6d251-6957-4a0d-a02a-5c22ca995496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990687338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.3990687338 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.3783541546 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 5123382148 ps |
| CPU time | 57.89 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:41:28 PM PST 24 |
| Peak memory | 553012 kb |
| Host | smart-73c000bd-b643-4c62-b9be-6e20e2aa8087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783541546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3783541546 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.2426731647 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 54272179625 ps |
| CPU time | 1016.11 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:57:21 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-dc2e1f11-8af2-4b5a-bea7-5d17dee16a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426731647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.2426731647 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.3807022958 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 533982912 ps |
| CPU time | 45.73 seconds |
| Started | Jan 10 01:40:34 PM PST 24 |
| Finished | Jan 10 01:41:25 PM PST 24 |
| Peak memory | 554752 kb |
| Host | smart-c40c54af-e2f0-4a52-842f-99813f89ce32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807022958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.3807022958 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.658968709 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 440372384 ps |
| CPU time | 31.73 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:40:54 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-5307969b-359a-420e-8d83-6a0dacb2bf66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658968709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.658968709 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.4052880761 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 201331674 ps |
| CPU time | 7.79 seconds |
| Started | Jan 10 01:40:37 PM PST 24 |
| Finished | Jan 10 01:40:49 PM PST 24 |
| Peak memory | 552928 kb |
| Host | smart-f8dc165f-07eb-464d-93cb-178b69e2396a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052880761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4052880761 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.2210416415 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 9692562261 ps |
| CPU time | 99.11 seconds |
| Started | Jan 10 01:40:33 PM PST 24 |
| Finished | Jan 10 01:42:18 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-7082b76c-15eb-4332-8490-30aecbb26508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210416415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2210416415 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.114964285 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 4651658855 ps |
| CPU time | 75.45 seconds |
| Started | Jan 10 01:40:37 PM PST 24 |
| Finished | Jan 10 01:41:57 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-3bdecd26-87f7-4134-820c-4187d1bf83cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114964285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.114964285 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1627098360 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 39819926 ps |
| CPU time | 5.2 seconds |
| Started | Jan 10 01:40:36 PM PST 24 |
| Finished | Jan 10 01:40:46 PM PST 24 |
| Peak memory | 552928 kb |
| Host | smart-ba024dca-5a50-4c93-9532-ae263c6655aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627098360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.1627098360 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.3664491258 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 6151923 ps |
| CPU time | 3.6 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:40:27 PM PST 24 |
| Peak memory | 544312 kb |
| Host | smart-97eb9fd3-2d8f-45c1-8beb-e87d337c3af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664491258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3664491258 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.878931660 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 3266556384 ps |
| CPU time | 222.57 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:44:12 PM PST 24 |
| Peak memory | 556148 kb |
| Host | smart-bd735b0f-d65b-4eb8-82bc-c2f677c3a9de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878931660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.878931660 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.4038079139 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 4044801042 ps |
| CPU time | 471.02 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:48:13 PM PST 24 |
| Peak memory | 557184 kb |
| Host | smart-10d9a9c6-32fc-4790-920c-8a3e0fcb9fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038079139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.4038079139 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1047527307 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 172234149 ps |
| CPU time | 45.25 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:41:09 PM PST 24 |
| Peak memory | 555848 kb |
| Host | smart-29738ac8-62a9-4c01-b492-f40a0da4cb52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047527307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1047527307 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3586605011 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 1360498477 ps |
| CPU time | 59.22 seconds |
| Started | Jan 10 01:40:23 PM PST 24 |
| Finished | Jan 10 01:41:25 PM PST 24 |
| Peak memory | 554020 kb |
| Host | smart-46bfb26d-7f0c-4314-9083-df5f6683f07f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586605011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3586605011 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2979300521 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 574672899 ps |
| CPU time | 24.66 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:40:54 PM PST 24 |
| Peak memory | 555080 kb |
| Host | smart-5bb13349-a155-4939-9c7c-d81f44261bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979300521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .2979300521 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.1631412036 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 92796893716 ps |
| CPU time | 1624.65 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 02:07:40 PM PST 24 |
| Peak memory | 556132 kb |
| Host | smart-b19d54f2-26d2-46a3-a305-e100ea800bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631412036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.1631412036 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1372448072 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 137031387 ps |
| CPU time | 14.58 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:40:48 PM PST 24 |
| Peak memory | 555020 kb |
| Host | smart-655b177a-fc71-4782-9ccf-551dbb9f3b6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372448072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.1372448072 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.2537835117 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 833301447 ps |
| CPU time | 30.04 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:41:01 PM PST 24 |
| Peak memory | 553876 kb |
| Host | smart-c7da2781-e567-442f-bc8d-0ca37442c800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537835117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2537835117 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.4243831519 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 1356240151 ps |
| CPU time | 41.91 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:41:09 PM PST 24 |
| Peak memory | 554780 kb |
| Host | smart-0f27af87-bcf2-43fd-86d9-c4e0c0ec5670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243831519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.4243831519 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3553286653 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 101481173193 ps |
| CPU time | 1155.92 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:59:47 PM PST 24 |
| Peak memory | 554080 kb |
| Host | smart-261eb074-d54f-4fc8-afe9-82efd745a3f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553286653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3553286653 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.3175773390 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 63572155449 ps |
| CPU time | 1222.79 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 02:00:53 PM PST 24 |
| Peak memory | 554044 kb |
| Host | smart-660768ad-c27f-46a1-a49b-92c515fe2bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175773390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.3175773390 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.980245486 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 54999054 ps |
| CPU time | 7.44 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:40:36 PM PST 24 |
| Peak memory | 553016 kb |
| Host | smart-de850c0c-98b3-4f66-8459-a7219785a761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980245486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_dela ys.980245486 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.2561389137 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 171460555 ps |
| CPU time | 13.03 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:40:40 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-f223c185-17d2-4b8f-9393-1ae39f2e40ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561389137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2561389137 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.4123679232 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 46504185 ps |
| CPU time | 5.73 seconds |
| Started | Jan 10 01:40:24 PM PST 24 |
| Finished | Jan 10 01:40:33 PM PST 24 |
| Peak memory | 552536 kb |
| Host | smart-b432daba-f677-44c4-8916-8396e62167ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123679232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4123679232 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.799439423 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 10896353954 ps |
| CPU time | 97.92 seconds |
| Started | Jan 10 01:40:25 PM PST 24 |
| Finished | Jan 10 01:42:06 PM PST 24 |
| Peak memory | 552736 kb |
| Host | smart-7d6d4150-5268-4678-a08a-fb61e2c13c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799439423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.799439423 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.3461915870 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 4977328661 ps |
| CPU time | 80.91 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:41:43 PM PST 24 |
| Peak memory | 552688 kb |
| Host | smart-2252bb91-13e4-4ee3-ae5c-43a37a8d8d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461915870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3461915870 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3981817254 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 40325500 ps |
| CPU time | 5.92 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:40:31 PM PST 24 |
| Peak memory | 552860 kb |
| Host | smart-7201efec-2ff4-432a-97ff-ba17f82a5d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981817254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.3981817254 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.3648925952 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 477196613 ps |
| CPU time | 32.63 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:41:03 PM PST 24 |
| Peak memory | 554900 kb |
| Host | smart-c355c44f-51f5-4be8-9877-c2bac8b2695c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648925952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3648925952 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.1024891384 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 13280822225 ps |
| CPU time | 482 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:48:26 PM PST 24 |
| Peak memory | 556012 kb |
| Host | smart-c93f4881-bbd4-4d17-a566-65645aa5ba6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024891384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1024891384 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3041207221 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 189539728 ps |
| CPU time | 121.05 seconds |
| Started | Jan 10 01:40:28 PM PST 24 |
| Finished | Jan 10 01:42:33 PM PST 24 |
| Peak memory | 556296 kb |
| Host | smart-92a9182e-c771-4e9a-849b-331c0401c571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041207221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.3041207221 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.49288497 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 2053605927 ps |
| CPU time | 165.97 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:43:21 PM PST 24 |
| Peak memory | 557012 kb |
| Host | smart-5492512d-fe4a-42e1-91c1-29c2c17f5ecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49288497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_ with_reset_error.49288497 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2384462852 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 440766691 ps |
| CPU time | 19.51 seconds |
| Started | Jan 10 01:40:26 PM PST 24 |
| Finished | Jan 10 01:40:49 PM PST 24 |
| Peak memory | 554928 kb |
| Host | smart-614816d0-fa8d-4a35-aaf4-f7c10b7e20e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384462852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2384462852 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2757219173 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 698512578 ps |
| CPU time | 55.22 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:41:28 PM PST 24 |
| Peak memory | 554728 kb |
| Host | smart-06904afb-b7c1-4c92-ae35-5abfd9c9a1c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757219173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .2757219173 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1638354835 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 323086029 ps |
| CPU time | 33.98 seconds |
| Started | Jan 10 01:41:04 PM PST 24 |
| Finished | Jan 10 01:41:41 PM PST 24 |
| Peak memory | 555060 kb |
| Host | smart-3a4d78f0-3d5f-467e-b776-e39ce792329d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638354835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.1638354835 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.2951723260 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 1012059845 ps |
| CPU time | 36.08 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:41:00 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-a2d3244d-c42a-4c59-843a-c0058cca3601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951723260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2951723260 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2243602556 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 2117093743 ps |
| CPU time | 77.2 seconds |
| Started | Jan 10 01:40:28 PM PST 24 |
| Finished | Jan 10 01:41:49 PM PST 24 |
| Peak memory | 553888 kb |
| Host | smart-00f9b59c-872a-454a-b346-ac98026f5f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243602556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2243602556 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.1956257473 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 53882140766 ps |
| CPU time | 558.85 seconds |
| Started | Jan 10 01:40:31 PM PST 24 |
| Finished | Jan 10 01:49:55 PM PST 24 |
| Peak memory | 554748 kb |
| Host | smart-4999ea89-2eb1-437c-ad60-8b25dc944193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956257473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1956257473 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3382436407 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 16149484431 ps |
| CPU time | 266.87 seconds |
| Started | Jan 10 01:40:31 PM PST 24 |
| Finished | Jan 10 01:45:03 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-192c66a7-be2f-4580-9ad7-4957856bce6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382436407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3382436407 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.3500489413 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 367773178 ps |
| CPU time | 32.01 seconds |
| Started | Jan 10 01:40:22 PM PST 24 |
| Finished | Jan 10 01:40:57 PM PST 24 |
| Peak memory | 554728 kb |
| Host | smart-a4ee62b8-b3e6-43d8-a9ac-b69824d8213c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500489413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.3500489413 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.4007077371 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 91902610 ps |
| CPU time | 9.08 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:40:44 PM PST 24 |
| Peak memory | 554732 kb |
| Host | smart-2418f280-e74a-4ebd-8ac9-ec75e1ee0852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007077371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.4007077371 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.127120215 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 45933011 ps |
| CPU time | 6.09 seconds |
| Started | Jan 10 01:40:21 PM PST 24 |
| Finished | Jan 10 01:40:29 PM PST 24 |
| Peak memory | 553000 kb |
| Host | smart-b611b768-0320-436c-a141-9d8886613c20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127120215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.127120215 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.3106510545 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 6072907181 ps |
| CPU time | 66.39 seconds |
| Started | Jan 10 01:40:27 PM PST 24 |
| Finished | Jan 10 01:41:38 PM PST 24 |
| Peak memory | 552712 kb |
| Host | smart-311d989a-9181-4294-9c5f-e2790765dbe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106510545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3106510545 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.2288207060 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 6188709342 ps |
| CPU time | 95.76 seconds |
| Started | Jan 10 01:40:29 PM PST 24 |
| Finished | Jan 10 01:42:10 PM PST 24 |
| Peak memory | 552772 kb |
| Host | smart-3faef0db-3f3f-484e-8e82-51d515acbdb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288207060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2288207060 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.607886831 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 43685343 ps |
| CPU time | 5.9 seconds |
| Started | Jan 10 01:40:30 PM PST 24 |
| Finished | Jan 10 01:40:41 PM PST 24 |
| Peak memory | 552956 kb |
| Host | smart-47766cb9-f977-4eff-bdc3-05b29f184889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607886831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .607886831 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.3617104437 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2887054665 ps |
| CPU time | 208.11 seconds |
| Started | Jan 10 01:41:01 PM PST 24 |
| Finished | Jan 10 01:44:30 PM PST 24 |
| Peak memory | 556668 kb |
| Host | smart-4f28f5f5-9c59-40a1-a295-dfd3b8ec32e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617104437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3617104437 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2157910655 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 4886054977 ps |
| CPU time | 323.18 seconds |
| Started | Jan 10 01:41:02 PM PST 24 |
| Finished | Jan 10 01:46:26 PM PST 24 |
| Peak memory | 556268 kb |
| Host | smart-b903e339-a3c5-4b97-a70c-9e797ff5b0b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157910655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2157910655 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3599251782 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 667104865 ps |
| CPU time | 196.64 seconds |
| Started | Jan 10 01:41:05 PM PST 24 |
| Finished | Jan 10 01:44:25 PM PST 24 |
| Peak memory | 557324 kb |
| Host | smart-a108f85d-4873-4ac2-a7f2-c599197e5c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599251782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3599251782 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.570328461 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 6012600986 ps |
| CPU time | 593.38 seconds |
| Started | Jan 10 01:41:11 PM PST 24 |
| Finished | Jan 10 01:51:24 PM PST 24 |
| Peak memory | 568140 kb |
| Host | smart-b6e4e7ac-1f38-4410-8fb0-fd7223b6b789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570328461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_reset_error.570328461 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.4259342697 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 749188806 ps |
| CPU time | 30.96 seconds |
| Started | Jan 10 01:41:05 PM PST 24 |
| Finished | Jan 10 01:41:40 PM PST 24 |
| Peak memory | 555052 kb |
| Host | smart-8b9be23e-cc76-420e-8434-e1a17ceb32d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259342697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4259342697 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.701552983 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 314896211 ps |
| CPU time | 30.37 seconds |
| Started | Jan 10 01:41:01 PM PST 24 |
| Finished | Jan 10 01:41:33 PM PST 24 |
| Peak memory | 555720 kb |
| Host | smart-ca3d712e-b74d-45f4-825b-a6a6a57de5cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701552983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device. 701552983 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1693719061 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 66066533211 ps |
| CPU time | 1186.15 seconds |
| Started | Jan 10 01:41:03 PM PST 24 |
| Finished | Jan 10 02:00:51 PM PST 24 |
| Peak memory | 554856 kb |
| Host | smart-9b43734c-b7dc-44be-82af-306c79311393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693719061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.1693719061 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.2520190643 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 660318825 ps |
| CPU time | 25.08 seconds |
| Started | Jan 10 01:41:00 PM PST 24 |
| Finished | Jan 10 01:41:27 PM PST 24 |
| Peak memory | 554692 kb |
| Host | smart-79535f48-e84a-492b-9c66-55f34fd4c561 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520190643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.2520190643 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.3467323425 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 2253438107 ps |
| CPU time | 77.88 seconds |
| Started | Jan 10 01:41:07 PM PST 24 |
| Finished | Jan 10 01:42:36 PM PST 24 |
| Peak memory | 554680 kb |
| Host | smart-15714813-6365-4c8a-91e3-1eef081c984b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467323425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3467323425 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.3756906053 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 70602101 ps |
| CPU time | 8.19 seconds |
| Started | Jan 10 01:41:03 PM PST 24 |
| Finished | Jan 10 01:41:13 PM PST 24 |
| Peak memory | 553968 kb |
| Host | smart-193434a5-b514-4150-ad30-837a421196e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756906053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3756906053 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.818912408 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 116644565786 ps |
| CPU time | 1402.67 seconds |
| Started | Jan 10 01:41:05 PM PST 24 |
| Finished | Jan 10 02:04:31 PM PST 24 |
| Peak memory | 554848 kb |
| Host | smart-6082a707-6796-4f7d-93f1-6d6479b36847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818912408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.818912408 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.3132241815 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 55296432874 ps |
| CPU time | 1041.98 seconds |
| Started | Jan 10 01:41:02 PM PST 24 |
| Finished | Jan 10 01:58:25 PM PST 24 |
| Peak memory | 554836 kb |
| Host | smart-78896854-00c3-4ec8-b6b4-a7d0921c4045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132241815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3132241815 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1971091759 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 481909627 ps |
| CPU time | 34.75 seconds |
| Started | Jan 10 01:41:06 PM PST 24 |
| Finished | Jan 10 01:41:44 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-73f1bf52-f5b8-4c67-9552-043342d469d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971091759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.1971091759 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.2390984811 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 406705010 ps |
| CPU time | 29.23 seconds |
| Started | Jan 10 01:41:02 PM PST 24 |
| Finished | Jan 10 01:41:32 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-dee7c45b-678f-48f3-b719-bb5747cbfc56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390984811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2390984811 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.3949101591 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 188618967 ps |
| CPU time | 8.29 seconds |
| Started | Jan 10 01:41:03 PM PST 24 |
| Finished | Jan 10 01:41:13 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-f947d3ad-6460-4b24-b788-f187dc857921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949101591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3949101591 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1150318614 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 6536656760 ps |
| CPU time | 65.82 seconds |
| Started | Jan 10 01:41:04 PM PST 24 |
| Finished | Jan 10 01:42:14 PM PST 24 |
| Peak memory | 552672 kb |
| Host | smart-61bc4168-7ae5-41c7-8b39-30c948d40874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150318614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1150318614 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.1360261035 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 4945646956 ps |
| CPU time | 74.26 seconds |
| Started | Jan 10 01:41:04 PM PST 24 |
| Finished | Jan 10 01:42:22 PM PST 24 |
| Peak memory | 552580 kb |
| Host | smart-58232c16-a23f-4eea-9f29-2ec33be377cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360261035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1360261035 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1731050842 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 47237992 ps |
| CPU time | 5.92 seconds |
| Started | Jan 10 01:41:04 PM PST 24 |
| Finished | Jan 10 01:41:14 PM PST 24 |
| Peak memory | 552632 kb |
| Host | smart-b830bb29-c6b6-4c1e-8c10-81adbd3605b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731050842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1731050842 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.3397037584 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 2768472784 ps |
| CPU time | 212.96 seconds |
| Started | Jan 10 01:41:04 PM PST 24 |
| Finished | Jan 10 01:44:41 PM PST 24 |
| Peak memory | 556028 kb |
| Host | smart-82f57389-a319-412c-8e37-cd03355f4101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397037584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3397037584 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.790971867 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 2618656940 ps |
| CPU time | 185.01 seconds |
| Started | Jan 10 01:41:04 PM PST 24 |
| Finished | Jan 10 01:44:13 PM PST 24 |
| Peak memory | 555968 kb |
| Host | smart-f9863750-400a-4db1-b7fe-a4b44269017f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790971867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.790971867 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1669393730 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 52263893 ps |
| CPU time | 12.1 seconds |
| Started | Jan 10 01:41:00 PM PST 24 |
| Finished | Jan 10 01:41:13 PM PST 24 |
| Peak memory | 553832 kb |
| Host | smart-6cb47bba-c7d6-41b4-8c17-79a6fd06d5af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669393730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.1669393730 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2362953704 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 2883318480 ps |
| CPU time | 356.7 seconds |
| Started | Jan 10 01:41:04 PM PST 24 |
| Finished | Jan 10 01:47:03 PM PST 24 |
| Peak memory | 559888 kb |
| Host | smart-bab5c797-77f7-4263-972c-bd4bb848f18b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362953704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.2362953704 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.1136494767 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1055177745 ps |
| CPU time | 43.49 seconds |
| Started | Jan 10 01:41:01 PM PST 24 |
| Finished | Jan 10 01:41:46 PM PST 24 |
| Peak memory | 554812 kb |
| Host | smart-bc23b81f-455a-4e66-83ff-cf14bbfa5bdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136494767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1136494767 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.3220238801 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 9001187720 ps |
| CPU time | 387.22 seconds |
| Started | Jan 10 01:36:10 PM PST 24 |
| Finished | Jan 10 01:42:43 PM PST 24 |
| Peak memory | 621192 kb |
| Host | smart-6fc44aac-1752-4a43-9e89-df18d7e2f44c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220238801 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.3220238801 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.2639977810 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 5874407700 ps |
| CPU time | 514.71 seconds |
| Started | Jan 10 01:35:51 PM PST 24 |
| Finished | Jan 10 01:44:41 PM PST 24 |
| Peak memory | 580852 kb |
| Host | smart-a128fe0c-1258-40de-a6c4-c1891b07ca56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639977810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2639977810 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.4269385663 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 16402329976 ps |
| CPU time | 1966.83 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 02:08:54 PM PST 24 |
| Peak memory | 580760 kb |
| Host | smart-70a57781-8f3c-4f32-baf2-4ebd734a9b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269385663 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.4269385663 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.589822858 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 3376550789 ps |
| CPU time | 180.54 seconds |
| Started | Jan 10 01:35:57 PM PST 24 |
| Finished | Jan 10 01:39:09 PM PST 24 |
| Peak memory | 580768 kb |
| Host | smart-b7299b30-c643-429f-9ed1-aac92fc0be37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589822858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.589822858 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3852424476 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 3305541715 ps |
| CPU time | 134.86 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:38:25 PM PST 24 |
| Peak memory | 555144 kb |
| Host | smart-0842e122-63a2-40a0-8bbe-25a0606b9c27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852424476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 3852424476 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1128411370 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 103152902353 ps |
| CPU time | 1933.29 seconds |
| Started | Jan 10 01:35:53 PM PST 24 |
| Finished | Jan 10 02:08:20 PM PST 24 |
| Peak memory | 556020 kb |
| Host | smart-ae6e0067-745c-4845-a1b1-f714cd7eec93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128411370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.1128411370 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1430732056 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 622893928 ps |
| CPU time | 23.74 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:36:32 PM PST 24 |
| Peak memory | 554784 kb |
| Host | smart-e9b74b81-ef29-4fec-85b2-4590f1f557ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430732056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1430732056 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.2485262771 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 1101090469 ps |
| CPU time | 37.04 seconds |
| Started | Jan 10 01:36:08 PM PST 24 |
| Finished | Jan 10 01:36:52 PM PST 24 |
| Peak memory | 554700 kb |
| Host | smart-ced4a7f1-0577-4b6d-a3d1-78f854b5b420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485262771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2485262771 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.900475774 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 281268983 ps |
| CPU time | 11.26 seconds |
| Started | Jan 10 01:35:55 PM PST 24 |
| Finished | Jan 10 01:36:19 PM PST 24 |
| Peak memory | 552732 kb |
| Host | smart-2b3144d5-906e-4e8e-81a7-add59bce0ebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900475774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.900475774 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.3816254851 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 63910360284 ps |
| CPU time | 667.45 seconds |
| Started | Jan 10 01:36:01 PM PST 24 |
| Finished | Jan 10 01:47:19 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-b93c422c-89a1-4413-9ca2-7d2a10711793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816254851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3816254851 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.4085949636 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 50001609111 ps |
| CPU time | 864 seconds |
| Started | Jan 10 01:35:57 PM PST 24 |
| Finished | Jan 10 01:50:33 PM PST 24 |
| Peak memory | 555132 kb |
| Host | smart-163e088e-2487-49a7-9db2-5e9413cc265b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085949636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4085949636 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.1138063167 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 90953178 ps |
| CPU time | 9.57 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:36:18 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-3f21323f-2673-48ec-b8ce-42584f017e5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138063167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.1138063167 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.3091156645 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 569314029 ps |
| CPU time | 40.52 seconds |
| Started | Jan 10 01:36:02 PM PST 24 |
| Finished | Jan 10 01:36:52 PM PST 24 |
| Peak memory | 553888 kb |
| Host | smart-459ab581-33c4-4fb4-99b1-2e4ab9259ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091156645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3091156645 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.3591397950 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 194290324 ps |
| CPU time | 8.42 seconds |
| Started | Jan 10 01:36:07 PM PST 24 |
| Finished | Jan 10 01:36:23 PM PST 24 |
| Peak memory | 552936 kb |
| Host | smart-1d6bb48e-c801-46c5-be31-a34b121fdda2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591397950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3591397950 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.2538549206 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 7077757749 ps |
| CPU time | 71.98 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:37:22 PM PST 24 |
| Peak memory | 552640 kb |
| Host | smart-39637770-01ac-4dac-bcad-47a4c2fcc89f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538549206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2538549206 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.3977976804 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 3245114864 ps |
| CPU time | 55.66 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:37:05 PM PST 24 |
| Peak memory | 552720 kb |
| Host | smart-5dd26b31-65e1-468e-93b6-337a4140f0ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977976804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3977976804 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3446919086 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 52011898 ps |
| CPU time | 5.89 seconds |
| Started | Jan 10 01:36:11 PM PST 24 |
| Finished | Jan 10 01:36:23 PM PST 24 |
| Peak memory | 552980 kb |
| Host | smart-5a2231fd-1299-4d4b-a511-82e2b3f9e516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446919086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .3446919086 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.1724662910 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 10007835667 ps |
| CPU time | 341.78 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:41:50 PM PST 24 |
| Peak memory | 556208 kb |
| Host | smart-8e70022d-5320-4a1b-895c-4ef517d990b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724662910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1724662910 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3533195843 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 8908749881 ps |
| CPU time | 496.28 seconds |
| Started | Jan 10 01:36:08 PM PST 24 |
| Finished | Jan 10 01:44:31 PM PST 24 |
| Peak memory | 557724 kb |
| Host | smart-c1caf4be-69b0-46c3-8755-ae53fc8a48e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533195843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3533195843 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.3898406428 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 2725627130 ps |
| CPU time | 424.64 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:43:15 PM PST 24 |
| Peak memory | 568004 kb |
| Host | smart-c0501934-87d6-4c1c-9c82-c2317172c952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898406428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.3898406428 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2930159097 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 53518527 ps |
| CPU time | 8.08 seconds |
| Started | Jan 10 01:36:11 PM PST 24 |
| Finished | Jan 10 01:36:25 PM PST 24 |
| Peak memory | 553796 kb |
| Host | smart-4c7a9c0c-cab4-4b7a-b015-cab97de96c3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930159097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2930159097 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.891458777 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 587460806 ps |
| CPU time | 43.45 seconds |
| Started | Jan 10 01:41:07 PM PST 24 |
| Finished | Jan 10 01:42:04 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-f8ad0ab8-785f-49fe-928c-f234911ad206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891458777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device. 891458777 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1479165315 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 126585150601 ps |
| CPU time | 2088.13 seconds |
| Started | Jan 10 01:41:03 PM PST 24 |
| Finished | Jan 10 02:15:53 PM PST 24 |
| Peak memory | 555148 kb |
| Host | smart-1b18eb51-f8cd-4111-91d8-d7f021040c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479165315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.1479165315 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3997411599 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 1223268692 ps |
| CPU time | 43.14 seconds |
| Started | Jan 10 01:41:05 PM PST 24 |
| Finished | Jan 10 01:41:52 PM PST 24 |
| Peak memory | 554612 kb |
| Host | smart-895c5678-ba6a-4ea8-81bb-a2b80d77682a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997411599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.3997411599 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.2901920224 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 2354950881 ps |
| CPU time | 79.61 seconds |
| Started | Jan 10 01:41:14 PM PST 24 |
| Finished | Jan 10 01:42:51 PM PST 24 |
| Peak memory | 554988 kb |
| Host | smart-99f5dd29-7577-42d1-889c-240c65db3fc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901920224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2901920224 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.2275567705 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 1912536779 ps |
| CPU time | 67.23 seconds |
| Started | Jan 10 01:41:02 PM PST 24 |
| Finished | Jan 10 01:42:10 PM PST 24 |
| Peak memory | 554772 kb |
| Host | smart-3fff3ab8-dbf1-41d0-85e2-aaa62c1f46da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275567705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.2275567705 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.140023088 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 93243156514 ps |
| CPU time | 1062.8 seconds |
| Started | Jan 10 01:41:06 PM PST 24 |
| Finished | Jan 10 01:59:00 PM PST 24 |
| Peak memory | 554772 kb |
| Host | smart-1034936f-9b23-4380-a339-66497864be1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140023088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.140023088 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.633484269 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 6103228788 ps |
| CPU time | 105.37 seconds |
| Started | Jan 10 01:41:02 PM PST 24 |
| Finished | Jan 10 01:42:49 PM PST 24 |
| Peak memory | 553024 kb |
| Host | smart-869e8333-38e3-4c2f-b55c-d53f05996f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633484269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.633484269 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.2291769480 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 492650886 ps |
| CPU time | 45.17 seconds |
| Started | Jan 10 01:41:03 PM PST 24 |
| Finished | Jan 10 01:41:50 PM PST 24 |
| Peak memory | 553940 kb |
| Host | smart-a79ae392-bf24-4b89-a496-876f74bcdb8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291769480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.2291769480 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.66313407 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 526237801 ps |
| CPU time | 34.71 seconds |
| Started | Jan 10 01:41:05 PM PST 24 |
| Finished | Jan 10 01:41:43 PM PST 24 |
| Peak memory | 554976 kb |
| Host | smart-c3198c4c-5bc4-4c28-9649-2f5532adcdcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66313407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.66313407 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.73396199 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 45723993 ps |
| CPU time | 6.05 seconds |
| Started | Jan 10 01:41:06 PM PST 24 |
| Finished | Jan 10 01:41:24 PM PST 24 |
| Peak memory | 552948 kb |
| Host | smart-dda81dc7-59da-4f8a-bc1c-9be4c0768528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73396199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.73396199 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.4226783164 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 5251827967 ps |
| CPU time | 56.42 seconds |
| Started | Jan 10 01:41:06 PM PST 24 |
| Finished | Jan 10 01:42:15 PM PST 24 |
| Peak memory | 552724 kb |
| Host | smart-6b89aa5f-1073-40d0-a305-0c664c72805f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226783164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.4226783164 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1606362816 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 4286767526 ps |
| CPU time | 70.15 seconds |
| Started | Jan 10 01:41:07 PM PST 24 |
| Finished | Jan 10 01:42:27 PM PST 24 |
| Peak memory | 552992 kb |
| Host | smart-2858437a-e922-4cc3-8923-10764e6a26d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606362816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.1606362816 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.2735573669 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 45491681 ps |
| CPU time | 6.1 seconds |
| Started | Jan 10 01:41:02 PM PST 24 |
| Finished | Jan 10 01:41:10 PM PST 24 |
| Peak memory | 552956 kb |
| Host | smart-d5576d1b-f671-4acf-afbb-e85e77e30251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735573669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.2735573669 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.2001448646 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 2008969516 ps |
| CPU time | 83.86 seconds |
| Started | Jan 10 01:41:04 PM PST 24 |
| Finished | Jan 10 01:42:31 PM PST 24 |
| Peak memory | 554860 kb |
| Host | smart-aa391362-6cbc-490b-83c7-2c8e7b915ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001448646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.2001448646 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.222097189 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 16254076174 ps |
| CPU time | 557.74 seconds |
| Started | Jan 10 01:41:16 PM PST 24 |
| Finished | Jan 10 01:50:50 PM PST 24 |
| Peak memory | 559468 kb |
| Host | smart-d0a05bf0-950a-439b-967c-338c6626835d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222097189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.222097189 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2133078678 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 3254282768 ps |
| CPU time | 560.22 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:50:52 PM PST 24 |
| Peak memory | 558984 kb |
| Host | smart-a517f47d-1ff9-49e0-acc6-220fc778e585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133078678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.2133078678 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1138547137 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 2431716969 ps |
| CPU time | 222.61 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:45:14 PM PST 24 |
| Peak memory | 559068 kb |
| Host | smart-19f23755-9753-43c4-9f9c-114e51226ae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138547137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.1138547137 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.815632210 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 267085622 ps |
| CPU time | 14.59 seconds |
| Started | Jan 10 01:41:16 PM PST 24 |
| Finished | Jan 10 01:41:46 PM PST 24 |
| Peak memory | 553948 kb |
| Host | smart-5da1c1ac-44dc-4d52-8bdb-21b4cb8d08ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815632210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.815632210 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.3227379830 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 2159735137 ps |
| CPU time | 87.14 seconds |
| Started | Jan 10 01:41:19 PM PST 24 |
| Finished | Jan 10 01:42:59 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-63ac45b6-8ddd-4838-b88c-64c7b2196cea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227379830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .3227379830 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.4281861438 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 83647052423 ps |
| CPU time | 1496.71 seconds |
| Started | Jan 10 01:41:18 PM PST 24 |
| Finished | Jan 10 02:06:28 PM PST 24 |
| Peak memory | 556160 kb |
| Host | smart-171528c2-e6e4-4993-8807-7a991032238c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281861438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.4281861438 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.4241511388 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 957284982 ps |
| CPU time | 33.36 seconds |
| Started | Jan 10 01:41:19 PM PST 24 |
| Finished | Jan 10 01:42:05 PM PST 24 |
| Peak memory | 555024 kb |
| Host | smart-6c4c0401-4e26-44c0-963b-0abddebecda3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241511388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.4241511388 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.3372564704 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 423971500 ps |
| CPU time | 38.23 seconds |
| Started | Jan 10 01:41:20 PM PST 24 |
| Finished | Jan 10 01:42:10 PM PST 24 |
| Peak memory | 554732 kb |
| Host | smart-1d6307bb-8dc1-423d-b534-7f6b64d13786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372564704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.3372564704 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.2813801975 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 1626047026 ps |
| CPU time | 55.41 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:42:27 PM PST 24 |
| Peak memory | 555080 kb |
| Host | smart-b674735f-47f5-4ff7-924e-cfe757b17388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813801975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.2813801975 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.1324441023 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 6450295717 ps |
| CPU time | 62.22 seconds |
| Started | Jan 10 01:41:16 PM PST 24 |
| Finished | Jan 10 01:42:34 PM PST 24 |
| Peak memory | 552976 kb |
| Host | smart-36107599-fb03-46d4-8757-3113a71efc4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324441023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1324441023 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.88023076 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 46497486717 ps |
| CPU time | 846.34 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:55:38 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-dbc778d2-420f-4699-b013-2d13d1fcb534 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88023076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.88023076 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.3760310221 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 473356878 ps |
| CPU time | 38.38 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:42:10 PM PST 24 |
| Peak memory | 553928 kb |
| Host | smart-d9cd393d-66de-49a4-ac30-f4964c2c7a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760310221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.3760310221 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.3430352155 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 1606036271 ps |
| CPU time | 52.52 seconds |
| Started | Jan 10 01:41:19 PM PST 24 |
| Finished | Jan 10 01:42:24 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-22692ef8-b2a0-43df-ac6a-667ee865f3af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430352155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.3430352155 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.1630567756 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 222135231 ps |
| CPU time | 9.63 seconds |
| Started | Jan 10 01:41:15 PM PST 24 |
| Finished | Jan 10 01:41:41 PM PST 24 |
| Peak memory | 552512 kb |
| Host | smart-f636e161-0863-4777-a04e-f762eda38917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630567756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.1630567756 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.173538586 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 7068706068 ps |
| CPU time | 76.97 seconds |
| Started | Jan 10 01:41:15 PM PST 24 |
| Finished | Jan 10 01:42:48 PM PST 24 |
| Peak memory | 552584 kb |
| Host | smart-61ed3f41-fa45-4da0-9a4b-b8f770399061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173538586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.173538586 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1590979093 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 5638789682 ps |
| CPU time | 95.8 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:43:08 PM PST 24 |
| Peak memory | 553036 kb |
| Host | smart-aec35bb8-f208-4699-9699-e9488350d70e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590979093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1590979093 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.481650208 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 42421219 ps |
| CPU time | 5.99 seconds |
| Started | Jan 10 01:41:06 PM PST 24 |
| Finished | Jan 10 01:41:15 PM PST 24 |
| Peak memory | 552560 kb |
| Host | smart-cfa42ead-6de9-44a4-ae65-4c9eb4c032f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481650208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays .481650208 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.3996451641 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 3205026653 ps |
| CPU time | 125.57 seconds |
| Started | Jan 10 01:41:20 PM PST 24 |
| Finished | Jan 10 01:43:38 PM PST 24 |
| Peak memory | 556280 kb |
| Host | smart-197c04bc-adf2-478b-9192-dc1c400bd288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996451641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.3996451641 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.2424194250 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 487041661 ps |
| CPU time | 36.88 seconds |
| Started | Jan 10 01:41:16 PM PST 24 |
| Finished | Jan 10 01:42:09 PM PST 24 |
| Peak memory | 554972 kb |
| Host | smart-14d3b780-9462-4e43-b632-540a3278477f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424194250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.2424194250 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.4017089373 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2161450864 ps |
| CPU time | 382.26 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:47:54 PM PST 24 |
| Peak memory | 557936 kb |
| Host | smart-3aa2b832-1732-45ea-9681-f122b3f28c77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017089373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.4017089373 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.1649977316 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 149111103 ps |
| CPU time | 17.02 seconds |
| Started | Jan 10 01:41:19 PM PST 24 |
| Finished | Jan 10 01:41:49 PM PST 24 |
| Peak memory | 554780 kb |
| Host | smart-a1038faf-67ca-4443-b911-0bca72b3e17d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649977316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.1649977316 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.208861950 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 1773534628 ps |
| CPU time | 71.2 seconds |
| Started | Jan 10 01:41:16 PM PST 24 |
| Finished | Jan 10 01:42:43 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-af36d656-bd40-4d40-b76e-a2b5d953d5ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208861950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device. 208861950 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2243055238 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 4252666779 ps |
| CPU time | 71.03 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:42:42 PM PST 24 |
| Peak memory | 553792 kb |
| Host | smart-df22c9aa-2c3a-430c-9aa9-290d5dba1c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243055238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.2243055238 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2958401900 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 472978866 ps |
| CPU time | 19.94 seconds |
| Started | Jan 10 01:41:25 PM PST 24 |
| Finished | Jan 10 01:41:59 PM PST 24 |
| Peak memory | 554984 kb |
| Host | smart-06bfb6cd-d637-440a-9410-2f1ed221cd06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958401900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.2958401900 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.4258801021 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 407814123 ps |
| CPU time | 32.72 seconds |
| Started | Jan 10 01:41:20 PM PST 24 |
| Finished | Jan 10 01:42:05 PM PST 24 |
| Peak memory | 554760 kb |
| Host | smart-19dddcd4-b1d4-4ee2-be21-2ef8e7c5df5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258801021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.4258801021 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1013294532 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2168395916 ps |
| CPU time | 77.08 seconds |
| Started | Jan 10 01:41:15 PM PST 24 |
| Finished | Jan 10 01:42:48 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-5e59e2f6-efe7-43d6-b2b3-3ec42499f8af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013294532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1013294532 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2863107799 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 101638308355 ps |
| CPU time | 1157.16 seconds |
| Started | Jan 10 01:41:16 PM PST 24 |
| Finished | Jan 10 02:00:48 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-00220c70-3d6f-411b-92ed-93c8b97bcf24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863107799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2863107799 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1291805059 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 41529951103 ps |
| CPU time | 723.99 seconds |
| Started | Jan 10 01:41:16 PM PST 24 |
| Finished | Jan 10 01:53:36 PM PST 24 |
| Peak memory | 555100 kb |
| Host | smart-cad84266-7c16-425a-bd98-53b9133ed1b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291805059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1291805059 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.1630140360 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 73027946 ps |
| CPU time | 8.34 seconds |
| Started | Jan 10 01:41:16 PM PST 24 |
| Finished | Jan 10 01:41:40 PM PST 24 |
| Peak memory | 552928 kb |
| Host | smart-f28237ea-d3cb-4dac-b8e3-048ffc27cb35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630140360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.1630140360 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.1348954259 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 2160826461 ps |
| CPU time | 65.54 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:42:37 PM PST 24 |
| Peak memory | 554776 kb |
| Host | smart-a0b46cb8-1147-4b3f-9c8e-00609979b902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348954259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.1348954259 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.1606251623 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 222173289 ps |
| CPU time | 9.26 seconds |
| Started | Jan 10 01:41:20 PM PST 24 |
| Finished | Jan 10 01:41:41 PM PST 24 |
| Peak memory | 552700 kb |
| Host | smart-2108393c-3686-4319-aaea-cdacec4293ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606251623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1606251623 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2820045802 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 7172470859 ps |
| CPU time | 74.09 seconds |
| Started | Jan 10 01:41:16 PM PST 24 |
| Finished | Jan 10 01:42:45 PM PST 24 |
| Peak memory | 552752 kb |
| Host | smart-ab971e50-4dd1-4f6d-94a0-8a8abd452064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820045802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2820045802 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1207313780 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 5637133977 ps |
| CPU time | 97.04 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:43:09 PM PST 24 |
| Peak memory | 552660 kb |
| Host | smart-39caa197-5bca-43d6-bf41-68c8ddce4f98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207313780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1207313780 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.644630480 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 43484782 ps |
| CPU time | 5.67 seconds |
| Started | Jan 10 01:41:17 PM PST 24 |
| Finished | Jan 10 01:41:37 PM PST 24 |
| Peak memory | 552528 kb |
| Host | smart-8a7d38b3-c2cf-42b9-b361-52f5b4fc0a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644630480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays .644630480 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.2091495924 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 6342910545 ps |
| CPU time | 268.02 seconds |
| Started | Jan 10 01:41:27 PM PST 24 |
| Finished | Jan 10 01:46:08 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-a2c76829-6d81-425e-9670-cdfaff20f0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091495924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.2091495924 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.3596445687 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 9261198908 ps |
| CPU time | 288.01 seconds |
| Started | Jan 10 01:41:28 PM PST 24 |
| Finished | Jan 10 01:46:29 PM PST 24 |
| Peak memory | 556232 kb |
| Host | smart-3f697190-d162-49a2-9c45-eed5ded81a3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596445687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.3596445687 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.656623212 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 95439249 ps |
| CPU time | 40.55 seconds |
| Started | Jan 10 01:41:25 PM PST 24 |
| Finished | Jan 10 01:42:19 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-f7fb6a02-f4d7-42c3-9951-6f0966778504 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656623212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.656623212 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1059962990 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 209651134 ps |
| CPU time | 45.47 seconds |
| Started | Jan 10 01:41:25 PM PST 24 |
| Finished | Jan 10 01:42:25 PM PST 24 |
| Peak memory | 556228 kb |
| Host | smart-075a7fd6-8e00-4254-8f1d-37d38e55c6fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059962990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.1059962990 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2441812410 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 274809026 ps |
| CPU time | 14.28 seconds |
| Started | Jan 10 01:41:26 PM PST 24 |
| Finished | Jan 10 01:41:53 PM PST 24 |
| Peak memory | 554780 kb |
| Host | smart-e6a6b26c-765d-48f9-8ad3-247cdc6aa6d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441812410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2441812410 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.3694219264 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 2592612826 ps |
| CPU time | 92.83 seconds |
| Started | Jan 10 01:42:12 PM PST 24 |
| Finished | Jan 10 01:43:46 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-b534c40e-8ab2-4ba1-b15e-aa5370d8f8cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694219264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .3694219264 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1022595288 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 71765324593 ps |
| CPU time | 1276.32 seconds |
| Started | Jan 10 01:42:11 PM PST 24 |
| Finished | Jan 10 02:03:29 PM PST 24 |
| Peak memory | 554884 kb |
| Host | smart-96bcec45-cc45-4c32-8517-cadc44033815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022595288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1022595288 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.4291974777 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 62225167 ps |
| CPU time | 8.78 seconds |
| Started | Jan 10 01:42:11 PM PST 24 |
| Finished | Jan 10 01:42:21 PM PST 24 |
| Peak memory | 554972 kb |
| Host | smart-4ff67883-7956-4a5c-8ddd-445e108824f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291974777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.4291974777 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.391390268 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 958146885 ps |
| CPU time | 32.83 seconds |
| Started | Jan 10 01:42:11 PM PST 24 |
| Finished | Jan 10 01:42:46 PM PST 24 |
| Peak memory | 554900 kb |
| Host | smart-4df92dd7-123d-4830-bfcf-1dea2ede5c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391390268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.391390268 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.3166949935 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1943771416 ps |
| CPU time | 77.06 seconds |
| Started | Jan 10 01:42:23 PM PST 24 |
| Finished | Jan 10 01:43:41 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-dc11b807-363f-4bd7-a39d-a1e84c6b5797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166949935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.3166949935 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.1767796659 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 78971256367 ps |
| CPU time | 872.43 seconds |
| Started | Jan 10 01:42:11 PM PST 24 |
| Finished | Jan 10 01:56:45 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-a7ebe9bd-4985-4629-9981-9f8f424edb98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767796659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.1767796659 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.3922428456 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 5013634845 ps |
| CPU time | 85.39 seconds |
| Started | Jan 10 01:42:11 PM PST 24 |
| Finished | Jan 10 01:43:38 PM PST 24 |
| Peak memory | 553100 kb |
| Host | smart-4c0f21ec-85dc-4cd1-a048-2533194c0736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922428456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.3922428456 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.869349614 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 575437933 ps |
| CPU time | 48.5 seconds |
| Started | Jan 10 01:42:12 PM PST 24 |
| Finished | Jan 10 01:43:01 PM PST 24 |
| Peak memory | 553888 kb |
| Host | smart-d351b064-8a5f-4baa-809f-6fb36e82e82a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869349614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_dela ys.869349614 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.2442454333 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 1968600755 ps |
| CPU time | 55.72 seconds |
| Started | Jan 10 01:42:13 PM PST 24 |
| Finished | Jan 10 01:43:10 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-6663addb-0393-40af-b6d5-2e8b1ee8e602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442454333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2442454333 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.2814015877 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 227355941 ps |
| CPU time | 9.34 seconds |
| Started | Jan 10 01:41:28 PM PST 24 |
| Finished | Jan 10 01:41:50 PM PST 24 |
| Peak memory | 552484 kb |
| Host | smart-5dca3376-7cd0-40a1-9ba8-54684a4bcca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814015877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2814015877 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3297906520 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 8331462799 ps |
| CPU time | 78.99 seconds |
| Started | Jan 10 01:41:28 PM PST 24 |
| Finished | Jan 10 01:42:59 PM PST 24 |
| Peak memory | 552728 kb |
| Host | smart-b5d1b50f-a3cb-4132-946f-5482e2a9b73f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297906520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.3297906520 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1427568394 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 4320603724 ps |
| CPU time | 69.3 seconds |
| Started | Jan 10 01:41:26 PM PST 24 |
| Finished | Jan 10 01:42:49 PM PST 24 |
| Peak memory | 553064 kb |
| Host | smart-cc03960a-110b-4590-adaf-092a1a31bfcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427568394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1427568394 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2401779108 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 45857005 ps |
| CPU time | 5.94 seconds |
| Started | Jan 10 01:41:27 PM PST 24 |
| Finished | Jan 10 01:41:46 PM PST 24 |
| Peak memory | 552888 kb |
| Host | smart-8d9113c1-ebf5-403a-af1f-c70583d47406 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401779108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.2401779108 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.3690386759 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 5712666324 ps |
| CPU time | 209.74 seconds |
| Started | Jan 10 01:42:25 PM PST 24 |
| Finished | Jan 10 01:45:57 PM PST 24 |
| Peak memory | 556220 kb |
| Host | smart-dc88ae06-574b-466a-8121-8b6d2affc2b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690386759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.3690386759 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1316589833 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 2351845015 ps |
| CPU time | 191.4 seconds |
| Started | Jan 10 01:42:28 PM PST 24 |
| Finished | Jan 10 01:45:41 PM PST 24 |
| Peak memory | 556000 kb |
| Host | smart-76d86dbf-4997-4c15-aa60-8d582703c11c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316589833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1316589833 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1686128444 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3304602323 ps |
| CPU time | 217.13 seconds |
| Started | Jan 10 01:42:39 PM PST 24 |
| Finished | Jan 10 01:46:18 PM PST 24 |
| Peak memory | 556004 kb |
| Host | smart-9c731c5e-ee71-47f0-940b-e1d6f2e9456c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686128444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.1686128444 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.3820691902 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 346879022 ps |
| CPU time | 78.8 seconds |
| Started | Jan 10 01:42:19 PM PST 24 |
| Finished | Jan 10 01:43:39 PM PST 24 |
| Peak memory | 556384 kb |
| Host | smart-98743096-a44c-4128-bf74-46d97d01f72a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820691902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.3820691902 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.3973664342 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 242911975 ps |
| CPU time | 24.9 seconds |
| Started | Jan 10 01:42:29 PM PST 24 |
| Finished | Jan 10 01:42:55 PM PST 24 |
| Peak memory | 554984 kb |
| Host | smart-9e3528b9-ce51-43c1-8772-309f799352a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973664342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.3973664342 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.481861471 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 73721403 ps |
| CPU time | 6.8 seconds |
| Started | Jan 10 01:42:44 PM PST 24 |
| Finished | Jan 10 01:42:53 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-7cc573b0-6e2c-4a1e-8acc-2d8d79a1c4bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481861471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device. 481861471 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2809962808 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 79889152265 ps |
| CPU time | 1436.75 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 02:06:41 PM PST 24 |
| Peak memory | 555080 kb |
| Host | smart-492fb794-82cd-4e3d-bbae-70967e7a37db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809962808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.2809962808 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1294202128 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 42121498 ps |
| CPU time | 7.35 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:42:51 PM PST 24 |
| Peak memory | 552904 kb |
| Host | smart-68185583-8a77-4c63-88c9-ee995b5fb99a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294202128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.1294202128 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.3439574825 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 970292452 ps |
| CPU time | 30.39 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:43:14 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-ebd71392-eda0-4d2f-bd6f-80f6dbddb0be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439574825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.3439574825 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.1342012839 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 393244910 ps |
| CPU time | 16.3 seconds |
| Started | Jan 10 01:42:26 PM PST 24 |
| Finished | Jan 10 01:42:44 PM PST 24 |
| Peak memory | 554988 kb |
| Host | smart-ebafd2df-4370-4ed2-b53c-ecb75f10a38a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342012839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.1342012839 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3167299512 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 67588199979 ps |
| CPU time | 742.14 seconds |
| Started | Jan 10 01:42:29 PM PST 24 |
| Finished | Jan 10 01:54:53 PM PST 24 |
| Peak memory | 554000 kb |
| Host | smart-e7a03297-e19f-4c45-a3d5-aac683d42132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167299512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.3167299512 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.3926084579 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 8982972930 ps |
| CPU time | 158.5 seconds |
| Started | Jan 10 01:42:27 PM PST 24 |
| Finished | Jan 10 01:45:07 PM PST 24 |
| Peak memory | 555120 kb |
| Host | smart-455ba0b9-2574-4dc3-8868-6f2ba4135a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926084579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.3926084579 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.316267782 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 207448012 ps |
| CPU time | 20.03 seconds |
| Started | Jan 10 01:42:27 PM PST 24 |
| Finished | Jan 10 01:42:49 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-1ae5934d-4cdb-411f-94ce-41fbc7b5e5fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316267782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_dela ys.316267782 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.1539291922 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 2524549037 ps |
| CPU time | 75.98 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:44:03 PM PST 24 |
| Peak memory | 554844 kb |
| Host | smart-6eee34e1-7885-4fe5-9b77-fc0a1698d105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539291922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1539291922 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.1150652687 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 175254779 ps |
| CPU time | 8.34 seconds |
| Started | Jan 10 01:42:19 PM PST 24 |
| Finished | Jan 10 01:42:29 PM PST 24 |
| Peak memory | 552512 kb |
| Host | smart-394fd691-af35-486a-a1a4-405c4a109afa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150652687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.1150652687 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.3644735247 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 5308159530 ps |
| CPU time | 54.94 seconds |
| Started | Jan 10 01:42:19 PM PST 24 |
| Finished | Jan 10 01:43:15 PM PST 24 |
| Peak memory | 552536 kb |
| Host | smart-aebcd079-c7b5-43ae-9280-c95af8ca7d4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644735247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.3644735247 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.1044241920 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 4261962856 ps |
| CPU time | 73.22 seconds |
| Started | Jan 10 01:42:33 PM PST 24 |
| Finished | Jan 10 01:43:47 PM PST 24 |
| Peak memory | 552768 kb |
| Host | smart-2b34aa81-52ed-4c0f-9f91-211558d092c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044241920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.1044241920 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1370677078 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 47365505 ps |
| CPU time | 6.03 seconds |
| Started | Jan 10 01:42:25 PM PST 24 |
| Finished | Jan 10 01:42:33 PM PST 24 |
| Peak memory | 552628 kb |
| Host | smart-ceb01579-f04e-43c7-b816-24ce566bc270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370677078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1370677078 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.2042062410 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 1886529953 ps |
| CPU time | 139.63 seconds |
| Started | Jan 10 01:42:39 PM PST 24 |
| Finished | Jan 10 01:44:59 PM PST 24 |
| Peak memory | 556132 kb |
| Host | smart-d79da4c8-a044-41b0-ad2d-19dd48517716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042062410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.2042062410 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.1284936025 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 6193505160 ps |
| CPU time | 213.72 seconds |
| Started | Jan 10 01:42:43 PM PST 24 |
| Finished | Jan 10 01:46:18 PM PST 24 |
| Peak memory | 556280 kb |
| Host | smart-89d57cf2-461b-4096-b128-ef1d5a40e9b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284936025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.1284936025 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2621049506 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 11456285838 ps |
| CPU time | 525.2 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:51:29 PM PST 24 |
| Peak memory | 558812 kb |
| Host | smart-754747f3-504e-4993-b9eb-339e7ac07bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621049506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.2621049506 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1279293428 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 239224003 ps |
| CPU time | 135.84 seconds |
| Started | Jan 10 01:42:44 PM PST 24 |
| Finished | Jan 10 01:45:01 PM PST 24 |
| Peak memory | 557088 kb |
| Host | smart-804208b6-092f-4dc0-bbce-79c495dfea5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279293428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.1279293428 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.2704203293 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 394144788 ps |
| CPU time | 18.37 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:43:01 PM PST 24 |
| Peak memory | 554816 kb |
| Host | smart-f61ae6ce-ddc9-439b-92cc-411ce843be28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704203293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.2704203293 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.3089682189 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 462357853 ps |
| CPU time | 32.57 seconds |
| Started | Jan 10 01:42:12 PM PST 24 |
| Finished | Jan 10 01:42:46 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-e8a17d73-1a6a-4a9a-93e6-65bfd6ffd69f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089682189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .3089682189 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3857699698 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 2781243615 ps |
| CPU time | 47.76 seconds |
| Started | Jan 10 01:42:13 PM PST 24 |
| Finished | Jan 10 01:43:03 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-e881b239-e1c4-48f4-b612-a9d342208e39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857699698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.3857699698 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3130569375 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 893966851 ps |
| CPU time | 34.63 seconds |
| Started | Jan 10 01:42:12 PM PST 24 |
| Finished | Jan 10 01:42:48 PM PST 24 |
| Peak memory | 554972 kb |
| Host | smart-96f91358-50d5-494d-9e88-1d569b30d847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130569375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.3130569375 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.1166243139 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 351565725 ps |
| CPU time | 29.96 seconds |
| Started | Jan 10 01:42:16 PM PST 24 |
| Finished | Jan 10 01:42:48 PM PST 24 |
| Peak memory | 554736 kb |
| Host | smart-1d45278b-a118-48dd-b8a9-bdf6022a53fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166243139 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1166243139 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.2161648884 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 273443937 ps |
| CPU time | 22.27 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:43:10 PM PST 24 |
| Peak memory | 554948 kb |
| Host | smart-dfd2493c-866f-4be8-a73d-27bfdf10194d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161648884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.2161648884 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.3474116465 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 46363848634 ps |
| CPU time | 567.48 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:52:12 PM PST 24 |
| Peak memory | 554852 kb |
| Host | smart-d0bfd31e-b2ce-4f5f-9743-67ada6c4c672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474116465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.3474116465 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.360657364 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 4052066945 ps |
| CPU time | 65.67 seconds |
| Started | Jan 10 01:42:14 PM PST 24 |
| Finished | Jan 10 01:43:21 PM PST 24 |
| Peak memory | 553036 kb |
| Host | smart-554d034d-0682-4348-876b-6208f24ebebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360657364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.360657364 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1224415933 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 547262984 ps |
| CPU time | 46.15 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:43:29 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-b0c8198d-6e0a-450f-975c-53445c0da04a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224415933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.1224415933 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.1783029415 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 2243738186 ps |
| CPU time | 76.74 seconds |
| Started | Jan 10 01:42:11 PM PST 24 |
| Finished | Jan 10 01:43:29 PM PST 24 |
| Peak memory | 554112 kb |
| Host | smart-4410a922-2879-4112-8a49-8b91686cbb14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783029415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.1783029415 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.852154924 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 262883431 ps |
| CPU time | 10.23 seconds |
| Started | Jan 10 01:42:37 PM PST 24 |
| Finished | Jan 10 01:42:49 PM PST 24 |
| Peak memory | 552976 kb |
| Host | smart-c4decf9a-8269-4c81-b3c2-e0a58986e761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852154924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.852154924 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2079927436 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 6233263667 ps |
| CPU time | 65.33 seconds |
| Started | Jan 10 01:42:39 PM PST 24 |
| Finished | Jan 10 01:43:46 PM PST 24 |
| Peak memory | 553040 kb |
| Host | smart-996dde69-2fc5-4cf3-9b4b-02324a4e2e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079927436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2079927436 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2958851882 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 5018506768 ps |
| CPU time | 86.88 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:44:11 PM PST 24 |
| Peak memory | 552736 kb |
| Host | smart-6224ed0b-44e8-4d20-a701-8415d944929f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958851882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.2958851882 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2501568795 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 52741573 ps |
| CPU time | 5.91 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:42:49 PM PST 24 |
| Peak memory | 552920 kb |
| Host | smart-c6290e1e-0806-4eab-be89-f6516502c00e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501568795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.2501568795 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.768439958 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 4561150286 ps |
| CPU time | 155.66 seconds |
| Started | Jan 10 01:42:14 PM PST 24 |
| Finished | Jan 10 01:44:51 PM PST 24 |
| Peak memory | 556028 kb |
| Host | smart-e6fa1016-6e84-46ca-a656-bd2ad7a52618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768439958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.768439958 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.260339631 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 11521592468 ps |
| CPU time | 385.82 seconds |
| Started | Jan 10 01:42:14 PM PST 24 |
| Finished | Jan 10 01:48:42 PM PST 24 |
| Peak memory | 556980 kb |
| Host | smart-51ee3ebe-a017-43e2-89f5-d5fb1b6342cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260339631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.260339631 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.170678871 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 129156843 ps |
| CPU time | 31.27 seconds |
| Started | Jan 10 01:42:23 PM PST 24 |
| Finished | Jan 10 01:42:56 PM PST 24 |
| Peak memory | 555392 kb |
| Host | smart-1b10df74-5469-4d10-9f59-97b5754aabce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170678871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_ with_rand_reset.170678871 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.624019573 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 2217666257 ps |
| CPU time | 312.2 seconds |
| Started | Jan 10 01:42:14 PM PST 24 |
| Finished | Jan 10 01:47:28 PM PST 24 |
| Peak memory | 559868 kb |
| Host | smart-88d35eef-babf-4dee-bae2-f819573928bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624019573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_reset_error.624019573 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.1307688837 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 141598603 ps |
| CPU time | 16.43 seconds |
| Started | Jan 10 01:42:17 PM PST 24 |
| Finished | Jan 10 01:42:35 PM PST 24 |
| Peak memory | 553876 kb |
| Host | smart-b4bcb751-c4f2-4bee-9a39-50e0c5ae1128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307688837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.1307688837 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2011513230 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 708051348 ps |
| CPU time | 54.01 seconds |
| Started | Jan 10 01:42:24 PM PST 24 |
| Finished | Jan 10 01:43:21 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-aa8d9a7c-fda1-48bd-845d-4dda30bf7220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011513230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .2011513230 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.2677557825 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 153107386832 ps |
| CPU time | 2693 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 02:27:37 PM PST 24 |
| Peak memory | 555968 kb |
| Host | smart-591f275d-7e64-4a18-ab46-04adedf218ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677557825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.2677557825 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.269783673 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 973607797 ps |
| CPU time | 36.7 seconds |
| Started | Jan 10 01:42:14 PM PST 24 |
| Finished | Jan 10 01:42:52 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-591fa024-1eec-4a91-b10a-7c2261f27e30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269783673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr .269783673 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.888550394 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 817421577 ps |
| CPU time | 28.62 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:43:13 PM PST 24 |
| Peak memory | 554624 kb |
| Host | smart-df867094-df3a-4093-b8c3-3cdc9ce77ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888550394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.888550394 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.1638987075 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 1609837012 ps |
| CPU time | 58.03 seconds |
| Started | Jan 10 01:42:14 PM PST 24 |
| Finished | Jan 10 01:43:14 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-dd9c3e72-92e8-4abe-9a69-b0f9075a9e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638987075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.1638987075 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1695062285 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 31228210732 ps |
| CPU time | 327.6 seconds |
| Started | Jan 10 01:42:15 PM PST 24 |
| Finished | Jan 10 01:47:45 PM PST 24 |
| Peak memory | 554848 kb |
| Host | smart-1b2025c3-da07-4106-ba01-0cece4be32c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695062285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1695062285 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.193708132 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 41935424730 ps |
| CPU time | 698.36 seconds |
| Started | Jan 10 01:42:13 PM PST 24 |
| Finished | Jan 10 01:53:53 PM PST 24 |
| Peak memory | 555160 kb |
| Host | smart-b9cac9ad-ce45-4f37-b439-774f4718cb6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193708132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.193708132 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.914071997 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 368060969 ps |
| CPU time | 30.87 seconds |
| Started | Jan 10 01:42:11 PM PST 24 |
| Finished | Jan 10 01:42:44 PM PST 24 |
| Peak memory | 554712 kb |
| Host | smart-59bb9ffd-9746-4dce-aa3c-ab9d459c460e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914071997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_dela ys.914071997 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.3368969223 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 241172212 ps |
| CPU time | 17.9 seconds |
| Started | Jan 10 01:42:20 PM PST 24 |
| Finished | Jan 10 01:42:39 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-6d1a84f1-2b75-49ed-9322-b880939b6964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368969223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3368969223 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.3991370615 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 169229287 ps |
| CPU time | 8.18 seconds |
| Started | Jan 10 01:42:13 PM PST 24 |
| Finished | Jan 10 01:42:23 PM PST 24 |
| Peak memory | 552608 kb |
| Host | smart-b3c8eb02-5a22-47db-8bb4-dbe3e9b7a956 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991370615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3991370615 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.4066493573 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 8198511050 ps |
| CPU time | 86.41 seconds |
| Started | Jan 10 01:42:24 PM PST 24 |
| Finished | Jan 10 01:43:53 PM PST 24 |
| Peak memory | 552652 kb |
| Host | smart-711253ca-e3ee-49fb-bdb9-1f208e46157a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066493573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.4066493573 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2812884895 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 3353065884 ps |
| CPU time | 55.66 seconds |
| Started | Jan 10 01:42:11 PM PST 24 |
| Finished | Jan 10 01:43:08 PM PST 24 |
| Peak memory | 552984 kb |
| Host | smart-1771af88-efdf-44be-8eb2-7a49427c3fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812884895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2812884895 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3894933809 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 50982563 ps |
| CPU time | 6.21 seconds |
| Started | Jan 10 01:42:14 PM PST 24 |
| Finished | Jan 10 01:42:22 PM PST 24 |
| Peak memory | 552604 kb |
| Host | smart-b7ef1520-40ba-48e1-b9b7-298e5b8482e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894933809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.3894933809 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.1182104056 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 11957095721 ps |
| CPU time | 445.76 seconds |
| Started | Jan 10 01:42:26 PM PST 24 |
| Finished | Jan 10 01:49:53 PM PST 24 |
| Peak memory | 558268 kb |
| Host | smart-8a56b4e0-aff7-4458-93e1-324957a3ead3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182104056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1182104056 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.1472710840 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2068919858 ps |
| CPU time | 149.21 seconds |
| Started | Jan 10 01:42:23 PM PST 24 |
| Finished | Jan 10 01:44:54 PM PST 24 |
| Peak memory | 555960 kb |
| Host | smart-d30de662-5f2e-4bd5-8789-3f8c4e7ccdf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472710840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.1472710840 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.929071168 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 5164165925 ps |
| CPU time | 337.31 seconds |
| Started | Jan 10 01:42:14 PM PST 24 |
| Finished | Jan 10 01:47:54 PM PST 24 |
| Peak memory | 558584 kb |
| Host | smart-2373a29e-6beb-425c-ad84-99ca047b1ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929071168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_ with_rand_reset.929071168 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3867149182 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 329808098 ps |
| CPU time | 87.47 seconds |
| Started | Jan 10 01:42:25 PM PST 24 |
| Finished | Jan 10 01:43:54 PM PST 24 |
| Peak memory | 556172 kb |
| Host | smart-b0130a32-6909-48d2-a249-66871801b8aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867149182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.3867149182 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.1234391395 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 763497986 ps |
| CPU time | 30.98 seconds |
| Started | Jan 10 01:42:14 PM PST 24 |
| Finished | Jan 10 01:42:47 PM PST 24 |
| Peak memory | 554832 kb |
| Host | smart-827805e8-2a3b-4b77-bebb-894597c5b70b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234391395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.1234391395 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.2468052459 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 1060767551 ps |
| CPU time | 72.77 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:43:56 PM PST 24 |
| Peak memory | 555012 kb |
| Host | smart-3b1591e0-7f84-4442-909a-885be3a4b257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468052459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .2468052459 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.4285386125 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 86994007561 ps |
| CPU time | 1391.96 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 02:05:56 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-e8099873-f7d9-4149-9f2c-488c9cd168c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285386125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.4285386125 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3329919471 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 277577454 ps |
| CPU time | 30.08 seconds |
| Started | Jan 10 01:42:44 PM PST 24 |
| Finished | Jan 10 01:43:16 PM PST 24 |
| Peak memory | 554740 kb |
| Host | smart-b1c2fa2b-5790-48a1-b5c9-9e79d84822c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329919471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.3329919471 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.1021037954 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 469925456 ps |
| CPU time | 35.9 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:43:20 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-917bda23-381b-4683-8f2c-bc50a1ac74ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021037954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.1021037954 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.3830934751 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 978035444 ps |
| CPU time | 40.85 seconds |
| Started | Jan 10 01:42:24 PM PST 24 |
| Finished | Jan 10 01:43:08 PM PST 24 |
| Peak memory | 554652 kb |
| Host | smart-95ac6868-9de2-4c4d-af5a-1dec00e49001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830934751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.3830934751 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.2681296611 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 35367140633 ps |
| CPU time | 402.61 seconds |
| Started | Jan 10 01:42:40 PM PST 24 |
| Finished | Jan 10 01:49:24 PM PST 24 |
| Peak memory | 555172 kb |
| Host | smart-39ed0450-853b-4c19-a497-4153d3e83dfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681296611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.2681296611 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.3023401490 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 26790504341 ps |
| CPU time | 468.26 seconds |
| Started | Jan 10 01:42:37 PM PST 24 |
| Finished | Jan 10 01:50:26 PM PST 24 |
| Peak memory | 554824 kb |
| Host | smart-52c3dfcb-5068-48b4-8e1e-ab49b8703537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023401490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.3023401490 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3913886757 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 450738551 ps |
| CPU time | 43.34 seconds |
| Started | Jan 10 01:42:38 PM PST 24 |
| Finished | Jan 10 01:43:22 PM PST 24 |
| Peak memory | 553948 kb |
| Host | smart-e6304237-e70e-4596-aa1c-98fd1fd8027e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913886757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.3913886757 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.2460135596 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 40979974 ps |
| CPU time | 5.85 seconds |
| Started | Jan 10 01:42:43 PM PST 24 |
| Finished | Jan 10 01:42:51 PM PST 24 |
| Peak memory | 552728 kb |
| Host | smart-5975330c-47e5-4d61-a620-3d0c537f3be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460135596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.2460135596 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.1727043113 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 195613398 ps |
| CPU time | 8.81 seconds |
| Started | Jan 10 01:42:40 PM PST 24 |
| Finished | Jan 10 01:42:51 PM PST 24 |
| Peak memory | 552932 kb |
| Host | smart-19567c27-f068-4b10-ad11-a6ef0e6514e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727043113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.1727043113 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.447540509 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 5886777140 ps |
| CPU time | 61.17 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:43:44 PM PST 24 |
| Peak memory | 552744 kb |
| Host | smart-e19ac226-00d6-42ad-91ca-79a8c5ae4014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447540509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.447540509 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2184581219 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 5815682227 ps |
| CPU time | 92.53 seconds |
| Started | Jan 10 01:42:26 PM PST 24 |
| Finished | Jan 10 01:44:00 PM PST 24 |
| Peak memory | 552728 kb |
| Host | smart-b1e49ed8-9524-4cb4-9d93-63ab90789fac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184581219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2184581219 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2774570817 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 54072098 ps |
| CPU time | 6.71 seconds |
| Started | Jan 10 01:42:27 PM PST 24 |
| Finished | Jan 10 01:42:35 PM PST 24 |
| Peak memory | 552616 kb |
| Host | smart-eeccaef8-29d2-4171-8d82-9f0c9b8e05a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774570817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.2774570817 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.1698812775 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 21475585020 ps |
| CPU time | 861.93 seconds |
| Started | Jan 10 01:42:43 PM PST 24 |
| Finished | Jan 10 01:57:07 PM PST 24 |
| Peak memory | 558512 kb |
| Host | smart-97d6a16a-d78e-4ae6-bd3c-4772e5054d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698812775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.1698812775 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2356964254 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 8076102943 ps |
| CPU time | 250.56 seconds |
| Started | Jan 10 01:42:44 PM PST 24 |
| Finished | Jan 10 01:46:56 PM PST 24 |
| Peak memory | 556244 kb |
| Host | smart-66571239-081b-4c88-8d27-ac8d6e26719f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356964254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2356964254 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.934103324 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 4731315453 ps |
| CPU time | 248.54 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:46:52 PM PST 24 |
| Peak memory | 556880 kb |
| Host | smart-3308e0d9-8a02-4786-8556-5da0df04b534 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934103324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_ with_rand_reset.934103324 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.4175625757 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 79464208 ps |
| CPU time | 13.47 seconds |
| Started | Jan 10 01:42:40 PM PST 24 |
| Finished | Jan 10 01:42:55 PM PST 24 |
| Peak memory | 554904 kb |
| Host | smart-8e551c26-11b6-449e-a1a8-1989883daaba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175625757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.4175625757 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.3421012166 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1098616052 ps |
| CPU time | 44.69 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:43:29 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-8899ad23-10b1-4558-b6f1-ee0a0a3694aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421012166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.3421012166 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.4257558198 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 1798510816 ps |
| CPU time | 69.84 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:43:52 PM PST 24 |
| Peak memory | 554984 kb |
| Host | smart-58116a05-d2ea-4d0d-804d-8cb1c7ab9e13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257558198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .4257558198 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3356829744 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 67303091636 ps |
| CPU time | 1288.72 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 02:04:19 PM PST 24 |
| Peak memory | 554824 kb |
| Host | smart-f8746e71-fbff-48cc-8038-7fe81f83e295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356829744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.3356829744 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2252419327 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 842988804 ps |
| CPU time | 29.43 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:43:19 PM PST 24 |
| Peak memory | 555024 kb |
| Host | smart-c23b149f-1376-4e43-9a05-a9c013b6646a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252419327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.2252419327 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.3241031895 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 1334103705 ps |
| CPU time | 42.85 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:43:32 PM PST 24 |
| Peak memory | 555024 kb |
| Host | smart-ed957d24-30bb-445f-ac59-f8331455e857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241031895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3241031895 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.2837378948 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1204683692 ps |
| CPU time | 45.92 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:43:29 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-c67e309f-ce36-4b14-8e58-1820f56fbcc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837378948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.2837378948 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.4123194999 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 38457412336 ps |
| CPU time | 448.63 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:50:13 PM PST 24 |
| Peak memory | 554800 kb |
| Host | smart-358761a3-7d61-4cfe-8401-a20c5b08fb73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123194999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.4123194999 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1903969945 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 34615346800 ps |
| CPU time | 556.93 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:52:05 PM PST 24 |
| Peak memory | 555100 kb |
| Host | smart-97bcc3f4-c320-4bf4-95d2-547f34165b77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903969945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1903969945 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.460796235 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 283472075 ps |
| CPU time | 25.49 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:43:13 PM PST 24 |
| Peak memory | 554944 kb |
| Host | smart-185719f7-3ceb-4faf-9189-1a40cc129904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460796235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_dela ys.460796235 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.4067900424 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2152580715 ps |
| CPU time | 55.96 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:43:45 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-f93799f5-844d-425f-b5d9-adb2ad1f8921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067900424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.4067900424 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.1059932061 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 35526636 ps |
| CPU time | 5.4 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:42:55 PM PST 24 |
| Peak memory | 552556 kb |
| Host | smart-f32537d2-9206-4cb4-9197-e2e0d679bed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059932061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.1059932061 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.4155529968 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 8400808455 ps |
| CPU time | 87.69 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:44:15 PM PST 24 |
| Peak memory | 552648 kb |
| Host | smart-f40a67d1-a4db-4ea0-b62e-cc6abc35074d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155529968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.4155529968 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.760035472 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 6536857096 ps |
| CPU time | 109.36 seconds |
| Started | Jan 10 01:42:44 PM PST 24 |
| Finished | Jan 10 01:44:35 PM PST 24 |
| Peak memory | 553020 kb |
| Host | smart-878f2219-a4c6-435c-87c4-e4fda2d1473b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760035472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.760035472 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1053508634 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 42054803 ps |
| CPU time | 5.52 seconds |
| Started | Jan 10 01:42:44 PM PST 24 |
| Finished | Jan 10 01:42:51 PM PST 24 |
| Peak memory | 552660 kb |
| Host | smart-846515b7-64a9-4c8d-8b2d-833f005eed3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053508634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.1053508634 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.4282499920 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 408602084 ps |
| CPU time | 39.51 seconds |
| Started | Jan 10 01:42:48 PM PST 24 |
| Finished | Jan 10 01:43:31 PM PST 24 |
| Peak memory | 556064 kb |
| Host | smart-60c0e245-8168-4a40-8dbf-230917f33962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282499920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.4282499920 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.2555199820 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 3505454752 ps |
| CPU time | 264.48 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:47:14 PM PST 24 |
| Peak memory | 556440 kb |
| Host | smart-63de7a9d-ff96-4e4b-8b60-ea38bbadda48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555199820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.2555199820 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1777151926 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 6070882902 ps |
| CPU time | 409.05 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:49:39 PM PST 24 |
| Peak memory | 558124 kb |
| Host | smart-93ec9acf-81ba-46ad-8d78-0b7591be5170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777151926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.1777151926 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1609314433 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2142415560 ps |
| CPU time | 161.4 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:45:30 PM PST 24 |
| Peak memory | 557684 kb |
| Host | smart-e5740203-d712-4d81-85c7-9046530f4333 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609314433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1609314433 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3137588998 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 1372824504 ps |
| CPU time | 55 seconds |
| Started | Jan 10 01:42:49 PM PST 24 |
| Finished | Jan 10 01:43:47 PM PST 24 |
| Peak memory | 554988 kb |
| Host | smart-e5179443-e7ae-4334-99e2-688c7a2f8756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137588998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3137588998 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.1887619628 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 695188581 ps |
| CPU time | 22.75 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:43:10 PM PST 24 |
| Peak memory | 553716 kb |
| Host | smart-0fc0f4d6-93f4-42b3-8582-c6166df9553e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887619628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .1887619628 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.601437898 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 53886796020 ps |
| CPU time | 945.11 seconds |
| Started | Jan 10 01:42:43 PM PST 24 |
| Finished | Jan 10 01:58:30 PM PST 24 |
| Peak memory | 555884 kb |
| Host | smart-989d2bec-a350-4cd6-896f-acdacc605b2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601437898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_d evice_slow_rsp.601437898 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.2157501156 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 847825874 ps |
| CPU time | 31.37 seconds |
| Started | Jan 10 01:42:49 PM PST 24 |
| Finished | Jan 10 01:43:24 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-55b2e276-2af3-4312-930e-959f8f57f354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157501156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.2157501156 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.894648716 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 419204466 ps |
| CPU time | 34.53 seconds |
| Started | Jan 10 01:42:49 PM PST 24 |
| Finished | Jan 10 01:43:27 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-1fada115-d0a4-4880-9332-de0bd6c83bcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894648716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.894648716 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.179164438 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 663459799 ps |
| CPU time | 26.64 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:43:16 PM PST 24 |
| Peak memory | 554800 kb |
| Host | smart-329483f2-9f93-405f-b18f-d75ea0553438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179164438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.179164438 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.219349000 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 55928717617 ps |
| CPU time | 978 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:59:07 PM PST 24 |
| Peak memory | 554844 kb |
| Host | smart-0daca734-2717-462c-8cbb-b2a3c9fb44f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219349000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.219349000 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.788534380 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 128558160 ps |
| CPU time | 12.17 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:43:01 PM PST 24 |
| Peak memory | 554728 kb |
| Host | smart-e6e8fec5-b95e-480e-83d2-4bfaabc36d8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788534380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela ys.788534380 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.1525227774 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 992737612 ps |
| CPU time | 28.91 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:43:20 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-922ebd0e-9d8e-4681-aa91-767f2be83655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525227774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1525227774 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.1077526754 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 55805053 ps |
| CPU time | 6.85 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:42:55 PM PST 24 |
| Peak memory | 552532 kb |
| Host | smart-ea9443c2-6104-4284-b772-e8cac756ceaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077526754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.1077526754 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2132353459 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 8545051849 ps |
| CPU time | 87.63 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:44:14 PM PST 24 |
| Peak memory | 552600 kb |
| Host | smart-b75d60fe-9541-4098-bf7a-1d50da5909c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132353459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.2132353459 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3733276866 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 4043101932 ps |
| CPU time | 69.99 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:43:59 PM PST 24 |
| Peak memory | 552708 kb |
| Host | smart-4280d759-8a86-4d49-82b1-72f1efa6b8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733276866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3733276866 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3804539645 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 48244785 ps |
| CPU time | 5.94 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:42:54 PM PST 24 |
| Peak memory | 552924 kb |
| Host | smart-fc3bb175-9896-4578-b567-f23b16453e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804539645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.3804539645 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.2590393331 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 105444077 ps |
| CPU time | 8.63 seconds |
| Started | Jan 10 01:42:49 PM PST 24 |
| Finished | Jan 10 01:43:01 PM PST 24 |
| Peak memory | 552676 kb |
| Host | smart-c006e19d-1ca2-40dd-8aba-cd08d57ddc95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590393331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.2590393331 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.1437757327 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 7031549744 ps |
| CPU time | 232.15 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:46:39 PM PST 24 |
| Peak memory | 555884 kb |
| Host | smart-c3ad1833-454e-4233-9753-0aacf2bdde8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437757327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.1437757327 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.982192313 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 6128977150 ps |
| CPU time | 362.84 seconds |
| Started | Jan 10 01:42:49 PM PST 24 |
| Finished | Jan 10 01:48:55 PM PST 24 |
| Peak memory | 557220 kb |
| Host | smart-d6039bb9-4d05-41e3-a844-bc6e22ea2ec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982192313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_ with_rand_reset.982192313 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3420694784 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 6516575210 ps |
| CPU time | 397.72 seconds |
| Started | Jan 10 01:42:57 PM PST 24 |
| Finished | Jan 10 01:49:36 PM PST 24 |
| Peak memory | 559888 kb |
| Host | smart-842ade6a-d010-4bd5-9c2a-ec93d7436908 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420694784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.3420694784 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.1699860239 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1102943199 ps |
| CPU time | 40.88 seconds |
| Started | Jan 10 01:42:48 PM PST 24 |
| Finished | Jan 10 01:43:33 PM PST 24 |
| Peak memory | 554760 kb |
| Host | smart-e58e4682-88b4-48ec-bcbc-aefe2a342006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699860239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.1699860239 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.3560192361 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 4176918561 ps |
| CPU time | 184.91 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:39:15 PM PST 24 |
| Peak memory | 612440 kb |
| Host | smart-861d42bb-b529-4b83-b035-944bf2aa91b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560192361 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.3560192361 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.3612217561 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 5202047248 ps |
| CPU time | 419.85 seconds |
| Started | Jan 10 01:36:07 PM PST 24 |
| Finished | Jan 10 01:43:14 PM PST 24 |
| Peak memory | 580828 kb |
| Host | smart-f62a7c2f-dfcd-4804-85e6-f6ed5161f34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612217561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3612217561 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.1629021849 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 15743793720 ps |
| CPU time | 2224.16 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 02:13:13 PM PST 24 |
| Peak memory | 580856 kb |
| Host | smart-1bb21fd5-67bc-4a00-af5c-2a0f26a04677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629021849 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.1629021849 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.4238673422 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 4628651228 ps |
| CPU time | 361.89 seconds |
| Started | Jan 10 01:35:57 PM PST 24 |
| Finished | Jan 10 01:42:11 PM PST 24 |
| Peak memory | 580800 kb |
| Host | smart-22be914d-64db-4e88-a90d-b80b36c10df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238673422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.4238673422 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.108599223 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 2911247902 ps |
| CPU time | 109.16 seconds |
| Started | Jan 10 01:35:57 PM PST 24 |
| Finished | Jan 10 01:37:58 PM PST 24 |
| Peak memory | 554864 kb |
| Host | smart-e6e99cbc-53a4-4427-85f0-310d666580d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108599223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.108599223 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2540956475 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 27826234869 ps |
| CPU time | 473.37 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:44:03 PM PST 24 |
| Peak memory | 554772 kb |
| Host | smart-2b229377-f676-4283-abaa-73ac210c214d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540956475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.2540956475 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2730931099 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 256767782 ps |
| CPU time | 23.19 seconds |
| Started | Jan 10 01:36:08 PM PST 24 |
| Finished | Jan 10 01:36:38 PM PST 24 |
| Peak memory | 554724 kb |
| Host | smart-79ca737a-c9df-4e17-be3a-51208f800bb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730931099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .2730931099 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.2331077430 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 668315082 ps |
| CPU time | 21.36 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:36:32 PM PST 24 |
| Peak memory | 554620 kb |
| Host | smart-31ebb9fe-0c5d-436f-b476-29ffaa647571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331077430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2331077430 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.1832222209 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 493263804 ps |
| CPU time | 42.25 seconds |
| Started | Jan 10 01:36:00 PM PST 24 |
| Finished | Jan 10 01:36:53 PM PST 24 |
| Peak memory | 553908 kb |
| Host | smart-9588f143-3d45-470d-8d33-2f9c015fe6f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832222209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.1832222209 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.2234748397 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 55115247912 ps |
| CPU time | 568.42 seconds |
| Started | Jan 10 01:35:58 PM PST 24 |
| Finished | Jan 10 01:45:39 PM PST 24 |
| Peak memory | 554760 kb |
| Host | smart-b60046d9-dbd2-4dbd-94b5-fed8f8296b6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234748397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2234748397 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.711578465 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 5964518108 ps |
| CPU time | 102.25 seconds |
| Started | Jan 10 01:35:59 PM PST 24 |
| Finished | Jan 10 01:37:53 PM PST 24 |
| Peak memory | 552944 kb |
| Host | smart-a97032a6-d1e0-4bde-af98-cad0e1b265fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711578465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.711578465 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.2367394307 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 34030675 ps |
| CPU time | 5.55 seconds |
| Started | Jan 10 01:36:07 PM PST 24 |
| Finished | Jan 10 01:36:20 PM PST 24 |
| Peak memory | 552712 kb |
| Host | smart-77e2300d-d061-48a9-b2a0-1a5dada5b891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367394307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.2367394307 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.4092235957 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 2694716775 ps |
| CPU time | 70.31 seconds |
| Started | Jan 10 01:36:00 PM PST 24 |
| Finished | Jan 10 01:37:21 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-cb133dcc-7fa0-4edd-ac0a-21ce01c672ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092235957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.4092235957 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.1462039305 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 160461230 ps |
| CPU time | 8.19 seconds |
| Started | Jan 10 01:36:09 PM PST 24 |
| Finished | Jan 10 01:36:24 PM PST 24 |
| Peak memory | 552940 kb |
| Host | smart-1ac5dd92-46ee-401d-b20d-f6211a7877d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462039305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1462039305 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3701111839 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 5149218448 ps |
| CPU time | 51.8 seconds |
| Started | Jan 10 01:36:09 PM PST 24 |
| Finished | Jan 10 01:37:08 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-039f128a-75f6-4c1d-ae76-9129410249eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701111839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3701111839 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.655263458 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 5145632420 ps |
| CPU time | 87.29 seconds |
| Started | Jan 10 01:35:54 PM PST 24 |
| Finished | Jan 10 01:37:35 PM PST 24 |
| Peak memory | 552752 kb |
| Host | smart-9012d257-a9c8-4d11-8a2d-8e4cbdc4e089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655263458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.655263458 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.754357860 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 48912966 ps |
| CPU time | 5.81 seconds |
| Started | Jan 10 01:36:07 PM PST 24 |
| Finished | Jan 10 01:36:20 PM PST 24 |
| Peak memory | 552924 kb |
| Host | smart-239490e3-673b-48b9-8d04-976b0c3bb7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754357860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays. 754357860 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.1970935554 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 7152717520 ps |
| CPU time | 282.63 seconds |
| Started | Jan 10 01:36:00 PM PST 24 |
| Finished | Jan 10 01:40:54 PM PST 24 |
| Peak memory | 556180 kb |
| Host | smart-f6d879bd-ecda-47b2-87e9-6f62eb3dadac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970935554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1970935554 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.770618180 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 4855611123 ps |
| CPU time | 171.02 seconds |
| Started | Jan 10 01:35:56 PM PST 24 |
| Finished | Jan 10 01:38:59 PM PST 24 |
| Peak memory | 554932 kb |
| Host | smart-910bdd36-caca-4135-8bb7-ff3d29237925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770618180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.770618180 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3961134877 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 7061409022 ps |
| CPU time | 592.63 seconds |
| Started | Jan 10 01:36:06 PM PST 24 |
| Finished | Jan 10 01:46:07 PM PST 24 |
| Peak memory | 559912 kb |
| Host | smart-fc854c40-bfea-4f76-8633-9907f85e5f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961134877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.3961134877 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.2049911682 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 232443713 ps |
| CPU time | 24.37 seconds |
| Started | Jan 10 01:35:57 PM PST 24 |
| Finished | Jan 10 01:36:33 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-741fe3b6-b6da-4de9-98c9-8775fb683f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049911682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2049911682 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.1428581596 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 2190184890 ps |
| CPU time | 82.75 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:44:09 PM PST 24 |
| Peak memory | 554872 kb |
| Host | smart-7cbb5ff7-76f6-48d4-91d1-bad07a5d8361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428581596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .1428581596 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3543290117 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 75245846624 ps |
| CPU time | 1396.91 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 02:06:01 PM PST 24 |
| Peak memory | 554784 kb |
| Host | smart-f198dae3-04a6-403e-832a-c81eecbae804 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543290117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.3543290117 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.4081674877 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 381726142 ps |
| CPU time | 18.22 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:43:02 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-c1942779-8d7f-4860-92bb-0d44bdaa4fa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081674877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.4081674877 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.1487835769 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 1211733518 ps |
| CPU time | 36.61 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:43:27 PM PST 24 |
| Peak memory | 554864 kb |
| Host | smart-26db71f0-4154-4e98-aab3-dd11ae7d99b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487835769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1487835769 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.3367349818 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 154306289 ps |
| CPU time | 15.45 seconds |
| Started | Jan 10 01:42:50 PM PST 24 |
| Finished | Jan 10 01:43:08 PM PST 24 |
| Peak memory | 554884 kb |
| Host | smart-6619016b-cd95-422d-a63e-21c1a2f0d6e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367349818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3367349818 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.896384 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 12676973079 ps |
| CPU time | 133.52 seconds |
| Started | Jan 10 01:42:40 PM PST 24 |
| Finished | Jan 10 01:44:56 PM PST 24 |
| Peak memory | 553752 kb |
| Host | smart-78f6fe9f-c28f-40a9-af93-e7b1f7556028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.896384 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.771136811 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 66228768877 ps |
| CPU time | 1172.12 seconds |
| Started | Jan 10 01:42:40 PM PST 24 |
| Finished | Jan 10 02:02:14 PM PST 24 |
| Peak memory | 553996 kb |
| Host | smart-1839ec56-98bc-4442-8f75-2d232d50a786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771136811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.771136811 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.1529890511 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 160829686 ps |
| CPU time | 15.33 seconds |
| Started | Jan 10 01:42:44 PM PST 24 |
| Finished | Jan 10 01:43:01 PM PST 24 |
| Peak memory | 555044 kb |
| Host | smart-02608b5e-6de0-47b4-8f1f-65b7a0d35133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529890511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.1529890511 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.1288930498 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 567681484 ps |
| CPU time | 41.06 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:43:25 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-3f881bf1-96e3-4654-809a-39320fac75c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288930498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.1288930498 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.405419681 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 49498000 ps |
| CPU time | 6.11 seconds |
| Started | Jan 10 01:42:56 PM PST 24 |
| Finished | Jan 10 01:43:04 PM PST 24 |
| Peak memory | 552956 kb |
| Host | smart-ce973a3a-1253-45b8-8d67-07ccb1afab1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405419681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.405419681 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3006951587 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 6330267879 ps |
| CPU time | 64.46 seconds |
| Started | Jan 10 01:42:56 PM PST 24 |
| Finished | Jan 10 01:44:02 PM PST 24 |
| Peak memory | 552544 kb |
| Host | smart-d4404c78-2409-4a7c-bc5e-a2cfad1524be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006951587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3006951587 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.4149807243 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 6693141172 ps |
| CPU time | 110.24 seconds |
| Started | Jan 10 01:42:49 PM PST 24 |
| Finished | Jan 10 01:44:43 PM PST 24 |
| Peak memory | 552720 kb |
| Host | smart-6529fada-cd6f-4034-b14a-ce57458c5aea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149807243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.4149807243 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.34934124 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 45078478 ps |
| CPU time | 6.17 seconds |
| Started | Jan 10 01:42:56 PM PST 24 |
| Finished | Jan 10 01:43:03 PM PST 24 |
| Peak memory | 552488 kb |
| Host | smart-7cf534e4-8926-4b2b-8b40-ea6aab4493fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34934124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delays.34934124 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.1138177963 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 6646831393 ps |
| CPU time | 236.24 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:46:39 PM PST 24 |
| Peak memory | 556016 kb |
| Host | smart-9779afe0-3c5d-4905-8add-6c223b96146c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138177963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.1138177963 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2541071221 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 13171063882 ps |
| CPU time | 468.22 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:50:39 PM PST 24 |
| Peak memory | 555976 kb |
| Host | smart-a30f388d-2e2f-423a-9d38-b6e258a884ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541071221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.2541071221 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.676470029 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 5942698142 ps |
| CPU time | 517.04 seconds |
| Started | Jan 10 01:42:43 PM PST 24 |
| Finished | Jan 10 01:51:22 PM PST 24 |
| Peak memory | 558144 kb |
| Host | smart-b2723da3-cec7-41f9-8e12-c260904ba9c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676470029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_rand_reset.676470029 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2282837122 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 1451295075 ps |
| CPU time | 199.47 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:46:04 PM PST 24 |
| Peak memory | 556916 kb |
| Host | smart-bf33611a-2e49-43fe-ae50-155597877cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282837122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.2282837122 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2703634966 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 1560049145 ps |
| CPU time | 67.04 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:43:51 PM PST 24 |
| Peak memory | 554824 kb |
| Host | smart-160580c7-8cf0-4004-bdcb-4d5b7f9b06f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703634966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2703634966 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.972985512 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 1167901745 ps |
| CPU time | 55.94 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:43:44 PM PST 24 |
| Peak memory | 554776 kb |
| Host | smart-a4f6f91a-e23b-4b76-b2c4-9f80306239d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972985512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 972985512 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2447862746 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 26033487882 ps |
| CPU time | 430.58 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:50:00 PM PST 24 |
| Peak memory | 555076 kb |
| Host | smart-9a945549-6beb-4f62-a3c2-0368e1493be1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447862746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.2447862746 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2952629042 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 34510942 ps |
| CPU time | 6.1 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:42:55 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-b813ff96-6a6c-46cc-9872-933157ef77d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952629042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.2952629042 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.3932718001 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 534113818 ps |
| CPU time | 38.19 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:43:21 PM PST 24 |
| Peak memory | 554744 kb |
| Host | smart-7f5e76a9-5996-46b3-bc5a-46503c6d8de6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932718001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.3932718001 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.609297664 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 962699349 ps |
| CPU time | 32.3 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:43:15 PM PST 24 |
| Peak memory | 554828 kb |
| Host | smart-1a9cba21-8566-46fe-b8d4-59987ab3c8b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609297664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.609297664 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.1870113412 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 108050228446 ps |
| CPU time | 1245.35 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 02:03:34 PM PST 24 |
| Peak memory | 555156 kb |
| Host | smart-a966ce45-267f-4e17-b463-4ccd3e84544e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870113412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.1870113412 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.3018594641 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 30400505285 ps |
| CPU time | 522.44 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:51:32 PM PST 24 |
| Peak memory | 554864 kb |
| Host | smart-c8a8994b-caa9-45c3-be67-783a9ae060ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018594641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.3018594641 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.260090469 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 140255806 ps |
| CPU time | 13.72 seconds |
| Started | Jan 10 01:42:40 PM PST 24 |
| Finished | Jan 10 01:42:56 PM PST 24 |
| Peak memory | 553924 kb |
| Host | smart-abdf413b-caa3-46c6-ae39-9fc38e0d7343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260090469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_dela ys.260090469 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.2308582948 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2153054549 ps |
| CPU time | 67.28 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:43:55 PM PST 24 |
| Peak memory | 555100 kb |
| Host | smart-61fc611d-bba0-42ce-8408-8d2fedb32294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308582948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2308582948 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.2660388139 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 49631665 ps |
| CPU time | 5.78 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:42:54 PM PST 24 |
| Peak memory | 552840 kb |
| Host | smart-d3256d38-6b95-47b6-96e0-1f6b4e18e50d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660388139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.2660388139 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.355721279 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 8556386164 ps |
| CPU time | 96.18 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:44:26 PM PST 24 |
| Peak memory | 552736 kb |
| Host | smart-03e3afba-631c-4b4c-ace0-7db058ea6145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355721279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.355721279 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.668617133 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 5555270252 ps |
| CPU time | 87.81 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:44:15 PM PST 24 |
| Peak memory | 552992 kb |
| Host | smart-ee74f190-707e-4c50-a99d-8d1f1eb89621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668617133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.668617133 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2777935179 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 42939896 ps |
| CPU time | 6.27 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:42:54 PM PST 24 |
| Peak memory | 552924 kb |
| Host | smart-ca7059e5-c940-40f5-9026-7093e9059d46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777935179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.2777935179 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.3884512791 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 1860234873 ps |
| CPU time | 54.91 seconds |
| Started | Jan 10 01:42:48 PM PST 24 |
| Finished | Jan 10 01:43:46 PM PST 24 |
| Peak memory | 553996 kb |
| Host | smart-f3cbacab-2921-4911-aafe-643fddc139a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884512791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.3884512791 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.4219742390 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 15414595709 ps |
| CPU time | 533.58 seconds |
| Started | Jan 10 01:42:49 PM PST 24 |
| Finished | Jan 10 01:51:46 PM PST 24 |
| Peak memory | 557824 kb |
| Host | smart-2304833b-8db0-4cc3-b294-f0ef95cdafdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219742390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.4219742390 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1447821158 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 81559128 ps |
| CPU time | 33.84 seconds |
| Started | Jan 10 01:42:49 PM PST 24 |
| Finished | Jan 10 01:43:26 PM PST 24 |
| Peak memory | 554272 kb |
| Host | smart-a74edbe9-80b0-480f-8417-d9e0ca52dd62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447821158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1447821158 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1444502048 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 210966707 ps |
| CPU time | 91.27 seconds |
| Started | Jan 10 01:42:48 PM PST 24 |
| Finished | Jan 10 01:44:23 PM PST 24 |
| Peak memory | 556232 kb |
| Host | smart-f8748ad2-fcc2-454b-a0ff-3b109bf2e636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444502048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.1444502048 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.1877349253 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 1283968940 ps |
| CPU time | 49.19 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:43:38 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-fb683843-6bbc-43ef-9545-d3f29e56fa9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877349253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1877349253 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.86639506 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3160554495 ps |
| CPU time | 120.64 seconds |
| Started | Jan 10 01:42:50 PM PST 24 |
| Finished | Jan 10 01:44:53 PM PST 24 |
| Peak memory | 555148 kb |
| Host | smart-04c5e7b9-c4bd-46df-b89e-f8929df47151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86639506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.86639506 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.840842411 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 70664600198 ps |
| CPU time | 1322.52 seconds |
| Started | Jan 10 01:42:51 PM PST 24 |
| Finished | Jan 10 02:04:56 PM PST 24 |
| Peak memory | 555888 kb |
| Host | smart-83483959-448f-4866-a2ea-89bf7fbb9624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840842411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d evice_slow_rsp.840842411 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3318677042 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 1327557659 ps |
| CPU time | 47.89 seconds |
| Started | Jan 10 01:42:57 PM PST 24 |
| Finished | Jan 10 01:43:46 PM PST 24 |
| Peak memory | 553660 kb |
| Host | smart-97a6a6a6-2179-479a-9a47-2fc8ceca325c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318677042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.3318677042 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.3099533975 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 284336532 ps |
| CPU time | 23.53 seconds |
| Started | Jan 10 01:42:57 PM PST 24 |
| Finished | Jan 10 01:43:21 PM PST 24 |
| Peak memory | 554508 kb |
| Host | smart-03e8b320-0f5e-413a-8c9b-b31355dd9781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099533975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.3099533975 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3452902094 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 1570066677 ps |
| CPU time | 54.22 seconds |
| Started | Jan 10 01:42:48 PM PST 24 |
| Finished | Jan 10 01:43:46 PM PST 24 |
| Peak memory | 554664 kb |
| Host | smart-21ea3b67-0c7c-4223-b78a-420585cfd5ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452902094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3452902094 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.188678866 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 21287059801 ps |
| CPU time | 228.29 seconds |
| Started | Jan 10 01:42:46 PM PST 24 |
| Finished | Jan 10 01:46:37 PM PST 24 |
| Peak memory | 554732 kb |
| Host | smart-7b8fd4c8-ebb3-4fb3-8a42-915cea565d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188678866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.188678866 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.78447285 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 31023970694 ps |
| CPU time | 523.35 seconds |
| Started | Jan 10 01:42:51 PM PST 24 |
| Finished | Jan 10 01:51:37 PM PST 24 |
| Peak memory | 553948 kb |
| Host | smart-b0fe8021-628d-4e32-8817-9394f0c489b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78447285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.78447285 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.1073149030 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 320337439 ps |
| CPU time | 28.43 seconds |
| Started | Jan 10 01:42:51 PM PST 24 |
| Finished | Jan 10 01:43:22 PM PST 24 |
| Peak memory | 554708 kb |
| Host | smart-5a6874ea-7ff4-4c39-9903-93be474c578b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073149030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.1073149030 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.427030680 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 382725734 ps |
| CPU time | 26.46 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:43:17 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-6164696d-f069-4b9e-9cdf-e8c5c16b3c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427030680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.427030680 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.2748448915 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 40096908 ps |
| CPU time | 5.57 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:42:53 PM PST 24 |
| Peak memory | 553004 kb |
| Host | smart-db1d5493-155d-4238-b5bc-206c2083c8c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748448915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2748448915 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.2712903618 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 7509092121 ps |
| CPU time | 75.8 seconds |
| Started | Jan 10 01:42:49 PM PST 24 |
| Finished | Jan 10 01:44:08 PM PST 24 |
| Peak memory | 552896 kb |
| Host | smart-43d99f35-9c11-4a74-a647-507759cd3399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712903618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.2712903618 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2689747819 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 6215031661 ps |
| CPU time | 93.72 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:44:21 PM PST 24 |
| Peak memory | 552652 kb |
| Host | smart-e465f7ee-0221-4401-9ccb-d897f41ed911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689747819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.2689747819 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3729762223 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 43007219 ps |
| CPU time | 5.92 seconds |
| Started | Jan 10 01:42:47 PM PST 24 |
| Finished | Jan 10 01:42:56 PM PST 24 |
| Peak memory | 552836 kb |
| Host | smart-8de4346c-099f-497e-b04b-983e505641c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729762223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.3729762223 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.871420143 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2869618468 ps |
| CPU time | 225.46 seconds |
| Started | Jan 10 01:42:50 PM PST 24 |
| Finished | Jan 10 01:46:38 PM PST 24 |
| Peak memory | 555252 kb |
| Host | smart-2b6ec397-b6f6-46f8-96d3-9b7523dc10b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871420143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.871420143 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.61574704 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 9243611249 ps |
| CPU time | 317.97 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:48:06 PM PST 24 |
| Peak memory | 555952 kb |
| Host | smart-1d7e5802-8e75-45fc-964d-2091afa28861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61574704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.61574704 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3494472006 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 995373347 ps |
| CPU time | 408.27 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:49:35 PM PST 24 |
| Peak memory | 558248 kb |
| Host | smart-95bf7302-e3c0-4025-8108-dff3cc6926c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494472006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.3494472006 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2293070750 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 178794640 ps |
| CPU time | 58.94 seconds |
| Started | Jan 10 01:42:50 PM PST 24 |
| Finished | Jan 10 01:43:52 PM PST 24 |
| Peak memory | 556048 kb |
| Host | smart-191c21e4-cc18-4e10-b5b5-0d4a8df67297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293070750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.2293070750 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1484454408 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 1066028897 ps |
| CPU time | 41.53 seconds |
| Started | Jan 10 01:42:50 PM PST 24 |
| Finished | Jan 10 01:43:35 PM PST 24 |
| Peak memory | 555060 kb |
| Host | smart-86a13c65-38f6-4369-ad57-be4a7af26696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484454408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1484454408 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.2761847166 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 853379451 ps |
| CPU time | 80.6 seconds |
| Started | Jan 10 01:42:59 PM PST 24 |
| Finished | Jan 10 01:44:21 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-785b4993-35fd-4695-934e-c2df1c4afdbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761847166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .2761847166 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.302997266 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 146375651305 ps |
| CPU time | 2502.78 seconds |
| Started | Jan 10 01:43:01 PM PST 24 |
| Finished | Jan 10 02:24:47 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-f7d09505-8f84-45b4-846a-31a45b112863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302997266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_d evice_slow_rsp.302997266 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3632798333 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 546883716 ps |
| CPU time | 22.47 seconds |
| Started | Jan 10 01:43:01 PM PST 24 |
| Finished | Jan 10 01:43:26 PM PST 24 |
| Peak memory | 553916 kb |
| Host | smart-8a6c3a89-bc68-4b14-8fe9-e71121285981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632798333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.3632798333 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.2984321125 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 489256102 ps |
| CPU time | 39.4 seconds |
| Started | Jan 10 01:43:00 PM PST 24 |
| Finished | Jan 10 01:43:41 PM PST 24 |
| Peak memory | 554708 kb |
| Host | smart-b38a7658-53fb-49f2-a937-f8e860f32a7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984321125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.2984321125 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.821924840 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 259481881 ps |
| CPU time | 23.44 seconds |
| Started | Jan 10 01:42:45 PM PST 24 |
| Finished | Jan 10 01:43:11 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-edcba408-6188-48d0-8178-eaaaa22ca4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821924840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.821924840 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.1467429522 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 9076213132 ps |
| CPU time | 92.39 seconds |
| Started | Jan 10 01:42:58 PM PST 24 |
| Finished | Jan 10 01:44:31 PM PST 24 |
| Peak memory | 552636 kb |
| Host | smart-cdf3853e-cc1b-4cfc-9fd1-9077f4fef1b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467429522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.1467429522 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1874852642 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 2508526118 ps |
| CPU time | 39.32 seconds |
| Started | Jan 10 01:42:59 PM PST 24 |
| Finished | Jan 10 01:43:40 PM PST 24 |
| Peak memory | 552796 kb |
| Host | smart-37edbf50-d359-4467-9b82-60a21b5f49c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874852642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1874852642 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.2798255271 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 599000213 ps |
| CPU time | 53.27 seconds |
| Started | Jan 10 01:43:00 PM PST 24 |
| Finished | Jan 10 01:43:55 PM PST 24 |
| Peak memory | 554692 kb |
| Host | smart-0aa60129-1340-4705-b69c-2616d616db05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798255271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.2798255271 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.1658641396 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 757464265 ps |
| CPU time | 24.64 seconds |
| Started | Jan 10 01:43:01 PM PST 24 |
| Finished | Jan 10 01:43:27 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-91f9d79d-2de9-4ba5-a3d7-2e5289f26086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658641396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.1658641396 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.2437068195 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 48344003 ps |
| CPU time | 6.22 seconds |
| Started | Jan 10 01:42:43 PM PST 24 |
| Finished | Jan 10 01:42:51 PM PST 24 |
| Peak memory | 552956 kb |
| Host | smart-b3de1580-525e-4d28-9ec7-9fe2d366d22f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437068195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2437068195 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1185199556 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 7331918440 ps |
| CPU time | 76.44 seconds |
| Started | Jan 10 01:42:42 PM PST 24 |
| Finished | Jan 10 01:44:01 PM PST 24 |
| Peak memory | 552964 kb |
| Host | smart-a8b28c2e-97d6-4936-b483-642f43cd3db3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185199556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1185199556 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.352607614 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 5919419032 ps |
| CPU time | 95.99 seconds |
| Started | Jan 10 01:42:41 PM PST 24 |
| Finished | Jan 10 01:44:18 PM PST 24 |
| Peak memory | 553004 kb |
| Host | smart-7a8708da-3c67-43db-aa9b-c8dbd5359599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352607614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.352607614 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3663418031 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 42374523 ps |
| CPU time | 5.71 seconds |
| Started | Jan 10 01:42:43 PM PST 24 |
| Finished | Jan 10 01:42:51 PM PST 24 |
| Peak memory | 552924 kb |
| Host | smart-fe366842-90e7-44c8-b199-18c0de3146af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663418031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.3663418031 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.3823977328 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 5673861204 ps |
| CPU time | 203.38 seconds |
| Started | Jan 10 01:43:01 PM PST 24 |
| Finished | Jan 10 01:46:27 PM PST 24 |
| Peak memory | 555940 kb |
| Host | smart-2e8068a2-5c48-4ca7-acc7-c4f43a541d86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823977328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.3823977328 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.613040095 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 3204526600 ps |
| CPU time | 131.11 seconds |
| Started | Jan 10 01:43:01 PM PST 24 |
| Finished | Jan 10 01:45:14 PM PST 24 |
| Peak memory | 555976 kb |
| Host | smart-a1206716-3fe9-4a5f-a7ab-790320ea962e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613040095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.613040095 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.2211095440 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 521259563 ps |
| CPU time | 149.27 seconds |
| Started | Jan 10 01:43:04 PM PST 24 |
| Finished | Jan 10 01:45:35 PM PST 24 |
| Peak memory | 556116 kb |
| Host | smart-0d6a17cd-8768-4e24-a236-eafeed7708f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211095440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.2211095440 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1018845556 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 383537587 ps |
| CPU time | 111.88 seconds |
| Started | Jan 10 01:43:02 PM PST 24 |
| Finished | Jan 10 01:44:56 PM PST 24 |
| Peak memory | 557676 kb |
| Host | smart-66b4fd04-d76a-4822-b922-188e12cbace8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018845556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.1018845556 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.2237317456 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 914854847 ps |
| CPU time | 35.45 seconds |
| Started | Jan 10 01:42:58 PM PST 24 |
| Finished | Jan 10 01:43:35 PM PST 24 |
| Peak memory | 554720 kb |
| Host | smart-c133dcaa-4839-4fe1-8b9f-674437a021f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237317456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.2237317456 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2684992821 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 1899580205 ps |
| CPU time | 67.76 seconds |
| Started | Jan 10 01:43:01 PM PST 24 |
| Finished | Jan 10 01:44:11 PM PST 24 |
| Peak memory | 554760 kb |
| Host | smart-a89b3471-44e6-4b02-816d-26e93b0b8f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684992821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .2684992821 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.176342351 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 67303352085 ps |
| CPU time | 1171.5 seconds |
| Started | Jan 10 01:43:03 PM PST 24 |
| Finished | Jan 10 02:02:36 PM PST 24 |
| Peak memory | 553912 kb |
| Host | smart-b8b01b7e-08fa-4fc6-8eea-6447595096e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176342351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.176342351 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1103782866 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 158511369 ps |
| CPU time | 17.68 seconds |
| Started | Jan 10 01:43:07 PM PST 24 |
| Finished | Jan 10 01:43:26 PM PST 24 |
| Peak memory | 555012 kb |
| Host | smart-b4cfc5db-711a-4eb0-a84b-65d09b43d308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103782866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.1103782866 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.2121366919 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 33615564 ps |
| CPU time | 5.29 seconds |
| Started | Jan 10 01:43:05 PM PST 24 |
| Finished | Jan 10 01:43:12 PM PST 24 |
| Peak memory | 552888 kb |
| Host | smart-34d266a4-bb01-4bad-b0b6-863eb32ace27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121366919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.2121366919 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.1491445655 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 281762823 ps |
| CPU time | 23.93 seconds |
| Started | Jan 10 01:43:05 PM PST 24 |
| Finished | Jan 10 01:43:30 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-f724fca9-d462-4e1b-a3eb-a6a648fb91f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491445655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1491445655 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.160205139 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 103183910440 ps |
| CPU time | 1131.26 seconds |
| Started | Jan 10 01:43:03 PM PST 24 |
| Finished | Jan 10 02:01:56 PM PST 24 |
| Peak memory | 554756 kb |
| Host | smart-2b06da44-ac01-472e-b936-89ea4f2576f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160205139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.160205139 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1716356958 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 21781088334 ps |
| CPU time | 357.62 seconds |
| Started | Jan 10 01:43:02 PM PST 24 |
| Finished | Jan 10 01:49:02 PM PST 24 |
| Peak memory | 554732 kb |
| Host | smart-c0d54668-c7e8-4c13-adcb-cb1951871dd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716356958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1716356958 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.1894062748 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 359757600 ps |
| CPU time | 30.82 seconds |
| Started | Jan 10 01:42:59 PM PST 24 |
| Finished | Jan 10 01:43:31 PM PST 24 |
| Peak memory | 553888 kb |
| Host | smart-a392ac5e-7dd5-4ba6-b512-1981f73a0357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894062748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.1894062748 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.787880936 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 535857705 ps |
| CPU time | 17.43 seconds |
| Started | Jan 10 01:43:03 PM PST 24 |
| Finished | Jan 10 01:43:23 PM PST 24 |
| Peak memory | 553880 kb |
| Host | smart-e2d86cb4-ed7c-41b5-a54a-877652155c33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787880936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.787880936 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.4026703106 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 50654095 ps |
| CPU time | 6.37 seconds |
| Started | Jan 10 01:43:07 PM PST 24 |
| Finished | Jan 10 01:43:16 PM PST 24 |
| Peak memory | 552416 kb |
| Host | smart-b1d0ca88-5a83-4fec-a9d1-e0ecece04d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026703106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.4026703106 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.3702411486 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 7595553450 ps |
| CPU time | 82.44 seconds |
| Started | Jan 10 01:43:07 PM PST 24 |
| Finished | Jan 10 01:44:31 PM PST 24 |
| Peak memory | 552548 kb |
| Host | smart-493fa58f-ae53-4c4f-bf8e-2c807e0b6c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702411486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.3702411486 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1353931408 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 5419719823 ps |
| CPU time | 89.65 seconds |
| Started | Jan 10 01:43:07 PM PST 24 |
| Finished | Jan 10 01:44:39 PM PST 24 |
| Peak memory | 552924 kb |
| Host | smart-59fae8d2-485f-43e7-a96b-23e5d2b233d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353931408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.1353931408 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.3978480964 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 41015501 ps |
| CPU time | 5.74 seconds |
| Started | Jan 10 01:43:02 PM PST 24 |
| Finished | Jan 10 01:43:10 PM PST 24 |
| Peak memory | 552908 kb |
| Host | smart-d142a6e7-586e-4d3a-939c-1a8ae20d80b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978480964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.3978480964 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3457555498 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 15226188261 ps |
| CPU time | 594.52 seconds |
| Started | Jan 10 01:43:06 PM PST 24 |
| Finished | Jan 10 01:53:03 PM PST 24 |
| Peak memory | 556252 kb |
| Host | smart-dc946cf6-b3c4-4687-b248-83b2d252cd04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457555498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3457555498 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2756611858 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 17615766143 ps |
| CPU time | 603.83 seconds |
| Started | Jan 10 01:43:07 PM PST 24 |
| Finished | Jan 10 01:53:13 PM PST 24 |
| Peak memory | 556284 kb |
| Host | smart-a798fb83-2603-4227-8acd-ef7f5d8b94ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756611858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.2756611858 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.289399509 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 2419385152 ps |
| CPU time | 207.14 seconds |
| Started | Jan 10 01:43:04 PM PST 24 |
| Finished | Jan 10 01:46:33 PM PST 24 |
| Peak memory | 556504 kb |
| Host | smart-5188ca6b-9618-49c5-a86e-d6d9b772062f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289399509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.289399509 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3177933878 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 3795403961 ps |
| CPU time | 362.44 seconds |
| Started | Jan 10 01:43:01 PM PST 24 |
| Finished | Jan 10 01:49:06 PM PST 24 |
| Peak memory | 559856 kb |
| Host | smart-ebef902d-2fbd-4482-8753-15cb11732308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177933878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.3177933878 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.4271652683 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 656187454 ps |
| CPU time | 29.45 seconds |
| Started | Jan 10 01:43:04 PM PST 24 |
| Finished | Jan 10 01:43:35 PM PST 24 |
| Peak memory | 553932 kb |
| Host | smart-64090900-6a09-4d38-b741-f32ae9cb877c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271652683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.4271652683 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.828578209 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 1348852849 ps |
| CPU time | 53.11 seconds |
| Started | Jan 10 01:43:01 PM PST 24 |
| Finished | Jan 10 01:43:57 PM PST 24 |
| Peak memory | 554784 kb |
| Host | smart-a94fad02-546c-4037-b55d-bd8238d58296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828578209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device. 828578209 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.684658530 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 289773363 ps |
| CPU time | 13.6 seconds |
| Started | Jan 10 01:43:16 PM PST 24 |
| Finished | Jan 10 01:43:31 PM PST 24 |
| Peak memory | 554968 kb |
| Host | smart-70fdf77a-37cc-4314-93ac-eef4f838cc85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684658530 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr .684658530 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.335855818 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 91265672 ps |
| CPU time | 8.81 seconds |
| Started | Jan 10 01:43:12 PM PST 24 |
| Finished | Jan 10 01:43:23 PM PST 24 |
| Peak memory | 554568 kb |
| Host | smart-a468953a-270d-4a83-b2f2-8ea75be0d857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335855818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.335855818 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.2916193854 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 594305309 ps |
| CPU time | 48.34 seconds |
| Started | Jan 10 01:43:06 PM PST 24 |
| Finished | Jan 10 01:43:56 PM PST 24 |
| Peak memory | 555060 kb |
| Host | smart-9908128d-298e-4fe8-ac5c-7c04bcc1a0f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916193854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2916193854 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1318099107 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 12220527942 ps |
| CPU time | 122.11 seconds |
| Started | Jan 10 01:43:12 PM PST 24 |
| Finished | Jan 10 01:45:16 PM PST 24 |
| Peak memory | 552588 kb |
| Host | smart-e9e35379-3ee6-4c7f-acd5-460a66fa9f6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318099107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.1318099107 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.907932418 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 30502256746 ps |
| CPU time | 537.33 seconds |
| Started | Jan 10 01:43:07 PM PST 24 |
| Finished | Jan 10 01:52:06 PM PST 24 |
| Peak memory | 553992 kb |
| Host | smart-4e120186-df2d-422e-b7df-0a2136906bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907932418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.907932418 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.848440437 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 375034726 ps |
| CPU time | 28.05 seconds |
| Started | Jan 10 01:43:03 PM PST 24 |
| Finished | Jan 10 01:43:33 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-24c093ec-6488-46fa-ae09-a34d21411f2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848440437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_dela ys.848440437 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.2565681445 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2170909517 ps |
| CPU time | 63.38 seconds |
| Started | Jan 10 01:43:16 PM PST 24 |
| Finished | Jan 10 01:44:20 PM PST 24 |
| Peak memory | 554780 kb |
| Host | smart-a611949e-274a-4890-9cb0-bc4e5d3c4690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565681445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.2565681445 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.3694656123 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 164942596 ps |
| CPU time | 7.66 seconds |
| Started | Jan 10 01:43:06 PM PST 24 |
| Finished | Jan 10 01:43:15 PM PST 24 |
| Peak memory | 552928 kb |
| Host | smart-b95c3525-14b0-4630-8c8f-b63b094512e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694656123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.3694656123 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2008537314 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 9002000145 ps |
| CPU time | 91.96 seconds |
| Started | Jan 10 01:43:15 PM PST 24 |
| Finished | Jan 10 01:44:48 PM PST 24 |
| Peak memory | 552992 kb |
| Host | smart-f6b4a282-7e74-4cfc-b64a-120ab08adeea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008537314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2008537314 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3215158070 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 5772103529 ps |
| CPU time | 94.04 seconds |
| Started | Jan 10 01:43:07 PM PST 24 |
| Finished | Jan 10 01:44:42 PM PST 24 |
| Peak memory | 552616 kb |
| Host | smart-12e04ae6-5654-469c-a013-c6760f91e7aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215158070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3215158070 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1867145680 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 50665948 ps |
| CPU time | 6.12 seconds |
| Started | Jan 10 01:43:01 PM PST 24 |
| Finished | Jan 10 01:43:10 PM PST 24 |
| Peak memory | 552668 kb |
| Host | smart-a0ea6b27-e50f-420b-852a-50bac8e1a407 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867145680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.1867145680 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3145712138 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 17627131993 ps |
| CPU time | 785.64 seconds |
| Started | Jan 10 01:43:04 PM PST 24 |
| Finished | Jan 10 01:56:11 PM PST 24 |
| Peak memory | 556672 kb |
| Host | smart-6563b343-c2fd-43d7-a45f-fe0cbf8b44ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145712138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3145712138 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.711276619 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 17056866605 ps |
| CPU time | 610.4 seconds |
| Started | Jan 10 01:43:15 PM PST 24 |
| Finished | Jan 10 01:53:27 PM PST 24 |
| Peak memory | 559548 kb |
| Host | smart-9abaa067-f17f-4b02-b459-33ad9956e164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711276619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.711276619 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1327130801 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 8072288 ps |
| CPU time | 17.41 seconds |
| Started | Jan 10 01:43:15 PM PST 24 |
| Finished | Jan 10 01:43:33 PM PST 24 |
| Peak memory | 552484 kb |
| Host | smart-a6e1f9a6-4eac-437e-8b70-ec66ae953258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327130801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.1327130801 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.746179979 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 9261344475 ps |
| CPU time | 430.44 seconds |
| Started | Jan 10 01:43:11 PM PST 24 |
| Finished | Jan 10 01:50:24 PM PST 24 |
| Peak memory | 557384 kb |
| Host | smart-9bf4585c-1132-4984-8457-ae21466972d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746179979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_reset_error.746179979 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1476522338 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 63272753 ps |
| CPU time | 5.99 seconds |
| Started | Jan 10 01:43:16 PM PST 24 |
| Finished | Jan 10 01:43:23 PM PST 24 |
| Peak memory | 552696 kb |
| Host | smart-b53e0c17-a28b-4cfe-8b9a-88c2dd0bfa59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476522338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1476522338 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.1131077739 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2114634769 ps |
| CPU time | 80.64 seconds |
| Started | Jan 10 01:43:04 PM PST 24 |
| Finished | Jan 10 01:44:27 PM PST 24 |
| Peak memory | 555060 kb |
| Host | smart-58f3610e-e22f-4508-954f-838492fb14fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131077739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .1131077739 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1418690132 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 48569905613 ps |
| CPU time | 848.53 seconds |
| Started | Jan 10 01:43:02 PM PST 24 |
| Finished | Jan 10 01:57:12 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-00ad50a3-8b6d-40f0-8273-ca51a04bf7f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418690132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.1418690132 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1526968257 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 228507517 ps |
| CPU time | 25.57 seconds |
| Started | Jan 10 01:43:21 PM PST 24 |
| Finished | Jan 10 01:43:50 PM PST 24 |
| Peak memory | 553888 kb |
| Host | smart-f4274622-c1f1-4291-8262-e6a67f1b45cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526968257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.1526968257 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.998649535 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 1833684238 ps |
| CPU time | 59.51 seconds |
| Started | Jan 10 01:43:22 PM PST 24 |
| Finished | Jan 10 01:44:26 PM PST 24 |
| Peak memory | 553820 kb |
| Host | smart-006bc50e-1078-4a88-8fbe-fd3fc6ae3d6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998649535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.998649535 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.4126232608 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1531474171 ps |
| CPU time | 45.31 seconds |
| Started | Jan 10 01:43:02 PM PST 24 |
| Finished | Jan 10 01:43:49 PM PST 24 |
| Peak memory | 554932 kb |
| Host | smart-b054b239-1ed3-4989-b9e3-0585901cb7f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126232608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.4126232608 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2609482855 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 51587145694 ps |
| CPU time | 582.51 seconds |
| Started | Jan 10 01:43:02 PM PST 24 |
| Finished | Jan 10 01:52:46 PM PST 24 |
| Peak memory | 555092 kb |
| Host | smart-e70d45b5-7a6f-47a8-9c30-470897e54f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609482855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.2609482855 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.726297798 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 3353252356 ps |
| CPU time | 56.91 seconds |
| Started | Jan 10 01:42:59 PM PST 24 |
| Finished | Jan 10 01:43:57 PM PST 24 |
| Peak memory | 552968 kb |
| Host | smart-97f831c3-facf-4d9f-a5ec-00783516c7b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726297798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.726297798 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.501810826 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 94650557 ps |
| CPU time | 10.8 seconds |
| Started | Jan 10 01:43:00 PM PST 24 |
| Finished | Jan 10 01:43:13 PM PST 24 |
| Peak memory | 554988 kb |
| Host | smart-7d2f784f-064e-418e-85f5-a8b7e4273235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501810826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela ys.501810826 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.436695 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 841964095 ps |
| CPU time | 25.32 seconds |
| Started | Jan 10 01:43:38 PM PST 24 |
| Finished | Jan 10 01:44:05 PM PST 24 |
| Peak memory | 554776 kb |
| Host | smart-1a080d63-80df-4703-8bc4-e0d1d454866b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.436695 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1603882606 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 49399069 ps |
| CPU time | 5.91 seconds |
| Started | Jan 10 01:43:04 PM PST 24 |
| Finished | Jan 10 01:43:12 PM PST 24 |
| Peak memory | 552948 kb |
| Host | smart-1a0a6c71-25de-41fc-8d2f-e33b6a7fc17d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603882606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1603882606 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.536265197 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 9315713649 ps |
| CPU time | 91.71 seconds |
| Started | Jan 10 01:43:05 PM PST 24 |
| Finished | Jan 10 01:44:38 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-6b56c0a8-c787-44b2-a246-7165d84f8780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536265197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.536265197 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.894846862 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 5167871434 ps |
| CPU time | 89.98 seconds |
| Started | Jan 10 01:43:11 PM PST 24 |
| Finished | Jan 10 01:44:42 PM PST 24 |
| Peak memory | 552940 kb |
| Host | smart-df536803-8d5a-4480-9dd9-7a081be28594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894846862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.894846862 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.455288277 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 45723839 ps |
| CPU time | 5.95 seconds |
| Started | Jan 10 01:43:00 PM PST 24 |
| Finished | Jan 10 01:43:08 PM PST 24 |
| Peak memory | 552480 kb |
| Host | smart-68864053-6fb5-4bc4-bbe5-9b0b90a3a017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455288277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .455288277 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.3731039651 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 8331772916 ps |
| CPU time | 330.94 seconds |
| Started | Jan 10 01:43:22 PM PST 24 |
| Finished | Jan 10 01:48:56 PM PST 24 |
| Peak memory | 558004 kb |
| Host | smart-eddeceb1-3047-459e-b4e4-6da8d8b5ac92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731039651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.3731039651 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.733171823 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 11336117267 ps |
| CPU time | 382.98 seconds |
| Started | Jan 10 01:43:22 PM PST 24 |
| Finished | Jan 10 01:49:48 PM PST 24 |
| Peak memory | 556296 kb |
| Host | smart-5f9ee65e-1125-4607-b5f3-6eec265f440f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733171823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.733171823 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.947443286 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 9757131747 ps |
| CPU time | 548.13 seconds |
| Started | Jan 10 01:43:27 PM PST 24 |
| Finished | Jan 10 01:52:40 PM PST 24 |
| Peak memory | 557312 kb |
| Host | smart-187da018-25bd-4db7-bf84-8fce46be30df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947443286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_ with_rand_reset.947443286 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.659239637 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 15570017120 ps |
| CPU time | 704.14 seconds |
| Started | Jan 10 01:43:31 PM PST 24 |
| Finished | Jan 10 01:55:17 PM PST 24 |
| Peak memory | 559880 kb |
| Host | smart-ca862b4d-3fb9-441d-ace3-01c266c45a18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659239637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_reset_error.659239637 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3676664274 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 129374038 ps |
| CPU time | 17.61 seconds |
| Started | Jan 10 01:43:25 PM PST 24 |
| Finished | Jan 10 01:43:49 PM PST 24 |
| Peak memory | 555088 kb |
| Host | smart-34aa53ab-d67f-4931-87fb-fcc50d91e0ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676664274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.3676664274 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.441476887 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 666814815 ps |
| CPU time | 49.59 seconds |
| Started | Jan 10 01:43:20 PM PST 24 |
| Finished | Jan 10 01:44:13 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-22b50f2a-3610-41b7-9bf2-6136a37117ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441476887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device. 441476887 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.584284031 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 88384587919 ps |
| CPU time | 1461.34 seconds |
| Started | Jan 10 01:43:27 PM PST 24 |
| Finished | Jan 10 02:07:53 PM PST 24 |
| Peak memory | 555132 kb |
| Host | smart-1bdedc9e-f073-4f4a-9082-a906c908dcc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584284031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_d evice_slow_rsp.584284031 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.807034116 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 184482102 ps |
| CPU time | 9.8 seconds |
| Started | Jan 10 01:43:19 PM PST 24 |
| Finished | Jan 10 01:43:30 PM PST 24 |
| Peak memory | 552792 kb |
| Host | smart-cef567e6-655c-417e-b883-7f49d657e237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807034116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_addr .807034116 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.3070465030 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 1935305107 ps |
| CPU time | 66.71 seconds |
| Started | Jan 10 01:43:21 PM PST 24 |
| Finished | Jan 10 01:44:31 PM PST 24 |
| Peak memory | 554688 kb |
| Host | smart-7b30b3d8-7c7c-4776-9734-7cfccca85a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070465030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.3070465030 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.611798900 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 34771243 ps |
| CPU time | 5.69 seconds |
| Started | Jan 10 01:43:31 PM PST 24 |
| Finished | Jan 10 01:43:39 PM PST 24 |
| Peak memory | 552676 kb |
| Host | smart-078bbbf5-f7f3-4244-aed5-ae9f1d3d168c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611798900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.611798900 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.2164654096 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 11646147899 ps |
| CPU time | 124.95 seconds |
| Started | Jan 10 01:43:34 PM PST 24 |
| Finished | Jan 10 01:45:40 PM PST 24 |
| Peak memory | 552836 kb |
| Host | smart-3a9b9166-a1a7-4443-bd69-c44ec29582bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164654096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.2164654096 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3971660148 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 7193968450 ps |
| CPU time | 118.86 seconds |
| Started | Jan 10 01:43:33 PM PST 24 |
| Finished | Jan 10 01:45:33 PM PST 24 |
| Peak memory | 553028 kb |
| Host | smart-b536937a-8c1f-483c-b645-0108d35a46eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971660148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3971660148 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.1538689146 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 237429111 ps |
| CPU time | 20.3 seconds |
| Started | Jan 10 01:43:33 PM PST 24 |
| Finished | Jan 10 01:43:54 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-deef91a7-d943-4c2f-a6bd-780726e513d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538689146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.1538689146 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.3920251071 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 850465870 ps |
| CPU time | 25.73 seconds |
| Started | Jan 10 01:43:19 PM PST 24 |
| Finished | Jan 10 01:43:46 PM PST 24 |
| Peak memory | 555152 kb |
| Host | smart-6e27c8c6-93a4-4ee5-8988-bdc320e964af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920251071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.3920251071 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.642387292 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 156338549 ps |
| CPU time | 7.38 seconds |
| Started | Jan 10 01:43:33 PM PST 24 |
| Finished | Jan 10 01:43:42 PM PST 24 |
| Peak memory | 552948 kb |
| Host | smart-b36c13e4-dea9-4511-bae1-0e41319f7798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642387292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.642387292 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.1116847629 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 7531650771 ps |
| CPU time | 84.13 seconds |
| Started | Jan 10 01:43:11 PM PST 24 |
| Finished | Jan 10 01:44:37 PM PST 24 |
| Peak memory | 552896 kb |
| Host | smart-3746fce0-b7ec-44f8-8210-17f141bd08d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116847629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1116847629 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2239766741 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 4222928653 ps |
| CPU time | 71.61 seconds |
| Started | Jan 10 01:43:40 PM PST 24 |
| Finished | Jan 10 01:44:54 PM PST 24 |
| Peak memory | 552916 kb |
| Host | smart-e445aaba-ae16-44cd-8bc1-52b8529b68ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239766741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2239766741 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1555487054 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 54457281 ps |
| CPU time | 6.83 seconds |
| Started | Jan 10 01:43:21 PM PST 24 |
| Finished | Jan 10 01:43:31 PM PST 24 |
| Peak memory | 552968 kb |
| Host | smart-a289dd6c-0a47-43ef-877a-88e08dcb5c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555487054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.1555487054 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1689273976 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 40054694 ps |
| CPU time | 5.57 seconds |
| Started | Jan 10 01:43:35 PM PST 24 |
| Finished | Jan 10 01:43:42 PM PST 24 |
| Peak memory | 552976 kb |
| Host | smart-dd5c7825-6658-490b-bcf0-a19d7d9bcffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689273976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1689273976 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3267320809 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 2882719275 ps |
| CPU time | 104.26 seconds |
| Started | Jan 10 01:43:35 PM PST 24 |
| Finished | Jan 10 01:45:20 PM PST 24 |
| Peak memory | 556044 kb |
| Host | smart-4c34354d-48f6-4716-92db-2d38cb7cddf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267320809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3267320809 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.3547441405 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1460761402 ps |
| CPU time | 228.71 seconds |
| Started | Jan 10 01:43:25 PM PST 24 |
| Finished | Jan 10 01:47:19 PM PST 24 |
| Peak memory | 556948 kb |
| Host | smart-bd81c71d-138c-4abe-98b2-effeaf9e6f67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547441405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.3547441405 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3913464780 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 273928630 ps |
| CPU time | 64.98 seconds |
| Started | Jan 10 01:43:18 PM PST 24 |
| Finished | Jan 10 01:44:24 PM PST 24 |
| Peak memory | 555948 kb |
| Host | smart-1124c23a-6560-4845-9d7c-10ff59a4fd88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913464780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.3913464780 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1204685394 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 1348091591 ps |
| CPU time | 52.08 seconds |
| Started | Jan 10 01:43:30 PM PST 24 |
| Finished | Jan 10 01:44:25 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-6ad15281-2cb3-4e9f-bd35-1cfdaadd75b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204685394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.1204685394 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1668287946 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 3132984835 ps |
| CPU time | 133.75 seconds |
| Started | Jan 10 01:43:23 PM PST 24 |
| Finished | Jan 10 01:45:42 PM PST 24 |
| Peak memory | 555160 kb |
| Host | smart-cf2731d0-b9d2-4082-8789-f87f904e2e11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668287946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1668287946 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3639290890 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 154548028282 ps |
| CPU time | 2691.21 seconds |
| Started | Jan 10 01:43:38 PM PST 24 |
| Finished | Jan 10 02:28:32 PM PST 24 |
| Peak memory | 556196 kb |
| Host | smart-d814e6a4-5702-456e-b04e-75b6df7a9fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639290890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.3639290890 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3068887578 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 471952973 ps |
| CPU time | 19.54 seconds |
| Started | Jan 10 01:43:23 PM PST 24 |
| Finished | Jan 10 01:43:47 PM PST 24 |
| Peak memory | 554712 kb |
| Host | smart-5e26f9fd-36bb-42bf-ab04-e26c7185d38a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068887578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.3068887578 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.3736014475 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 528294933 ps |
| CPU time | 39.54 seconds |
| Started | Jan 10 01:43:24 PM PST 24 |
| Finished | Jan 10 01:44:09 PM PST 24 |
| Peak memory | 554972 kb |
| Host | smart-cab87f71-4bf9-47d6-9656-8ae5620ce386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736014475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.3736014475 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.2458386548 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 923969085 ps |
| CPU time | 32.78 seconds |
| Started | Jan 10 01:43:32 PM PST 24 |
| Finished | Jan 10 01:44:06 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-e991add6-7ddd-4c0b-9157-728d23bd35e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458386548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2458386548 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1063812406 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 57327846143 ps |
| CPU time | 675.11 seconds |
| Started | Jan 10 01:43:37 PM PST 24 |
| Finished | Jan 10 01:54:54 PM PST 24 |
| Peak memory | 554012 kb |
| Host | smart-bd9f1f6a-ba9e-4ce8-82b8-691e3fa5b890 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063812406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1063812406 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.77448636 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 32502895419 ps |
| CPU time | 565.57 seconds |
| Started | Jan 10 01:43:19 PM PST 24 |
| Finished | Jan 10 01:52:46 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-a08be6de-f293-45fb-933c-80948d3d3991 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77448636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.77448636 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.298716882 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 134986533 ps |
| CPU time | 14.02 seconds |
| Started | Jan 10 01:43:22 PM PST 24 |
| Finished | Jan 10 01:43:39 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-807c60fd-da1c-4480-9bff-b917758e1856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298716882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela ys.298716882 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1266604137 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 324338231 ps |
| CPU time | 23.9 seconds |
| Started | Jan 10 01:43:36 PM PST 24 |
| Finished | Jan 10 01:44:02 PM PST 24 |
| Peak memory | 554944 kb |
| Host | smart-de2f5a9a-5dd2-4b55-9e3a-af1c2d253be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266604137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1266604137 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.2917975986 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 126691454 ps |
| CPU time | 7.41 seconds |
| Started | Jan 10 01:43:36 PM PST 24 |
| Finished | Jan 10 01:43:46 PM PST 24 |
| Peak memory | 552948 kb |
| Host | smart-5d04b403-abca-48bb-9946-fad084493092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917975986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2917975986 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2949502348 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 8167195617 ps |
| CPU time | 88.16 seconds |
| Started | Jan 10 01:43:18 PM PST 24 |
| Finished | Jan 10 01:44:48 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-5875f11d-817c-4e0b-a74e-578f6939264a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949502348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2949502348 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3956384615 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 5396723073 ps |
| CPU time | 91.31 seconds |
| Started | Jan 10 01:43:28 PM PST 24 |
| Finished | Jan 10 01:45:03 PM PST 24 |
| Peak memory | 552960 kb |
| Host | smart-1d70f028-5ae3-4061-885c-b283b95d2fbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956384615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3956384615 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2063322294 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 47032071 ps |
| CPU time | 6.02 seconds |
| Started | Jan 10 01:43:25 PM PST 24 |
| Finished | Jan 10 01:43:37 PM PST 24 |
| Peak memory | 552676 kb |
| Host | smart-1e7467cf-3c2e-46ae-8d98-d1211d960c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063322294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.2063322294 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1403943141 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 2675706313 ps |
| CPU time | 181.99 seconds |
| Started | Jan 10 01:43:34 PM PST 24 |
| Finished | Jan 10 01:46:37 PM PST 24 |
| Peak memory | 556244 kb |
| Host | smart-26fc5dd6-1ac5-4275-8076-d92e9551a8b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403943141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1403943141 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2594692630 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 1683256617 ps |
| CPU time | 409.09 seconds |
| Started | Jan 10 01:43:24 PM PST 24 |
| Finished | Jan 10 01:50:20 PM PST 24 |
| Peak memory | 557932 kb |
| Host | smart-8e85dfb2-b2b3-4ae5-9f93-26d9b94b2cc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594692630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.2594692630 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3396207190 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 115005227 ps |
| CPU time | 34.92 seconds |
| Started | Jan 10 01:43:24 PM PST 24 |
| Finished | Jan 10 01:44:05 PM PST 24 |
| Peak memory | 553900 kb |
| Host | smart-5666865f-4fcd-4115-8f1a-aff92bc48312 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396207190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3396207190 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.322533761 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 1542499465 ps |
| CPU time | 63.1 seconds |
| Started | Jan 10 01:43:28 PM PST 24 |
| Finished | Jan 10 01:44:35 PM PST 24 |
| Peak memory | 553916 kb |
| Host | smart-5eac257e-e904-4137-8df4-4dbd36a474cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322533761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.322533761 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.165706323 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 787987391 ps |
| CPU time | 31.93 seconds |
| Started | Jan 10 01:43:42 PM PST 24 |
| Finished | Jan 10 01:44:17 PM PST 24 |
| Peak memory | 552948 kb |
| Host | smart-d6d6fae1-06e3-49fb-9fe1-5f2f57b57020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165706323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device. 165706323 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2896489540 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 90625992176 ps |
| CPU time | 1581.54 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 02:10:09 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-3fc3e058-6a42-47be-ac8d-6709fba6b429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896489540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.2896489540 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.597103470 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 1352274497 ps |
| CPU time | 51.6 seconds |
| Started | Jan 10 01:43:40 PM PST 24 |
| Finished | Jan 10 01:44:34 PM PST 24 |
| Peak memory | 553816 kb |
| Host | smart-05020fbc-e168-4eaa-bdab-5f6433129484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597103470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr .597103470 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.93494264 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 443621923 ps |
| CPU time | 17.14 seconds |
| Started | Jan 10 01:43:34 PM PST 24 |
| Finished | Jan 10 01:43:52 PM PST 24 |
| Peak memory | 554700 kb |
| Host | smart-dd22e017-1efe-4d09-8d0d-6a5d37c30840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93494264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.93494264 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2203517299 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 1158637866 ps |
| CPU time | 41.51 seconds |
| Started | Jan 10 01:43:19 PM PST 24 |
| Finished | Jan 10 01:44:02 PM PST 24 |
| Peak memory | 555088 kb |
| Host | smart-63973a60-62f3-42e9-959b-29d0b3fad4a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203517299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2203517299 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3567533106 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 7596407446 ps |
| CPU time | 83.98 seconds |
| Started | Jan 10 01:43:45 PM PST 24 |
| Finished | Jan 10 01:45:13 PM PST 24 |
| Peak memory | 552940 kb |
| Host | smart-ca38cd30-ac14-46bb-acb6-790bd1a42318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567533106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3567533106 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.1058183387 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 67601954323 ps |
| CPU time | 1186.57 seconds |
| Started | Jan 10 01:43:36 PM PST 24 |
| Finished | Jan 10 02:03:25 PM PST 24 |
| Peak memory | 555052 kb |
| Host | smart-34c8ae5f-bbd7-4268-9212-066466f3c1db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058183387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.1058183387 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.1346572653 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 512262840 ps |
| CPU time | 44.46 seconds |
| Started | Jan 10 01:43:24 PM PST 24 |
| Finished | Jan 10 01:44:14 PM PST 24 |
| Peak memory | 553960 kb |
| Host | smart-3f31e3fe-3ee1-4478-8103-a4b1a206bb7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346572653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.1346572653 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.3716043377 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 1845968020 ps |
| CPU time | 54.41 seconds |
| Started | Jan 10 01:43:41 PM PST 24 |
| Finished | Jan 10 01:44:39 PM PST 24 |
| Peak memory | 554756 kb |
| Host | smart-f691bd5d-5fdc-4f33-a6be-d137e27a51bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716043377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.3716043377 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.3675304350 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 40072330 ps |
| CPU time | 5.47 seconds |
| Started | Jan 10 01:43:19 PM PST 24 |
| Finished | Jan 10 01:43:26 PM PST 24 |
| Peak memory | 552684 kb |
| Host | smart-ca90c808-1f92-4334-9d22-8080256e6574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675304350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3675304350 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.3493901643 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 9919541439 ps |
| CPU time | 102.71 seconds |
| Started | Jan 10 01:43:23 PM PST 24 |
| Finished | Jan 10 01:45:09 PM PST 24 |
| Peak memory | 552988 kb |
| Host | smart-ca3c7274-9574-4ddb-a9bc-4a8190ae7e60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493901643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.3493901643 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3513579145 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 2937894105 ps |
| CPU time | 46.9 seconds |
| Started | Jan 10 01:43:37 PM PST 24 |
| Finished | Jan 10 01:44:26 PM PST 24 |
| Peak memory | 552964 kb |
| Host | smart-a4e27590-bc71-43cb-b9bb-60d2891af752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513579145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3513579145 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1632008979 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 52628124 ps |
| CPU time | 6.15 seconds |
| Started | Jan 10 01:43:18 PM PST 24 |
| Finished | Jan 10 01:43:26 PM PST 24 |
| Peak memory | 552976 kb |
| Host | smart-631bec8d-6047-43bc-9687-6f6fda11dee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632008979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.1632008979 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.3267925726 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 13657810624 ps |
| CPU time | 484.03 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 01:51:54 PM PST 24 |
| Peak memory | 556368 kb |
| Host | smart-b6eedea2-371b-4c70-903d-7446539232af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267925726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.3267925726 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.511507229 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 3300204126 ps |
| CPU time | 99.8 seconds |
| Started | Jan 10 01:43:38 PM PST 24 |
| Finished | Jan 10 01:45:20 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-df3b1b7c-553e-4dc7-967b-61a53bb1fcd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511507229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.511507229 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2997519935 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 410172397 ps |
| CPU time | 162.11 seconds |
| Started | Jan 10 01:43:48 PM PST 24 |
| Finished | Jan 10 01:46:33 PM PST 24 |
| Peak memory | 556764 kb |
| Host | smart-2e2727f5-9cb1-4312-bc70-2150d29be18d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997519935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.2997519935 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.1433851622 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 3201752163 ps |
| CPU time | 268.66 seconds |
| Started | Jan 10 01:43:49 PM PST 24 |
| Finished | Jan 10 01:48:21 PM PST 24 |
| Peak memory | 556944 kb |
| Host | smart-6784c428-3a6f-4f69-897b-9918ebcc9626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433851622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.1433851622 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.3053834876 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 159455947 ps |
| CPU time | 18.55 seconds |
| Started | Jan 10 01:43:45 PM PST 24 |
| Finished | Jan 10 01:44:08 PM PST 24 |
| Peak memory | 555040 kb |
| Host | smart-336559ae-396c-477a-82c1-60985928fd72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053834876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.3053834876 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3810642022 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 5093699794 ps |
| CPU time | 518.17 seconds |
| Started | Jan 10 01:36:22 PM PST 24 |
| Finished | Jan 10 01:45:06 PM PST 24 |
| Peak memory | 580856 kb |
| Host | smart-3a818279-9f8c-44fc-8383-e46fc77086f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810642022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3810642022 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2449501777 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 17609580639 ps |
| CPU time | 2447.31 seconds |
| Started | Jan 10 01:36:02 PM PST 24 |
| Finished | Jan 10 02:17:00 PM PST 24 |
| Peak memory | 580768 kb |
| Host | smart-58722c55-e92a-45a5-b80e-939bda9f875f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449501777 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2449501777 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.566702085 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2793305704 ps |
| CPU time | 162.81 seconds |
| Started | Jan 10 01:36:00 PM PST 24 |
| Finished | Jan 10 01:38:54 PM PST 24 |
| Peak memory | 580848 kb |
| Host | smart-628336a1-a500-4cac-80c0-310d41216cc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566702085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.566702085 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.2753408128 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 2009493225 ps |
| CPU time | 83.31 seconds |
| Started | Jan 10 01:36:31 PM PST 24 |
| Finished | Jan 10 01:37:57 PM PST 24 |
| Peak memory | 554728 kb |
| Host | smart-1224c2ba-cd68-4914-b9fc-58235a8a21f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753408128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 2753408128 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.792237270 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 34214745695 ps |
| CPU time | 545.45 seconds |
| Started | Jan 10 01:36:24 PM PST 24 |
| Finished | Jan 10 01:45:35 PM PST 24 |
| Peak memory | 556112 kb |
| Host | smart-c0266f19-cedd-4df3-af9d-a1dc89cea6f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792237270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_de vice_slow_rsp.792237270 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1103296775 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 85839487 ps |
| CPU time | 6.06 seconds |
| Started | Jan 10 01:36:18 PM PST 24 |
| Finished | Jan 10 01:36:30 PM PST 24 |
| Peak memory | 552988 kb |
| Host | smart-6e742be5-59f9-4cc8-aea5-16adad747bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103296775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .1103296775 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.604967468 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 1390235088 ps |
| CPU time | 51.02 seconds |
| Started | Jan 10 01:36:33 PM PST 24 |
| Finished | Jan 10 01:37:26 PM PST 24 |
| Peak memory | 554624 kb |
| Host | smart-0cda1b2a-1b18-4ca7-8e1e-156b9cc2f330 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604967468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.604967468 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.3320939407 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 1718154884 ps |
| CPU time | 65.56 seconds |
| Started | Jan 10 01:36:32 PM PST 24 |
| Finished | Jan 10 01:37:40 PM PST 24 |
| Peak memory | 553916 kb |
| Host | smart-4e2f50c7-188e-4f16-a187-9b0cdb170eb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320939407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3320939407 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.975637 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 17827703087 ps |
| CPU time | 199.11 seconds |
| Started | Jan 10 01:36:27 PM PST 24 |
| Finished | Jan 10 01:39:51 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-4e8a4d85-ee47-4047-9ea9-5c5d0bedc393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.975637 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1620849433 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 65959263388 ps |
| CPU time | 1175.56 seconds |
| Started | Jan 10 01:36:34 PM PST 24 |
| Finished | Jan 10 01:56:11 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-6f87ef46-8dcd-443e-91e1-003bd711e76e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620849433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1620849433 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.2516793238 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 157499394 ps |
| CPU time | 14.72 seconds |
| Started | Jan 10 01:36:30 PM PST 24 |
| Finished | Jan 10 01:36:48 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-3f14f7d1-25a0-4520-9de3-b410b883340c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516793238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.2516793238 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2052574585 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 468294020 ps |
| CPU time | 34.01 seconds |
| Started | Jan 10 01:36:12 PM PST 24 |
| Finished | Jan 10 01:36:52 PM PST 24 |
| Peak memory | 554748 kb |
| Host | smart-44b56dad-405d-4a35-a880-d5afe824bf8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052574585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2052574585 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.1674585238 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 43817393 ps |
| CPU time | 5.73 seconds |
| Started | Jan 10 01:36:09 PM PST 24 |
| Finished | Jan 10 01:36:21 PM PST 24 |
| Peak memory | 552532 kb |
| Host | smart-0e9964b2-f8cc-42ec-b4cd-a743cc8f85d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674585238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1674585238 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.1477845195 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 8059532535 ps |
| CPU time | 87.92 seconds |
| Started | Jan 10 01:36:04 PM PST 24 |
| Finished | Jan 10 01:37:41 PM PST 24 |
| Peak memory | 552696 kb |
| Host | smart-084f859e-0a83-4af3-83ce-68dea9c179a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477845195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1477845195 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.3755427998 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 5875774651 ps |
| CPU time | 98.97 seconds |
| Started | Jan 10 01:36:21 PM PST 24 |
| Finished | Jan 10 01:38:06 PM PST 24 |
| Peak memory | 552688 kb |
| Host | smart-1f764625-e93d-4338-8ec5-7f38de5a4a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755427998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.3755427998 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.462095832 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 33961611 ps |
| CPU time | 5.07 seconds |
| Started | Jan 10 01:36:07 PM PST 24 |
| Finished | Jan 10 01:36:19 PM PST 24 |
| Peak memory | 552640 kb |
| Host | smart-e37d4039-9b61-4465-a831-9a63639ff868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462095832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 462095832 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.3872017191 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 8653343985 ps |
| CPU time | 305.15 seconds |
| Started | Jan 10 01:36:21 PM PST 24 |
| Finished | Jan 10 01:41:32 PM PST 24 |
| Peak memory | 555932 kb |
| Host | smart-a2c71b7a-d558-438c-a323-b89952f0e82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872017191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3872017191 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.3364633437 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 2541504431 ps |
| CPU time | 79.95 seconds |
| Started | Jan 10 01:36:26 PM PST 24 |
| Finished | Jan 10 01:37:51 PM PST 24 |
| Peak memory | 555848 kb |
| Host | smart-2e1dffbc-73fd-4dc4-bde9-362dfc9ad1fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364633437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3364633437 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3571503739 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 15018608940 ps |
| CPU time | 806.15 seconds |
| Started | Jan 10 01:36:33 PM PST 24 |
| Finished | Jan 10 01:50:02 PM PST 24 |
| Peak memory | 558340 kb |
| Host | smart-16e7f760-0c0c-4a98-b322-2881985f43c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571503739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.3571503739 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3707852761 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2254580597 ps |
| CPU time | 254.74 seconds |
| Started | Jan 10 01:36:33 PM PST 24 |
| Finished | Jan 10 01:40:50 PM PST 24 |
| Peak memory | 559940 kb |
| Host | smart-86eb93f2-76f5-4837-a400-2b25202dc9c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707852761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3707852761 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1624317526 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 1234664620 ps |
| CPU time | 50.01 seconds |
| Started | Jan 10 01:36:23 PM PST 24 |
| Finished | Jan 10 01:37:19 PM PST 24 |
| Peak memory | 554740 kb |
| Host | smart-39b09e0d-944c-46d1-a479-9b6c6cb839e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624317526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1624317526 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.187752181 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 2671079829 ps |
| CPU time | 104.81 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:45:38 PM PST 24 |
| Peak memory | 554868 kb |
| Host | smart-de7fa9a8-1ac6-4e4a-9ec1-0bcf7443eb86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187752181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device. 187752181 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3351175965 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 122868460 ps |
| CPU time | 13.24 seconds |
| Started | Jan 10 01:43:39 PM PST 24 |
| Finished | Jan 10 01:43:54 PM PST 24 |
| Peak memory | 553924 kb |
| Host | smart-3141b680-1326-4c7c-8d33-be8314700abb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351175965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.3351175965 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.2032732408 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 54524296 ps |
| CPU time | 6.87 seconds |
| Started | Jan 10 01:43:35 PM PST 24 |
| Finished | Jan 10 01:43:43 PM PST 24 |
| Peak memory | 552972 kb |
| Host | smart-71bddf3d-bb3c-4fbb-acfb-e997bf0a4319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032732408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.2032732408 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.1873569627 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2340859302 ps |
| CPU time | 89.82 seconds |
| Started | Jan 10 01:43:49 PM PST 24 |
| Finished | Jan 10 01:45:22 PM PST 24 |
| Peak memory | 554752 kb |
| Host | smart-db115bb0-0770-4e35-9cd0-ce4e8dd64252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873569627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.1873569627 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3793873252 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 102499618894 ps |
| CPU time | 1159.63 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 02:03:10 PM PST 24 |
| Peak memory | 555156 kb |
| Host | smart-e2a395fe-cce1-4c7e-89a5-523e6c7e4fa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793873252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3793873252 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.441538393 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 30144294765 ps |
| CPU time | 519.8 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:52:25 PM PST 24 |
| Peak memory | 554016 kb |
| Host | smart-abe4b379-480e-4054-9eda-34e913d831fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441538393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.441538393 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.4076159241 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 553803604 ps |
| CPU time | 43.83 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:44:34 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-dc7067ee-dad0-47fa-8c85-bbd390f23229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076159241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.4076159241 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.1898013869 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 110589995 ps |
| CPU time | 10.33 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:04 PM PST 24 |
| Peak memory | 555044 kb |
| Host | smart-54b52469-9ed3-49ae-b8fd-5dfc79c5c8c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898013869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.1898013869 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.1431243011 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 223944476 ps |
| CPU time | 8.43 seconds |
| Started | Jan 10 01:43:42 PM PST 24 |
| Finished | Jan 10 01:43:53 PM PST 24 |
| Peak memory | 552932 kb |
| Host | smart-b85a48a9-9949-457d-9565-7d17d2dbde89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431243011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1431243011 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.1597199681 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 5465062840 ps |
| CPU time | 56.71 seconds |
| Started | Jan 10 01:43:36 PM PST 24 |
| Finished | Jan 10 01:44:34 PM PST 24 |
| Peak memory | 552896 kb |
| Host | smart-224b1205-6f84-48b5-ad6f-e8b60066a1fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597199681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.1597199681 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.641325059 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 5410494950 ps |
| CPU time | 94.43 seconds |
| Started | Jan 10 01:43:49 PM PST 24 |
| Finished | Jan 10 01:45:27 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-b4804e10-34e9-474c-a083-31dc4ec05dbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641325059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.641325059 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1864411484 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 44853202 ps |
| CPU time | 5.93 seconds |
| Started | Jan 10 01:43:35 PM PST 24 |
| Finished | Jan 10 01:43:42 PM PST 24 |
| Peak memory | 552632 kb |
| Host | smart-c56fffe7-ccca-4a9d-b63f-1e679271ce99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864411484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.1864411484 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.2074244883 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 1616534824 ps |
| CPU time | 119.79 seconds |
| Started | Jan 10 01:43:49 PM PST 24 |
| Finished | Jan 10 01:45:52 PM PST 24 |
| Peak memory | 555824 kb |
| Host | smart-0a67f0de-ffb4-48f4-9049-13ecbf9f155a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074244883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2074244883 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.1494580969 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 10719148246 ps |
| CPU time | 385.88 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:50:12 PM PST 24 |
| Peak memory | 556416 kb |
| Host | smart-fcf3edf2-82b6-433d-9213-fbcbb5ff4bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494580969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.1494580969 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1296493177 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 246266426 ps |
| CPU time | 126.44 seconds |
| Started | Jan 10 01:43:44 PM PST 24 |
| Finished | Jan 10 01:45:55 PM PST 24 |
| Peak memory | 556480 kb |
| Host | smart-3f4b819c-4f55-4d55-a1f0-de836cb802df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296493177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.1296493177 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.582749946 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 2563066348 ps |
| CPU time | 172.48 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:46:40 PM PST 24 |
| Peak memory | 556620 kb |
| Host | smart-c27fda88-c932-4dc8-b85c-3dd71ac7b8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582749946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_reset_error.582749946 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.1640186961 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 572569302 ps |
| CPU time | 25.7 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:44:18 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-f9e5803b-28a8-4182-a67a-c56851c5508c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640186961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.1640186961 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3465954524 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 16282373 ps |
| CPU time | 5.83 seconds |
| Started | Jan 10 01:43:42 PM PST 24 |
| Finished | Jan 10 01:43:51 PM PST 24 |
| Peak memory | 552740 kb |
| Host | smart-36fdedba-721f-44d5-ae68-f74503bc7a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465954524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .3465954524 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.457247185 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 57014214877 ps |
| CPU time | 976.37 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 02:00:07 PM PST 24 |
| Peak memory | 555224 kb |
| Host | smart-da8fc421-d1fe-43a4-9915-6f689d5f690d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457247185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_d evice_slow_rsp.457247185 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.97563432 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 1326539905 ps |
| CPU time | 52.5 seconds |
| Started | Jan 10 01:43:36 PM PST 24 |
| Finished | Jan 10 01:44:31 PM PST 24 |
| Peak memory | 553892 kb |
| Host | smart-b2ac5d82-d8b8-4666-944e-3199cb2eb125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97563432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr.97563432 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.1952642974 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 1994930472 ps |
| CPU time | 67.49 seconds |
| Started | Jan 10 01:43:34 PM PST 24 |
| Finished | Jan 10 01:44:43 PM PST 24 |
| Peak memory | 554652 kb |
| Host | smart-d8e3a095-b041-4c23-abaf-db9bd616a2de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952642974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.1952642974 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.196715553 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 283764441 ps |
| CPU time | 25.58 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:44:12 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-2d4d2ee9-fd08-443c-8e4f-b84fa47e22a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196715553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.196715553 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.3886400391 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 111341809974 ps |
| CPU time | 1276.35 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 02:05:06 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-d53506bb-7356-42e2-b374-aaec03bee0ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886400391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.3886400391 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2349711449 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 38531343535 ps |
| CPU time | 708.57 seconds |
| Started | Jan 10 01:43:34 PM PST 24 |
| Finished | Jan 10 01:55:24 PM PST 24 |
| Peak memory | 554852 kb |
| Host | smart-6f03cbae-14f2-4d44-88b9-660f9943dfbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349711449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2349711449 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.3805923918 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 226211736 ps |
| CPU time | 17.99 seconds |
| Started | Jan 10 01:43:37 PM PST 24 |
| Finished | Jan 10 01:43:57 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-c5833ee1-c2c5-466a-8dd2-dffc692d1a8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805923918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.3805923918 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.406999093 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 2089894375 ps |
| CPU time | 58.67 seconds |
| Started | Jan 10 01:43:41 PM PST 24 |
| Finished | Jan 10 01:44:43 PM PST 24 |
| Peak memory | 553960 kb |
| Host | smart-9b3fc980-cf0f-442a-a647-4fb7faaf66bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406999093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.406999093 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.2179512098 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 163923320 ps |
| CPU time | 7.47 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:02 PM PST 24 |
| Peak memory | 552596 kb |
| Host | smart-947fc00d-5514-405b-a018-ffd497b52262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179512098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.2179512098 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1048951961 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 7638549656 ps |
| CPU time | 75.6 seconds |
| Started | Jan 10 01:43:42 PM PST 24 |
| Finished | Jan 10 01:45:00 PM PST 24 |
| Peak memory | 553048 kb |
| Host | smart-39b112e1-74d6-4c40-aa0f-873e6d156f44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048951961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.1048951961 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.4163046519 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 3840331901 ps |
| CPU time | 64.48 seconds |
| Started | Jan 10 01:43:35 PM PST 24 |
| Finished | Jan 10 01:44:40 PM PST 24 |
| Peak memory | 553032 kb |
| Host | smart-862b489a-dd89-40b8-8ad1-d83320758618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163046519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.4163046519 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3563327110 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 48407222 ps |
| CPU time | 6.2 seconds |
| Started | Jan 10 01:43:45 PM PST 24 |
| Finished | Jan 10 01:43:55 PM PST 24 |
| Peak memory | 552668 kb |
| Host | smart-b6bf38d3-dc59-4a14-8151-9805567bcd0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563327110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.3563327110 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.3116121758 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 823795083 ps |
| CPU time | 67.66 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:44:58 PM PST 24 |
| Peak memory | 555876 kb |
| Host | smart-e583fdff-446b-4454-9b91-a5e83c8274e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116121758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.3116121758 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.2533520177 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 11020942516 ps |
| CPU time | 375.06 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:50:01 PM PST 24 |
| Peak memory | 556252 kb |
| Host | smart-1e141f16-5dea-445f-89fd-277fbb6b8b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533520177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.2533520177 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.853198166 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 525635823 ps |
| CPU time | 177.74 seconds |
| Started | Jan 10 01:43:33 PM PST 24 |
| Finished | Jan 10 01:46:32 PM PST 24 |
| Peak memory | 557596 kb |
| Host | smart-63e4957b-4f62-4184-9d99-6be78a0be851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853198166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_ with_rand_reset.853198166 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3195323629 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 300902272 ps |
| CPU time | 148.57 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:46:14 PM PST 24 |
| Peak memory | 558624 kb |
| Host | smart-1ed5a41a-80d3-42c7-baed-dedb28e8f844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195323629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.3195323629 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3258532511 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 811212542 ps |
| CPU time | 32.03 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:44:25 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-eff3bfb6-fc5f-4ac9-93ad-c1ca6b874e0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258532511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3258532511 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.1458043912 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 423042218 ps |
| CPU time | 34.97 seconds |
| Started | Jan 10 01:43:39 PM PST 24 |
| Finished | Jan 10 01:44:16 PM PST 24 |
| Peak memory | 554832 kb |
| Host | smart-63d79eb4-0e1e-4892-a4a8-1d259fe2222b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458043912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .1458043912 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1221020020 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 87162906305 ps |
| CPU time | 1392.94 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 02:07:04 PM PST 24 |
| Peak memory | 553976 kb |
| Host | smart-f4426dd1-8e9e-4662-8d7c-07e2cf16370b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221020020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.1221020020 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.3180711175 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 1363401471 ps |
| CPU time | 49.57 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:44:42 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-81b25c2f-c22a-4ab2-a14b-97cdd43b43bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180711175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.3180711175 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.1615922970 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 138069407 ps |
| CPU time | 12.77 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:44:03 PM PST 24 |
| Peak memory | 554676 kb |
| Host | smart-a4f2fcf4-5226-46d9-b184-3ef2fc920800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615922970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1615922970 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.2457406904 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 2593489363 ps |
| CPU time | 94.05 seconds |
| Started | Jan 10 01:43:42 PM PST 24 |
| Finished | Jan 10 01:45:18 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-d8b58164-3aff-473e-a68b-e5f0ada19177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457406904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.2457406904 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.225729425 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 22405073523 ps |
| CPU time | 238.3 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:47:45 PM PST 24 |
| Peak memory | 555148 kb |
| Host | smart-49be2891-1c80-4fb6-89e0-c88b7d14ab52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225729425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.225729425 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.2936346794 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 61516738362 ps |
| CPU time | 979.96 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 02:00:10 PM PST 24 |
| Peak memory | 554892 kb |
| Host | smart-15744a4a-efd9-4fe6-ade8-0b49983de7e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936346794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.2936346794 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3736092664 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 243370094 ps |
| CPU time | 22.11 seconds |
| Started | Jan 10 01:43:34 PM PST 24 |
| Finished | Jan 10 01:43:57 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-340058ac-d935-415b-b626-43268cd237a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736092664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.3736092664 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.1309147468 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 235393020 ps |
| CPU time | 16.51 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 01:44:07 PM PST 24 |
| Peak memory | 554904 kb |
| Host | smart-cd8eee8e-dc75-4109-a93f-88e8b459ee34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309147468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.1309147468 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.2282687470 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 42410865 ps |
| CPU time | 5.94 seconds |
| Started | Jan 10 01:43:52 PM PST 24 |
| Finished | Jan 10 01:44:00 PM PST 24 |
| Peak memory | 552924 kb |
| Host | smart-d44bf187-5c16-4a44-9ab9-0af336e2fdd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282687470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.2282687470 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.473156273 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 7351528838 ps |
| CPU time | 69.61 seconds |
| Started | Jan 10 01:43:42 PM PST 24 |
| Finished | Jan 10 01:44:54 PM PST 24 |
| Peak memory | 553024 kb |
| Host | smart-95b342e3-c965-496c-bc9f-61a90e0360e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473156273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.473156273 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.299224403 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 4849354049 ps |
| CPU time | 74.88 seconds |
| Started | Jan 10 01:43:45 PM PST 24 |
| Finished | Jan 10 01:45:04 PM PST 24 |
| Peak memory | 552964 kb |
| Host | smart-3480ee28-9348-434b-a246-e9a892fb087c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299224403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.299224403 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2210864267 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 47744996 ps |
| CPU time | 5.94 seconds |
| Started | Jan 10 01:43:34 PM PST 24 |
| Finished | Jan 10 01:43:41 PM PST 24 |
| Peak memory | 552592 kb |
| Host | smart-c20a9ab4-d036-465f-92e0-829db663eccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210864267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.2210864267 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.2592149808 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 8215415967 ps |
| CPU time | 269.38 seconds |
| Started | Jan 10 01:43:45 PM PST 24 |
| Finished | Jan 10 01:48:19 PM PST 24 |
| Peak memory | 556296 kb |
| Host | smart-339e3796-457e-4504-a5f8-37ad6fe8c957 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592149808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2592149808 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.521160 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 5682188605 ps |
| CPU time | 164.6 seconds |
| Started | Jan 10 01:43:52 PM PST 24 |
| Finished | Jan 10 01:46:39 PM PST 24 |
| Peak memory | 556208 kb |
| Host | smart-65e9aa92-866e-434a-a700-aa59c7669163 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.521160 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1082346023 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 162190505 ps |
| CPU time | 52.17 seconds |
| Started | Jan 10 01:43:48 PM PST 24 |
| Finished | Jan 10 01:44:44 PM PST 24 |
| Peak memory | 556120 kb |
| Host | smart-45c7802f-23a5-44b3-bc7d-192c448d6578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082346023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.1082346023 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3354791920 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 977220035 ps |
| CPU time | 260.42 seconds |
| Started | Jan 10 01:43:49 PM PST 24 |
| Finished | Jan 10 01:48:13 PM PST 24 |
| Peak memory | 559772 kb |
| Host | smart-4b6cc708-8343-4ef0-bc7a-bb8c1bf16825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354791920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.3354791920 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.3945182961 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 295861501 ps |
| CPU time | 34.26 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:28 PM PST 24 |
| Peak memory | 555088 kb |
| Host | smart-e642765a-81dd-4ef1-aa29-ed9920a00d7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945182961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.3945182961 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.690497971 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 263045812 ps |
| CPU time | 26.45 seconds |
| Started | Jan 10 01:43:52 PM PST 24 |
| Finished | Jan 10 01:44:21 PM PST 24 |
| Peak memory | 553972 kb |
| Host | smart-b7ab830d-de4d-4176-aeb2-030c93cbedf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690497971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device. 690497971 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3784872210 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 156389093690 ps |
| CPU time | 2444.61 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 02:24:39 PM PST 24 |
| Peak memory | 555232 kb |
| Host | smart-8a68152f-4090-4f25-b7b7-d1e364d4c0f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784872210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.3784872210 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3808001868 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 462983743 ps |
| CPU time | 19.2 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:13 PM PST 24 |
| Peak memory | 555000 kb |
| Host | smart-c2b9928e-e496-4849-9c1e-72ae459de2f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808001868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.3808001868 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.3197910032 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 2220525953 ps |
| CPU time | 72.8 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 01:45:03 PM PST 24 |
| Peak memory | 554960 kb |
| Host | smart-e995ff7c-f832-4a81-ba54-8b9a939acc63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197910032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.3197910032 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.3524331177 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 2023668347 ps |
| CPU time | 65.43 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:59 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-cb272abf-28e5-4952-8919-65f161007594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524331177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3524331177 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.381531437 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 64642142130 ps |
| CPU time | 703.73 seconds |
| Started | Jan 10 01:43:42 PM PST 24 |
| Finished | Jan 10 01:55:29 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-99a80cca-84a6-40ed-920f-44dd443ecfb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381531437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.381531437 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.604153752 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 51843574516 ps |
| CPU time | 886.52 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:58:37 PM PST 24 |
| Peak memory | 554012 kb |
| Host | smart-5d4e53fd-cfe9-4dbe-a7a5-a18a1968382f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604153752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.604153752 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.69209203 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 272976391 ps |
| CPU time | 25.14 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:19 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-35a2956b-dd51-4c79-885b-5f6ba303ae23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69209203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_delay s.69209203 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.18553367 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 545826830 ps |
| CPU time | 16.52 seconds |
| Started | Jan 10 01:43:42 PM PST 24 |
| Finished | Jan 10 01:44:01 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-71e0128d-98cc-4af4-ba06-513a2e35168d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18553367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.18553367 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.3249172955 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 44992152 ps |
| CPU time | 5.97 seconds |
| Started | Jan 10 01:43:49 PM PST 24 |
| Finished | Jan 10 01:43:58 PM PST 24 |
| Peak memory | 552832 kb |
| Host | smart-5471f235-91c0-4985-b276-102512b45308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249172955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.3249172955 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.2431611267 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 9492180417 ps |
| CPU time | 93.27 seconds |
| Started | Jan 10 01:43:48 PM PST 24 |
| Finished | Jan 10 01:45:24 PM PST 24 |
| Peak memory | 552632 kb |
| Host | smart-01af8af4-f01d-4b4e-8010-2d2d381d7638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431611267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.2431611267 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1608702098 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 5335396127 ps |
| CPU time | 82.01 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:45:16 PM PST 24 |
| Peak memory | 552736 kb |
| Host | smart-b65e67de-6901-4c72-b6ad-99397a0f30f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608702098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1608702098 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3069271250 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 42008407 ps |
| CPU time | 5.76 seconds |
| Started | Jan 10 01:43:48 PM PST 24 |
| Finished | Jan 10 01:43:57 PM PST 24 |
| Peak memory | 552552 kb |
| Host | smart-9be0319b-1d7f-41b6-89e2-2b51b5bddf3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069271250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.3069271250 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.644221778 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 10514987181 ps |
| CPU time | 376.38 seconds |
| Started | Jan 10 01:43:48 PM PST 24 |
| Finished | Jan 10 01:50:07 PM PST 24 |
| Peak memory | 557044 kb |
| Host | smart-35e63261-f9ea-47d4-b919-55d0d0e81583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644221778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.644221778 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.817452523 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 5761462115 ps |
| CPU time | 188.14 seconds |
| Started | Jan 10 01:43:48 PM PST 24 |
| Finished | Jan 10 01:46:59 PM PST 24 |
| Peak memory | 556240 kb |
| Host | smart-e4d8c885-2d1b-4e2f-9892-ba21851a8def |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817452523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.817452523 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.1410060633 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4401507740 ps |
| CPU time | 350.11 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 01:49:40 PM PST 24 |
| Peak memory | 559132 kb |
| Host | smart-ff950298-5b9e-4ec2-91a6-8be29eaec04d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410060633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.1410060633 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2061358910 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 833705014 ps |
| CPU time | 273.21 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 01:48:23 PM PST 24 |
| Peak memory | 559816 kb |
| Host | smart-fa5e31a4-0c2f-464a-9f81-914cf8bdedf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061358910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.2061358910 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.487142409 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 486346891 ps |
| CPU time | 21.75 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:15 PM PST 24 |
| Peak memory | 554760 kb |
| Host | smart-17d9f2ae-5c11-4073-a7b3-a4086b13769e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487142409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.487142409 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.718157105 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 293917801 ps |
| CPU time | 25.33 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:44:13 PM PST 24 |
| Peak memory | 553872 kb |
| Host | smart-502eb1f2-4231-4ae0-a271-dca3fca2ad32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718157105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device. 718157105 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3224200837 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 51102639827 ps |
| CPU time | 824.33 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:57:35 PM PST 24 |
| Peak memory | 556152 kb |
| Host | smart-b45cb927-d7b1-41e8-8042-cb8cbf0840a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224200837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.3224200837 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3198664678 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 1227745119 ps |
| CPU time | 44.97 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:39 PM PST 24 |
| Peak memory | 554692 kb |
| Host | smart-51e1e035-a8d9-4a95-a462-cd98a224552c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198664678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3198664678 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.4097635707 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 143387410 ps |
| CPU time | 13.47 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:07 PM PST 24 |
| Peak memory | 553808 kb |
| Host | smart-843321d2-96fb-445e-8815-892e21289902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097635707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.4097635707 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.2025985788 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 1151761433 ps |
| CPU time | 35.39 seconds |
| Started | Jan 10 01:43:38 PM PST 24 |
| Finished | Jan 10 01:44:15 PM PST 24 |
| Peak memory | 555056 kb |
| Host | smart-13c9e156-405d-421e-aa33-42223093cae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025985788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.2025985788 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.2297145514 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 10165358011 ps |
| CPU time | 100.61 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:45:31 PM PST 24 |
| Peak memory | 552640 kb |
| Host | smart-d61805ed-9f1b-41bf-b4ab-808dd3c527d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297145514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.2297145514 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.732905598 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 39518520812 ps |
| CPU time | 692.73 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:55:27 PM PST 24 |
| Peak memory | 554836 kb |
| Host | smart-563964ed-3a31-414f-8b2b-c1a3d680a111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732905598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.732905598 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1047014124 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 68520919 ps |
| CPU time | 8.57 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:43:59 PM PST 24 |
| Peak memory | 552900 kb |
| Host | smart-c5ada316-c006-4867-b1f9-fa233f9b81b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047014124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1047014124 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.3612603315 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 352793853 ps |
| CPU time | 24.87 seconds |
| Started | Jan 10 01:43:45 PM PST 24 |
| Finished | Jan 10 01:44:14 PM PST 24 |
| Peak memory | 555080 kb |
| Host | smart-7ccb29ba-b691-4ff4-bc18-11ed9c4e4649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612603315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.3612603315 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.911842513 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 46844843 ps |
| CPU time | 6.01 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:43:57 PM PST 24 |
| Peak memory | 552884 kb |
| Host | smart-988c6cd2-eb0c-4c4f-98ed-15aff20be741 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911842513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.911842513 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2018872910 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 8488868924 ps |
| CPU time | 86.22 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:45:20 PM PST 24 |
| Peak memory | 553012 kb |
| Host | smart-6a7f21b6-3e95-4bd9-b6d4-122d9d044eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018872910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2018872910 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.595457880 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 4909233785 ps |
| CPU time | 77 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:45:11 PM PST 24 |
| Peak memory | 552956 kb |
| Host | smart-c741995c-09d1-4b2b-b051-d2fd7038c144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595457880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.595457880 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3391305531 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 52146978 ps |
| CPU time | 6.31 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:00 PM PST 24 |
| Peak memory | 552912 kb |
| Host | smart-54f16ebc-654e-4ee6-86eb-ce889fe63088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391305531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.3391305531 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.3777896105 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 1918357442 ps |
| CPU time | 165.94 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:46:36 PM PST 24 |
| Peak memory | 556148 kb |
| Host | smart-8664c97a-dd35-4a5c-9dbf-c2b99b798b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777896105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.3777896105 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.3484695765 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 1571785831 ps |
| CPU time | 91.87 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:45:18 PM PST 24 |
| Peak memory | 556116 kb |
| Host | smart-4f12e381-38cf-4ec2-8b33-bc4ad1011963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484695765 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.3484695765 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.742048388 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 4325313965 ps |
| CPU time | 626.69 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:54:21 PM PST 24 |
| Peak memory | 559980 kb |
| Host | smart-d3b90c9c-24b9-428f-a314-ab37a489c165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742048388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_ with_rand_reset.742048388 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3333097910 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 170613529 ps |
| CPU time | 55.07 seconds |
| Started | Jan 10 01:43:52 PM PST 24 |
| Finished | Jan 10 01:44:49 PM PST 24 |
| Peak memory | 556220 kb |
| Host | smart-8e197fa0-b180-48bd-86a3-078dc4dc0dc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333097910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.3333097910 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.3913108826 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 716965390 ps |
| CPU time | 27.45 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 01:44:17 PM PST 24 |
| Peak memory | 553972 kb |
| Host | smart-75c176bd-8f68-43ea-95fe-bdc30c1d7d88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913108826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.3913108826 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.3017627717 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 1146356335 ps |
| CPU time | 44.83 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:44:38 PM PST 24 |
| Peak memory | 554748 kb |
| Host | smart-b40d1194-d311-413a-8567-7f42083bd64e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017627717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .3017627717 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3784318898 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 111887530377 ps |
| CPU time | 1854.75 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 02:14:45 PM PST 24 |
| Peak memory | 555848 kb |
| Host | smart-d31bbb0b-04c1-4a84-9615-5fcc88fb2bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784318898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.3784318898 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.102421858 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 174048975 ps |
| CPU time | 9.15 seconds |
| Started | Jan 10 01:44:02 PM PST 24 |
| Finished | Jan 10 01:44:12 PM PST 24 |
| Peak memory | 552932 kb |
| Host | smart-f7621a28-5a74-44e5-9fbd-20f0b61609b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102421858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr .102421858 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.1664003286 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 1656954653 ps |
| CPU time | 50.03 seconds |
| Started | Jan 10 01:43:51 PM PST 24 |
| Finished | Jan 10 01:44:44 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-813fbacb-f8b1-4cc4-adf4-7d72d59cca68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664003286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.1664003286 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.405363897 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 226967783 ps |
| CPU time | 19.47 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:44:10 PM PST 24 |
| Peak memory | 554884 kb |
| Host | smart-b9c703ce-ef2f-41c5-b41d-a6648ba0b1b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405363897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.405363897 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3266783388 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 26650268432 ps |
| CPU time | 281.21 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 01:48:31 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-c39d7b2d-1bbc-48b8-8609-add6b7003a57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266783388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3266783388 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3245570758 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 4557209139 ps |
| CPU time | 71.29 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:45:02 PM PST 24 |
| Peak memory | 553068 kb |
| Host | smart-f9f6b884-407a-45d0-9498-eb6635ad5572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245570758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3245570758 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.3341593157 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 255282457 ps |
| CPU time | 23.54 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:44:17 PM PST 24 |
| Peak memory | 555060 kb |
| Host | smart-50e3ceb5-27dc-4a3d-8f49-029eb42596d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341593157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.3341593157 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.53211827 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 127328382 ps |
| CPU time | 11.23 seconds |
| Started | Jan 10 01:43:46 PM PST 24 |
| Finished | Jan 10 01:44:01 PM PST 24 |
| Peak memory | 555120 kb |
| Host | smart-e28f2488-f7f7-4512-b74c-b60cab1555fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53211827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.53211827 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.1825687717 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 198399156 ps |
| CPU time | 8.22 seconds |
| Started | Jan 10 01:43:43 PM PST 24 |
| Finished | Jan 10 01:43:54 PM PST 24 |
| Peak memory | 552452 kb |
| Host | smart-610d2240-bb76-47be-bd3f-6dc02bb3d694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825687717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.1825687717 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.459447850 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 7208444912 ps |
| CPU time | 67.37 seconds |
| Started | Jan 10 01:43:44 PM PST 24 |
| Finished | Jan 10 01:44:56 PM PST 24 |
| Peak memory | 553036 kb |
| Host | smart-8a496361-da85-42b3-aa8c-a0d601700e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459447850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.459447850 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2907508261 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 5410655230 ps |
| CPU time | 83.7 seconds |
| Started | Jan 10 01:43:47 PM PST 24 |
| Finished | Jan 10 01:45:14 PM PST 24 |
| Peak memory | 552632 kb |
| Host | smart-c023698c-37e4-4755-82ea-5d24558cbfb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907508261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.2907508261 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.13134589 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 49567469 ps |
| CPU time | 6.36 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:43:59 PM PST 24 |
| Peak memory | 552708 kb |
| Host | smart-e31eff36-1935-49fa-aa1a-aa3520b010ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays.13134589 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.3790378476 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 4849513944 ps |
| CPU time | 189.37 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 01:47:07 PM PST 24 |
| Peak memory | 556024 kb |
| Host | smart-8218ded0-4d27-4507-9e0d-29296f77e9b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790378476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3790378476 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2860846726 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 191951306 ps |
| CPU time | 65.22 seconds |
| Started | Jan 10 01:43:59 PM PST 24 |
| Finished | Jan 10 01:45:06 PM PST 24 |
| Peak memory | 555184 kb |
| Host | smart-f95650e7-4800-44e4-94ec-de61d2b6c9e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860846726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.2860846726 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.3446072821 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 4176345653 ps |
| CPU time | 485.01 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 01:52:03 PM PST 24 |
| Peak memory | 567968 kb |
| Host | smart-2b6acd8d-5e2f-4168-ab5d-296a6595277c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446072821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.3446072821 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.2503479555 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 553849723 ps |
| CPU time | 24.2 seconds |
| Started | Jan 10 01:43:50 PM PST 24 |
| Finished | Jan 10 01:44:17 PM PST 24 |
| Peak memory | 554832 kb |
| Host | smart-85cace5f-1e60-462e-b1e3-6b82e78fa822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503479555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.2503479555 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.2454611186 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 748362736 ps |
| CPU time | 52.86 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 01:44:51 PM PST 24 |
| Peak memory | 554736 kb |
| Host | smart-6e74d9c7-e410-42ab-aa32-1c4767721745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454611186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .2454611186 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3652851778 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 86666772508 ps |
| CPU time | 1709.26 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 02:12:27 PM PST 24 |
| Peak memory | 555088 kb |
| Host | smart-d0b0ab14-4556-4c3e-8056-52d02a63446a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652851778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3652851778 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2223274293 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 560505977 ps |
| CPU time | 21.92 seconds |
| Started | Jan 10 01:44:00 PM PST 24 |
| Finished | Jan 10 01:44:23 PM PST 24 |
| Peak memory | 554684 kb |
| Host | smart-4f0bea78-2d42-4d0d-82c6-d881cdf6dd46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223274293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2223274293 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.1516487326 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 1247756781 ps |
| CPU time | 40.45 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 01:44:38 PM PST 24 |
| Peak memory | 554972 kb |
| Host | smart-b983d50a-91d8-4812-a29b-2abfb139a2a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516487326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.1516487326 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.4023077727 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 703045072 ps |
| CPU time | 26.85 seconds |
| Started | Jan 10 01:43:59 PM PST 24 |
| Finished | Jan 10 01:44:28 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-7fa74d49-3107-4225-a12e-57b8cb27bc25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023077727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.4023077727 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.2568600391 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 8345133344 ps |
| CPU time | 86.68 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 01:45:25 PM PST 24 |
| Peak memory | 552780 kb |
| Host | smart-355fdebd-c2a7-4fc5-a69b-4b65eeafe832 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568600391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.2568600391 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2305368311 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 22044792359 ps |
| CPU time | 404.89 seconds |
| Started | Jan 10 01:43:58 PM PST 24 |
| Finished | Jan 10 01:50:43 PM PST 24 |
| Peak memory | 554852 kb |
| Host | smart-c3f4312d-b3c8-4314-8891-938cf472a3a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305368311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.2305368311 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.2913534288 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 589865229 ps |
| CPU time | 49.46 seconds |
| Started | Jan 10 01:43:58 PM PST 24 |
| Finished | Jan 10 01:44:49 PM PST 24 |
| Peak memory | 554980 kb |
| Host | smart-31cc95ca-5e1f-440a-9a9e-9ebbdd3a1ed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913534288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.2913534288 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.1246956469 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 336920182 ps |
| CPU time | 12.97 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 01:44:11 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-c5752d99-4da2-4a58-8d7a-fd5c51b51a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246956469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.1246956469 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.2352893538 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 45661364 ps |
| CPU time | 5.54 seconds |
| Started | Jan 10 01:43:59 PM PST 24 |
| Finished | Jan 10 01:44:06 PM PST 24 |
| Peak memory | 552968 kb |
| Host | smart-0ee99159-ebfe-4316-9d93-29f286e3d51f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352893538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2352893538 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.270498543 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 8204447056 ps |
| CPU time | 86.3 seconds |
| Started | Jan 10 01:44:00 PM PST 24 |
| Finished | Jan 10 01:45:28 PM PST 24 |
| Peak memory | 552792 kb |
| Host | smart-74dfb6ec-df12-4f53-9aa6-1c1c7e731fa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270498543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.270498543 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.4135212116 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 4921460153 ps |
| CPU time | 85.76 seconds |
| Started | Jan 10 01:43:58 PM PST 24 |
| Finished | Jan 10 01:45:24 PM PST 24 |
| Peak memory | 552684 kb |
| Host | smart-36c99772-e2a8-43fe-a94f-54d6856861c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135212116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.4135212116 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.594906408 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 43874672 ps |
| CPU time | 5.81 seconds |
| Started | Jan 10 01:43:59 PM PST 24 |
| Finished | Jan 10 01:44:06 PM PST 24 |
| Peak memory | 552880 kb |
| Host | smart-b8ace319-f0fa-48fd-9972-8456599431d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594906408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays .594906408 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.3855253547 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 1392575172 ps |
| CPU time | 110.36 seconds |
| Started | Jan 10 01:44:00 PM PST 24 |
| Finished | Jan 10 01:45:52 PM PST 24 |
| Peak memory | 555960 kb |
| Host | smart-aa8fcf2b-38f0-4bf8-b74b-ca39d90db208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855253547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.3855253547 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.4123492954 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 5794116278 ps |
| CPU time | 200.82 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 01:47:19 PM PST 24 |
| Peak memory | 555920 kb |
| Host | smart-0acacff3-b1da-47b1-9781-f57c4837d5e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123492954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.4123492954 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.4182429365 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 6679533408 ps |
| CPU time | 836.96 seconds |
| Started | Jan 10 01:44:02 PM PST 24 |
| Finished | Jan 10 01:58:00 PM PST 24 |
| Peak memory | 568180 kb |
| Host | smart-a6bd504a-3f02-4309-a123-e25cd8171837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182429365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.4182429365 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2456308237 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 87890931 ps |
| CPU time | 51.28 seconds |
| Started | Jan 10 01:44:00 PM PST 24 |
| Finished | Jan 10 01:44:53 PM PST 24 |
| Peak memory | 554900 kb |
| Host | smart-d6651fa4-1195-4491-8c8d-f60a18249b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456308237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.2456308237 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1596309748 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 631937080 ps |
| CPU time | 27.65 seconds |
| Started | Jan 10 01:43:59 PM PST 24 |
| Finished | Jan 10 01:44:29 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-1f8db324-d4c9-43cf-89c2-fffc661539c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596309748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1596309748 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1373572952 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 727613066 ps |
| CPU time | 52.37 seconds |
| Started | Jan 10 01:44:15 PM PST 24 |
| Finished | Jan 10 01:45:10 PM PST 24 |
| Peak memory | 555008 kb |
| Host | smart-772aa27c-7db4-44c8-b276-83c14d9e9710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373572952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .1373572952 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.274724216 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 51017247884 ps |
| CPU time | 932.48 seconds |
| Started | Jan 10 01:44:27 PM PST 24 |
| Finished | Jan 10 02:00:02 PM PST 24 |
| Peak memory | 554860 kb |
| Host | smart-4b55deeb-e060-46db-b0f5-0da07b7ed938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274724216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_d evice_slow_rsp.274724216 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.4119085425 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 171739844 ps |
| CPU time | 20.56 seconds |
| Started | Jan 10 01:44:39 PM PST 24 |
| Finished | Jan 10 01:45:01 PM PST 24 |
| Peak memory | 554704 kb |
| Host | smart-d47320ae-ff55-43c5-892b-04741035b19c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119085425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.4119085425 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.3925123644 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 2015504638 ps |
| CPU time | 71.35 seconds |
| Started | Jan 10 01:44:41 PM PST 24 |
| Finished | Jan 10 01:45:55 PM PST 24 |
| Peak memory | 553876 kb |
| Host | smart-f7ac5945-50c6-4940-9709-c1759e8e4df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925123644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3925123644 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.1788107737 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 602541316 ps |
| CPU time | 54.63 seconds |
| Started | Jan 10 01:44:02 PM PST 24 |
| Finished | Jan 10 01:44:58 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-000fddbe-8634-4bd7-9e2e-87e9df5c8e1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788107737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1788107737 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.671538908 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 97419736254 ps |
| CPU time | 1109.56 seconds |
| Started | Jan 10 01:44:40 PM PST 24 |
| Finished | Jan 10 02:03:12 PM PST 24 |
| Peak memory | 554820 kb |
| Host | smart-f421f35c-0499-4467-ac0a-3a1d4011c2d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671538908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.671538908 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.3477015653 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 23844027449 ps |
| CPU time | 453.45 seconds |
| Started | Jan 10 01:44:43 PM PST 24 |
| Finished | Jan 10 01:52:19 PM PST 24 |
| Peak memory | 554824 kb |
| Host | smart-852f3419-8997-467d-9a44-9b0327cc2aa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477015653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.3477015653 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1017977325 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 570961604 ps |
| CPU time | 43.01 seconds |
| Started | Jan 10 01:44:26 PM PST 24 |
| Finished | Jan 10 01:45:11 PM PST 24 |
| Peak memory | 555172 kb |
| Host | smart-6a6b520e-24b3-4121-a77f-3328bb513b16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017977325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1017977325 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.840039382 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 230639706 ps |
| CPU time | 17.16 seconds |
| Started | Jan 10 01:44:32 PM PST 24 |
| Finished | Jan 10 01:44:50 PM PST 24 |
| Peak memory | 554964 kb |
| Host | smart-6735f30f-53bb-474f-8780-a55bc4016eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840039382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.840039382 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.3260558568 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 195471645 ps |
| CPU time | 8.67 seconds |
| Started | Jan 10 01:44:01 PM PST 24 |
| Finished | Jan 10 01:44:11 PM PST 24 |
| Peak memory | 552944 kb |
| Host | smart-11f5ab25-eb7c-4e19-9197-72257df150e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260558568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3260558568 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.2286881249 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 9152438936 ps |
| CPU time | 91.16 seconds |
| Started | Jan 10 01:43:58 PM PST 24 |
| Finished | Jan 10 01:45:30 PM PST 24 |
| Peak memory | 552624 kb |
| Host | smart-af14c6dc-349c-486e-a79f-55dadaa5d7a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286881249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.2286881249 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1686671820 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 5934978956 ps |
| CPU time | 102.1 seconds |
| Started | Jan 10 01:44:00 PM PST 24 |
| Finished | Jan 10 01:45:43 PM PST 24 |
| Peak memory | 552924 kb |
| Host | smart-064ba6a5-3a36-4a2c-9b28-08844c4320a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686671820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1686671820 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.553836933 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 44246618 ps |
| CPU time | 5.56 seconds |
| Started | Jan 10 01:43:57 PM PST 24 |
| Finished | Jan 10 01:44:03 PM PST 24 |
| Peak memory | 552916 kb |
| Host | smart-4d666e41-5967-42eb-8c6e-f340967b6d58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553836933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays .553836933 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.21537665 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 13872296968 ps |
| CPU time | 535.61 seconds |
| Started | Jan 10 01:44:39 PM PST 24 |
| Finished | Jan 10 01:53:36 PM PST 24 |
| Peak memory | 556204 kb |
| Host | smart-17bd33c2-9430-4a28-8ce3-07ca1ef2866e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21537665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.21537665 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3730871087 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 17539036821 ps |
| CPU time | 732.8 seconds |
| Started | Jan 10 01:44:27 PM PST 24 |
| Finished | Jan 10 01:56:41 PM PST 24 |
| Peak memory | 559924 kb |
| Host | smart-dd0e0176-7d7b-4709-a264-0fba8d558f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730871087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3730871087 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1171857771 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 116524489 ps |
| CPU time | 51.13 seconds |
| Started | Jan 10 01:44:13 PM PST 24 |
| Finished | Jan 10 01:45:06 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-fa0e8906-4071-432a-b10b-7e6355aa60fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171857771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.1171857771 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2681605029 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 661994072 ps |
| CPU time | 159.38 seconds |
| Started | Jan 10 01:44:16 PM PST 24 |
| Finished | Jan 10 01:46:58 PM PST 24 |
| Peak memory | 559752 kb |
| Host | smart-8af3301c-80ce-4b33-841d-b7bc9fdb4f54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681605029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.2681605029 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.902221109 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 69750774 ps |
| CPU time | 10.05 seconds |
| Started | Jan 10 01:44:41 PM PST 24 |
| Finished | Jan 10 01:44:53 PM PST 24 |
| Peak memory | 555152 kb |
| Host | smart-b42155ff-1b51-41f9-91c1-82a880c51b42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902221109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.902221109 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2248261476 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 274814151 ps |
| CPU time | 20.29 seconds |
| Started | Jan 10 01:44:29 PM PST 24 |
| Finished | Jan 10 01:44:52 PM PST 24 |
| Peak memory | 556072 kb |
| Host | smart-622f7d68-127b-493a-bf9e-604625a7cecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248261476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .2248261476 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.933322990 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 24505870923 ps |
| CPU time | 433.55 seconds |
| Started | Jan 10 01:44:42 PM PST 24 |
| Finished | Jan 10 01:51:58 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-30873004-9f19-4246-bc30-d79872d9ad10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933322990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_d evice_slow_rsp.933322990 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.626949924 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 322531828 ps |
| CPU time | 33.56 seconds |
| Started | Jan 10 01:44:40 PM PST 24 |
| Finished | Jan 10 01:45:16 PM PST 24 |
| Peak memory | 554756 kb |
| Host | smart-84bfb6c8-fc8d-4807-9585-ee91f0fce598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626949924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr .626949924 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.3639474574 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 455466672 ps |
| CPU time | 40.55 seconds |
| Started | Jan 10 01:44:30 PM PST 24 |
| Finished | Jan 10 01:45:12 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-b27ef9d7-1200-4d72-8e79-0be03767984f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639474574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.3639474574 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.1719160808 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 1556629171 ps |
| CPU time | 57.48 seconds |
| Started | Jan 10 01:44:43 PM PST 24 |
| Finished | Jan 10 01:45:43 PM PST 24 |
| Peak memory | 554920 kb |
| Host | smart-b29e2de6-40d8-4ffc-9bf9-f29501ea5b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719160808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.1719160808 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.1821866033 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 86243461723 ps |
| CPU time | 993.01 seconds |
| Started | Jan 10 01:44:44 PM PST 24 |
| Finished | Jan 10 02:01:19 PM PST 24 |
| Peak memory | 554816 kb |
| Host | smart-08d816d7-5285-4fb9-846b-dd737b80f999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821866033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.1821866033 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.976380318 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 66052016124 ps |
| CPU time | 1255.3 seconds |
| Started | Jan 10 01:44:28 PM PST 24 |
| Finished | Jan 10 02:05:25 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-70e0b953-9e47-4af2-8a43-3f8c4daa2761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976380318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.976380318 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.2200287816 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 526958444 ps |
| CPU time | 45.98 seconds |
| Started | Jan 10 01:44:30 PM PST 24 |
| Finished | Jan 10 01:45:18 PM PST 24 |
| Peak memory | 553892 kb |
| Host | smart-b28f8632-d60c-4a5e-b7e0-9075844ed064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200287816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.2200287816 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.787505293 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 2657465700 ps |
| CPU time | 82.19 seconds |
| Started | Jan 10 01:44:15 PM PST 24 |
| Finished | Jan 10 01:45:40 PM PST 24 |
| Peak memory | 553976 kb |
| Host | smart-27dcfa5d-5c93-4a08-8a52-77fcf4ce47d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787505293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.787505293 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.2462511016 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 39377661 ps |
| CPU time | 6.01 seconds |
| Started | Jan 10 01:44:40 PM PST 24 |
| Finished | Jan 10 01:44:48 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-65e0c9b3-e826-41ca-83dc-a153908f3a9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462511016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.2462511016 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.404490040 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 7347212086 ps |
| CPU time | 86.09 seconds |
| Started | Jan 10 01:44:17 PM PST 24 |
| Finished | Jan 10 01:45:46 PM PST 24 |
| Peak memory | 553032 kb |
| Host | smart-03486929-7e86-4ce5-9d91-1090345fc2dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404490040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.404490040 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3258719402 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 6494139908 ps |
| CPU time | 107.09 seconds |
| Started | Jan 10 01:44:41 PM PST 24 |
| Finished | Jan 10 01:46:31 PM PST 24 |
| Peak memory | 552720 kb |
| Host | smart-511cb342-0ab4-4266-99e6-0f7abd810df9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258719402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3258719402 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.4238016047 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 46158834 ps |
| CPU time | 5.7 seconds |
| Started | Jan 10 01:44:16 PM PST 24 |
| Finished | Jan 10 01:44:25 PM PST 24 |
| Peak memory | 552680 kb |
| Host | smart-3e731310-769d-48fb-9c86-9f8bf2d40576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238016047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.4238016047 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.1322874503 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 9649781116 ps |
| CPU time | 364.29 seconds |
| Started | Jan 10 01:44:43 PM PST 24 |
| Finished | Jan 10 01:50:50 PM PST 24 |
| Peak memory | 556496 kb |
| Host | smart-40c47ebf-f023-4893-8f55-b9b548d6d6d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322874503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.1322874503 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2246042253 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1810496380 ps |
| CPU time | 151.46 seconds |
| Started | Jan 10 01:44:50 PM PST 24 |
| Finished | Jan 10 01:47:31 PM PST 24 |
| Peak memory | 555904 kb |
| Host | smart-faa2e3de-7355-4d5c-906f-5c90fe929cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246042253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.2246042253 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2558260971 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 5292164628 ps |
| CPU time | 234.66 seconds |
| Started | Jan 10 01:44:39 PM PST 24 |
| Finished | Jan 10 01:48:35 PM PST 24 |
| Peak memory | 556848 kb |
| Host | smart-05fb1e17-ce15-49bf-8352-b3676ed1155b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558260971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2558260971 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.2159519877 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 274750038 ps |
| CPU time | 96.92 seconds |
| Started | Jan 10 01:44:43 PM PST 24 |
| Finished | Jan 10 01:46:22 PM PST 24 |
| Peak memory | 556004 kb |
| Host | smart-f57c7c82-adc2-4a6d-b684-8edc411d0fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159519877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.2159519877 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2139367699 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 908768980 ps |
| CPU time | 37 seconds |
| Started | Jan 10 01:44:42 PM PST 24 |
| Finished | Jan 10 01:45:22 PM PST 24 |
| Peak memory | 554952 kb |
| Host | smart-f96d1837-b94b-4e4e-8948-e7545262f928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139367699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2139367699 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.814954514 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 2346099831 ps |
| CPU time | 107.57 seconds |
| Started | Jan 10 01:44:30 PM PST 24 |
| Finished | Jan 10 01:46:20 PM PST 24 |
| Peak memory | 555272 kb |
| Host | smart-ebc08856-9ee1-4c33-b909-583c205d18de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814954514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device. 814954514 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1619092138 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 132389652063 ps |
| CPU time | 2457.99 seconds |
| Started | Jan 10 01:44:19 PM PST 24 |
| Finished | Jan 10 02:25:20 PM PST 24 |
| Peak memory | 556232 kb |
| Host | smart-7a3d6c66-fe43-47de-b41f-2299d202c79c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619092138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.1619092138 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.388709366 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 1512939076 ps |
| CPU time | 56.4 seconds |
| Started | Jan 10 01:44:43 PM PST 24 |
| Finished | Jan 10 01:45:42 PM PST 24 |
| Peak memory | 554940 kb |
| Host | smart-80676f42-5071-4edb-8cad-2c986200e9a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388709366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr .388709366 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.2775647867 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 971732511 ps |
| CPU time | 30.67 seconds |
| Started | Jan 10 01:44:40 PM PST 24 |
| Finished | Jan 10 01:45:13 PM PST 24 |
| Peak memory | 554976 kb |
| Host | smart-ffcb2365-c420-4679-90cb-74677fe3bde5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775647867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.2775647867 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.903162405 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 388154648 ps |
| CPU time | 33.56 seconds |
| Started | Jan 10 01:44:26 PM PST 24 |
| Finished | Jan 10 01:45:01 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-dcd6a236-3af9-4e98-affd-c45f20133d3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903162405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.903162405 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.246659452 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 98304971515 ps |
| CPU time | 1168.6 seconds |
| Started | Jan 10 01:44:38 PM PST 24 |
| Finished | Jan 10 02:04:09 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-d768f333-a968-478d-8e65-4ce3b37af1f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246659452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.246659452 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.4258945619 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 49485535402 ps |
| CPU time | 878.91 seconds |
| Started | Jan 10 01:44:29 PM PST 24 |
| Finished | Jan 10 01:59:11 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-a1ed50a4-1f7f-4a60-84cf-7d7c482dd373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258945619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.4258945619 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.1079841061 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 369513041 ps |
| CPU time | 31.11 seconds |
| Started | Jan 10 01:44:44 PM PST 24 |
| Finished | Jan 10 01:45:17 PM PST 24 |
| Peak memory | 554736 kb |
| Host | smart-bf22e535-d8ed-4603-83a4-7cad038cb8d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079841061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.1079841061 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.402568612 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 416582157 ps |
| CPU time | 29.26 seconds |
| Started | Jan 10 01:44:29 PM PST 24 |
| Finished | Jan 10 01:45:01 PM PST 24 |
| Peak memory | 553956 kb |
| Host | smart-b68bbae6-c20e-4da2-bb96-5aa3bc057bf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402568612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.402568612 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.876065054 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 47833190 ps |
| CPU time | 6.43 seconds |
| Started | Jan 10 01:44:29 PM PST 24 |
| Finished | Jan 10 01:44:38 PM PST 24 |
| Peak memory | 552996 kb |
| Host | smart-547f30fc-c367-4a1a-825d-8bf4e0f52e50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876065054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.876065054 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2192485950 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 8286210282 ps |
| CPU time | 82.4 seconds |
| Started | Jan 10 01:44:26 PM PST 24 |
| Finished | Jan 10 01:45:50 PM PST 24 |
| Peak memory | 552656 kb |
| Host | smart-a18c1177-7a04-4e38-8269-abe86e0ec29c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192485950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2192485950 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.241215782 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 4594731476 ps |
| CPU time | 79.37 seconds |
| Started | Jan 10 01:44:30 PM PST 24 |
| Finished | Jan 10 01:45:51 PM PST 24 |
| Peak memory | 552980 kb |
| Host | smart-f0940ca3-a9b2-48c8-84b8-019930d0e034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241215782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.241215782 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1180380660 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 52132912 ps |
| CPU time | 6.35 seconds |
| Started | Jan 10 01:44:27 PM PST 24 |
| Finished | Jan 10 01:44:35 PM PST 24 |
| Peak memory | 552900 kb |
| Host | smart-cffacbc3-ddbf-46e5-bbfc-bf1a17535936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180380660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.1180380660 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.1523770212 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 9486807530 ps |
| CPU time | 339.49 seconds |
| Started | Jan 10 01:44:14 PM PST 24 |
| Finished | Jan 10 01:49:55 PM PST 24 |
| Peak memory | 556060 kb |
| Host | smart-1595f8a8-ea40-46d8-957a-4880a18be28c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523770212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.1523770212 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1913409442 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 15519448411 ps |
| CPU time | 542.06 seconds |
| Started | Jan 10 01:44:41 PM PST 24 |
| Finished | Jan 10 01:53:46 PM PST 24 |
| Peak memory | 556852 kb |
| Host | smart-e66b17a2-3301-4746-ab81-0dfdf48386c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913409442 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1913409442 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.3861339409 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 797511413 ps |
| CPU time | 269.58 seconds |
| Started | Jan 10 01:44:16 PM PST 24 |
| Finished | Jan 10 01:48:49 PM PST 24 |
| Peak memory | 557192 kb |
| Host | smart-ac89b660-6ace-4d3e-b6a1-ee05cb2cd543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861339409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.3861339409 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1922992679 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 217027404 ps |
| CPU time | 63.6 seconds |
| Started | Jan 10 01:44:15 PM PST 24 |
| Finished | Jan 10 01:45:22 PM PST 24 |
| Peak memory | 555956 kb |
| Host | smart-e41e7a9b-2f56-4a3f-a65f-24b16de8839a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922992679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.1922992679 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3712014369 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 386049824 ps |
| CPU time | 16.69 seconds |
| Started | Jan 10 01:44:32 PM PST 24 |
| Finished | Jan 10 01:44:49 PM PST 24 |
| Peak memory | 553956 kb |
| Host | smart-8d5e3ea4-5b91-4f4c-8ef3-669afb0b7711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712014369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3712014369 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.316728262 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 7071658816 ps |
| CPU time | 329.31 seconds |
| Started | Jan 10 01:36:31 PM PST 24 |
| Finished | Jan 10 01:42:04 PM PST 24 |
| Peak memory | 621532 kb |
| Host | smart-97f4ccf0-6d26-42dd-852b-10108521e25d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316728262 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.316728262 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.2670373449 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 4147462520 ps |
| CPU time | 322.23 seconds |
| Started | Jan 10 01:36:31 PM PST 24 |
| Finished | Jan 10 01:41:56 PM PST 24 |
| Peak memory | 580828 kb |
| Host | smart-e4c8a6d7-f5f3-4c6d-afc2-95af8e7996fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670373449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2670373449 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3982798141 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 14730903901 ps |
| CPU time | 2261.9 seconds |
| Started | Jan 10 01:36:19 PM PST 24 |
| Finished | Jan 10 02:14:07 PM PST 24 |
| Peak memory | 580784 kb |
| Host | smart-e568b9e1-5c66-4cc5-a256-a9ac8f0fcedc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982798141 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.3982798141 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1417643090 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2872090076 ps |
| CPU time | 151.55 seconds |
| Started | Jan 10 01:36:32 PM PST 24 |
| Finished | Jan 10 01:39:06 PM PST 24 |
| Peak memory | 580268 kb |
| Host | smart-3c76df49-72b1-4736-9ffd-a91d205217d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417643090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1417643090 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.458061282 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 16221111 ps |
| CPU time | 5.75 seconds |
| Started | Jan 10 01:36:24 PM PST 24 |
| Finished | Jan 10 01:36:36 PM PST 24 |
| Peak memory | 552976 kb |
| Host | smart-b200bf09-df39-4fb7-8a8d-931285d35bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458061282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.458061282 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.804055068 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 12410596094 ps |
| CPU time | 193.37 seconds |
| Started | Jan 10 01:36:34 PM PST 24 |
| Finished | Jan 10 01:39:50 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-caa3eca7-352d-4471-bd05-fa31abd1838f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804055068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de vice_slow_rsp.804055068 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.2153820161 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 1239843381 ps |
| CPU time | 48.35 seconds |
| Started | Jan 10 01:36:34 PM PST 24 |
| Finished | Jan 10 01:37:24 PM PST 24 |
| Peak memory | 554728 kb |
| Host | smart-c2e78435-b3d5-409d-aa30-bf277ebe2d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153820161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .2153820161 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.49715209 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 273957367 ps |
| CPU time | 19.71 seconds |
| Started | Jan 10 01:36:32 PM PST 24 |
| Finished | Jan 10 01:36:54 PM PST 24 |
| Peak memory | 554648 kb |
| Host | smart-d2b0eb61-997a-45a0-a6d5-5092bbd70435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49715209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.49715209 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.375366602 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 624375709 ps |
| CPU time | 48.99 seconds |
| Started | Jan 10 01:36:24 PM PST 24 |
| Finished | Jan 10 01:37:19 PM PST 24 |
| Peak memory | 555012 kb |
| Host | smart-cc841f37-b961-4fdd-8cf7-eda5ba61385b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375366602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.375366602 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2397281834 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 82868419355 ps |
| CPU time | 745.33 seconds |
| Started | Jan 10 01:36:23 PM PST 24 |
| Finished | Jan 10 01:48:55 PM PST 24 |
| Peak memory | 553972 kb |
| Host | smart-cef6c6d7-d0c7-4d85-b2d5-d9a409a5f5d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397281834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2397281834 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.125361175 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 11464796886 ps |
| CPU time | 205.33 seconds |
| Started | Jan 10 01:36:20 PM PST 24 |
| Finished | Jan 10 01:39:51 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-c8c4fcaf-0860-4b36-b9be-7d87dacc0d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125361175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.125361175 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.2401692074 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 446322218 ps |
| CPU time | 36.69 seconds |
| Started | Jan 10 01:36:23 PM PST 24 |
| Finished | Jan 10 01:37:05 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-25afa632-5970-4d08-a458-8dd6b41f7efc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401692074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.2401692074 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.3411170345 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 279866102 ps |
| CPU time | 10.99 seconds |
| Started | Jan 10 01:36:24 PM PST 24 |
| Finished | Jan 10 01:36:41 PM PST 24 |
| Peak memory | 552844 kb |
| Host | smart-7b58a455-c048-469c-a86d-4abb2e6fa3ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411170345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3411170345 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.3752851570 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 195751788 ps |
| CPU time | 8.36 seconds |
| Started | Jan 10 01:36:32 PM PST 24 |
| Finished | Jan 10 01:36:43 PM PST 24 |
| Peak memory | 552904 kb |
| Host | smart-179e1a92-f94d-4bea-b81c-6693a0cf6cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752851570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3752851570 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.2191265869 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 7988328267 ps |
| CPU time | 87.1 seconds |
| Started | Jan 10 01:36:30 PM PST 24 |
| Finished | Jan 10 01:38:01 PM PST 24 |
| Peak memory | 552988 kb |
| Host | smart-bf718ce1-4edf-4c07-a71c-f252fa33853a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191265869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2191265869 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.4092036601 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 4002892055 ps |
| CPU time | 64.18 seconds |
| Started | Jan 10 01:36:26 PM PST 24 |
| Finished | Jan 10 01:37:35 PM PST 24 |
| Peak memory | 552728 kb |
| Host | smart-2b0fb210-a090-4954-9e5a-f6b37a03c344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092036601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4092036601 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.451180526 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 42387288 ps |
| CPU time | 5.51 seconds |
| Started | Jan 10 01:36:25 PM PST 24 |
| Finished | Jan 10 01:36:36 PM PST 24 |
| Peak memory | 553020 kb |
| Host | smart-2074f31d-d5b8-4b74-82be-018392ed24ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451180526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays. 451180526 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.97465800 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 21136581462 ps |
| CPU time | 836.87 seconds |
| Started | Jan 10 01:36:25 PM PST 24 |
| Finished | Jan 10 01:50:28 PM PST 24 |
| Peak memory | 557228 kb |
| Host | smart-e7fcafca-4de9-4a56-9847-ae30680f29ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97465800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.97465800 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.336356586 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 13668073546 ps |
| CPU time | 432.22 seconds |
| Started | Jan 10 01:36:31 PM PST 24 |
| Finished | Jan 10 01:43:46 PM PST 24 |
| Peak memory | 556232 kb |
| Host | smart-140640e5-1271-4786-a60e-0dabf8d16b7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336356586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.336356586 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3497776902 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 38748577 ps |
| CPU time | 22.86 seconds |
| Started | Jan 10 01:36:25 PM PST 24 |
| Finished | Jan 10 01:36:54 PM PST 24 |
| Peak memory | 553844 kb |
| Host | smart-8b6f6c3c-2172-4210-98f3-8b07cbd7d690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497776902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.3497776902 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3702546733 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 3416168476 ps |
| CPU time | 302.03 seconds |
| Started | Jan 10 01:36:20 PM PST 24 |
| Finished | Jan 10 01:41:27 PM PST 24 |
| Peak memory | 559992 kb |
| Host | smart-7f7bf25b-4931-470a-8100-47ac4caeafd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702546733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.3702546733 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.492398353 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 349311856 ps |
| CPU time | 15.35 seconds |
| Started | Jan 10 01:36:20 PM PST 24 |
| Finished | Jan 10 01:36:42 PM PST 24 |
| Peak memory | 554716 kb |
| Host | smart-cb66e854-6174-4ddd-b1ad-d920fd3101c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492398353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.492398353 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1931115480 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 73322564 ps |
| CPU time | 8.87 seconds |
| Started | Jan 10 01:44:46 PM PST 24 |
| Finished | Jan 10 01:44:59 PM PST 24 |
| Peak memory | 553996 kb |
| Host | smart-0dfdcc27-39e6-4e18-8f52-d32987cf36b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931115480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .1931115480 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3136502743 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 98031835297 ps |
| CPU time | 1724.61 seconds |
| Started | Jan 10 01:44:43 PM PST 24 |
| Finished | Jan 10 02:13:30 PM PST 24 |
| Peak memory | 556216 kb |
| Host | smart-55f6b11c-c813-43d8-a00b-91b6fe6305ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136502743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.3136502743 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.569152930 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 370259662 ps |
| CPU time | 15.71 seconds |
| Started | Jan 10 01:44:51 PM PST 24 |
| Finished | Jan 10 01:45:22 PM PST 24 |
| Peak memory | 554700 kb |
| Host | smart-a6a998d7-21d0-4568-9b9d-571c91e5f9a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569152930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr .569152930 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.4125108085 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 660005030 ps |
| CPU time | 24.43 seconds |
| Started | Jan 10 01:44:43 PM PST 24 |
| Finished | Jan 10 01:45:10 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-5e82d134-34b2-4e02-b1b3-8581e4403295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125108085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.4125108085 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.3396551551 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 394531140 ps |
| CPU time | 32.63 seconds |
| Started | Jan 10 01:44:42 PM PST 24 |
| Finished | Jan 10 01:45:18 PM PST 24 |
| Peak memory | 555104 kb |
| Host | smart-e9f30ecd-503b-48e2-ab25-b15705fc2190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396551551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3396551551 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1674403557 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 71516352567 ps |
| CPU time | 880.36 seconds |
| Started | Jan 10 01:44:28 PM PST 24 |
| Finished | Jan 10 01:59:10 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-f0c97232-9e40-41b9-a1f0-c07eccac5490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674403557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1674403557 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2988029580 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 24819545793 ps |
| CPU time | 418.65 seconds |
| Started | Jan 10 01:44:43 PM PST 24 |
| Finished | Jan 10 01:51:44 PM PST 24 |
| Peak memory | 554844 kb |
| Host | smart-64cec6c5-6bc4-4fab-95d7-04490fd3f7a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988029580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2988029580 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.839211171 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 487302541 ps |
| CPU time | 40.9 seconds |
| Started | Jan 10 01:44:42 PM PST 24 |
| Finished | Jan 10 01:45:26 PM PST 24 |
| Peak memory | 554956 kb |
| Host | smart-8f5ab2b1-a020-4abe-bf34-e4ce19f5bb0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839211171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_dela ys.839211171 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.2343027513 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 108859854 ps |
| CPU time | 10.01 seconds |
| Started | Jan 10 01:44:46 PM PST 24 |
| Finished | Jan 10 01:45:01 PM PST 24 |
| Peak memory | 553912 kb |
| Host | smart-d90240c6-e12b-4fe2-9a0b-0c4b4b59e3d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343027513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.2343027513 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.583431001 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 43253432 ps |
| CPU time | 6.05 seconds |
| Started | Jan 10 01:44:15 PM PST 24 |
| Finished | Jan 10 01:44:25 PM PST 24 |
| Peak memory | 552968 kb |
| Host | smart-f9a32f8d-a3f0-4874-a1c0-d80556477408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583431001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.583431001 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1860840118 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 7175146552 ps |
| CPU time | 73.8 seconds |
| Started | Jan 10 01:44:31 PM PST 24 |
| Finished | Jan 10 01:45:46 PM PST 24 |
| Peak memory | 552540 kb |
| Host | smart-7432d8b8-dc5f-4f5b-a155-0e3eb7b041d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860840118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1860840118 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2239998504 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 5282837868 ps |
| CPU time | 95.06 seconds |
| Started | Jan 10 01:44:28 PM PST 24 |
| Finished | Jan 10 01:46:05 PM PST 24 |
| Peak memory | 553056 kb |
| Host | smart-9850c39c-8622-43f0-a60c-f01f3c8ae9b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239998504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.2239998504 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.1239046697 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 44425188 ps |
| CPU time | 5.86 seconds |
| Started | Jan 10 01:44:43 PM PST 24 |
| Finished | Jan 10 01:44:51 PM PST 24 |
| Peak memory | 552984 kb |
| Host | smart-7be1ed71-243c-40cf-9e88-5be6103c1876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239046697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.1239046697 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.250220946 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 14164712442 ps |
| CPU time | 526.51 seconds |
| Started | Jan 10 01:44:40 PM PST 24 |
| Finished | Jan 10 01:53:28 PM PST 24 |
| Peak memory | 556012 kb |
| Host | smart-60b3d97f-3cdb-4277-b1df-5fec9d135c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250220946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.250220946 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2572012165 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 390162560 ps |
| CPU time | 187.52 seconds |
| Started | Jan 10 01:44:42 PM PST 24 |
| Finished | Jan 10 01:47:53 PM PST 24 |
| Peak memory | 557368 kb |
| Host | smart-cd2840e0-2267-4653-ac84-55caf77b54fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572012165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2572012165 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2876407167 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1861640178 ps |
| CPU time | 167.78 seconds |
| Started | Jan 10 01:44:42 PM PST 24 |
| Finished | Jan 10 01:47:33 PM PST 24 |
| Peak memory | 555084 kb |
| Host | smart-517639e6-02f3-4337-b615-0d6f811f1591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876407167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.2876407167 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.3015048552 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 192467583 ps |
| CPU time | 11.41 seconds |
| Started | Jan 10 01:44:30 PM PST 24 |
| Finished | Jan 10 01:44:43 PM PST 24 |
| Peak memory | 553996 kb |
| Host | smart-714cb554-3321-48c0-beee-474e5517a677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015048552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.3015048552 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1364804720 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 156845621 ps |
| CPU time | 14.46 seconds |
| Started | Jan 10 01:45:01 PM PST 24 |
| Finished | Jan 10 01:45:36 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-5516468e-e7ba-40c0-b57d-fcde2951d454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364804720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1364804720 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.4180483705 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 107348325575 ps |
| CPU time | 1692.52 seconds |
| Started | Jan 10 01:45:07 PM PST 24 |
| Finished | Jan 10 02:13:41 PM PST 24 |
| Peak memory | 554908 kb |
| Host | smart-604328d5-52de-4675-9d22-a0cda5ad368b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180483705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.4180483705 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3696221024 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 116057531 ps |
| CPU time | 8.05 seconds |
| Started | Jan 10 01:45:01 PM PST 24 |
| Finished | Jan 10 01:45:29 PM PST 24 |
| Peak memory | 552600 kb |
| Host | smart-ac1720fb-38c7-443b-b89a-373c1e8a631f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696221024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.3696221024 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.4290289140 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 1316096078 ps |
| CPU time | 41.28 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:46:06 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-d9c3c857-5693-4a76-afc5-84992213414d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290289140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.4290289140 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.43181822 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 725032216 ps |
| CPU time | 28.41 seconds |
| Started | Jan 10 01:44:57 PM PST 24 |
| Finished | Jan 10 01:45:44 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-b8c3b236-314b-4761-b9ae-a2c5ceb9f123 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43181822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.43181822 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.3593374758 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 44721102602 ps |
| CPU time | 482.48 seconds |
| Started | Jan 10 01:44:47 PM PST 24 |
| Finished | Jan 10 01:52:54 PM PST 24 |
| Peak memory | 553960 kb |
| Host | smart-77c1ad36-eca5-469f-8b57-7f38412439ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593374758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.3593374758 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.890292276 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 46860931184 ps |
| CPU time | 914.98 seconds |
| Started | Jan 10 01:44:57 PM PST 24 |
| Finished | Jan 10 02:00:31 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-7674d78f-6b2b-4247-ba14-559576afd9c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890292276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.890292276 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2946245522 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 68409259 ps |
| CPU time | 9.15 seconds |
| Started | Jan 10 01:45:02 PM PST 24 |
| Finished | Jan 10 01:45:30 PM PST 24 |
| Peak memory | 553728 kb |
| Host | smart-2ef9607c-806c-44f0-b7e7-9954de2df42e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946245522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2946245522 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.599603064 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 503826849 ps |
| CPU time | 34.62 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:46:00 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-1f72667a-9918-4753-af70-0cdd6150ae26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599603064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.599603064 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.2760629315 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 37493438 ps |
| CPU time | 5.56 seconds |
| Started | Jan 10 01:44:44 PM PST 24 |
| Finished | Jan 10 01:44:52 PM PST 24 |
| Peak memory | 552688 kb |
| Host | smart-7fe923e6-ef3d-4ee1-94d5-f4ca0167f463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760629315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.2760629315 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.87698772 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 6963701687 ps |
| CPU time | 75.15 seconds |
| Started | Jan 10 01:44:47 PM PST 24 |
| Finished | Jan 10 01:46:07 PM PST 24 |
| Peak memory | 553044 kb |
| Host | smart-f6940ea4-ae2e-4b15-a4af-df3472c896e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87698772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.87698772 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.197351834 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4657261049 ps |
| CPU time | 78.11 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:46:39 PM PST 24 |
| Peak memory | 553028 kb |
| Host | smart-058ebca1-8053-45f9-a398-1665ff57fa22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197351834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.197351834 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2319040899 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 55859997 ps |
| CPU time | 6.2 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:45:31 PM PST 24 |
| Peak memory | 552952 kb |
| Host | smart-fa236d39-ef90-4c2d-b30e-17d60caf77f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319040899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.2319040899 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.1525307990 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 1516362870 ps |
| CPU time | 59.47 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:46:21 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-067607d2-9df6-4a90-b2f6-1a4198026646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525307990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1525307990 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1963228952 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 8966260812 ps |
| CPU time | 321.84 seconds |
| Started | Jan 10 01:45:08 PM PST 24 |
| Finished | Jan 10 01:50:52 PM PST 24 |
| Peak memory | 557252 kb |
| Host | smart-76467629-aadf-417b-9cac-12c2eed9db4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963228952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1963228952 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2291041499 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 11266792645 ps |
| CPU time | 607.27 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:55:31 PM PST 24 |
| Peak memory | 557900 kb |
| Host | smart-c106bb73-3146-470f-ba3e-cb9c8e424f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291041499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.2291041499 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.829716852 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 300597610 ps |
| CPU time | 87.36 seconds |
| Started | Jan 10 01:45:06 PM PST 24 |
| Finished | Jan 10 01:46:54 PM PST 24 |
| Peak memory | 556020 kb |
| Host | smart-ddd498c1-0687-49f2-80d5-f333ec85f936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829716852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_reset_error.829716852 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.904719099 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 1000302236 ps |
| CPU time | 38.77 seconds |
| Started | Jan 10 01:45:08 PM PST 24 |
| Finished | Jan 10 01:46:10 PM PST 24 |
| Peak memory | 555020 kb |
| Host | smart-091d38c7-97b2-4c7f-8231-48156f99f5c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904719099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.904719099 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3793898169 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 1586282522 ps |
| CPU time | 59.64 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:46:37 PM PST 24 |
| Peak memory | 555104 kb |
| Host | smart-712ae929-111a-4330-8820-237e7e7209a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793898169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .3793898169 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.844483761 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 83649871366 ps |
| CPU time | 1481.33 seconds |
| Started | Jan 10 01:45:14 PM PST 24 |
| Finished | Jan 10 02:10:17 PM PST 24 |
| Peak memory | 554960 kb |
| Host | smart-68cbecc3-5593-48e7-9aec-aee92d536c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844483761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_d evice_slow_rsp.844483761 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2725257908 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 196395803 ps |
| CPU time | 22.33 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:46:00 PM PST 24 |
| Peak memory | 555004 kb |
| Host | smart-e1ceee42-3bba-4330-9e58-d322463e2d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725257908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.2725257908 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.3901750133 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 503339580 ps |
| CPU time | 37.05 seconds |
| Started | Jan 10 01:45:19 PM PST 24 |
| Finished | Jan 10 01:46:15 PM PST 24 |
| Peak memory | 554696 kb |
| Host | smart-ced3f7f8-0a1b-4666-ba92-cb00d0ba8531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901750133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.3901750133 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.2806032653 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 155070705 ps |
| CPU time | 7.63 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:45:39 PM PST 24 |
| Peak memory | 552728 kb |
| Host | smart-c738b003-f9e8-4409-97ee-4b74bba437c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806032653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.2806032653 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2433417159 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 104487330990 ps |
| CPU time | 1267.18 seconds |
| Started | Jan 10 01:45:10 PM PST 24 |
| Finished | Jan 10 02:06:40 PM PST 24 |
| Peak memory | 555008 kb |
| Host | smart-389352e5-b72c-4ad1-a8d3-1d7e61bd93d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433417159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2433417159 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2896340210 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 56403581387 ps |
| CPU time | 984.22 seconds |
| Started | Jan 10 01:45:14 PM PST 24 |
| Finished | Jan 10 02:02:00 PM PST 24 |
| Peak memory | 555160 kb |
| Host | smart-ada9b097-a1cd-4d85-9ecd-06fb84e8ef2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896340210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2896340210 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.118249848 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 193359222 ps |
| CPU time | 18.03 seconds |
| Started | Jan 10 01:45:11 PM PST 24 |
| Finished | Jan 10 01:45:52 PM PST 24 |
| Peak memory | 554628 kb |
| Host | smart-56d8e43f-d39a-41a4-aea6-945fd5e178ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118249848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_dela ys.118249848 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.2838638007 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 2656239999 ps |
| CPU time | 79.08 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:46:56 PM PST 24 |
| Peak memory | 554860 kb |
| Host | smart-853bd3af-d004-4914-a9e5-4668b0200879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838638007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.2838638007 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.618463908 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 253850760 ps |
| CPU time | 9.46 seconds |
| Started | Jan 10 01:45:07 PM PST 24 |
| Finished | Jan 10 01:45:39 PM PST 24 |
| Peak memory | 552920 kb |
| Host | smart-7adf7edf-8e6d-449d-8f4c-37c9bf5075cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618463908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.618463908 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.4151475780 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 9529941820 ps |
| CPU time | 98.18 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:47:11 PM PST 24 |
| Peak memory | 552544 kb |
| Host | smart-ad4c20bb-0d47-4a99-bb25-5965967f1204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151475780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.4151475780 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.491413081 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 4393807752 ps |
| CPU time | 67.27 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:46:39 PM PST 24 |
| Peak memory | 552976 kb |
| Host | smart-49c823bf-cd47-4646-86a1-61d1cd73bdd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491413081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.491413081 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.282293766 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 42382375 ps |
| CPU time | 5.89 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:45:38 PM PST 24 |
| Peak memory | 552948 kb |
| Host | smart-e3441567-6eee-40c1-9218-28ee58d4b5a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282293766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delays .282293766 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.1699896071 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 7967657631 ps |
| CPU time | 278.3 seconds |
| Started | Jan 10 01:45:17 PM PST 24 |
| Finished | Jan 10 01:50:15 PM PST 24 |
| Peak memory | 556240 kb |
| Host | smart-391e4cde-3cbf-4f51-97fe-aa58395006b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699896071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.1699896071 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.2545821224 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 159286965 ps |
| CPU time | 10.77 seconds |
| Started | Jan 10 01:45:01 PM PST 24 |
| Finished | Jan 10 01:45:32 PM PST 24 |
| Peak memory | 553624 kb |
| Host | smart-1e371467-ccc6-4ff6-a598-fa2dc086e931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545821224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.2545821224 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3330868651 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 174426639 ps |
| CPU time | 48.45 seconds |
| Started | Jan 10 01:45:16 PM PST 24 |
| Finished | Jan 10 01:46:24 PM PST 24 |
| Peak memory | 555948 kb |
| Host | smart-7f7b7153-7341-4356-8626-71b67fef045f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330868651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.3330868651 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.577744608 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 692891319 ps |
| CPU time | 220.66 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:49:06 PM PST 24 |
| Peak memory | 559628 kb |
| Host | smart-eb3d8e99-0262-41e5-92bd-7c2686ddd8b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577744608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_reset_error.577744608 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.1098879889 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1180102674 ps |
| CPU time | 45.06 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:46:22 PM PST 24 |
| Peak memory | 554864 kb |
| Host | smart-c95d289e-3945-44a2-ac45-20c84a471ec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098879889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.1098879889 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.3071302742 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 1675165984 ps |
| CPU time | 70.41 seconds |
| Started | Jan 10 01:44:57 PM PST 24 |
| Finished | Jan 10 01:46:26 PM PST 24 |
| Peak memory | 554852 kb |
| Host | smart-8136545b-52dc-4682-a0e2-c8892dfd0246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071302742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .3071302742 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2838877415 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 56291692013 ps |
| CPU time | 1099.04 seconds |
| Started | Jan 10 01:44:47 PM PST 24 |
| Finished | Jan 10 02:03:11 PM PST 24 |
| Peak memory | 555092 kb |
| Host | smart-b9f177a3-482e-4324-b931-5101d68086e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838877415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.2838877415 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.44810456 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 50292334 ps |
| CPU time | 8.72 seconds |
| Started | Jan 10 01:44:55 PM PST 24 |
| Finished | Jan 10 01:45:23 PM PST 24 |
| Peak memory | 553704 kb |
| Host | smart-08ed58dc-3382-4c15-ae0a-6a1aee2e75ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44810456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_addr.44810456 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.2099911447 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 540914632 ps |
| CPU time | 44.38 seconds |
| Started | Jan 10 01:44:53 PM PST 24 |
| Finished | Jan 10 01:45:59 PM PST 24 |
| Peak memory | 554984 kb |
| Host | smart-41aee3e6-db6c-4757-b096-6b90c763df20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099911447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2099911447 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.3090476252 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 490330319 ps |
| CPU time | 38.75 seconds |
| Started | Jan 10 01:44:54 PM PST 24 |
| Finished | Jan 10 01:45:53 PM PST 24 |
| Peak memory | 554888 kb |
| Host | smart-da1f7824-39eb-4c7b-9bf4-453a450521f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090476252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.3090476252 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2350050835 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 32005637953 ps |
| CPU time | 367.69 seconds |
| Started | Jan 10 01:44:46 PM PST 24 |
| Finished | Jan 10 01:50:58 PM PST 24 |
| Peak memory | 553988 kb |
| Host | smart-89ebdce5-4d2b-491d-a505-e4630c765827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350050835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.2350050835 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.196647683 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 55211321168 ps |
| CPU time | 1021.08 seconds |
| Started | Jan 10 01:44:58 PM PST 24 |
| Finished | Jan 10 02:02:18 PM PST 24 |
| Peak memory | 554796 kb |
| Host | smart-ecae733d-c1ee-48da-9076-3838f38cb6bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196647683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.196647683 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.63982750 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 68571175 ps |
| CPU time | 8.39 seconds |
| Started | Jan 10 01:44:55 PM PST 24 |
| Finished | Jan 10 01:45:23 PM PST 24 |
| Peak memory | 552836 kb |
| Host | smart-dae80362-82eb-411c-ba00-ee70c797a9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63982750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_delay s.63982750 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.3370089082 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 346219947 ps |
| CPU time | 25.91 seconds |
| Started | Jan 10 01:44:46 PM PST 24 |
| Finished | Jan 10 01:45:16 PM PST 24 |
| Peak memory | 555008 kb |
| Host | smart-1d98d180-17c9-43c8-8d9b-99a4c7543d87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370089082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3370089082 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.893145240 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 174550850 ps |
| CPU time | 8.22 seconds |
| Started | Jan 10 01:44:58 PM PST 24 |
| Finished | Jan 10 01:45:25 PM PST 24 |
| Peak memory | 552636 kb |
| Host | smart-023d79e8-70fe-4613-b6b1-a2836a2e61aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893145240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.893145240 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.570732995 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 8048797450 ps |
| CPU time | 80.8 seconds |
| Started | Jan 10 01:44:59 PM PST 24 |
| Finished | Jan 10 01:46:38 PM PST 24 |
| Peak memory | 552640 kb |
| Host | smart-8ba7dfaa-7bd5-4d14-a1e8-68915660b88f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570732995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.570732995 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3942216732 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 5706199986 ps |
| CPU time | 94.31 seconds |
| Started | Jan 10 01:44:55 PM PST 24 |
| Finished | Jan 10 01:46:49 PM PST 24 |
| Peak memory | 553060 kb |
| Host | smart-b06e1e71-d5d8-4835-8b85-835d7513f473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942216732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3942216732 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1204667961 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 57048036 ps |
| CPU time | 6.66 seconds |
| Started | Jan 10 01:44:58 PM PST 24 |
| Finished | Jan 10 01:45:23 PM PST 24 |
| Peak memory | 552664 kb |
| Host | smart-765b57d5-6b05-4baa-8fff-27e39dc94316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204667961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1204667961 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3351001046 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 9017997832 ps |
| CPU time | 367.68 seconds |
| Started | Jan 10 01:45:02 PM PST 24 |
| Finished | Jan 10 01:51:29 PM PST 24 |
| Peak memory | 557564 kb |
| Host | smart-392e92d2-ff2b-4cdf-8fa9-e1e7ad61f07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351001046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3351001046 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2378584645 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 859102491 ps |
| CPU time | 66.36 seconds |
| Started | Jan 10 01:44:54 PM PST 24 |
| Finished | Jan 10 01:46:21 PM PST 24 |
| Peak memory | 556136 kb |
| Host | smart-35fe35ae-2f7a-4413-87d8-0009a3eb03c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378584645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2378584645 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.265630913 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 2353902426 ps |
| CPU time | 114.87 seconds |
| Started | Jan 10 01:44:53 PM PST 24 |
| Finished | Jan 10 01:47:09 PM PST 24 |
| Peak memory | 556016 kb |
| Host | smart-c35bb4a4-9869-4edb-aeb0-0d40a96e0491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265630913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.265630913 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3503583242 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 8767063710 ps |
| CPU time | 935.07 seconds |
| Started | Jan 10 01:44:47 PM PST 24 |
| Finished | Jan 10 02:00:27 PM PST 24 |
| Peak memory | 574724 kb |
| Host | smart-571969d3-1049-4b5f-a19b-78568b6cab88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503583242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.3503583242 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.16259277 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 829905753 ps |
| CPU time | 35.33 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:45:57 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-11e2e418-aca0-4b51-9f4d-cb0e0fa6a1a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16259277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.16259277 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3973358390 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 1199924306 ps |
| CPU time | 83.74 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:46:45 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-78f63402-20ac-4fb7-b03b-88df020b9d7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973358390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .3973358390 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2224954977 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 13944353555 ps |
| CPU time | 243.5 seconds |
| Started | Jan 10 01:44:59 PM PST 24 |
| Finished | Jan 10 01:49:22 PM PST 24 |
| Peak memory | 555148 kb |
| Host | smart-8eea47ae-2bfd-440a-8d23-d818ef49de13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224954977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.2224954977 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.2531901833 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 1000425419 ps |
| CPU time | 38.95 seconds |
| Started | Jan 10 01:44:46 PM PST 24 |
| Finished | Jan 10 01:45:29 PM PST 24 |
| Peak memory | 555080 kb |
| Host | smart-2621ae25-f4f8-4038-8390-b6833a2d2158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531901833 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.2531901833 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.740869611 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 666302704 ps |
| CPU time | 23.95 seconds |
| Started | Jan 10 01:44:46 PM PST 24 |
| Finished | Jan 10 01:45:13 PM PST 24 |
| Peak memory | 554976 kb |
| Host | smart-ae508b38-6abf-47df-8653-0d48349a6d1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740869611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.740869611 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.4065646389 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 1518782264 ps |
| CPU time | 54.2 seconds |
| Started | Jan 10 01:44:58 PM PST 24 |
| Finished | Jan 10 01:46:11 PM PST 24 |
| Peak memory | 555044 kb |
| Host | smart-2ca60956-3810-4d2e-a1bd-39791c0d14a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065646389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.4065646389 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.4088489908 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 69850107808 ps |
| CPU time | 771.74 seconds |
| Started | Jan 10 01:44:55 PM PST 24 |
| Finished | Jan 10 01:58:06 PM PST 24 |
| Peak memory | 554812 kb |
| Host | smart-8ce6bc41-8565-4a4d-9669-0ba709d522a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088489908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.4088489908 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3888381128 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 32033121581 ps |
| CPU time | 596.58 seconds |
| Started | Jan 10 01:44:47 PM PST 24 |
| Finished | Jan 10 01:54:48 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-bf37d2c9-0a8f-4dd3-ad87-4af716eb7132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888381128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3888381128 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.315561057 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 469866725 ps |
| CPU time | 35.59 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:45:56 PM PST 24 |
| Peak memory | 554792 kb |
| Host | smart-2969f089-bc95-4aa8-9726-7397d47c4472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315561057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.315561057 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.193022898 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1780936606 ps |
| CPU time | 54.84 seconds |
| Started | Jan 10 01:44:45 PM PST 24 |
| Finished | Jan 10 01:45:44 PM PST 24 |
| Peak memory | 555060 kb |
| Host | smart-2acfc1e4-bbe0-43c9-bf91-c4dd0be11863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193022898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.193022898 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.3523715783 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 212718344 ps |
| CPU time | 8.67 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:45:33 PM PST 24 |
| Peak memory | 552492 kb |
| Host | smart-462e6717-e2b0-4c43-b170-a55422a49ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523715783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.3523715783 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1972485236 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 7322563221 ps |
| CPU time | 78.72 seconds |
| Started | Jan 10 01:44:58 PM PST 24 |
| Finished | Jan 10 01:46:35 PM PST 24 |
| Peak memory | 552668 kb |
| Host | smart-b8f24ecb-2b2e-4602-851a-c258ba33ea53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972485236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1972485236 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.2035623077 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 5320090514 ps |
| CPU time | 93.41 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:46:54 PM PST 24 |
| Peak memory | 552736 kb |
| Host | smart-47cf8ba1-4ebf-4b4b-8fe0-6e4ff86ae9f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035623077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.2035623077 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3460024444 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 54339282 ps |
| CPU time | 6.35 seconds |
| Started | Jan 10 01:45:03 PM PST 24 |
| Finished | Jan 10 01:45:28 PM PST 24 |
| Peak memory | 552684 kb |
| Host | smart-d70fa58f-c2c7-4ec2-b864-a728410317f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460024444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.3460024444 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.4137732903 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 2117365776 ps |
| CPU time | 72.66 seconds |
| Started | Jan 10 01:45:11 PM PST 24 |
| Finished | Jan 10 01:46:47 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-d6556059-988a-4b22-b241-f22345ec44bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137732903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.4137732903 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1564235800 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 10775916513 ps |
| CPU time | 386.3 seconds |
| Started | Jan 10 01:44:48 PM PST 24 |
| Finished | Jan 10 01:51:19 PM PST 24 |
| Peak memory | 556056 kb |
| Host | smart-3405be7b-c3da-401a-9429-ab678a344a51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564235800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.1564235800 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3942686645 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 75657133 ps |
| CPU time | 37.46 seconds |
| Started | Jan 10 01:44:59 PM PST 24 |
| Finished | Jan 10 01:45:55 PM PST 24 |
| Peak memory | 554952 kb |
| Host | smart-951aa969-fb5a-4220-b5d7-94b7dcbf83c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942686645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.3942686645 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1818194023 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 1876673200 ps |
| CPU time | 134.26 seconds |
| Started | Jan 10 01:44:47 PM PST 24 |
| Finished | Jan 10 01:47:06 PM PST 24 |
| Peak memory | 556356 kb |
| Host | smart-8038b967-7bb5-44fa-9965-50f3e2cbe644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818194023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.1818194023 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.2253316309 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 66605783 ps |
| CPU time | 6.07 seconds |
| Started | Jan 10 01:44:47 PM PST 24 |
| Finished | Jan 10 01:44:58 PM PST 24 |
| Peak memory | 552720 kb |
| Host | smart-4ddaeeaf-7500-45fe-af33-af0888128c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253316309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.2253316309 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2932189552 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 445720242 ps |
| CPU time | 22.86 seconds |
| Started | Jan 10 01:44:53 PM PST 24 |
| Finished | Jan 10 01:45:37 PM PST 24 |
| Peak memory | 553956 kb |
| Host | smart-dc6e2704-1cae-4ba1-adad-bffe5c2f7e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932189552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .2932189552 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.3895958271 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 976517064 ps |
| CPU time | 38.13 seconds |
| Started | Jan 10 01:44:57 PM PST 24 |
| Finished | Jan 10 01:45:54 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-53c634e0-8993-43cc-8882-0620268abcee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895958271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.3895958271 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.856579640 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 884968279 ps |
| CPU time | 28.88 seconds |
| Started | Jan 10 01:45:02 PM PST 24 |
| Finished | Jan 10 01:45:50 PM PST 24 |
| Peak memory | 553844 kb |
| Host | smart-8a6a1a1f-15b3-43e7-812c-cc128b0e462b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856579640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.856579640 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.1624506103 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 239333863 ps |
| CPU time | 21.68 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:45:45 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-2a4b40cf-e0c1-4354-beff-d8268449f501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624506103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.1624506103 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.3743957032 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 36597919112 ps |
| CPU time | 388.31 seconds |
| Started | Jan 10 01:45:01 PM PST 24 |
| Finished | Jan 10 01:51:50 PM PST 24 |
| Peak memory | 555100 kb |
| Host | smart-1760061e-f2a3-4dc2-a555-b5ba456493c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743957032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.3743957032 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.1199134321 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 52539192274 ps |
| CPU time | 944.63 seconds |
| Started | Jan 10 01:44:58 PM PST 24 |
| Finished | Jan 10 02:01:00 PM PST 24 |
| Peak memory | 555116 kb |
| Host | smart-3c77e6df-a972-405b-ae3b-0b630a06847a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199134321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.1199134321 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.1961749481 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 199039028 ps |
| CPU time | 21 seconds |
| Started | Jan 10 01:44:46 PM PST 24 |
| Finished | Jan 10 01:45:12 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-6b8d1aec-4184-4bad-b20d-9063cb9755eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961749481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.1961749481 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.2919940057 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 862261758 ps |
| CPU time | 25.46 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:45:46 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-74bf4d9a-a75a-4f9d-9192-5f9ecd73235a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919940057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.2919940057 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.2873026000 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 49622150 ps |
| CPU time | 6.71 seconds |
| Started | Jan 10 01:44:51 PM PST 24 |
| Finished | Jan 10 01:45:14 PM PST 24 |
| Peak memory | 552940 kb |
| Host | smart-b9876b0a-11c0-4458-85d3-4c6db7baf9a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873026000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.2873026000 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.3453980315 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 8904857469 ps |
| CPU time | 96.48 seconds |
| Started | Jan 10 01:44:59 PM PST 24 |
| Finished | Jan 10 01:46:54 PM PST 24 |
| Peak memory | 552604 kb |
| Host | smart-3b1b5d45-e029-475e-9a71-d98dba6ed601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453980315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.3453980315 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.39416457 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 4415000864 ps |
| CPU time | 75.05 seconds |
| Started | Jan 10 01:44:54 PM PST 24 |
| Finished | Jan 10 01:46:30 PM PST 24 |
| Peak memory | 552688 kb |
| Host | smart-de3d818d-192a-4b97-bdfd-a1793f487fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39416457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.39416457 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2542362400 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 41275441 ps |
| CPU time | 5.57 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:45:27 PM PST 24 |
| Peak memory | 552656 kb |
| Host | smart-f8f253ae-8e90-4263-8aa2-52b9ef971e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542362400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.2542362400 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.4203652602 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 3539423541 ps |
| CPU time | 291.3 seconds |
| Started | Jan 10 01:44:58 PM PST 24 |
| Finished | Jan 10 01:50:08 PM PST 24 |
| Peak memory | 556988 kb |
| Host | smart-5f2b90f6-2366-49e0-859c-378b740104b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203652602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.4203652602 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3145059051 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 4520826420 ps |
| CPU time | 160.49 seconds |
| Started | Jan 10 01:45:07 PM PST 24 |
| Finished | Jan 10 01:48:10 PM PST 24 |
| Peak memory | 555844 kb |
| Host | smart-7ce1b3cc-c6b7-4daf-9ad7-078530ac55af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145059051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3145059051 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.2603768636 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 2224943390 ps |
| CPU time | 242.15 seconds |
| Started | Jan 10 01:45:06 PM PST 24 |
| Finished | Jan 10 01:49:29 PM PST 24 |
| Peak memory | 557388 kb |
| Host | smart-0aabe5b4-7577-4da2-bf79-a4553016cfd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603768636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.2603768636 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.4001911881 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 8371826386 ps |
| CPU time | 318.51 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:50:44 PM PST 24 |
| Peak memory | 556180 kb |
| Host | smart-78cfd393-d52f-4692-af0f-78e25f140d66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001911881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.4001911881 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.906622379 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 116781512 ps |
| CPU time | 16.27 seconds |
| Started | Jan 10 01:45:02 PM PST 24 |
| Finished | Jan 10 01:45:38 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-f33dacf4-3cf2-4faf-8cd5-bd94ac881996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906622379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.906622379 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.3883953301 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 840893454 ps |
| CPU time | 62.9 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:46:35 PM PST 24 |
| Peak memory | 553996 kb |
| Host | smart-bde765df-b868-4b6a-80e7-efec8d07cf35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883953301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .3883953301 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2906755239 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 87958351583 ps |
| CPU time | 1622.66 seconds |
| Started | Jan 10 01:45:01 PM PST 24 |
| Finished | Jan 10 02:12:24 PM PST 24 |
| Peak memory | 555884 kb |
| Host | smart-ec52a427-cf77-4b88-8ca2-a3f4d7741309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906755239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.2906755239 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2713191319 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 909531260 ps |
| CPU time | 32.44 seconds |
| Started | Jan 10 01:45:07 PM PST 24 |
| Finished | Jan 10 01:46:01 PM PST 24 |
| Peak memory | 554704 kb |
| Host | smart-fac95115-dd99-4b4f-9a46-18b323fbb606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713191319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.2713191319 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2646606708 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 464753527 ps |
| CPU time | 33.79 seconds |
| Started | Jan 10 01:45:08 PM PST 24 |
| Finished | Jan 10 01:46:04 PM PST 24 |
| Peak memory | 553840 kb |
| Host | smart-10bca022-a750-443f-b72f-70367a0c9d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646606708 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2646606708 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.605574713 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 107875236 ps |
| CPU time | 7.18 seconds |
| Started | Jan 10 01:45:07 PM PST 24 |
| Finished | Jan 10 01:45:36 PM PST 24 |
| Peak memory | 552668 kb |
| Host | smart-738f3128-6e38-4558-94f2-671a3bbbd552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605574713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.605574713 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3366996413 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 48040394889 ps |
| CPU time | 549.47 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:54:31 PM PST 24 |
| Peak memory | 554768 kb |
| Host | smart-3bcc6951-be76-40e4-b10d-813b6437243b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366996413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3366996413 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.579169562 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 17057601886 ps |
| CPU time | 293.65 seconds |
| Started | Jan 10 01:45:10 PM PST 24 |
| Finished | Jan 10 01:50:27 PM PST 24 |
| Peak memory | 554760 kb |
| Host | smart-4214ca8b-bf5a-4e0a-9c50-cbd9793e893d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579169562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.579169562 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.1426885088 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 505646788 ps |
| CPU time | 36.52 seconds |
| Started | Jan 10 01:45:06 PM PST 24 |
| Finished | Jan 10 01:46:04 PM PST 24 |
| Peak memory | 555020 kb |
| Host | smart-9b95df7e-f522-4188-8765-bd2dd147d7ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426885088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.1426885088 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.2713644637 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 140533192 ps |
| CPU time | 11.17 seconds |
| Started | Jan 10 01:45:10 PM PST 24 |
| Finished | Jan 10 01:45:45 PM PST 24 |
| Peak memory | 554952 kb |
| Host | smart-300769da-fca8-4d8e-ab13-6ae81ff80e39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713644637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.2713644637 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.3258836807 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 161864225 ps |
| CPU time | 7.56 seconds |
| Started | Jan 10 01:44:57 PM PST 24 |
| Finished | Jan 10 01:45:23 PM PST 24 |
| Peak memory | 552644 kb |
| Host | smart-fe9209f6-5589-426a-a26b-13cf993833b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258836807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.3258836807 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.3175570790 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 7632140014 ps |
| CPU time | 81.06 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:46:46 PM PST 24 |
| Peak memory | 552516 kb |
| Host | smart-17a8a4a5-c34c-4c61-864f-205663c33611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175570790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.3175570790 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.242044774 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 4777155391 ps |
| CPU time | 77.58 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:46:44 PM PST 24 |
| Peak memory | 552988 kb |
| Host | smart-a51738d7-9b02-460d-b641-82d5bb595cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242044774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.242044774 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2112496280 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 49376079 ps |
| CPU time | 6.28 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:45:27 PM PST 24 |
| Peak memory | 552676 kb |
| Host | smart-9a0a6e92-cb15-41c7-8c21-6f4111c6d09f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112496280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.2112496280 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.1253759509 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 1869013678 ps |
| CPU time | 69.16 seconds |
| Started | Jan 10 01:45:11 PM PST 24 |
| Finished | Jan 10 01:46:43 PM PST 24 |
| Peak memory | 554756 kb |
| Host | smart-b52a68df-0e54-409e-b9d2-06417c558c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253759509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1253759509 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2680701079 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 951683818 ps |
| CPU time | 65.2 seconds |
| Started | Jan 10 01:45:10 PM PST 24 |
| Finished | Jan 10 01:46:38 PM PST 24 |
| Peak memory | 555816 kb |
| Host | smart-9f8792bc-f00f-4246-8e3e-10ad6a21baa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680701079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2680701079 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.78137175 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 8605977 ps |
| CPU time | 26.18 seconds |
| Started | Jan 10 01:45:03 PM PST 24 |
| Finished | Jan 10 01:45:47 PM PST 24 |
| Peak memory | 552612 kb |
| Host | smart-cf00f311-ec5c-4d97-835b-9c050b0b2aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78137175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_w ith_rand_reset.78137175 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1399999916 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 93257395 ps |
| CPU time | 22.1 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:45:55 PM PST 24 |
| Peak memory | 554112 kb |
| Host | smart-6aa66efb-3950-4934-9818-0c9fd9bee471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399999916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.1399999916 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.769854303 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 116758020 ps |
| CPU time | 14.61 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:45:47 PM PST 24 |
| Peak memory | 555088 kb |
| Host | smart-3cdc4120-9533-44ee-b7e0-d38191378afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769854303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.769854303 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.3107103656 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 256932347 ps |
| CPU time | 11.48 seconds |
| Started | Jan 10 01:45:06 PM PST 24 |
| Finished | Jan 10 01:45:38 PM PST 24 |
| Peak memory | 552672 kb |
| Host | smart-f354c240-b659-4dcd-a751-15c4b3bf2ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107103656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .3107103656 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.4053231187 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 627290036 ps |
| CPU time | 25.2 seconds |
| Started | Jan 10 01:45:03 PM PST 24 |
| Finished | Jan 10 01:45:46 PM PST 24 |
| Peak memory | 554664 kb |
| Host | smart-2b371657-d6f0-47fa-8ca4-0dc3fa9cd088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053231187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.4053231187 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.2574356048 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 1309519811 ps |
| CPU time | 41.36 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:46:13 PM PST 24 |
| Peak memory | 554572 kb |
| Host | smart-12fe50aa-62bf-4072-a436-ec99e75520d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574356048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2574356048 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.1069768410 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 394330835 ps |
| CPU time | 34.9 seconds |
| Started | Jan 10 01:45:10 PM PST 24 |
| Finished | Jan 10 01:46:09 PM PST 24 |
| Peak memory | 554744 kb |
| Host | smart-c438d50d-c0e2-4964-953c-f032e33d18f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069768410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.1069768410 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.9599376 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 83687998795 ps |
| CPU time | 998.71 seconds |
| Started | Jan 10 01:44:57 PM PST 24 |
| Finished | Jan 10 02:01:54 PM PST 24 |
| Peak memory | 554728 kb |
| Host | smart-db0b8da8-40a1-42d4-ab14-3db018533979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9599376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.9599376 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2894252788 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 62564316291 ps |
| CPU time | 1093.35 seconds |
| Started | Jan 10 01:45:08 PM PST 24 |
| Finished | Jan 10 02:03:45 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-636f99b3-cdfb-47be-8c35-96aa13b9d477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894252788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2894252788 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2720918702 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 430531309 ps |
| CPU time | 33.64 seconds |
| Started | Jan 10 01:44:59 PM PST 24 |
| Finished | Jan 10 01:45:53 PM PST 24 |
| Peak memory | 555012 kb |
| Host | smart-be4813d3-2498-43f3-8a47-64dc91b1f2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720918702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.2720918702 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.3785986440 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 374848553 ps |
| CPU time | 13.13 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:45:45 PM PST 24 |
| Peak memory | 554912 kb |
| Host | smart-09c695eb-d80b-4b95-bec7-b00005dcb069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785986440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3785986440 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.3564674175 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 50977376 ps |
| CPU time | 5.97 seconds |
| Started | Jan 10 01:45:16 PM PST 24 |
| Finished | Jan 10 01:45:42 PM PST 24 |
| Peak memory | 552980 kb |
| Host | smart-50888efd-219f-4290-a457-6179d00422e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564674175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.3564674175 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.3619346711 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 9280991283 ps |
| CPU time | 100.15 seconds |
| Started | Jan 10 01:45:17 PM PST 24 |
| Finished | Jan 10 01:47:17 PM PST 24 |
| Peak memory | 553044 kb |
| Host | smart-b2144066-49ab-48fa-a0eb-c5119f0dce45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619346711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.3619346711 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2135035753 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 5350684513 ps |
| CPU time | 82.95 seconds |
| Started | Jan 10 01:45:13 PM PST 24 |
| Finished | Jan 10 01:46:58 PM PST 24 |
| Peak memory | 552760 kb |
| Host | smart-160d467d-00ee-4df9-90af-d7d3a6b51b78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135035753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2135035753 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3945701293 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 44568579 ps |
| CPU time | 5.7 seconds |
| Started | Jan 10 01:45:13 PM PST 24 |
| Finished | Jan 10 01:45:41 PM PST 24 |
| Peak memory | 552480 kb |
| Host | smart-0b7bd751-9d02-444d-a8a7-12de84b0095e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945701293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3945701293 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.308922975 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 3220027635 ps |
| CPU time | 239.43 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:49:23 PM PST 24 |
| Peak memory | 555888 kb |
| Host | smart-305e16bb-350a-4739-8370-8a52cc4c3790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308922975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.308922975 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.965658180 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 13518858825 ps |
| CPU time | 528.87 seconds |
| Started | Jan 10 01:45:07 PM PST 24 |
| Finished | Jan 10 01:54:18 PM PST 24 |
| Peak memory | 555144 kb |
| Host | smart-d13729e3-086c-484a-8adb-de8bda87325e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965658180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.965658180 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.202721787 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 679083546 ps |
| CPU time | 221.21 seconds |
| Started | Jan 10 01:45:02 PM PST 24 |
| Finished | Jan 10 01:49:03 PM PST 24 |
| Peak memory | 557288 kb |
| Host | smart-08f1cb99-b7a5-4380-bed6-ce35cc0d64de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202721787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_ with_rand_reset.202721787 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.597976384 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 2015200364 ps |
| CPU time | 140.4 seconds |
| Started | Jan 10 01:44:59 PM PST 24 |
| Finished | Jan 10 01:47:37 PM PST 24 |
| Peak memory | 555932 kb |
| Host | smart-91a3c156-4a35-4e54-b31b-19ab4ef2ae05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597976384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_reset_error.597976384 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.311539458 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 324475380 ps |
| CPU time | 14.93 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:45:47 PM PST 24 |
| Peak memory | 555040 kb |
| Host | smart-4c9e2752-923e-47fd-ba11-f37817287376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311539458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.311539458 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.28790363 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 65982751 ps |
| CPU time | 7.03 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:45:31 PM PST 24 |
| Peak memory | 552644 kb |
| Host | smart-7797c565-70eb-4081-9a5d-75c15ecf9c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28790363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device.28790363 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.4201757116 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 136622700503 ps |
| CPU time | 2415.15 seconds |
| Started | Jan 10 01:45:02 PM PST 24 |
| Finished | Jan 10 02:25:37 PM PST 24 |
| Peak memory | 555944 kb |
| Host | smart-3d584b4f-60f0-41a6-a93c-a635b8526292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201757116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.4201757116 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2565014074 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 425435969 ps |
| CPU time | 18.62 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:45:42 PM PST 24 |
| Peak memory | 554920 kb |
| Host | smart-69610a87-3b72-4845-ac85-ff1a9c4fd9c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565014074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.2565014074 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.125333569 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 578642666 ps |
| CPU time | 43.55 seconds |
| Started | Jan 10 01:45:00 PM PST 24 |
| Finished | Jan 10 01:46:05 PM PST 24 |
| Peak memory | 554964 kb |
| Host | smart-dcb78aa6-1414-4318-9c50-c71022f5182a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125333569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.125333569 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.2066747183 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 355022194 ps |
| CPU time | 30.01 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:46:02 PM PST 24 |
| Peak memory | 553952 kb |
| Host | smart-c5c6110a-eae3-45cb-80c8-d9a9bcda536b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066747183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2066747183 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.2288488898 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 10304077423 ps |
| CPU time | 116.34 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:47:21 PM PST 24 |
| Peak memory | 552756 kb |
| Host | smart-5d303820-3d76-4d25-b8fd-f9180ec30780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288488898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.2288488898 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.3160674735 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 42826387565 ps |
| CPU time | 885.51 seconds |
| Started | Jan 10 01:45:02 PM PST 24 |
| Finished | Jan 10 02:00:07 PM PST 24 |
| Peak memory | 554704 kb |
| Host | smart-7201d52c-fbaa-482b-8abb-65029ac3f0b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160674735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.3160674735 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1765293387 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 173901418 ps |
| CPU time | 16.24 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:45:40 PM PST 24 |
| Peak memory | 554736 kb |
| Host | smart-bbfc90e6-14e4-49e7-a594-2d3e01b79f23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765293387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.1765293387 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.1232756564 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 2669138967 ps |
| CPU time | 78.9 seconds |
| Started | Jan 10 01:45:07 PM PST 24 |
| Finished | Jan 10 01:46:48 PM PST 24 |
| Peak memory | 555112 kb |
| Host | smart-705664c3-8db2-4651-a777-7f4841b84ab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232756564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1232756564 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.2950047722 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 149011075 ps |
| CPU time | 7.35 seconds |
| Started | Jan 10 01:45:06 PM PST 24 |
| Finished | Jan 10 01:45:34 PM PST 24 |
| Peak memory | 552652 kb |
| Host | smart-362e8c79-687d-4ffb-9672-b53dd04d8446 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950047722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.2950047722 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.662478866 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 6112153614 ps |
| CPU time | 64.15 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:46:30 PM PST 24 |
| Peak memory | 552708 kb |
| Host | smart-d65d4471-101b-4daa-a4dc-e49dad146bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662478866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.662478866 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.2866728209 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 4265223642 ps |
| CPU time | 64.08 seconds |
| Started | Jan 10 01:45:12 PM PST 24 |
| Finished | Jan 10 01:46:39 PM PST 24 |
| Peak memory | 553020 kb |
| Host | smart-2e4feb6c-e6c4-47dc-9093-d6e5b5001285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866728209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.2866728209 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.2474025476 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 49438177 ps |
| CPU time | 5.89 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:45:31 PM PST 24 |
| Peak memory | 552648 kb |
| Host | smart-87c89d49-1e2b-4d82-83bd-ab06e952063b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474025476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.2474025476 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.2575841090 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 17926850998 ps |
| CPU time | 780.36 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:58:33 PM PST 24 |
| Peak memory | 559300 kb |
| Host | smart-2c0a4a3c-d827-4b4c-984e-af112ba7493b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575841090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.2575841090 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.187894090 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 1600443107 ps |
| CPU time | 46.54 seconds |
| Started | Jan 10 01:45:07 PM PST 24 |
| Finished | Jan 10 01:46:16 PM PST 24 |
| Peak memory | 554716 kb |
| Host | smart-f41fcb6f-bd63-43a2-9744-537c6b6a93c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187894090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.187894090 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2254703868 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3274375710 ps |
| CPU time | 502.88 seconds |
| Started | Jan 10 01:44:59 PM PST 24 |
| Finished | Jan 10 01:53:43 PM PST 24 |
| Peak memory | 559524 kb |
| Host | smart-d53594c7-c78e-4ca3-81fe-aa6e785c7950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254703868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.2254703868 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2602164018 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 3668307632 ps |
| CPU time | 491.91 seconds |
| Started | Jan 10 01:45:07 PM PST 24 |
| Finished | Jan 10 01:53:41 PM PST 24 |
| Peak memory | 568224 kb |
| Host | smart-034f6383-add3-478e-9e81-535f185ac89a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602164018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2602164018 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.394567603 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 1142947689 ps |
| CPU time | 45.91 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:46:23 PM PST 24 |
| Peak memory | 555112 kb |
| Host | smart-e1e0ab7a-629d-4fc7-bcc5-16fba2803146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394567603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.394567603 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1699385845 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 1355374548 ps |
| CPU time | 58.12 seconds |
| Started | Jan 10 01:45:08 PM PST 24 |
| Finished | Jan 10 01:46:29 PM PST 24 |
| Peak memory | 555100 kb |
| Host | smart-6601cfd2-27ff-4672-b0ab-a1bc1fb61338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699385845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .1699385845 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.856826002 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 117208322760 ps |
| CPU time | 1950.74 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 02:17:55 PM PST 24 |
| Peak memory | 556212 kb |
| Host | smart-db0e595a-1bc6-4ad8-97cc-3497f95954e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856826002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d evice_slow_rsp.856826002 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1203723821 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 326321401 ps |
| CPU time | 32.98 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:46:06 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-b39e232a-f581-4c64-9a4e-e70efedf3bec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203723821 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.1203723821 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.1912686997 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 1161500842 ps |
| CPU time | 38.67 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:46:04 PM PST 24 |
| Peak memory | 554744 kb |
| Host | smart-1e61a053-335e-4063-addf-a21e3540b484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912686997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.1912686997 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.3788160919 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 1756965465 ps |
| CPU time | 61.6 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:46:28 PM PST 24 |
| Peak memory | 554648 kb |
| Host | smart-2c9ca255-edb2-4cc1-9dad-1b2d1a256ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788160919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.3788160919 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.126146302 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 15906632126 ps |
| CPU time | 167.62 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:48:12 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-385620aa-2816-46a3-bb06-0088c92da414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126146302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.126146302 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.800059862 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 27164934636 ps |
| CPU time | 490.76 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:53:43 PM PST 24 |
| Peak memory | 554876 kb |
| Host | smart-52de64f7-8c9a-4cab-bc40-98218f2de747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800059862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.800059862 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.1926327272 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 98312881 ps |
| CPU time | 10.56 seconds |
| Started | Jan 10 01:45:08 PM PST 24 |
| Finished | Jan 10 01:45:41 PM PST 24 |
| Peak memory | 553896 kb |
| Host | smart-0ccf5ced-2747-4799-b010-5b0db7c9c815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926327272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.1926327272 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.1805286166 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 771446742 ps |
| CPU time | 21.91 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:45:55 PM PST 24 |
| Peak memory | 553920 kb |
| Host | smart-e3a055a1-7eaf-4d1c-8706-e3dc98e77b6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805286166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.1805286166 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.672637360 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 242829998 ps |
| CPU time | 9.6 seconds |
| Started | Jan 10 01:45:06 PM PST 24 |
| Finished | Jan 10 01:45:36 PM PST 24 |
| Peak memory | 552908 kb |
| Host | smart-c7bbac0f-f205-4b0e-885f-79dcee5a9e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672637360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.672637360 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.2191316956 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 8746914279 ps |
| CPU time | 89.59 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:46:54 PM PST 24 |
| Peak memory | 552980 kb |
| Host | smart-6fcd44e8-ba69-496e-8a06-cd0c5b8259f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191316956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.2191316956 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2093116524 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 4112902189 ps |
| CPU time | 66.53 seconds |
| Started | Jan 10 01:45:08 PM PST 24 |
| Finished | Jan 10 01:46:38 PM PST 24 |
| Peak memory | 552736 kb |
| Host | smart-f1440929-11f2-48d0-bcc3-354463942708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093116524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.2093116524 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.4101804773 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 42458940 ps |
| CPU time | 5.8 seconds |
| Started | Jan 10 01:45:08 PM PST 24 |
| Finished | Jan 10 01:45:36 PM PST 24 |
| Peak memory | 552936 kb |
| Host | smart-9a4095e3-8492-4128-bd6d-d4722b0c6296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101804773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.4101804773 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.2589166687 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 12612533818 ps |
| CPU time | 422.71 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:52:35 PM PST 24 |
| Peak memory | 555992 kb |
| Host | smart-1c51a506-36f8-498e-b189-cba1a1e74a8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589166687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.2589166687 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2355254599 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 4503709241 ps |
| CPU time | 147.65 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:48:00 PM PST 24 |
| Peak memory | 555980 kb |
| Host | smart-c867b284-5bb6-4a09-96de-54c0965e1006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355254599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2355254599 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.677959611 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 7090720578 ps |
| CPU time | 411.03 seconds |
| Started | Jan 10 01:45:15 PM PST 24 |
| Finished | Jan 10 01:52:27 PM PST 24 |
| Peak memory | 557368 kb |
| Host | smart-2a3ca866-0d02-42ef-992a-6ccd4fceee8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677959611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_ with_rand_reset.677959611 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.844836706 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 1480059380 ps |
| CPU time | 203.23 seconds |
| Started | Jan 10 01:45:15 PM PST 24 |
| Finished | Jan 10 01:48:59 PM PST 24 |
| Peak memory | 559604 kb |
| Host | smart-6b7699b3-ab6a-40b4-bef8-36bf6779f14f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844836706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.844836706 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.2117702615 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 107653361 ps |
| CPU time | 13.03 seconds |
| Started | Jan 10 01:45:11 PM PST 24 |
| Finished | Jan 10 01:45:47 PM PST 24 |
| Peak memory | 554960 kb |
| Host | smart-29bc7220-5ab1-4392-89b1-b305654279ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117702615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.2117702615 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.4262914675 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 5144357612 ps |
| CPU time | 261.81 seconds |
| Started | Jan 10 01:36:42 PM PST 24 |
| Finished | Jan 10 01:41:06 PM PST 24 |
| Peak memory | 612540 kb |
| Host | smart-dbbb255b-f08d-4403-b817-e4c6ab55ee67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262914675 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.4262914675 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.3591765219 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 3956293240 ps |
| CPU time | 365.49 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:42:47 PM PST 24 |
| Peak memory | 580800 kb |
| Host | smart-eeab99c9-3795-4f40-b81e-5163e2ffd6f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591765219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.3591765219 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2952440516 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 18003424928 ps |
| CPU time | 2048.29 seconds |
| Started | Jan 10 01:36:24 PM PST 24 |
| Finished | Jan 10 02:10:39 PM PST 24 |
| Peak memory | 580876 kb |
| Host | smart-a18f381e-1cb2-4884-a02b-40ef1a474619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952440516 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.2952440516 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.2495134100 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 2759540478 ps |
| CPU time | 130.55 seconds |
| Started | Jan 10 01:36:21 PM PST 24 |
| Finished | Jan 10 01:38:37 PM PST 24 |
| Peak memory | 580808 kb |
| Host | smart-3f16e878-8ee5-45ac-b982-cc004c84ea09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495134100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.2495134100 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2931825229 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 2909152779 ps |
| CPU time | 117.25 seconds |
| Started | Jan 10 01:36:36 PM PST 24 |
| Finished | Jan 10 01:38:36 PM PST 24 |
| Peak memory | 554888 kb |
| Host | smart-ee3e416f-6461-4df3-a927-73cffe834f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931825229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2931825229 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3614926805 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 22952229473 ps |
| CPU time | 346.9 seconds |
| Started | Jan 10 01:36:37 PM PST 24 |
| Finished | Jan 10 01:42:25 PM PST 24 |
| Peak memory | 555140 kb |
| Host | smart-4218ab13-5818-4b9f-ac3f-a51f861d8918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614926805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.3614926805 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2445704201 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 343479454 ps |
| CPU time | 36.55 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:37:18 PM PST 24 |
| Peak memory | 554692 kb |
| Host | smart-ddbd29f9-f728-461b-b9a4-e3fb1196eff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445704201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2445704201 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.1262428055 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 432213582 ps |
| CPU time | 16.01 seconds |
| Started | Jan 10 01:36:36 PM PST 24 |
| Finished | Jan 10 01:36:54 PM PST 24 |
| Peak memory | 554928 kb |
| Host | smart-eff030b0-b0d0-4e91-875e-54d3ab8f5c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262428055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1262428055 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.2777817401 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 432408354 ps |
| CPU time | 34.6 seconds |
| Started | Jan 10 01:36:36 PM PST 24 |
| Finished | Jan 10 01:37:12 PM PST 24 |
| Peak memory | 555048 kb |
| Host | smart-8696da79-8590-42cf-a3de-34afd026caa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777817401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.2777817401 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.925785499 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 124106145263 ps |
| CPU time | 1421.38 seconds |
| Started | Jan 10 01:36:36 PM PST 24 |
| Finished | Jan 10 02:00:21 PM PST 24 |
| Peak memory | 554884 kb |
| Host | smart-8b7ed852-f4e7-4767-935a-f4f959563ba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925785499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.925785499 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.4035374085 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 38705837094 ps |
| CPU time | 695.47 seconds |
| Started | Jan 10 01:36:35 PM PST 24 |
| Finished | Jan 10 01:48:14 PM PST 24 |
| Peak memory | 554860 kb |
| Host | smart-4638e486-d60d-4e2d-b83a-b93f0294d959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035374085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.4035374085 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.680800719 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 406763693 ps |
| CPU time | 33.69 seconds |
| Started | Jan 10 01:36:35 PM PST 24 |
| Finished | Jan 10 01:37:11 PM PST 24 |
| Peak memory | 554696 kb |
| Host | smart-4cb63ba9-1a80-4f43-83f6-e2606557bbca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680800719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delay s.680800719 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.2610222392 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 92192205 ps |
| CPU time | 9 seconds |
| Started | Jan 10 01:36:33 PM PST 24 |
| Finished | Jan 10 01:36:44 PM PST 24 |
| Peak memory | 555000 kb |
| Host | smart-b1ccd218-ea81-4e21-bbb0-2b986cdbaec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610222392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2610222392 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.1289138688 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 49808506 ps |
| CPU time | 5.87 seconds |
| Started | Jan 10 01:36:26 PM PST 24 |
| Finished | Jan 10 01:36:37 PM PST 24 |
| Peak memory | 552932 kb |
| Host | smart-2893c568-03e7-4db3-934b-6d6b9095c50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289138688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1289138688 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2362749598 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 8214548288 ps |
| CPU time | 90.65 seconds |
| Started | Jan 10 01:36:36 PM PST 24 |
| Finished | Jan 10 01:38:08 PM PST 24 |
| Peak memory | 553040 kb |
| Host | smart-f6a8766f-40c7-4d41-962c-b40eab7eb2de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362749598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2362749598 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1212743616 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 4500581877 ps |
| CPU time | 71.88 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:37:53 PM PST 24 |
| Peak memory | 552944 kb |
| Host | smart-d5be39b0-1b9c-458e-85e8-b255c5d12004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212743616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1212743616 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.48493090 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 49751247 ps |
| CPU time | 5.96 seconds |
| Started | Jan 10 01:36:30 PM PST 24 |
| Finished | Jan 10 01:36:39 PM PST 24 |
| Peak memory | 552656 kb |
| Host | smart-95bce70c-37e6-49c7-907e-7dc4dd25ccc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48493090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.48493090 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.4180921556 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 5552868234 ps |
| CPU time | 167.34 seconds |
| Started | Jan 10 01:36:38 PM PST 24 |
| Finished | Jan 10 01:39:28 PM PST 24 |
| Peak memory | 555920 kb |
| Host | smart-3347c91d-06a5-42b8-8800-df708e76da65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180921556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4180921556 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2063962706 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 53168109 ps |
| CPU time | 6.06 seconds |
| Started | Jan 10 01:36:34 PM PST 24 |
| Finished | Jan 10 01:36:42 PM PST 24 |
| Peak memory | 552920 kb |
| Host | smart-729c29c4-1789-4c9d-8fea-e7eba6878bf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063962706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2063962706 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1701276491 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 4433748308 ps |
| CPU time | 176.18 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:39:39 PM PST 24 |
| Peak memory | 556440 kb |
| Host | smart-0b3b17fa-b800-4a6c-af7e-da8bd6c909cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701276491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.1701276491 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2469727806 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 365010873 ps |
| CPU time | 97.48 seconds |
| Started | Jan 10 01:36:33 PM PST 24 |
| Finished | Jan 10 01:38:12 PM PST 24 |
| Peak memory | 556300 kb |
| Host | smart-4d626687-55ed-4a9a-86ee-5c43ca19833e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469727806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.2469727806 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.571541302 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 166036533 ps |
| CPU time | 19.76 seconds |
| Started | Jan 10 01:36:39 PM PST 24 |
| Finished | Jan 10 01:37:01 PM PST 24 |
| Peak memory | 554736 kb |
| Host | smart-fff1a7d9-8a93-430f-b039-b0e0a680b73d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571541302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.571541302 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.2096976306 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 257910130 ps |
| CPU time | 21.36 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:45:46 PM PST 24 |
| Peak memory | 554740 kb |
| Host | smart-77feff20-0ce8-4aa7-8d94-c38bbf1bec69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096976306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .2096976306 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1327656180 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 85185426978 ps |
| CPU time | 1572.1 seconds |
| Started | Jan 10 01:45:03 PM PST 24 |
| Finished | Jan 10 02:11:34 PM PST 24 |
| Peak memory | 555152 kb |
| Host | smart-9d117eff-8028-4a99-95c1-cf1c06f053c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327656180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.1327656180 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3038710740 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 616049712 ps |
| CPU time | 24.14 seconds |
| Started | Jan 10 01:45:16 PM PST 24 |
| Finished | Jan 10 01:46:00 PM PST 24 |
| Peak memory | 554988 kb |
| Host | smart-27e75699-065a-447e-a120-532420aecf12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038710740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.3038710740 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.1624478909 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 1410801184 ps |
| CPU time | 44.75 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:46:22 PM PST 24 |
| Peak memory | 554960 kb |
| Host | smart-5412f791-07f5-4f5c-9cc8-2689a3798f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624478909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1624478909 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.2506725039 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 126129743 ps |
| CPU time | 12.37 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:45:50 PM PST 24 |
| Peak memory | 555060 kb |
| Host | smart-a6ba5422-ef1a-4008-a75f-1c36af438f50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506725039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2506725039 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2161303674 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 47164849329 ps |
| CPU time | 554.49 seconds |
| Started | Jan 10 01:45:13 PM PST 24 |
| Finished | Jan 10 01:54:50 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-0f708070-055c-4c71-9620-3079acfcf1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161303674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2161303674 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.1399515490 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 69189689495 ps |
| CPU time | 1147.78 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 02:04:32 PM PST 24 |
| Peak memory | 554928 kb |
| Host | smart-22662cc3-763a-4b13-b7fb-1da530f3c5e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399515490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.1399515490 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2211858436 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 470708659 ps |
| CPU time | 43.45 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:46:21 PM PST 24 |
| Peak memory | 554736 kb |
| Host | smart-674dba60-a8ba-4110-a40c-d791f22d7d6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211858436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.2211858436 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.3838840077 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 463656218 ps |
| CPU time | 30.98 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:46:08 PM PST 24 |
| Peak memory | 554748 kb |
| Host | smart-66bc7f10-6664-46d0-89db-ebf6a895ec88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838840077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.3838840077 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.461753555 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 207584020 ps |
| CPU time | 8.43 seconds |
| Started | Jan 10 01:45:12 PM PST 24 |
| Finished | Jan 10 01:45:43 PM PST 24 |
| Peak memory | 552704 kb |
| Host | smart-289e669b-5868-42f4-bdec-71a1be5b8e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461753555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.461753555 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1926697437 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 8627668984 ps |
| CPU time | 86.02 seconds |
| Started | Jan 10 01:45:15 PM PST 24 |
| Finished | Jan 10 01:47:02 PM PST 24 |
| Peak memory | 553072 kb |
| Host | smart-36c72675-1a3e-4425-843a-febc0238ac26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926697437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1926697437 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.530467058 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 4642980152 ps |
| CPU time | 76.91 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:46:48 PM PST 24 |
| Peak memory | 553004 kb |
| Host | smart-d5a15326-56e9-4a71-a9af-59c69c8371f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530467058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.530467058 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2884203896 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 37564868 ps |
| CPU time | 5.49 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:45:43 PM PST 24 |
| Peak memory | 552660 kb |
| Host | smart-123f3b24-0eb7-4c1c-b5c6-c2044ed7322a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884203896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2884203896 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.4112989429 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 9307021839 ps |
| CPU time | 369.01 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:51:46 PM PST 24 |
| Peak memory | 556832 kb |
| Host | smart-baf8a15c-b2d6-4297-9847-286126ae6b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112989429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.4112989429 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2032791922 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 3621475841 ps |
| CPU time | 292.72 seconds |
| Started | Jan 10 01:45:17 PM PST 24 |
| Finished | Jan 10 01:50:29 PM PST 24 |
| Peak memory | 556792 kb |
| Host | smart-b8565c2c-839f-452a-b00a-67fa7e489171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032791922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2032791922 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.566021986 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 467427912 ps |
| CPU time | 77.76 seconds |
| Started | Jan 10 01:45:04 PM PST 24 |
| Finished | Jan 10 01:46:41 PM PST 24 |
| Peak memory | 555924 kb |
| Host | smart-9c05b2fa-3727-4d9b-97fb-a2094583a87a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566021986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.566021986 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.107132919 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 4949989355 ps |
| CPU time | 260.65 seconds |
| Started | Jan 10 01:45:11 PM PST 24 |
| Finished | Jan 10 01:49:56 PM PST 24 |
| Peak memory | 559324 kb |
| Host | smart-9f64a4de-0058-42d4-acf2-431bcb4dc459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107132919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_reset_error.107132919 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.4274190914 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 254636786 ps |
| CPU time | 26.31 seconds |
| Started | Jan 10 01:45:06 PM PST 24 |
| Finished | Jan 10 01:45:53 PM PST 24 |
| Peak memory | 555072 kb |
| Host | smart-df9c3454-91b8-4816-8221-b593d822606d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274190914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.4274190914 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.2313158035 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 1126862304 ps |
| CPU time | 43.7 seconds |
| Started | Jan 10 01:45:17 PM PST 24 |
| Finished | Jan 10 01:46:20 PM PST 24 |
| Peak memory | 553940 kb |
| Host | smart-807c1ede-aa87-48e7-84a2-c7f8ec189e79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313158035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .2313158035 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3338943010 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 2803051487 ps |
| CPU time | 50.12 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:46:22 PM PST 24 |
| Peak memory | 553064 kb |
| Host | smart-cb101f0a-1174-45cb-a94f-8e4ebf96c45b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338943010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.3338943010 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.953652911 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 261787038 ps |
| CPU time | 11.33 seconds |
| Started | Jan 10 01:45:50 PM PST 24 |
| Finished | Jan 10 01:46:06 PM PST 24 |
| Peak memory | 554784 kb |
| Host | smart-95f589d5-c7a5-414f-80ec-188518753dec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953652911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr .953652911 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.1294986097 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 437499525 ps |
| CPU time | 16.86 seconds |
| Started | Jan 10 01:45:48 PM PST 24 |
| Finished | Jan 10 01:46:10 PM PST 24 |
| Peak memory | 554704 kb |
| Host | smart-3440f239-4ee2-4319-a2bd-6c49137e0545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294986097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.1294986097 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.146517808 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 1294648424 ps |
| CPU time | 40.85 seconds |
| Started | Jan 10 01:45:13 PM PST 24 |
| Finished | Jan 10 01:46:16 PM PST 24 |
| Peak memory | 554828 kb |
| Host | smart-ec26667d-ddf5-4046-9209-7c2cc99af613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146517808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.146517808 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.1642168297 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 94007748615 ps |
| CPU time | 1150.93 seconds |
| Started | Jan 10 01:45:12 PM PST 24 |
| Finished | Jan 10 02:04:46 PM PST 24 |
| Peak memory | 554828 kb |
| Host | smart-ff10baa2-4bb4-4a66-80b4-6579550f2855 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642168297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.1642168297 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.1783203398 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 22626413927 ps |
| CPU time | 413.36 seconds |
| Started | Jan 10 01:45:05 PM PST 24 |
| Finished | Jan 10 01:52:19 PM PST 24 |
| Peak memory | 555176 kb |
| Host | smart-73d0272f-192c-4dea-8647-a4276a597ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783203398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.1783203398 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.1437418543 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 131839837 ps |
| CPU time | 12.06 seconds |
| Started | Jan 10 01:45:11 PM PST 24 |
| Finished | Jan 10 01:45:47 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-1672f0ff-4364-40af-8519-a7535c3d09c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437418543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.1437418543 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3712385790 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 666888305 ps |
| CPU time | 21.22 seconds |
| Started | Jan 10 01:45:48 PM PST 24 |
| Finished | Jan 10 01:46:14 PM PST 24 |
| Peak memory | 554700 kb |
| Host | smart-d573c048-b243-433f-9317-dc7867fa170c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712385790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3712385790 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.872988916 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 50596233 ps |
| CPU time | 6.12 seconds |
| Started | Jan 10 01:45:18 PM PST 24 |
| Finished | Jan 10 01:45:43 PM PST 24 |
| Peak memory | 552692 kb |
| Host | smart-25ef5f2c-36af-44a3-8b1c-7246392db9b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872988916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.872988916 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.912091754 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 7983934511 ps |
| CPU time | 80.99 seconds |
| Started | Jan 10 01:45:09 PM PST 24 |
| Finished | Jan 10 01:46:53 PM PST 24 |
| Peak memory | 553048 kb |
| Host | smart-1a81ea65-f06d-4eee-8490-a889f56f866b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912091754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.912091754 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2806339098 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 7253477622 ps |
| CPU time | 116.25 seconds |
| Started | Jan 10 01:45:12 PM PST 24 |
| Finished | Jan 10 01:47:31 PM PST 24 |
| Peak memory | 552800 kb |
| Host | smart-4d2dd613-600c-4796-8899-d33557b91dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806339098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.2806339098 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2130512465 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 47011549 ps |
| CPU time | 5.78 seconds |
| Started | Jan 10 01:45:12 PM PST 24 |
| Finished | Jan 10 01:45:41 PM PST 24 |
| Peak memory | 552528 kb |
| Host | smart-81b063b1-5b6e-42a7-b272-672c497a7714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130512465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.2130512465 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.2919457184 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 2722485292 ps |
| CPU time | 93.8 seconds |
| Started | Jan 10 01:45:50 PM PST 24 |
| Finished | Jan 10 01:47:28 PM PST 24 |
| Peak memory | 554932 kb |
| Host | smart-f3dfba47-8528-4b75-8658-54f0375cf5bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919457184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.2919457184 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.316748232 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 128235708 ps |
| CPU time | 8.32 seconds |
| Started | Jan 10 01:45:48 PM PST 24 |
| Finished | Jan 10 01:46:01 PM PST 24 |
| Peak memory | 552700 kb |
| Host | smart-07d51642-af6b-4f76-8b75-b4d6a913966e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316748232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.316748232 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3388727803 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 302598705 ps |
| CPU time | 98.14 seconds |
| Started | Jan 10 01:45:49 PM PST 24 |
| Finished | Jan 10 01:47:32 PM PST 24 |
| Peak memory | 556192 kb |
| Host | smart-ca83f3ee-e112-4075-a2d7-bd5a914dc9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388727803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.3388727803 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2332454577 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 754781570 ps |
| CPU time | 225.01 seconds |
| Started | Jan 10 01:45:48 PM PST 24 |
| Finished | Jan 10 01:49:38 PM PST 24 |
| Peak memory | 559816 kb |
| Host | smart-ccc274ce-ce0a-413b-ad30-ace1ad33033e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332454577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.2332454577 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3661722085 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 276537937 ps |
| CPU time | 29.93 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:46:33 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-9e15d794-ab92-4f8c-9fff-02b7d9d15a09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661722085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.3661722085 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1724762972 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 1774991723 ps |
| CPU time | 76.68 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:47:20 PM PST 24 |
| Peak memory | 554848 kb |
| Host | smart-3dcb0d83-a76c-4d68-953a-5d08b6843aa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724762972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .1724762972 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2099668577 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 44296073972 ps |
| CPU time | 854.87 seconds |
| Started | Jan 10 01:45:55 PM PST 24 |
| Finished | Jan 10 02:00:13 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-159fb88d-cf2a-4e67-ba23-0ba8810183b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099668577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.2099668577 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.2831196007 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 244043382 ps |
| CPU time | 11.96 seconds |
| Started | Jan 10 01:45:54 PM PST 24 |
| Finished | Jan 10 01:46:10 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-f80bd8b3-b225-4f0e-be6f-005f63223431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831196007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.2831196007 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2781751853 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 2118276760 ps |
| CPU time | 69.52 seconds |
| Started | Jan 10 01:45:52 PM PST 24 |
| Finished | Jan 10 01:47:06 PM PST 24 |
| Peak memory | 555024 kb |
| Host | smart-1983ea66-ef2a-4b7a-a38a-feefa363bafd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781751853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2781751853 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.2747535472 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 584052508 ps |
| CPU time | 49.2 seconds |
| Started | Jan 10 01:45:48 PM PST 24 |
| Finished | Jan 10 01:46:42 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-98eb4dc1-2a90-4850-bb98-1c41acca4002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747535472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2747535472 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.270971308 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 20136373250 ps |
| CPU time | 188.86 seconds |
| Started | Jan 10 01:45:49 PM PST 24 |
| Finished | Jan 10 01:49:03 PM PST 24 |
| Peak memory | 555052 kb |
| Host | smart-e4dd132f-adb1-4a80-9572-d21a6cf2ddf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270971308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.270971308 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.3825757681 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 25006301843 ps |
| CPU time | 547.11 seconds |
| Started | Jan 10 01:45:50 PM PST 24 |
| Finished | Jan 10 01:55:02 PM PST 24 |
| Peak memory | 554836 kb |
| Host | smart-c48c86e7-f784-457c-9a26-8b9419f9efb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825757681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.3825757681 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.993606222 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 149457678 ps |
| CPU time | 15.03 seconds |
| Started | Jan 10 01:45:53 PM PST 24 |
| Finished | Jan 10 01:46:12 PM PST 24 |
| Peak memory | 553856 kb |
| Host | smart-a408bef8-de2f-4164-9469-4c9a9bdb94af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993606222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_dela ys.993606222 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.2959352177 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 483317535 ps |
| CPU time | 15.07 seconds |
| Started | Jan 10 01:45:53 PM PST 24 |
| Finished | Jan 10 01:46:12 PM PST 24 |
| Peak memory | 554744 kb |
| Host | smart-75915708-0780-4b33-a5c8-73767268b9f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959352177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.2959352177 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.1445153327 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 44636104 ps |
| CPU time | 5.97 seconds |
| Started | Jan 10 01:45:40 PM PST 24 |
| Finished | Jan 10 01:45:53 PM PST 24 |
| Peak memory | 552976 kb |
| Host | smart-41ae4ef8-38b8-4194-b74f-d808d50572b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445153327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.1445153327 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.395140367 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 6332546555 ps |
| CPU time | 63.74 seconds |
| Started | Jan 10 01:45:40 PM PST 24 |
| Finished | Jan 10 01:46:51 PM PST 24 |
| Peak memory | 552704 kb |
| Host | smart-1b806cfe-9768-476a-b661-f869a722efb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395140367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.395140367 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3068730072 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 6732490304 ps |
| CPU time | 116.71 seconds |
| Started | Jan 10 01:45:53 PM PST 24 |
| Finished | Jan 10 01:47:54 PM PST 24 |
| Peak memory | 552656 kb |
| Host | smart-ff3eec7c-3660-4026-875d-fc71a82e24b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068730072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.3068730072 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3712236344 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 39009447 ps |
| CPU time | 5.84 seconds |
| Started | Jan 10 01:45:54 PM PST 24 |
| Finished | Jan 10 01:46:03 PM PST 24 |
| Peak memory | 552624 kb |
| Host | smart-4fa8abdc-dac8-4512-a54f-e94e6192cb0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712236344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.3712236344 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.1319594290 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1331032983 ps |
| CPU time | 120.95 seconds |
| Started | Jan 10 01:45:53 PM PST 24 |
| Finished | Jan 10 01:47:58 PM PST 24 |
| Peak memory | 555064 kb |
| Host | smart-4bcc3618-61e0-4e7e-b9ee-59ce82ebd23b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319594290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1319594290 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.1609126866 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 3523313796 ps |
| CPU time | 132.88 seconds |
| Started | Jan 10 01:45:54 PM PST 24 |
| Finished | Jan 10 01:48:10 PM PST 24 |
| Peak memory | 556056 kb |
| Host | smart-9a8bd3d1-345b-48db-bf67-3e9c1eebcd5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609126866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.1609126866 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.4116999460 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 818722240 ps |
| CPU time | 260.88 seconds |
| Started | Jan 10 01:45:56 PM PST 24 |
| Finished | Jan 10 01:50:20 PM PST 24 |
| Peak memory | 556976 kb |
| Host | smart-1af72a98-3230-4094-8f3e-302a1d195855 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116999460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.4116999460 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.306163514 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 57409844 ps |
| CPU time | 9.08 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:46:14 PM PST 24 |
| Peak memory | 554080 kb |
| Host | smart-145f3092-e49d-48e6-9b01-8bc0740d8a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306163514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.306163514 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2472552158 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 914129080 ps |
| CPU time | 65.24 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:47:08 PM PST 24 |
| Peak memory | 555008 kb |
| Host | smart-c532aebe-812f-4c10-bfa8-81b53fd8d49b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472552158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .2472552158 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2802894672 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 53447512943 ps |
| CPU time | 958.38 seconds |
| Started | Jan 10 01:45:58 PM PST 24 |
| Finished | Jan 10 02:02:00 PM PST 24 |
| Peak memory | 555136 kb |
| Host | smart-1032b42f-4f75-4523-ba16-9f333c8eba07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802894672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.2802894672 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2679001228 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 137204256 ps |
| CPU time | 15.19 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:46:19 PM PST 24 |
| Peak memory | 554752 kb |
| Host | smart-a34a6603-9107-4c24-b30c-9b683d7c5028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679001228 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.2679001228 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.3687429852 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 344242563 ps |
| CPU time | 13.41 seconds |
| Started | Jan 10 01:45:58 PM PST 24 |
| Finished | Jan 10 01:46:14 PM PST 24 |
| Peak memory | 554956 kb |
| Host | smart-8eabbb00-86ee-4210-b228-4216051b3f62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687429852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.3687429852 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.227824652 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 388852648 ps |
| CPU time | 16.54 seconds |
| Started | Jan 10 01:45:57 PM PST 24 |
| Finished | Jan 10 01:46:16 PM PST 24 |
| Peak memory | 553940 kb |
| Host | smart-4c949e23-396a-4bf9-af6b-a35686ecf7a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227824652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.227824652 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.2409262181 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 28755170949 ps |
| CPU time | 333.09 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:51:37 PM PST 24 |
| Peak memory | 555076 kb |
| Host | smart-57e400cc-bf07-4fa7-9371-02aecc6b2935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409262181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.2409262181 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3144113510 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 54491114425 ps |
| CPU time | 906.04 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 02:01:08 PM PST 24 |
| Peak memory | 554848 kb |
| Host | smart-ff46ba55-181e-4355-9e19-47d8dafd30ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144113510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3144113510 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.1856951603 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 263720449 ps |
| CPU time | 22.55 seconds |
| Started | Jan 10 01:45:57 PM PST 24 |
| Finished | Jan 10 01:46:22 PM PST 24 |
| Peak memory | 554764 kb |
| Host | smart-970c8892-fef0-4084-b50b-9ad5c4a33e2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856951603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.1856951603 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.158182324 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 467700755 ps |
| CPU time | 31.37 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:46:37 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-9f72b0e7-a8dc-47eb-98a1-f169f0fa2434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158182324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.158182324 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.2514459718 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 188895093 ps |
| CPU time | 7.88 seconds |
| Started | Jan 10 01:45:54 PM PST 24 |
| Finished | Jan 10 01:46:05 PM PST 24 |
| Peak memory | 552592 kb |
| Host | smart-175b657f-8bfc-4b5b-8a34-a4e939305eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514459718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.2514459718 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2859500363 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 9895778766 ps |
| CPU time | 107.43 seconds |
| Started | Jan 10 01:45:55 PM PST 24 |
| Finished | Jan 10 01:47:45 PM PST 24 |
| Peak memory | 552584 kb |
| Host | smart-d159d732-abde-4f54-8fa2-719e80794ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859500363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2859500363 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.349921427 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 4070530150 ps |
| CPU time | 64.28 seconds |
| Started | Jan 10 01:45:55 PM PST 24 |
| Finished | Jan 10 01:47:02 PM PST 24 |
| Peak memory | 552652 kb |
| Host | smart-25cd6def-738c-4741-8683-7c702e49e034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349921427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.349921427 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.976836924 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 52840702 ps |
| CPU time | 6.5 seconds |
| Started | Jan 10 01:45:36 PM PST 24 |
| Finished | Jan 10 01:45:49 PM PST 24 |
| Peak memory | 552948 kb |
| Host | smart-56af3f95-59d9-46e6-8a4d-51bb4f78de52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976836924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .976836924 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.2057346154 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1811791425 ps |
| CPU time | 72.04 seconds |
| Started | Jan 10 01:45:57 PM PST 24 |
| Finished | Jan 10 01:47:11 PM PST 24 |
| Peak memory | 556176 kb |
| Host | smart-14984168-e958-4747-a0af-1a48bb31eb14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057346154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2057346154 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.1042251850 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 7929328982 ps |
| CPU time | 242.11 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:50:10 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-59dc8c13-0c74-45d7-a3de-0c2e47d8c011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042251850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.1042251850 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3984456315 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 568340436 ps |
| CPU time | 251.26 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:50:16 PM PST 24 |
| Peak memory | 557176 kb |
| Host | smart-af2d3eb8-a1c7-4107-a78b-d9ca5fbda47f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984456315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3984456315 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2675026431 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 2080838929 ps |
| CPU time | 318.67 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:51:27 PM PST 24 |
| Peak memory | 559720 kb |
| Host | smart-f7f9cced-daf6-4134-83aa-8d301d2510f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675026431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.2675026431 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.3629042610 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1356549151 ps |
| CPU time | 49.75 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:46:52 PM PST 24 |
| Peak memory | 555172 kb |
| Host | smart-3fbdde8f-ff93-44d0-8815-06214cc18714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629042610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.3629042610 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.3158135894 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1452791433 ps |
| CPU time | 66.71 seconds |
| Started | Jan 10 01:46:04 PM PST 24 |
| Finished | Jan 10 01:47:30 PM PST 24 |
| Peak memory | 554776 kb |
| Host | smart-df70feb7-255f-49cf-a315-5fce94b9c55a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158135894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .3158135894 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2353944253 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 73615587013 ps |
| CPU time | 1297 seconds |
| Started | Jan 10 01:46:06 PM PST 24 |
| Finished | Jan 10 02:08:05 PM PST 24 |
| Peak memory | 556216 kb |
| Host | smart-cc13da8a-f3fb-4947-aa28-7fcefd55a338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353944253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.2353944253 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.2314057107 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 757461807 ps |
| CPU time | 29.4 seconds |
| Started | Jan 10 01:45:41 PM PST 24 |
| Finished | Jan 10 01:46:17 PM PST 24 |
| Peak memory | 555028 kb |
| Host | smart-d52db82e-1182-4d84-956e-8cdcf88f638b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314057107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.2314057107 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.2289720341 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 467179135 ps |
| CPU time | 34.43 seconds |
| Started | Jan 10 01:46:01 PM PST 24 |
| Finished | Jan 10 01:46:42 PM PST 24 |
| Peak memory | 554704 kb |
| Host | smart-cb153689-1b81-46d4-a240-3ffbcebe7bcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289720341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.2289720341 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.2854886206 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 228895607 ps |
| CPU time | 18.89 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:46:24 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-2cc99f18-d84f-4e7b-a03d-1482def63630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854886206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.2854886206 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1689358857 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 28357536534 ps |
| CPU time | 314.24 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:51:19 PM PST 24 |
| Peak memory | 554828 kb |
| Host | smart-a0205fe1-bbcd-43d5-879e-23b643d3c15d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689358857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1689358857 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3812593714 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 49383037303 ps |
| CPU time | 952.19 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 02:02:00 PM PST 24 |
| Peak memory | 553968 kb |
| Host | smart-6a763fbc-67be-4530-9c8c-d41586601960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812593714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3812593714 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.2180014801 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 185377899 ps |
| CPU time | 18.45 seconds |
| Started | Jan 10 01:46:01 PM PST 24 |
| Finished | Jan 10 01:46:25 PM PST 24 |
| Peak memory | 554780 kb |
| Host | smart-791a55f8-8c40-47f1-b612-e1abe77446d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180014801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.2180014801 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.1835621692 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 2275675942 ps |
| CPU time | 62.14 seconds |
| Started | Jan 10 01:46:06 PM PST 24 |
| Finished | Jan 10 01:47:30 PM PST 24 |
| Peak memory | 555124 kb |
| Host | smart-1b9c1e6e-34ad-4ead-b3f9-0dc87ccf078e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835621692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.1835621692 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.3097127800 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 216710009 ps |
| CPU time | 9.14 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:46:17 PM PST 24 |
| Peak memory | 552548 kb |
| Host | smart-3ed7232f-6215-4629-b690-7cf5ab488bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097127800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3097127800 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.3622915294 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 6383398341 ps |
| CPU time | 69.88 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:47:18 PM PST 24 |
| Peak memory | 553016 kb |
| Host | smart-c6b72152-ca2f-41df-a7ce-0d5669d59c5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622915294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.3622915294 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.976142709 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 5318928701 ps |
| CPU time | 90.18 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:47:35 PM PST 24 |
| Peak memory | 553068 kb |
| Host | smart-633e9c3d-1d74-4b1e-858d-0d929e7dba97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976142709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.976142709 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.265870418 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 43385746 ps |
| CPU time | 5.67 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:46:11 PM PST 24 |
| Peak memory | 552684 kb |
| Host | smart-19e687b6-d65d-4fae-a2d9-4b8d02c7d08d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265870418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays .265870418 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.3240072434 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1029124751 ps |
| CPU time | 91.56 seconds |
| Started | Jan 10 01:45:45 PM PST 24 |
| Finished | Jan 10 01:47:22 PM PST 24 |
| Peak memory | 555900 kb |
| Host | smart-0a325b02-cfa5-4bf5-922a-ed408d32842c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240072434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.3240072434 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.3752563236 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 3577771779 ps |
| CPU time | 125.59 seconds |
| Started | Jan 10 01:45:54 PM PST 24 |
| Finished | Jan 10 01:48:03 PM PST 24 |
| Peak memory | 556080 kb |
| Host | smart-ae7a7c03-2e58-4809-8c0a-1f03a1104d9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752563236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3752563236 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2508815937 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 9241125473 ps |
| CPU time | 570.31 seconds |
| Started | Jan 10 01:45:53 PM PST 24 |
| Finished | Jan 10 01:55:28 PM PST 24 |
| Peak memory | 557604 kb |
| Host | smart-fd88b07d-d195-4c02-b780-e90cc74cbe3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508815937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.2508815937 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.2701369616 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 1891027044 ps |
| CPU time | 253.75 seconds |
| Started | Jan 10 01:45:51 PM PST 24 |
| Finished | Jan 10 01:50:09 PM PST 24 |
| Peak memory | 557936 kb |
| Host | smart-81fdecf4-7cd5-4b7b-93f9-32c5d72103b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701369616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.2701369616 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1294480592 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 91832336 ps |
| CPU time | 12.66 seconds |
| Started | Jan 10 01:45:57 PM PST 24 |
| Finished | Jan 10 01:46:12 PM PST 24 |
| Peak memory | 553976 kb |
| Host | smart-e90b5e9f-fd86-43b6-bc30-e51dfcd14854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294480592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1294480592 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.1956742919 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 495681779 ps |
| CPU time | 20.46 seconds |
| Started | Jan 10 01:45:54 PM PST 24 |
| Finished | Jan 10 01:46:18 PM PST 24 |
| Peak memory | 554052 kb |
| Host | smart-38c7940b-ebed-424a-9e89-9a7ad7370d6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956742919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .1956742919 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3824175538 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 99570934925 ps |
| CPU time | 1803.19 seconds |
| Started | Jan 10 01:45:57 PM PST 24 |
| Finished | Jan 10 02:16:03 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-2aac5f9a-267e-47f1-938c-f2d45b305a99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824175538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.3824175538 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.92312795 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 137764142 ps |
| CPU time | 17.46 seconds |
| Started | Jan 10 01:45:58 PM PST 24 |
| Finished | Jan 10 01:46:18 PM PST 24 |
| Peak memory | 555008 kb |
| Host | smart-b410528a-d335-46c8-8c25-1408d5623ce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92312795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_addr.92312795 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.896289222 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 2315055538 ps |
| CPU time | 80.44 seconds |
| Started | Jan 10 01:45:54 PM PST 24 |
| Finished | Jan 10 01:47:18 PM PST 24 |
| Peak memory | 554752 kb |
| Host | smart-16420a45-879d-4464-89d2-0fc40c1ef97e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896289222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.896289222 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.1605222483 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 499144282 ps |
| CPU time | 40.86 seconds |
| Started | Jan 10 01:45:47 PM PST 24 |
| Finished | Jan 10 01:46:34 PM PST 24 |
| Peak memory | 554776 kb |
| Host | smart-015de60d-ef94-4510-a6ec-c20e788016eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605222483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.1605222483 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.1967867047 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 45394316420 ps |
| CPU time | 488.68 seconds |
| Started | Jan 10 01:45:55 PM PST 24 |
| Finished | Jan 10 01:54:07 PM PST 24 |
| Peak memory | 555136 kb |
| Host | smart-2f559bed-dec8-4788-97c2-a58321a3c3c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967867047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.1967867047 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.907158501 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 27339827912 ps |
| CPU time | 512.17 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:54:34 PM PST 24 |
| Peak memory | 553988 kb |
| Host | smart-8fdd3db3-1741-4cb5-8bd2-0f49c73c1a7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907158501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.907158501 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.34266871 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 490184962 ps |
| CPU time | 39.51 seconds |
| Started | Jan 10 01:45:57 PM PST 24 |
| Finished | Jan 10 01:46:39 PM PST 24 |
| Peak memory | 554716 kb |
| Host | smart-7318aa50-0e06-46fd-a66a-cc1935c2ed24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34266871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_delay s.34266871 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.1695172193 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 547673156 ps |
| CPU time | 35.83 seconds |
| Started | Jan 10 01:45:56 PM PST 24 |
| Finished | Jan 10 01:46:34 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-d41506be-949f-4a14-8e08-9c5622ba9240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695172193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.1695172193 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.897793192 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 261405342 ps |
| CPU time | 9.64 seconds |
| Started | Jan 10 01:45:52 PM PST 24 |
| Finished | Jan 10 01:46:06 PM PST 24 |
| Peak memory | 552688 kb |
| Host | smart-55631a5b-d0b4-4fe0-b2d1-2b166ed7a948 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897793192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.897793192 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2949770565 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 10320886141 ps |
| CPU time | 111.54 seconds |
| Started | Jan 10 01:45:54 PM PST 24 |
| Finished | Jan 10 01:47:49 PM PST 24 |
| Peak memory | 552612 kb |
| Host | smart-c3198bc5-0e1a-450a-b5e6-a2818af5617d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949770565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2949770565 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.4109971126 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 3652506010 ps |
| CPU time | 62.05 seconds |
| Started | Jan 10 01:45:45 PM PST 24 |
| Finished | Jan 10 01:46:53 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-b401c260-8368-4e27-86e6-4b68dded7614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109971126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.4109971126 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1764587648 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 50306831 ps |
| CPU time | 6.31 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:46:10 PM PST 24 |
| Peak memory | 552928 kb |
| Host | smart-a5a119d7-9ec0-41c7-9d3c-0419d35652ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764587648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.1764587648 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.4236732821 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 3358041960 ps |
| CPU time | 308.19 seconds |
| Started | Jan 10 01:45:55 PM PST 24 |
| Finished | Jan 10 01:51:06 PM PST 24 |
| Peak memory | 557164 kb |
| Host | smart-269bb01f-6f5d-4189-9651-e1da7060d6eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236732821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.4236732821 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.739527303 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 513240188 ps |
| CPU time | 229.11 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:49:53 PM PST 24 |
| Peak memory | 556952 kb |
| Host | smart-6d0b838f-85ff-41f6-9c1c-df2fe89ad929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739527303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_ with_rand_reset.739527303 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1363304854 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 121226209 ps |
| CPU time | 16.24 seconds |
| Started | Jan 10 01:45:55 PM PST 24 |
| Finished | Jan 10 01:46:14 PM PST 24 |
| Peak memory | 553864 kb |
| Host | smart-7b0e9913-b655-4751-bd80-1fe8504c56f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363304854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1363304854 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.1338026326 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 36662141 ps |
| CPU time | 7.12 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:46:15 PM PST 24 |
| Peak memory | 552992 kb |
| Host | smart-5189b300-7cc5-42fb-a89a-443145800dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338026326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.1338026326 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.806271536 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 2971595117 ps |
| CPU time | 105.86 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:47:51 PM PST 24 |
| Peak memory | 555132 kb |
| Host | smart-d5241744-25db-4bd9-a646-8f4e69cd2e85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806271536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device. 806271536 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1954171692 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 98793268885 ps |
| CPU time | 1694.64 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 02:14:21 PM PST 24 |
| Peak memory | 555096 kb |
| Host | smart-92342bb9-6ef3-42f3-a3ea-ca85c9ce3bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954171692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.1954171692 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1371608113 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 1258251673 ps |
| CPU time | 45.25 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:46:53 PM PST 24 |
| Peak memory | 554656 kb |
| Host | smart-36a8a70c-bfc9-412c-b285-f36024ca1fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371608113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1371608113 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.3301618769 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 1588191227 ps |
| CPU time | 49.53 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:46:55 PM PST 24 |
| Peak memory | 554720 kb |
| Host | smart-5bfc0bf8-6e76-46ab-8cdf-ce63f266a4ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301618769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3301618769 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.2362212080 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 363348333 ps |
| CPU time | 32.97 seconds |
| Started | Jan 10 01:45:57 PM PST 24 |
| Finished | Jan 10 01:46:32 PM PST 24 |
| Peak memory | 555024 kb |
| Host | smart-b62529dd-54da-4dfc-b15d-583851e6025e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362212080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.2362212080 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.1400863668 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 102293078587 ps |
| CPU time | 1151.81 seconds |
| Started | Jan 10 01:46:01 PM PST 24 |
| Finished | Jan 10 02:05:19 PM PST 24 |
| Peak memory | 554848 kb |
| Host | smart-49f6e389-2a65-48a9-88b4-b57d059251bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400863668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.1400863668 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.873835271 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 13603979287 ps |
| CPU time | 220.14 seconds |
| Started | Jan 10 01:46:01 PM PST 24 |
| Finished | Jan 10 01:49:47 PM PST 24 |
| Peak memory | 555204 kb |
| Host | smart-9940374a-c7ab-44db-9800-840fd6e700a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873835271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.873835271 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.4278939104 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 141047040 ps |
| CPU time | 14.56 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:46:17 PM PST 24 |
| Peak memory | 554964 kb |
| Host | smart-871c4d47-4a77-4371-b8a2-74420546598c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278939104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.4278939104 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.3216491818 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 2060376960 ps |
| CPU time | 60.5 seconds |
| Started | Jan 10 01:46:05 PM PST 24 |
| Finished | Jan 10 01:47:28 PM PST 24 |
| Peak memory | 554804 kb |
| Host | smart-62695415-302e-4a3e-8b0e-98e2e01aa715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216491818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3216491818 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.936095822 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 130714713 ps |
| CPU time | 7 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:46:09 PM PST 24 |
| Peak memory | 552556 kb |
| Host | smart-fd73f7d0-e3a3-4da0-a623-2fe234cc3eb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936095822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.936095822 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2793068483 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 6940777970 ps |
| CPU time | 72.82 seconds |
| Started | Jan 10 01:45:57 PM PST 24 |
| Finished | Jan 10 01:47:12 PM PST 24 |
| Peak memory | 552560 kb |
| Host | smart-25f6dddc-7d4c-40b8-ae35-0c3c095bafc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793068483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2793068483 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.4044961178 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 4503095857 ps |
| CPU time | 75.84 seconds |
| Started | Jan 10 01:46:01 PM PST 24 |
| Finished | Jan 10 01:47:22 PM PST 24 |
| Peak memory | 552784 kb |
| Host | smart-a0548b4e-9ab6-41b0-aa03-d2422e9cade6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044961178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.4044961178 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.1976807014 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 55044046 ps |
| CPU time | 6.45 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:46:12 PM PST 24 |
| Peak memory | 552924 kb |
| Host | smart-5292ccb7-0934-4211-8ecc-d863aef02a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976807014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.1976807014 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.3191412792 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 537087757 ps |
| CPU time | 52.49 seconds |
| Started | Jan 10 01:46:01 PM PST 24 |
| Finished | Jan 10 01:47:00 PM PST 24 |
| Peak memory | 554868 kb |
| Host | smart-eea14a58-26ad-4953-adb7-1b7366ca9b66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191412792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.3191412792 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.712303015 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 1840328958 ps |
| CPU time | 151.66 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:48:39 PM PST 24 |
| Peak memory | 555808 kb |
| Host | smart-d0c4b13a-084b-4738-b9a7-5a68ed4ae792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712303015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.712303015 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3314907294 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 3232972162 ps |
| CPU time | 320.18 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:51:28 PM PST 24 |
| Peak memory | 556672 kb |
| Host | smart-583bc5f6-d321-43b5-9e15-7a6b5871a67b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314907294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.3314907294 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.1107695977 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 16668472 ps |
| CPU time | 12.26 seconds |
| Started | Jan 10 01:46:01 PM PST 24 |
| Finished | Jan 10 01:46:19 PM PST 24 |
| Peak memory | 553020 kb |
| Host | smart-1217d507-a35b-4e5d-b777-cf46f8af168a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107695977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.1107695977 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.1445954428 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 215261281 ps |
| CPU time | 11.96 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:46:21 PM PST 24 |
| Peak memory | 553688 kb |
| Host | smart-05000af5-dccf-460f-8095-b074f2cf5eb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445954428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.1445954428 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.3099437425 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 2485951066 ps |
| CPU time | 106.58 seconds |
| Started | Jan 10 01:46:06 PM PST 24 |
| Finished | Jan 10 01:48:15 PM PST 24 |
| Peak memory | 556276 kb |
| Host | smart-3ba8067a-0358-4bc2-b667-a21e53591af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099437425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .3099437425 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.3300252561 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 130738297020 ps |
| CPU time | 2257.9 seconds |
| Started | Jan 10 01:45:41 PM PST 24 |
| Finished | Jan 10 02:23:26 PM PST 24 |
| Peak memory | 556196 kb |
| Host | smart-2d85e818-0e80-4aed-848b-007d18d0a779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300252561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.3300252561 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3233058318 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 394446571 ps |
| CPU time | 17.57 seconds |
| Started | Jan 10 01:45:48 PM PST 24 |
| Finished | Jan 10 01:46:11 PM PST 24 |
| Peak memory | 554732 kb |
| Host | smart-8fe5b2d8-5b5c-45d2-8968-cb80fcc145a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233058318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.3233058318 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.1186156415 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 472492639 ps |
| CPU time | 38.7 seconds |
| Started | Jan 10 01:45:49 PM PST 24 |
| Finished | Jan 10 01:46:33 PM PST 24 |
| Peak memory | 554716 kb |
| Host | smart-42cb9d42-74e3-4b57-9836-7e34560640f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186156415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1186156415 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.462031751 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 925170249 ps |
| CPU time | 34.06 seconds |
| Started | Jan 10 01:46:00 PM PST 24 |
| Finished | Jan 10 01:46:39 PM PST 24 |
| Peak memory | 554772 kb |
| Host | smart-eb019cdc-d221-42b4-95d9-467b8b652fa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462031751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.462031751 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.886574915 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 63895101078 ps |
| CPU time | 735.92 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:58:19 PM PST 24 |
| Peak memory | 555076 kb |
| Host | smart-59e18915-c2ca-4472-8640-0168f685f350 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886574915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.886574915 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.2882164439 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 21350498835 ps |
| CPU time | 418.01 seconds |
| Started | Jan 10 01:45:52 PM PST 24 |
| Finished | Jan 10 01:52:54 PM PST 24 |
| Peak memory | 554828 kb |
| Host | smart-a4c86446-60bd-44d1-b848-b0a056dd3dfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882164439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.2882164439 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.223352901 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 338895219 ps |
| CPU time | 30.23 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:46:38 PM PST 24 |
| Peak memory | 555036 kb |
| Host | smart-57855ed2-8792-41d0-ad24-4285fc0a931e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223352901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_dela ys.223352901 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.2484616083 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 306293807 ps |
| CPU time | 21.39 seconds |
| Started | Jan 10 01:45:58 PM PST 24 |
| Finished | Jan 10 01:46:22 PM PST 24 |
| Peak memory | 555068 kb |
| Host | smart-b5b8e718-c9a9-4d82-a940-eaf3fce81fc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484616083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.2484616083 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.1765623486 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 168617615 ps |
| CPU time | 7.91 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:46:11 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-0fd5779b-e644-494e-8c37-f425c2385a7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765623486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1765623486 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.2796139535 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 7573621255 ps |
| CPU time | 87.95 seconds |
| Started | Jan 10 01:45:59 PM PST 24 |
| Finished | Jan 10 01:47:31 PM PST 24 |
| Peak memory | 552704 kb |
| Host | smart-3e20aaaa-b960-422c-b793-ec1a37e15317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796139535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.2796139535 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.785418133 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 4770851347 ps |
| CPU time | 84.71 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:47:35 PM PST 24 |
| Peak memory | 552644 kb |
| Host | smart-f2141296-7dbf-4646-80cd-d0c1c026b3da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785418133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.785418133 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.109639255 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 46933518 ps |
| CPU time | 6.29 seconds |
| Started | Jan 10 01:46:04 PM PST 24 |
| Finished | Jan 10 01:46:30 PM PST 24 |
| Peak memory | 552576 kb |
| Host | smart-92d5281f-438b-4223-944c-d765376645a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109639255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays .109639255 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.264840272 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 2768371891 ps |
| CPU time | 108.53 seconds |
| Started | Jan 10 01:45:49 PM PST 24 |
| Finished | Jan 10 01:47:43 PM PST 24 |
| Peak memory | 555132 kb |
| Host | smart-17eb3757-af91-48a3-81d7-2bbb14d31103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264840272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.264840272 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.46488337 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 10646981579 ps |
| CPU time | 366.1 seconds |
| Started | Jan 10 01:46:05 PM PST 24 |
| Finished | Jan 10 01:52:31 PM PST 24 |
| Peak memory | 557252 kb |
| Host | smart-c8dd2608-3b91-4ab0-bb6d-434b36a1b0ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46488337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.46488337 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.4199213922 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 789389380 ps |
| CPU time | 314.52 seconds |
| Started | Jan 10 01:46:06 PM PST 24 |
| Finished | Jan 10 01:51:42 PM PST 24 |
| Peak memory | 558412 kb |
| Host | smart-8074cf0c-7373-49d8-aff3-ab62e3ac3b45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199213922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.4199213922 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.212932694 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 210742584 ps |
| CPU time | 76.61 seconds |
| Started | Jan 10 01:46:04 PM PST 24 |
| Finished | Jan 10 01:47:40 PM PST 24 |
| Peak memory | 555912 kb |
| Host | smart-0bdff1af-b1f4-43b8-8ca7-7af585267e5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212932694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_reset_error.212932694 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1143076527 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 331016916 ps |
| CPU time | 16.21 seconds |
| Started | Jan 10 01:45:47 PM PST 24 |
| Finished | Jan 10 01:46:09 PM PST 24 |
| Peak memory | 554696 kb |
| Host | smart-6eb30e44-49f0-4bb9-94a2-a93c4f9229f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143076527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1143076527 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.2523577420 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 565527994 ps |
| CPU time | 36.37 seconds |
| Started | Jan 10 01:46:02 PM PST 24 |
| Finished | Jan 10 01:46:44 PM PST 24 |
| Peak memory | 555024 kb |
| Host | smart-73f7164f-abd6-4dbc-b675-34b75a0b4fad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523577420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .2523577420 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.355563026 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 112223466840 ps |
| CPU time | 2189.95 seconds |
| Started | Jan 10 01:46:11 PM PST 24 |
| Finished | Jan 10 02:23:08 PM PST 24 |
| Peak memory | 555228 kb |
| Host | smart-20e1cf5f-d176-42d8-be75-fccddd62d7d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355563026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_d evice_slow_rsp.355563026 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.687717120 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 1485747511 ps |
| CPU time | 59.29 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:47:09 PM PST 24 |
| Peak memory | 554988 kb |
| Host | smart-b13cb9a9-2664-41b7-a51e-9e5983ab3e1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687717120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .687717120 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.894827356 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 1579964143 ps |
| CPU time | 57.71 seconds |
| Started | Jan 10 01:46:04 PM PST 24 |
| Finished | Jan 10 01:47:21 PM PST 24 |
| Peak memory | 554716 kb |
| Host | smart-2537f028-cb20-462d-9804-5b191655034b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894827356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.894827356 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.3126819407 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 156095755 ps |
| CPU time | 14.94 seconds |
| Started | Jan 10 01:46:08 PM PST 24 |
| Finished | Jan 10 01:46:47 PM PST 24 |
| Peak memory | 554776 kb |
| Host | smart-05620c6e-8728-4ae1-9e08-e95bf7351690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126819407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.3126819407 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.1972732899 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 62006896074 ps |
| CPU time | 793.27 seconds |
| Started | Jan 10 01:46:06 PM PST 24 |
| Finished | Jan 10 01:59:41 PM PST 24 |
| Peak memory | 554112 kb |
| Host | smart-44195c67-7b3e-4157-b618-36f5d890bb43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972732899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1972732899 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.2318087930 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 29060555979 ps |
| CPU time | 547.53 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:55:26 PM PST 24 |
| Peak memory | 554808 kb |
| Host | smart-f2a62a38-7a7e-4943-815e-63a59e625ea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318087930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.2318087930 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.1556430946 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 389180383 ps |
| CPU time | 29.88 seconds |
| Started | Jan 10 01:46:05 PM PST 24 |
| Finished | Jan 10 01:46:56 PM PST 24 |
| Peak memory | 554732 kb |
| Host | smart-24c85b58-757e-4997-b402-8a317bdb8dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556430946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.1556430946 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.3199476303 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 155233511 ps |
| CPU time | 13.1 seconds |
| Started | Jan 10 01:46:06 PM PST 24 |
| Finished | Jan 10 01:46:43 PM PST 24 |
| Peak memory | 554660 kb |
| Host | smart-4cd42b40-4ff1-4a58-982e-973d7b304ec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199476303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.3199476303 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.3065490601 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 237200339 ps |
| CPU time | 10.05 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:46:19 PM PST 24 |
| Peak memory | 553060 kb |
| Host | smart-a23920ad-f35b-4a53-a36c-6e6aaad86c9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065490601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.3065490601 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3950236601 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 5918520350 ps |
| CPU time | 59.96 seconds |
| Started | Jan 10 01:46:05 PM PST 24 |
| Finished | Jan 10 01:47:27 PM PST 24 |
| Peak memory | 552896 kb |
| Host | smart-a6f54947-da67-4ad0-82cc-6e5826b7838d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950236601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3950236601 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1221441831 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 5357157203 ps |
| CPU time | 95.43 seconds |
| Started | Jan 10 01:46:05 PM PST 24 |
| Finished | Jan 10 01:48:00 PM PST 24 |
| Peak memory | 552704 kb |
| Host | smart-e7631b48-2305-4031-b844-ec434313bc3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221441831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1221441831 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2123177130 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 47099846 ps |
| CPU time | 6 seconds |
| Started | Jan 10 01:46:06 PM PST 24 |
| Finished | Jan 10 01:46:34 PM PST 24 |
| Peak memory | 552912 kb |
| Host | smart-cff4ed80-0cb6-4a15-9a3d-750d4977d1c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123177130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.2123177130 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.2589660174 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1441184080 ps |
| CPU time | 121.39 seconds |
| Started | Jan 10 01:46:05 PM PST 24 |
| Finished | Jan 10 01:48:29 PM PST 24 |
| Peak memory | 556108 kb |
| Host | smart-63e23f8d-a831-4731-a70f-8c910fe2fe1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589660174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2589660174 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.3436271962 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 3664599003 ps |
| CPU time | 143.79 seconds |
| Started | Jan 10 01:46:05 PM PST 24 |
| Finished | Jan 10 01:48:49 PM PST 24 |
| Peak memory | 555032 kb |
| Host | smart-a680a5d7-ab97-47e1-887a-82da2337ec68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436271962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.3436271962 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2509222712 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 2016503575 ps |
| CPU time | 312.51 seconds |
| Started | Jan 10 01:46:08 PM PST 24 |
| Finished | Jan 10 01:51:45 PM PST 24 |
| Peak memory | 557476 kb |
| Host | smart-66d39b6c-4671-417f-96b9-1c428a07ad60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509222712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.2509222712 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.377574710 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 360104387 ps |
| CPU time | 114.17 seconds |
| Started | Jan 10 01:46:01 PM PST 24 |
| Finished | Jan 10 01:48:00 PM PST 24 |
| Peak memory | 557580 kb |
| Host | smart-5f590754-4452-426e-b10e-8b96babd95cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377574710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.377574710 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.4165796616 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 162723534 ps |
| CPU time | 20.55 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:46:29 PM PST 24 |
| Peak memory | 554680 kb |
| Host | smart-082fcef1-3864-4ba8-911e-5183b1b8a10a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165796616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.4165796616 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.362641911 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 353472131 ps |
| CPU time | 17.1 seconds |
| Started | Jan 10 01:46:06 PM PST 24 |
| Finished | Jan 10 01:46:45 PM PST 24 |
| Peak memory | 554996 kb |
| Host | smart-f0fd878b-9d95-4481-9bba-c95147b89c87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362641911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device. 362641911 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3054078672 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 2651462440 ps |
| CPU time | 47.01 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:46:57 PM PST 24 |
| Peak memory | 552716 kb |
| Host | smart-90f62c03-9fa6-4c35-8eb0-727be45bb6f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054078672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.3054078672 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.849622601 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 581079202 ps |
| CPU time | 24.81 seconds |
| Started | Jan 10 01:47:03 PM PST 24 |
| Finished | Jan 10 01:47:31 PM PST 24 |
| Peak memory | 555016 kb |
| Host | smart-969ebddd-e575-4fa6-83c4-ad479453b2ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849622601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr .849622601 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.1281116002 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 331918418 ps |
| CPU time | 25.64 seconds |
| Started | Jan 10 01:46:51 PM PST 24 |
| Finished | Jan 10 01:47:19 PM PST 24 |
| Peak memory | 554720 kb |
| Host | smart-b44008f6-a0dc-44b5-948a-f4bb273a8826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281116002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.1281116002 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.4075171892 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 362747452 ps |
| CPU time | 15.64 seconds |
| Started | Jan 10 01:46:04 PM PST 24 |
| Finished | Jan 10 01:46:39 PM PST 24 |
| Peak memory | 555148 kb |
| Host | smart-816d178c-7f6e-44f9-8d03-1740bd0a8635 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075171892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.4075171892 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.993553548 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 72801894064 ps |
| CPU time | 906.45 seconds |
| Started | Jan 10 01:46:05 PM PST 24 |
| Finished | Jan 10 02:01:33 PM PST 24 |
| Peak memory | 554992 kb |
| Host | smart-546584cc-59d6-44f1-bb24-ab88a87c388c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993553548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.993553548 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2216092580 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 12011170425 ps |
| CPU time | 220.32 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:49:50 PM PST 24 |
| Peak memory | 555108 kb |
| Host | smart-f3671993-3341-499f-a36d-2b8ad549e2ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216092580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2216092580 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1904184120 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 598812920 ps |
| CPU time | 47.96 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:46:57 PM PST 24 |
| Peak memory | 555080 kb |
| Host | smart-11fe0a24-fb0c-4554-9682-56a6ab3974a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904184120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.1904184120 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.3123756040 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 391653870 ps |
| CPU time | 25.93 seconds |
| Started | Jan 10 01:46:06 PM PST 24 |
| Finished | Jan 10 01:46:54 PM PST 24 |
| Peak memory | 554788 kb |
| Host | smart-bb316c94-3ae6-4e1d-ba9e-a1e889d4ed15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123756040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.3123756040 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.2382038104 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 172109534 ps |
| CPU time | 7.95 seconds |
| Started | Jan 10 01:46:07 PM PST 24 |
| Finished | Jan 10 01:46:38 PM PST 24 |
| Peak memory | 552956 kb |
| Host | smart-e94e7055-494c-4686-a51d-7ab3e5fea91a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382038104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.2382038104 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2058302253 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 8350561642 ps |
| CPU time | 87.51 seconds |
| Started | Jan 10 01:46:01 PM PST 24 |
| Finished | Jan 10 01:47:35 PM PST 24 |
| Peak memory | 553084 kb |
| Host | smart-e34d189f-0d6a-4e11-871a-7f89bade0698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058302253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2058302253 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3985325471 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 3877231632 ps |
| CPU time | 69.54 seconds |
| Started | Jan 10 01:46:04 PM PST 24 |
| Finished | Jan 10 01:47:28 PM PST 24 |
| Peak memory | 552684 kb |
| Host | smart-8d6fa88c-78e4-4020-a810-2bdfaaff6d48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985325471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3985325471 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.4240844499 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 54224337 ps |
| CPU time | 6.66 seconds |
| Started | Jan 10 01:46:03 PM PST 24 |
| Finished | Jan 10 01:46:16 PM PST 24 |
| Peak memory | 552708 kb |
| Host | smart-ed42d7dd-61bc-4569-93de-b906bc73efae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240844499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.4240844499 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.2340873100 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 13639690238 ps |
| CPU time | 521.03 seconds |
| Started | Jan 10 01:46:53 PM PST 24 |
| Finished | Jan 10 01:55:39 PM PST 24 |
| Peak memory | 556272 kb |
| Host | smart-47aa4411-284d-46aa-9b1d-152034d27135 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340873100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2340873100 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.1722549949 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 2378437397 ps |
| CPU time | 81.87 seconds |
| Started | Jan 10 01:46:45 PM PST 24 |
| Finished | Jan 10 01:48:11 PM PST 24 |
| Peak memory | 556120 kb |
| Host | smart-18f2b122-e599-483f-803e-51dc7ef0f31e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722549949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1722549949 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.4065167124 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 238231529 ps |
| CPU time | 94.14 seconds |
| Started | Jan 10 01:46:50 PM PST 24 |
| Finished | Jan 10 01:48:27 PM PST 24 |
| Peak memory | 555964 kb |
| Host | smart-0c2938a4-4b22-402d-9a22-2310c4912d40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065167124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.4065167124 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2690891788 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 6919522008 ps |
| CPU time | 495.76 seconds |
| Started | Jan 10 01:46:43 PM PST 24 |
| Finished | Jan 10 01:55:04 PM PST 24 |
| Peak memory | 559956 kb |
| Host | smart-acc12aa1-c361-4fba-a6b8-cb421febe84f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690891788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.2690891788 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.3572920636 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 1023612709 ps |
| CPU time | 47.09 seconds |
| Started | Jan 10 01:47:06 PM PST 24 |
| Finished | Jan 10 01:47:56 PM PST 24 |
| Peak memory | 555144 kb |
| Host | smart-a569bb2b-4bcc-4dc4-a7f2-e3eaf6e6afe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572920636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.3572920636 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.865149981 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 13428694572 ps |
| CPU time | 1328.37 seconds |
| Started | Jan 10 01:47:24 PM PST 24 |
| Finished | Jan 10 02:09:35 PM PST 24 |
| Peak memory | 596240 kb |
| Host | smart-d3ba37d0-6e38-4796-9092-25ccbd78fd2e |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865149981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.865149981 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2485551572 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5123984112 ps |
| CPU time | 467.32 seconds |
| Started | Jan 10 01:55:32 PM PST 24 |
| Finished | Jan 10 02:03:22 PM PST 24 |
| Peak memory | 617376 kb |
| Host | smart-eb3598a2-8fc9-4c96-9709-62b7587ed900 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 485551572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.2485551572 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.4191371317 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 2584360488 ps |
| CPU time | 176.94 seconds |
| Started | Jan 10 01:57:53 PM PST 24 |
| Finished | Jan 10 02:00:53 PM PST 24 |
| Peak memory | 602360 kb |
| Host | smart-3f2cc2ac-91e1-4e3e-bdb6-aa999fb00344 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191371317 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.4191371317 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.844314420 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 2536828920 ps |
| CPU time | 245.83 seconds |
| Started | Jan 10 01:58:50 PM PST 24 |
| Finished | Jan 10 02:03:04 PM PST 24 |
| Peak memory | 601976 kb |
| Host | smart-5fec2622-1785-4e24-9d48-e27f65d92466 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844314420 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.844314420 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1869558142 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 2995023808 ps |
| CPU time | 269.6 seconds |
| Started | Jan 10 02:01:17 PM PST 24 |
| Finished | Jan 10 02:05:56 PM PST 24 |
| Peak memory | 602400 kb |
| Host | smart-7fedc4df-7231-4ef2-8dc5-0443d8788782 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1869558142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.1869558142 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.4204742054 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 3381942460 ps |
| CPU time | 212.41 seconds |
| Started | Jan 10 01:55:20 PM PST 24 |
| Finished | Jan 10 01:58:58 PM PST 24 |
| Peak memory | 602060 kb |
| Host | smart-eb86b58a-c9ed-491d-9b8a-4b74cc8bce53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204742054 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.4204742054 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.1479584438 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2998341970 ps |
| CPU time | 201.84 seconds |
| Started | Jan 10 01:54:57 PM PST 24 |
| Finished | Jan 10 01:58:25 PM PST 24 |
| Peak memory | 590352 kb |
| Host | smart-c02eeef2-148b-4651-9cb0-504f7728fc55 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479584438 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1479584438 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.269427380 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3258255949 ps |
| CPU time | 313.51 seconds |
| Started | Jan 10 01:54:43 PM PST 24 |
| Finished | Jan 10 01:59:57 PM PST 24 |
| Peak memory | 602708 kb |
| Host | smart-b9dd38a3-7c8c-45f8-805e-d178ea5e025b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269427380 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.269427380 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.2487582797 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 2518598720 ps |
| CPU time | 235.9 seconds |
| Started | Jan 10 02:02:05 PM PST 24 |
| Finished | Jan 10 02:06:08 PM PST 24 |
| Peak memory | 602360 kb |
| Host | smart-d99853ab-87b1-4d9f-9a9c-46bf6bf62d56 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487582797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2487582797 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1990923472 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 3135225240 ps |
| CPU time | 364.88 seconds |
| Started | Jan 10 01:54:40 PM PST 24 |
| Finished | Jan 10 02:00:46 PM PST 24 |
| Peak memory | 602280 kb |
| Host | smart-15eceea4-21e2-47f2-93c0-cd62ce34a782 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1990923472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1990923472 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3958578758 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 4914018760 ps |
| CPU time | 505.33 seconds |
| Started | Jan 10 01:55:32 PM PST 24 |
| Finished | Jan 10 02:04:00 PM PST 24 |
| Peak memory | 608608 kb |
| Host | smart-0edc492f-cba7-4a8e-ad2a-f5336a053104 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3958578758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3958578758 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.463876234 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 6762479832 ps |
| CPU time | 1069.8 seconds |
| Started | Jan 10 01:54:08 PM PST 24 |
| Finished | Jan 10 02:11:59 PM PST 24 |
| Peak memory | 602928 kb |
| Host | smart-25aa2a8b-1bc4-4628-a792-28924e87138f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=463876234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.463876234 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1029650009 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 7795986656 ps |
| CPU time | 1489.11 seconds |
| Started | Jan 10 01:54:01 PM PST 24 |
| Finished | Jan 10 02:18:53 PM PST 24 |
| Peak memory | 602836 kb |
| Host | smart-347eb83f-f28c-47ba-af22-41410cb57fb9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029650009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.1029650009 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.605717871 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2795399500 ps |
| CPU time | 298.92 seconds |
| Started | Jan 10 01:55:01 PM PST 24 |
| Finished | Jan 10 02:00:07 PM PST 24 |
| Peak memory | 590436 kb |
| Host | smart-f0e865d0-fa4a-4567-943a-283af6495122 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=605717871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.605717871 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1179827962 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 254808958200 ps |
| CPU time | 12569.7 seconds |
| Started | Jan 10 01:53:57 PM PST 24 |
| Finished | Jan 10 05:23:30 PM PST 24 |
| Peak memory | 603404 kb |
| Host | smart-4976fbae-ee89-4ad6-8603-bf4eae98ba18 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1179827962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1179827962 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.4271806440 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3463259416 ps |
| CPU time | 353.12 seconds |
| Started | Jan 10 01:53:24 PM PST 24 |
| Finished | Jan 10 01:59:19 PM PST 24 |
| Peak memory | 602480 kb |
| Host | smart-435fffbf-55b5-4cb5-b767-31d7e18f60e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271806440 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.4271806440 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3380966218 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 6851167620 ps |
| CPU time | 480.76 seconds |
| Started | Jan 10 01:54:53 PM PST 24 |
| Finished | Jan 10 02:03:04 PM PST 24 |
| Peak memory | 603140 kb |
| Host | smart-9c95be72-5293-414c-841c-f7b468e42e61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3380966218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3380966218 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.161161828 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 2918691944 ps |
| CPU time | 264.27 seconds |
| Started | Jan 10 01:59:11 PM PST 24 |
| Finished | Jan 10 02:03:37 PM PST 24 |
| Peak memory | 602388 kb |
| Host | smart-999ebac8-8b00-4e49-aadc-a193da1969a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161161828 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.161161828 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1061416892 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 7251080784 ps |
| CPU time | 618.3 seconds |
| Started | Jan 10 01:56:02 PM PST 24 |
| Finished | Jan 10 02:06:21 PM PST 24 |
| Peak memory | 602864 kb |
| Host | smart-714dfd4e-81e4-4d29-b05b-2eb9d49e150a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1061416892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.1061416892 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3370100591 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 5444592534 ps |
| CPU time | 586.33 seconds |
| Started | Jan 10 01:54:54 PM PST 24 |
| Finished | Jan 10 02:04:50 PM PST 24 |
| Peak memory | 603408 kb |
| Host | smart-a33dbe59-d3cd-478a-ad5c-bbcef17cb50e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3370100591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3370100591 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1883046362 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 7523116160 ps |
| CPU time | 986.34 seconds |
| Started | Jan 10 01:56:04 PM PST 24 |
| Finished | Jan 10 02:12:32 PM PST 24 |
| Peak memory | 609748 kb |
| Host | smart-d454ebf5-86a2-43d5-9d81-49ce70706f1b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883046362 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1883046362 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3798133053 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 6325414948 ps |
| CPU time | 552.91 seconds |
| Started | Jan 10 01:56:30 PM PST 24 |
| Finished | Jan 10 02:05:46 PM PST 24 |
| Peak memory | 604668 kb |
| Host | smart-601f6b2e-6d37-4a4f-845e-4c14134f3132 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3798133053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.3798133053 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.73889416 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4069504772 ps |
| CPU time | 615.23 seconds |
| Started | Jan 10 01:55:23 PM PST 24 |
| Finished | Jan 10 02:05:46 PM PST 24 |
| Peak memory | 595352 kb |
| Host | smart-a28ecd20-38ba-4547-bca3-f6c3cb589ada |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73889416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clk mgr_external_clk_src_for_sw_fast_rma.73889416 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1643943602 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 3740991676 ps |
| CPU time | 612.12 seconds |
| Started | Jan 10 01:56:47 PM PST 24 |
| Finished | Jan 10 02:07:04 PM PST 24 |
| Peak memory | 594312 kb |
| Host | smart-33401d92-cdf1-4cbb-b344-f9bf398c7a4c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643943602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1643943602 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2085042977 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 4387794120 ps |
| CPU time | 538.97 seconds |
| Started | Jan 10 01:56:08 PM PST 24 |
| Finished | Jan 10 02:05:08 PM PST 24 |
| Peak memory | 595184 kb |
| Host | smart-3ca55971-f932-4db9-882c-51e08b00249b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085042977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2085042977 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.289967835 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 4840416360 ps |
| CPU time | 625.86 seconds |
| Started | Jan 10 01:55:51 PM PST 24 |
| Finished | Jan 10 02:06:17 PM PST 24 |
| Peak memory | 594336 kb |
| Host | smart-8bbf5821-1b5a-4375-ad69-77c9093bdbe2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289967835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.289967835 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.861909109 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 4479667880 ps |
| CPU time | 598.11 seconds |
| Started | Jan 10 01:53:46 PM PST 24 |
| Finished | Jan 10 02:03:46 PM PST 24 |
| Peak memory | 595504 kb |
| Host | smart-82f48602-e4b4-4d00-9c80-aa0cf11f55a4 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861909109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.861909109 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3361719537 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2645894053 ps |
| CPU time | 263.98 seconds |
| Started | Jan 10 01:53:27 PM PST 24 |
| Finished | Jan 10 01:57:53 PM PST 24 |
| Peak memory | 602440 kb |
| Host | smart-cdb26ab4-c183-48c5-9b16-85a38e0c1df5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361719537 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3361719537 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.895278657 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 2835176614 ps |
| CPU time | 395.89 seconds |
| Started | Jan 10 01:55:37 PM PST 24 |
| Finished | Jan 10 02:02:14 PM PST 24 |
| Peak memory | 602484 kb |
| Host | smart-5c313e3a-f365-4905-88df-ae14e58328f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895278657 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.895278657 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3461986801 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 2811186984 ps |
| CPU time | 221.2 seconds |
| Started | Jan 10 01:58:12 PM PST 24 |
| Finished | Jan 10 02:02:00 PM PST 24 |
| Peak memory | 602388 kb |
| Host | smart-a5d010aa-168d-4fd4-bb56-1022bc6b4bf4 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461986801 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.3461986801 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.138673950 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 5121471890 ps |
| CPU time | 603.91 seconds |
| Started | Jan 10 01:55:22 PM PST 24 |
| Finished | Jan 10 02:05:34 PM PST 24 |
| Peak memory | 603140 kb |
| Host | smart-e3c8a8b7-230b-4530-b424-6da54a65d60d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138673950 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.138673950 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.4184625527 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 5276562070 ps |
| CPU time | 652.95 seconds |
| Started | Jan 10 01:56:11 PM PST 24 |
| Finished | Jan 10 02:07:06 PM PST 24 |
| Peak memory | 603168 kb |
| Host | smart-a9646fdc-9dc0-4a67-b373-79f7467187c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184625527 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.4184625527 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3588739592 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 4511293980 ps |
| CPU time | 432.65 seconds |
| Started | Jan 10 01:56:32 PM PST 24 |
| Finished | Jan 10 02:03:46 PM PST 24 |
| Peak memory | 603256 kb |
| Host | smart-8940169e-2321-4487-9112-b0bdf0f866a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588739592 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3588739592 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2795597046 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 5407672116 ps |
| CPU time | 525.23 seconds |
| Started | Jan 10 01:56:04 PM PST 24 |
| Finished | Jan 10 02:04:50 PM PST 24 |
| Peak memory | 603332 kb |
| Host | smart-b29ae58f-2e9d-4c1c-a93d-f89089046704 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795597046 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2795597046 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2166740760 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 8910516358 ps |
| CPU time | 1188.14 seconds |
| Started | Jan 10 01:54:50 PM PST 24 |
| Finished | Jan 10 02:14:40 PM PST 24 |
| Peak memory | 602884 kb |
| Host | smart-369bbe5b-00a8-4f02-8e56-cc5b7fa49ac1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166740760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2166740760 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.605641346 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3655352858 ps |
| CPU time | 468.46 seconds |
| Started | Jan 10 01:54:36 PM PST 24 |
| Finished | Jan 10 02:02:26 PM PST 24 |
| Peak memory | 602528 kb |
| Host | smart-ba6e96fa-4b82-4a59-8cc6-57860cb3eed4 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605641346 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.605641346 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2868485908 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 4639142580 ps |
| CPU time | 530.21 seconds |
| Started | Jan 10 01:55:53 PM PST 24 |
| Finished | Jan 10 02:04:44 PM PST 24 |
| Peak memory | 602768 kb |
| Host | smart-c270b656-0458-4509-b55a-ecf9cd76e17b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868485908 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.2868485908 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.56007323 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 2867516838 ps |
| CPU time | 243.03 seconds |
| Started | Jan 10 01:59:45 PM PST 24 |
| Finished | Jan 10 02:03:50 PM PST 24 |
| Peak memory | 602432 kb |
| Host | smart-4fedfcdc-e221-4059-8b81-65cfec40f85b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56007323 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_clkmgr_smoketest.56007323 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.1103595152 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 50252543878 ps |
| CPU time | 9291.78 seconds |
| Started | Jan 10 01:54:30 PM PST 24 |
| Finished | Jan 10 04:29:24 PM PST 24 |
| Peak memory | 602996 kb |
| Host | smart-919c362d-21b9-485c-bb8e-682d5933794d |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1103595152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1103595152 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.145887684 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 6509237240 ps |
| CPU time | 1429.15 seconds |
| Started | Jan 10 01:55:16 PM PST 24 |
| Finished | Jan 10 02:19:07 PM PST 24 |
| Peak memory | 603036 kb |
| Host | smart-0f16fe92-783c-49f7-b5eb-a4b895ed8b8c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145887684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.145887684 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3403937721 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 22790851316 ps |
| CPU time | 3417.28 seconds |
| Started | Jan 10 02:00:56 PM PST 24 |
| Finished | Jan 10 02:57:56 PM PST 24 |
| Peak memory | 602616 kb |
| Host | smart-94532338-2aac-4361-80e7-dc49381e3b3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403937721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _csrng_edn_concurrency_reduced_freq.3403937721 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.827386072 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 4552732038 ps |
| CPU time | 500.39 seconds |
| Started | Jan 10 01:53:21 PM PST 24 |
| Finished | Jan 10 02:01:42 PM PST 24 |
| Peak memory | 603508 kb |
| Host | smart-90b1446d-a8f8-40d5-9e37-fc056c2420b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82738 6072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.827386072 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.3942176057 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 2589845200 ps |
| CPU time | 228.06 seconds |
| Started | Jan 10 01:53:52 PM PST 24 |
| Finished | Jan 10 01:57:42 PM PST 24 |
| Peak memory | 602084 kb |
| Host | smart-13e108b6-977e-463f-88ea-a403a9c170bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942176057 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3942176057 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.476042313 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 2598623976 ps |
| CPU time | 169.89 seconds |
| Started | Jan 10 01:54:48 PM PST 24 |
| Finished | Jan 10 01:57:38 PM PST 24 |
| Peak memory | 602104 kb |
| Host | smart-982f7126-7c3d-48cd-b72d-76b0b103a781 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476042313 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_csrng_smoketest.476042313 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.4225115063 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 6214795272 ps |
| CPU time | 624.35 seconds |
| Started | Jan 10 01:56:33 PM PST 24 |
| Finished | Jan 10 02:07:08 PM PST 24 |
| Peak memory | 603824 kb |
| Host | smart-df2fe227-f8cd-4336-b434-9d76d35c2808 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4225115063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.4225115063 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2365017668 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 3652409692 ps |
| CPU time | 580.4 seconds |
| Started | Jan 10 01:53:28 PM PST 24 |
| Finished | Jan 10 02:03:10 PM PST 24 |
| Peak memory | 608560 kb |
| Host | smart-d44be6b8-1434-4295-8229-cddbe21adc74 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365017668 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2365017668 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.374731214 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 6335322988 ps |
| CPU time | 1324.36 seconds |
| Started | Jan 10 01:55:02 PM PST 24 |
| Finished | Jan 10 02:17:14 PM PST 24 |
| Peak memory | 602748 kb |
| Host | smart-17f5bd7f-645a-4c9d-8006-c15c06965387 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374731214 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.374731214 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2528116820 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 2850925300 ps |
| CPU time | 278.02 seconds |
| Started | Jan 10 01:53:56 PM PST 24 |
| Finished | Jan 10 01:58:37 PM PST 24 |
| Peak memory | 602124 kb |
| Host | smart-ec0dade8-cc7e-4d0a-ae7d-53072122e050 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 28116820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2528116820 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_fuse_en_fw_read_test.2116809091 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 4038641200 ps |
| CPU time | 436.27 seconds |
| Started | Jan 10 01:53:44 PM PST 24 |
| Finished | Jan 10 02:01:02 PM PST 24 |
| Peak memory | 602872 kb |
| Host | smart-56015199-e412-475a-9a5e-66c5123463f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18000000 +sw_build_device=sim_dv +sw_images=entropy_src_fuse_en_fw_read_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2116809091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_fuse_en_fw_read_test.2116809091 |
| Directory | /workspace/0.chip_sw_entropy_src_fuse_en_fw_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2522738204 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 3208243996 ps |
| CPU time | 224.73 seconds |
| Started | Jan 10 01:54:50 PM PST 24 |
| Finished | Jan 10 01:58:37 PM PST 24 |
| Peak memory | 602324 kb |
| Host | smart-a7b2f588-5909-435e-9ed6-61f7fcb9a33a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522738204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.2522738204 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3136298937 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2955803416 ps |
| CPU time | 425.41 seconds |
| Started | Jan 10 01:59:05 PM PST 24 |
| Finished | Jan 10 02:06:12 PM PST 24 |
| Peak memory | 602052 kb |
| Host | smart-0d021b13-2b72-41f1-a393-8b2415fc9c61 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3136298937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3136298937 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.4013982337 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 2587972844 ps |
| CPU time | 198.35 seconds |
| Started | Jan 10 01:54:17 PM PST 24 |
| Finished | Jan 10 01:57:37 PM PST 24 |
| Peak memory | 602364 kb |
| Host | smart-22da059f-5a65-4b87-a80e-a6c0fdba8903 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013982337 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.4013982337 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3255945433 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 2764211584 ps |
| CPU time | 180.87 seconds |
| Started | Jan 10 01:54:48 PM PST 24 |
| Finished | Jan 10 01:57:50 PM PST 24 |
| Peak memory | 602308 kb |
| Host | smart-190e4706-e95c-4050-98a5-e9cd3cc054cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255945433 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3255945433 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.3692420416 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 2614975160 ps |
| CPU time | 283.71 seconds |
| Started | Jan 10 01:55:32 PM PST 24 |
| Finished | Jan 10 02:00:18 PM PST 24 |
| Peak memory | 602216 kb |
| Host | smart-3516a261-cd00-488c-bdf2-ce52c1dd38ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692420416 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.3692420416 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.728424504 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2010767068 ps |
| CPU time | 134.75 seconds |
| Started | Jan 10 01:54:02 PM PST 24 |
| Finished | Jan 10 01:56:18 PM PST 24 |
| Peak memory | 601720 kb |
| Host | smart-a748c07c-261d-4a8e-8bd4-481404680cdc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728424504 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_example_rom.728424504 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3623563838 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 61286273028 ps |
| CPU time | 9800.45 seconds |
| Started | Jan 10 02:00:27 PM PST 24 |
| Finished | Jan 10 04:43:53 PM PST 24 |
| Peak memory | 616512 kb |
| Host | smart-08a6c699-b951-49b6-9ab8-4ee321de3fb9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3623563838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3623563838 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.1429481771 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 5406775800 ps |
| CPU time | 585.25 seconds |
| Started | Jan 10 01:56:33 PM PST 24 |
| Finished | Jan 10 02:06:28 PM PST 24 |
| Peak memory | 603988 kb |
| Host | smart-c3d67a7b-bfef-4a7a-be3f-80b04b8e1308 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1429481771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1429481771 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1139056835 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 5398563998 ps |
| CPU time | 764.31 seconds |
| Started | Jan 10 01:53:20 PM PST 24 |
| Finished | Jan 10 02:06:05 PM PST 24 |
| Peak memory | 602716 kb |
| Host | smart-f66ab72e-d112-4285-98df-9bf179543f7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139056835 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1139056835 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2381494924 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 5411816755 ps |
| CPU time | 1015.97 seconds |
| Started | Jan 10 01:54:20 PM PST 24 |
| Finished | Jan 10 02:11:17 PM PST 24 |
| Peak memory | 602764 kb |
| Host | smart-efdc421f-8d89-424b-87d3-f77913cf25bc |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381494924 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.2381494924 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3676578635 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 8052819289 ps |
| CPU time | 1046.54 seconds |
| Started | Jan 10 01:57:11 PM PST 24 |
| Finished | Jan 10 02:14:40 PM PST 24 |
| Peak memory | 602900 kb |
| Host | smart-3a2e6e22-9230-45c9-a476-226b1d23618a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676578635 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3676578635 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2204656718 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 5669155382 ps |
| CPU time | 1130.91 seconds |
| Started | Jan 10 01:53:31 PM PST 24 |
| Finished | Jan 10 02:12:23 PM PST 24 |
| Peak memory | 602668 kb |
| Host | smart-32bed655-09ca-45c9-b4a0-e49b1594a807 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204656718 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.2204656718 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.781579527 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 3555640600 ps |
| CPU time | 307.55 seconds |
| Started | Jan 10 01:53:53 PM PST 24 |
| Finished | Jan 10 01:59:02 PM PST 24 |
| Peak memory | 602152 kb |
| Host | smart-5adc5ac7-a950-467a-9956-74f5e9f3886e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781579527 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.781579527 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3908325752 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4653013685 ps |
| CPU time | 545.91 seconds |
| Started | Jan 10 01:53:35 PM PST 24 |
| Finished | Jan 10 02:02:42 PM PST 24 |
| Peak memory | 603412 kb |
| Host | smart-199a7814-6f59-4f2d-a286-19da29f94b9e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39 08325752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3908325752 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.418480985 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 5019607500 ps |
| CPU time | 833.21 seconds |
| Started | Jan 10 01:53:33 PM PST 24 |
| Finished | Jan 10 02:07:28 PM PST 24 |
| Peak memory | 602880 kb |
| Host | smart-0e496c95-c25d-4cf7-8e24-52f2b3a31051 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418480985 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.418480985 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2180589751 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 5357165940 ps |
| CPU time | 990.53 seconds |
| Started | Jan 10 01:54:47 PM PST 24 |
| Finished | Jan 10 02:11:19 PM PST 24 |
| Peak memory | 602944 kb |
| Host | smart-f1108112-ff12-481b-8b3f-e82172b645af |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2180589751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2180589751 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.1724299591 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 16413454512 ps |
| CPU time | 1958.82 seconds |
| Started | Jan 10 01:53:45 PM PST 24 |
| Finished | Jan 10 02:26:26 PM PST 24 |
| Peak memory | 603260 kb |
| Host | smart-78c3a6c3-0888-4ea4-bd11-d61745094a08 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724299591 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.1724299591 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2213265348 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 23368579204 ps |
| CPU time | 1949.51 seconds |
| Started | Jan 10 01:56:06 PM PST 24 |
| Finished | Jan 10 02:28:37 PM PST 24 |
| Peak memory | 603252 kb |
| Host | smart-37110041-6118-4b86-963b-3a6d72d01b3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2213265348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2213265348 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4000445388 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 2535982632 ps |
| CPU time | 196.1 seconds |
| Started | Jan 10 02:04:29 PM PST 24 |
| Finished | Jan 10 02:07:49 PM PST 24 |
| Peak memory | 602088 kb |
| Host | smart-6fb82f9c-09d4-401c-939b-962df3033d1f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4000445388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.4000445388 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.3036034972 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2741610642 ps |
| CPU time | 297.27 seconds |
| Started | Jan 10 01:59:48 PM PST 24 |
| Finished | Jan 10 02:04:55 PM PST 24 |
| Peak memory | 602720 kb |
| Host | smart-2626a6e8-277d-4d15-b360-0852778da61f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036034972 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.3036034972 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.427790192 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2485941848 ps |
| CPU time | 315.62 seconds |
| Started | Jan 10 01:53:57 PM PST 24 |
| Finished | Jan 10 01:59:15 PM PST 24 |
| Peak memory | 602552 kb |
| Host | smart-06f5967a-74a4-48e7-bf24-c36cb1269eaf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427790192 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.427790192 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.57712229 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 2863059948 ps |
| CPU time | 261.98 seconds |
| Started | Jan 10 01:54:20 PM PST 24 |
| Finished | Jan 10 01:58:43 PM PST 24 |
| Peak memory | 602476 kb |
| Host | smart-bf9f1579-0758-4b2c-948d-cea58f79e6ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57712229 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_hmac_enc_idle.57712229 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.386530691 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 3544395569 ps |
| CPU time | 267.11 seconds |
| Started | Jan 10 01:53:59 PM PST 24 |
| Finished | Jan 10 01:58:27 PM PST 24 |
| Peak memory | 602572 kb |
| Host | smart-a949f8e3-65d6-46f3-81ae-6b220026dbfb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386530691 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.386530691 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3745914914 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 2957203486 ps |
| CPU time | 307.49 seconds |
| Started | Jan 10 01:58:04 PM PST 24 |
| Finished | Jan 10 02:03:22 PM PST 24 |
| Peak memory | 602556 kb |
| Host | smart-39e496cb-9ce0-4ce0-92bc-614e51be160f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745914914 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.3745914914 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.1857805137 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 3192205816 ps |
| CPU time | 353.57 seconds |
| Started | Jan 10 01:59:29 PM PST 24 |
| Finished | Jan 10 02:05:25 PM PST 24 |
| Peak memory | 602120 kb |
| Host | smart-b8e9e2d2-2442-4e08-9201-7d2638831326 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857805137 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.1857805137 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.4066215600 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 3377332878 ps |
| CPU time | 614.8 seconds |
| Started | Jan 10 01:58:41 PM PST 24 |
| Finished | Jan 10 02:09:05 PM PST 24 |
| Peak memory | 603540 kb |
| Host | smart-68bbabc6-97a6-498a-a3d3-93c315db1192 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066215600 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.4066215600 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2256290305 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 66744270918 ps |
| CPU time | 10385.9 seconds |
| Started | Jan 10 01:53:57 PM PST 24 |
| Finished | Jan 10 04:47:07 PM PST 24 |
| Peak memory | 617052 kb |
| Host | smart-329702f2-b786-48b1-8f94-deae1712840a |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2256290305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.2256290305 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.124334973 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 4014044286 ps |
| CPU time | 490.15 seconds |
| Started | Jan 10 01:53:28 PM PST 24 |
| Finished | Jan 10 02:01:41 PM PST 24 |
| Peak memory | 610488 kb |
| Host | smart-8b2de165-8436-44bb-8360-9585af638245 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243 34973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.124334973 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.780787666 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 3238778858 ps |
| CPU time | 382.17 seconds |
| Started | Jan 10 01:54:22 PM PST 24 |
| Finished | Jan 10 02:00:45 PM PST 24 |
| Peak memory | 610540 kb |
| Host | smart-d28b78d7-4839-4867-90c3-985c99a29b19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=780787666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.780787666 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3794054262 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4410793420 ps |
| CPU time | 409.64 seconds |
| Started | Jan 10 01:54:20 PM PST 24 |
| Finished | Jan 10 02:01:11 PM PST 24 |
| Peak memory | 610480 kb |
| Host | smart-01d45df3-33b6-4212-a92c-eb2f9fc862a8 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3794054262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3794054262 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1642020418 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5300496604 ps |
| CPU time | 474.54 seconds |
| Started | Jan 10 01:55:15 PM PST 24 |
| Finished | Jan 10 02:03:11 PM PST 24 |
| Peak memory | 603972 kb |
| Host | smart-bc5d534b-2c40-4091-9ab3-81a13fe09910 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16420 20418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1642020418 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.4078658371 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 3149676360 ps |
| CPU time | 235.55 seconds |
| Started | Jan 10 01:55:05 PM PST 24 |
| Finished | Jan 10 01:59:06 PM PST 24 |
| Peak memory | 602020 kb |
| Host | smart-1925f66b-bcfa-402b-942c-7a99144bc486 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078658371 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.4078658371 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.552324334 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 2277340280 ps |
| CPU time | 268.95 seconds |
| Started | Jan 10 01:54:19 PM PST 24 |
| Finished | Jan 10 01:58:49 PM PST 24 |
| Peak memory | 602416 kb |
| Host | smart-d13e865c-660a-472b-a69c-a6d4985c98df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552324334 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.552324334 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.1107461895 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 3306156692 ps |
| CPU time | 263.62 seconds |
| Started | Jan 10 01:54:34 PM PST 24 |
| Finished | Jan 10 01:58:59 PM PST 24 |
| Peak memory | 602340 kb |
| Host | smart-94d56b94-d66f-4e17-9824-d46bf9723cdc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107461895 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.1107461895 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2818623492 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 3546195056 ps |
| CPU time | 271.87 seconds |
| Started | Jan 10 01:56:04 PM PST 24 |
| Finished | Jan 10 02:00:37 PM PST 24 |
| Peak memory | 601976 kb |
| Host | smart-c211a9ee-a138-40a5-a316-1309c93c6a73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818623492 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.2818623492 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2581794770 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3709189680 ps |
| CPU time | 304.11 seconds |
| Started | Jan 10 01:54:59 PM PST 24 |
| Finished | Jan 10 02:00:08 PM PST 24 |
| Peak memory | 602380 kb |
| Host | smart-4d293bd7-8522-44f2-af55-7e5a510cc5ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581794770 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.2581794770 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2608236365 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 3049233674 ps |
| CPU time | 220.06 seconds |
| Started | Jan 10 01:53:25 PM PST 24 |
| Finished | Jan 10 01:57:07 PM PST 24 |
| Peak memory | 602384 kb |
| Host | smart-d8255838-ee78-4557-b42f-d5356965ca92 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608236365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2608236365 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3031046130 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 3531352392 ps |
| CPU time | 328.03 seconds |
| Started | Jan 10 01:57:28 PM PST 24 |
| Finished | Jan 10 02:02:58 PM PST 24 |
| Peak memory | 602456 kb |
| Host | smart-54af57ac-0a5c-4d29-a0e2-5007865a0403 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30310461 30 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3031046130 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.1011842837 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 2818572152 ps |
| CPU time | 272.74 seconds |
| Started | Jan 10 01:56:27 PM PST 24 |
| Finished | Jan 10 02:01:00 PM PST 24 |
| Peak memory | 602408 kb |
| Host | smart-f1ddff7b-f333-487f-8bb9-d6ea73796e3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011842837 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.1011842837 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg.2204789107 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2371279180 ps |
| CPU time | 219.18 seconds |
| Started | Jan 10 01:53:59 PM PST 24 |
| Finished | Jan 10 01:57:40 PM PST 24 |
| Peak memory | 602032 kb |
| Host | smart-79761d35-4b53-413b-922a-967280546761 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204789107 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg.2204789107 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3007574857 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 3916225634 ps |
| CPU time | 133.78 seconds |
| Started | Jan 10 01:54:10 PM PST 24 |
| Finished | Jan 10 01:56:25 PM PST 24 |
| Peak memory | 601968 kb |
| Host | smart-5573cdd8-5acf-4635-b2f0-ae48e5a7dfd6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30075748 57 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3007574857 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3695885856 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 3026979999 ps |
| CPU time | 155.85 seconds |
| Started | Jan 10 01:53:56 PM PST 24 |
| Finished | Jan 10 01:56:34 PM PST 24 |
| Peak memory | 603264 kb |
| Host | smart-23eaa72f-0a6a-4fe2-bbd7-d205cc642cd2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695885856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3695885856 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1669794086 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 3007468956 ps |
| CPU time | 132.44 seconds |
| Started | Jan 10 01:53:51 PM PST 24 |
| Finished | Jan 10 01:56:05 PM PST 24 |
| Peak memory | 603160 kb |
| Host | smart-546ae141-1d31-49e2-8278-269165075dfd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669794086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1669794086 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3490857141 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 9279179441 ps |
| CPU time | 1048.15 seconds |
| Started | Jan 10 01:53:18 PM PST 24 |
| Finished | Jan 10 02:10:48 PM PST 24 |
| Peak memory | 604684 kb |
| Host | smart-dfdb9651-411c-453f-997f-81db7ac7c80e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490857141 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.3490857141 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3395307309 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 3865340580 ps |
| CPU time | 300.05 seconds |
| Started | Jan 10 01:55:03 PM PST 24 |
| Finished | Jan 10 02:00:10 PM PST 24 |
| Peak memory | 601696 kb |
| Host | smart-15063ada-bb6c-40f2-9972-1cc42b774c2a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=lc_ctrl_volat ile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395307309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_ unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_vol atile_raw_unlock_ext_clk_48mhz.3395307309 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1643895762 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 34234593603 ps |
| CPU time | 2340.82 seconds |
| Started | Jan 10 01:53:58 PM PST 24 |
| Finished | Jan 10 02:33:01 PM PST 24 |
| Peak memory | 608852 kb |
| Host | smart-69ba498e-65b6-48e6-8769-77827ebb989e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1643895762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.1643895762 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2559273519 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 16637903970 ps |
| CPU time | 2792.42 seconds |
| Started | Jan 10 01:56:13 PM PST 24 |
| Finished | Jan 10 02:42:47 PM PST 24 |
| Peak memory | 603068 kb |
| Host | smart-81863c23-a662-4d19-b7ca-af864d2b509b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2559273519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2559273519 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3899525472 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 18338188416 ps |
| CPU time | 2674.03 seconds |
| Started | Jan 10 01:55:37 PM PST 24 |
| Finished | Jan 10 02:40:13 PM PST 24 |
| Peak memory | 602900 kb |
| Host | smart-5c494b92-daf4-4b10-b328-ab9e952cc009 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3899525472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3899525472 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.518262479 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 23873623664 ps |
| CPU time | 3181.44 seconds |
| Started | Jan 10 01:57:25 PM PST 24 |
| Finished | Jan 10 02:50:29 PM PST 24 |
| Peak memory | 602684 kb |
| Host | smart-469d4d16-1518-41ca-9c9c-fd6451218588 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518262479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.518262479 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3562428785 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 3368112516 ps |
| CPU time | 390.14 seconds |
| Started | Jan 10 01:56:07 PM PST 24 |
| Finished | Jan 10 02:02:38 PM PST 24 |
| Peak memory | 602432 kb |
| Host | smart-17f8b922-5a0a-44fd-aba2-87dc4bf85f3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562428785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.3562428785 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.1538571112 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 6197659120 ps |
| CPU time | 554.62 seconds |
| Started | Jan 10 01:54:33 PM PST 24 |
| Finished | Jan 10 02:03:48 PM PST 24 |
| Peak memory | 602512 kb |
| Host | smart-0b2956a5-67af-4874-b55b-0fa4750b7614 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1538571112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.1538571112 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.207265713 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 9494820716 ps |
| CPU time | 1634.34 seconds |
| Started | Jan 10 01:59:27 PM PST 24 |
| Finished | Jan 10 02:26:43 PM PST 24 |
| Peak memory | 602984 kb |
| Host | smart-20df4b08-b24a-45b3-a3d3-d10d515add26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207265713 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_smoketest.207265713 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1383461993 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 8085587720 ps |
| CPU time | 919.01 seconds |
| Started | Jan 10 01:53:18 PM PST 24 |
| Finished | Jan 10 02:08:39 PM PST 24 |
| Peak memory | 603192 kb |
| Host | smart-6113bcc3-2e40-4f14-adf6-bb4ac434ac8d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1383461993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1383461993 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3713660741 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 7010255746 ps |
| CPU time | 1227.94 seconds |
| Started | Jan 10 01:55:36 PM PST 24 |
| Finished | Jan 10 02:16:06 PM PST 24 |
| Peak memory | 603584 kb |
| Host | smart-75308925-b074-4f25-8b77-299cdaf56e86 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3713660741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3713660741 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2605819451 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 7742585880 ps |
| CPU time | 1121.94 seconds |
| Started | Jan 10 01:54:32 PM PST 24 |
| Finished | Jan 10 02:13:16 PM PST 24 |
| Peak memory | 603208 kb |
| Host | smart-244f0cbe-5c69-412e-bce2-1c41bf624c61 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2605819451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.2605819451 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1777152703 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 4768669216 ps |
| CPU time | 695.25 seconds |
| Started | Jan 10 01:54:15 PM PST 24 |
| Finished | Jan 10 02:05:51 PM PST 24 |
| Peak memory | 602848 kb |
| Host | smart-12b2165e-744b-4992-b82b-22b618d3f609 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1777152703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1777152703 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.168361836 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 3535204206 ps |
| CPU time | 315.57 seconds |
| Started | Jan 10 02:03:01 PM PST 24 |
| Finished | Jan 10 02:08:39 PM PST 24 |
| Peak memory | 602400 kb |
| Host | smart-002b6bb5-7766-40fb-b84a-57766c500d39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168361836 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_otp_ctrl_smoketest.168361836 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.165005228 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3036110392 ps |
| CPU time | 264.6 seconds |
| Started | Jan 10 01:56:38 PM PST 24 |
| Finished | Jan 10 02:01:12 PM PST 24 |
| Peak memory | 602328 kb |
| Host | smart-b29b3fd8-a558-4e31-bdad-9b726388c30b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165005228 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_plic_sw_irq.165005228 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.2753650495 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 3990305476 ps |
| CPU time | 649.11 seconds |
| Started | Jan 10 02:01:04 PM PST 24 |
| Finished | Jan 10 02:11:54 PM PST 24 |
| Peak memory | 602880 kb |
| Host | smart-f879383c-2d21-4cde-8948-0fb4c2ef6b84 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753650495 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2753650495 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2510556464 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 3820117280 ps |
| CPU time | 425.31 seconds |
| Started | Jan 10 01:58:40 PM PST 24 |
| Finished | Jan 10 02:05:57 PM PST 24 |
| Peak memory | 590648 kb |
| Host | smart-97986ae0-57be-4be1-a905-0929a0b3e652 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510556464 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2510556464 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2430865068 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 9944693707 ps |
| CPU time | 1141.68 seconds |
| Started | Jan 10 01:55:31 PM PST 24 |
| Finished | Jan 10 02:14:36 PM PST 24 |
| Peak memory | 604264 kb |
| Host | smart-d03f93ca-12b2-477d-8150-e57966970dee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430 865068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2430865068 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1859901511 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 19936348250 ps |
| CPU time | 1721.17 seconds |
| Started | Jan 10 01:56:26 PM PST 24 |
| Finished | Jan 10 02:25:08 PM PST 24 |
| Peak memory | 603596 kb |
| Host | smart-6bbcfbae-fe20-478e-b090-8a010dd1c4f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185 9901511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.1859901511 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1187944051 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 16284842170 ps |
| CPU time | 1230.02 seconds |
| Started | Jan 10 01:55:01 PM PST 24 |
| Finished | Jan 10 02:15:38 PM PST 24 |
| Peak memory | 603916 kb |
| Host | smart-ce8e9f4c-7bde-45cc-85ac-f5809926f07c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1187944051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1187944051 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.231621750 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 20418776332 ps |
| CPU time | 1261.45 seconds |
| Started | Jan 10 01:55:00 PM PST 24 |
| Finished | Jan 10 02:16:10 PM PST 24 |
| Peak memory | 603404 kb |
| Host | smart-b210b3fc-303f-4e97-b1a6-9712d717e206 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 231621750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.231621750 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.131720622 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 8797849200 ps |
| CPU time | 784.88 seconds |
| Started | Jan 10 01:54:04 PM PST 24 |
| Finished | Jan 10 02:07:11 PM PST 24 |
| Peak memory | 590440 kb |
| Host | smart-7d3de2d3-2da8-4eaf-a843-5d6ce1549018 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131720622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.131720622 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3213969553 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 5234560752 ps |
| CPU time | 493.16 seconds |
| Started | Jan 10 01:53:31 PM PST 24 |
| Finished | Jan 10 02:01:45 PM PST 24 |
| Peak memory | 609764 kb |
| Host | smart-c3e88802-23bb-4cef-9828-39e712913d6e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3213969553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3213969553 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.633612642 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 8588080300 ps |
| CPU time | 420.42 seconds |
| Started | Jan 10 01:54:02 PM PST 24 |
| Finished | Jan 10 02:01:05 PM PST 24 |
| Peak memory | 603232 kb |
| Host | smart-abd70707-ebda-4065-bc75-1e6d88538137 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633612642 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.633612642 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2781589244 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 10024966905 ps |
| CPU time | 1192.46 seconds |
| Started | Jan 10 01:53:55 PM PST 24 |
| Finished | Jan 10 02:13:49 PM PST 24 |
| Peak memory | 603976 kb |
| Host | smart-1cf67e70-ffbf-40d0-8c32-2530d79ab764 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781589244 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2781589244 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2678878690 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 7332186734 ps |
| CPU time | 396.92 seconds |
| Started | Jan 10 01:57:05 PM PST 24 |
| Finished | Jan 10 02:03:43 PM PST 24 |
| Peak memory | 603288 kb |
| Host | smart-65421ebe-070f-44be-855d-10209ddab6ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678878690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2678878690 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3014837406 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 32148419588 ps |
| CPU time | 2734.5 seconds |
| Started | Jan 10 01:53:50 PM PST 24 |
| Finished | Jan 10 02:39:26 PM PST 24 |
| Peak memory | 593300 kb |
| Host | smart-ed0f23fd-9d40-41fc-98d6-85e42ec0f3bf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014837406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3014837406 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2095862779 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 2757480846 ps |
| CPU time | 296.01 seconds |
| Started | Jan 10 01:54:34 PM PST 24 |
| Finished | Jan 10 01:59:31 PM PST 24 |
| Peak memory | 602300 kb |
| Host | smart-64976325-6c5f-4c5e-8823-d766cd33f915 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095862779 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.2095862779 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1131370338 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 4351805600 ps |
| CPU time | 454.99 seconds |
| Started | Jan 10 01:54:20 PM PST 24 |
| Finished | Jan 10 02:01:56 PM PST 24 |
| Peak memory | 610204 kb |
| Host | smart-84303ce1-411d-410f-b779-1f0dda7bb711 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1131370338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.1131370338 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3050692272 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 5418099000 ps |
| CPU time | 434.23 seconds |
| Started | Jan 10 01:57:06 PM PST 24 |
| Finished | Jan 10 02:04:22 PM PST 24 |
| Peak memory | 602520 kb |
| Host | smart-5a50ade9-ced6-4da7-b54c-6098f74f1235 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30506922 72 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3050692272 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3386822495 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 5567495550 ps |
| CPU time | 485.46 seconds |
| Started | Jan 10 01:55:51 PM PST 24 |
| Finished | Jan 10 02:03:57 PM PST 24 |
| Peak memory | 603196 kb |
| Host | smart-88510921-ad9e-4fc9-bf05-7e5b54fcb19e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386822495 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3386822495 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2652793730 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 6243563760 ps |
| CPU time | 988.98 seconds |
| Started | Jan 10 01:54:11 PM PST 24 |
| Finished | Jan 10 02:10:42 PM PST 24 |
| Peak memory | 591484 kb |
| Host | smart-8a5a7304-990f-4922-a974-c89417d02b85 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652793730 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2652793730 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2184588263 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 4568969416 ps |
| CPU time | 452.77 seconds |
| Started | Jan 10 01:54:55 PM PST 24 |
| Finished | Jan 10 02:02:36 PM PST 24 |
| Peak memory | 603232 kb |
| Host | smart-a3cc5679-09cc-4053-ae54-a8411557b058 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184588263 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2184588263 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.599118924 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 5010123176 ps |
| CPU time | 373.11 seconds |
| Started | Jan 10 01:57:14 PM PST 24 |
| Finished | Jan 10 02:03:28 PM PST 24 |
| Peak memory | 602812 kb |
| Host | smart-6380a5df-d297-48b4-8ed7-8fdbbb3dc692 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599118924 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.599118924 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3426409382 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 4045720340 ps |
| CPU time | 379.14 seconds |
| Started | Jan 10 01:54:56 PM PST 24 |
| Finished | Jan 10 02:01:23 PM PST 24 |
| Peak memory | 602880 kb |
| Host | smart-6b388328-4b7e-40aa-9532-b6d6d27ced67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342 6409382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3426409382 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2682544242 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 9386953930 ps |
| CPU time | 462.43 seconds |
| Started | Jan 10 01:55:25 PM PST 24 |
| Finished | Jan 10 02:03:13 PM PST 24 |
| Peak memory | 607072 kb |
| Host | smart-a5e09681-1e5f-44ed-8a6b-6c0d897a0db0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682544242 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.2682544242 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.680417330 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 6333911098 ps |
| CPU time | 506.01 seconds |
| Started | Jan 10 01:54:31 PM PST 24 |
| Finished | Jan 10 02:02:59 PM PST 24 |
| Peak memory | 603356 kb |
| Host | smart-b2d1c850-6457-4797-9dc8-ef25fbc39dfe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680417330 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_rstmgr_cpu_info.680417330 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1087728727 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5915016390 ps |
| CPU time | 609.51 seconds |
| Started | Jan 10 01:53:54 PM PST 24 |
| Finished | Jan 10 02:04:06 PM PST 24 |
| Peak memory | 634536 kb |
| Host | smart-52d2fe7a-b526-42f3-94fd-d28e7bbd4dbd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1087728727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1087728727 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3366113592 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 2443700806 ps |
| CPU time | 212.6 seconds |
| Started | Jan 10 01:54:41 PM PST 24 |
| Finished | Jan 10 01:58:15 PM PST 24 |
| Peak memory | 602388 kb |
| Host | smart-0f9294d6-e447-4723-9d17-9fd13db746be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366113592 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.3366113592 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3606210851 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 3795103152 ps |
| CPU time | 341.62 seconds |
| Started | Jan 10 01:53:12 PM PST 24 |
| Finished | Jan 10 01:58:59 PM PST 24 |
| Peak memory | 602912 kb |
| Host | smart-41f97d70-911a-4333-9f0a-e6e840a8c362 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606210851 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.3606210851 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.857888919 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 2284214096 ps |
| CPU time | 239.04 seconds |
| Started | Jan 10 01:54:25 PM PST 24 |
| Finished | Jan 10 01:58:26 PM PST 24 |
| Peak memory | 602520 kb |
| Host | smart-5217bd9e-a166-4e16-bffd-1bb105657533 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857888919 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.857888919 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.63194839 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2561396256 ps |
| CPU time | 246.31 seconds |
| Started | Jan 10 01:56:22 PM PST 24 |
| Finished | Jan 10 02:00:29 PM PST 24 |
| Peak memory | 590392 kb |
| Host | smart-16bfcff6-0d5b-45dc-a6df-5617c6264668 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63194839 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.63194839 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1129091601 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 5231010800 ps |
| CPU time | 915.5 seconds |
| Started | Jan 10 01:56:38 PM PST 24 |
| Finished | Jan 10 02:12:03 PM PST 24 |
| Peak memory | 602352 kb |
| Host | smart-53d2e866-3e11-4c5b-9239-57398f3569ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1129091601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1129091601 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2728463976 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4678123064 ps |
| CPU time | 427.75 seconds |
| Started | Jan 10 01:56:39 PM PST 24 |
| Finished | Jan 10 02:03:56 PM PST 24 |
| Peak memory | 616152 kb |
| Host | smart-6981e7e1-3b6c-43b7-92e1-e98a14e3fdf0 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup:1:new_rules,test_rom:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728463976 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.2728463976 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3560357705 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2710913750 ps |
| CPU time | 180.46 seconds |
| Started | Jan 10 01:56:34 PM PST 24 |
| Finished | Jan 10 01:59:48 PM PST 24 |
| Peak memory | 602336 kb |
| Host | smart-c6c64932-704d-45dd-820c-3593c81f8792 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560357705 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.3560357705 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.2985412830 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2889501840 ps |
| CPU time | 338.62 seconds |
| Started | Jan 10 01:55:01 PM PST 24 |
| Finished | Jan 10 02:00:47 PM PST 24 |
| Peak memory | 602016 kb |
| Host | smart-0144d7d5-9046-4a33-b21b-33506743a51e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985412830 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.2985412830 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2087068909 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 3361926342 ps |
| CPU time | 224.58 seconds |
| Started | Jan 10 01:56:52 PM PST 24 |
| Finished | Jan 10 02:00:38 PM PST 24 |
| Peak memory | 602024 kb |
| Host | smart-fd6c99bd-b18a-4d0b-bfe2-32dd3503db01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087068909 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.2087068909 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3907877884 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 8671077512 ps |
| CPU time | 1063.39 seconds |
| Started | Jan 10 01:55:34 PM PST 24 |
| Finished | Jan 10 02:13:19 PM PST 24 |
| Peak memory | 591284 kb |
| Host | smart-73c5d320-f182-4892-8b07-826dce85c5ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907877884 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3907877884 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4232605455 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 5931298536 ps |
| CPU time | 454.21 seconds |
| Started | Jan 10 01:55:25 PM PST 24 |
| Finished | Jan 10 02:03:04 PM PST 24 |
| Peak memory | 602976 kb |
| Host | smart-c6652921-be6d-464e-aa8a-49b82992bf8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232605455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.4232605455 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3336779603 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 4881010826 ps |
| CPU time | 686.39 seconds |
| Started | Jan 10 01:53:57 PM PST 24 |
| Finished | Jan 10 02:05:26 PM PST 24 |
| Peak memory | 618092 kb |
| Host | smart-d9fbe1ac-614e-4594-a1ff-4ef2a3e710cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336779603 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3336779603 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.526650949 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2844055493 ps |
| CPU time | 342.39 seconds |
| Started | Jan 10 01:54:16 PM PST 24 |
| Finished | Jan 10 01:59:59 PM PST 24 |
| Peak memory | 608644 kb |
| Host | smart-da11bb36-6dd6-424e-bfdc-e6bd12d6858b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526650949 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.526650949 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tx_rx.3764398443 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 3283778424 ps |
| CPU time | 338.7 seconds |
| Started | Jan 10 01:53:13 PM PST 24 |
| Finished | Jan 10 01:58:56 PM PST 24 |
| Peak memory | 601704 kb |
| Host | smart-ebd4b5a6-f227-4596-aa10-70304e7f304e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764398443 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_spi_device_tx_rx.3764398443 |
| Directory | /workspace/0.chip_sw_spi_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2171813174 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 7782928410 ps |
| CPU time | 629.06 seconds |
| Started | Jan 10 01:54:50 PM PST 24 |
| Finished | Jan 10 02:05:21 PM PST 24 |
| Peak memory | 603468 kb |
| Host | smart-661efb86-3938-44ed-853b-44138e5bfa88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171813174 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2171813174 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2140868155 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4965867360 ps |
| CPU time | 605.33 seconds |
| Started | Jan 10 01:56:05 PM PST 24 |
| Finished | Jan 10 02:06:12 PM PST 24 |
| Peak memory | 602688 kb |
| Host | smart-9d1f2d85-c640-4f7d-8e00-2371fdd32ed5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140868155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2140868155 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1617913423 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 4125218070 ps |
| CPU time | 631.62 seconds |
| Started | Jan 10 01:55:06 PM PST 24 |
| Finished | Jan 10 02:05:42 PM PST 24 |
| Peak memory | 602824 kb |
| Host | smart-ebc599bc-b4a0-4e5a-86d8-6bafccb0edea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617913423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1617913423 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.772024845 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4889501164 ps |
| CPU time | 643.57 seconds |
| Started | Jan 10 02:00:21 PM PST 24 |
| Finished | Jan 10 02:11:07 PM PST 24 |
| Peak memory | 603052 kb |
| Host | smart-d15c9b05-6c45-4588-aeca-0a52cdfb641f |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772024845 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.772024845 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.584041641 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2938831048 ps |
| CPU time | 185.02 seconds |
| Started | Jan 10 01:55:20 PM PST 24 |
| Finished | Jan 10 01:58:33 PM PST 24 |
| Peak memory | 602388 kb |
| Host | smart-a2b38b14-53f1-4a39-b9ed-bf14923b4253 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584041641 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sram_ctrl_smoketest.584041641 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3065466186 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 2632398689 ps |
| CPU time | 303.81 seconds |
| Started | Jan 10 01:53:29 PM PST 24 |
| Finished | Jan 10 01:58:36 PM PST 24 |
| Peak memory | 602676 kb |
| Host | smart-0e0e7051-f386-4d72-b2c1-442cc4ace844 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065466186 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.3065466186 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.774881901 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 3676683992 ps |
| CPU time | 394.74 seconds |
| Started | Jan 10 01:55:01 PM PST 24 |
| Finished | Jan 10 02:01:43 PM PST 24 |
| Peak memory | 602684 kb |
| Host | smart-f7c0140d-e74e-48c8-9779-c60716e765a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774881901 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.774881901 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1381655537 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 21156525300 ps |
| CPU time | 1508.95 seconds |
| Started | Jan 10 01:55:38 PM PST 24 |
| Finished | Jan 10 02:20:49 PM PST 24 |
| Peak memory | 603868 kb |
| Host | smart-556c222c-9e13-4f5b-abeb-0f6cb20db76a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13816555 37 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.1381655537 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1108387817 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 4320654242 ps |
| CPU time | 427.7 seconds |
| Started | Jan 10 01:55:26 PM PST 24 |
| Finished | Jan 10 02:02:40 PM PST 24 |
| Peak memory | 603564 kb |
| Host | smart-88a68680-84b7-4d6c-9115-aed9bc13cc3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108387817 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1108387817 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.4289650954 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2778454560 ps |
| CPU time | 265.55 seconds |
| Started | Jan 10 01:56:00 PM PST 24 |
| Finished | Jan 10 02:00:27 PM PST 24 |
| Peak memory | 590368 kb |
| Host | smart-78a8d1e0-c14a-4edf-a5ae-0b701b1f2969 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289650954 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.4289650954 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest_signed.1482059171 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 8868429608 ps |
| CPU time | 1854.66 seconds |
| Started | Jan 10 01:59:03 PM PST 24 |
| Finished | Jan 10 02:29:59 PM PST 24 |
| Peak memory | 590428 kb |
| Host | smart-5ad59fcf-7726-450e-a8f5-31739e725aa5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=uart_smoketest_signed:1:signed:fake_rsa_test_key_0,rom_with_fa ke_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1482059171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_smoketest_signed.1482059171 |
| Directory | /workspace/0.chip_sw_uart_smoketest_signed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2597088192 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 23478508736 ps |
| CPU time | 3525.95 seconds |
| Started | Jan 10 01:58:08 PM PST 24 |
| Finished | Jan 10 02:57:01 PM PST 24 |
| Peak memory | 599504 kb |
| Host | smart-6552806c-e563-476b-a921-71c25dcaa734 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597088192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_r x_alt_clk_freq.2597088192 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1229128243 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 5768829349 ps |
| CPU time | 859.67 seconds |
| Started | Jan 10 01:58:42 PM PST 24 |
| Finished | Jan 10 02:13:11 PM PST 24 |
| Peak memory | 599132 kb |
| Host | smart-00c1cf3b-dab8-4d3b-b039-1ee4464404a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229128243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_r x_alt_clk_freq_low_speed.1229128243 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2397942560 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 6107749352 ps |
| CPU time | 831.08 seconds |
| Started | Jan 10 01:56:23 PM PST 24 |
| Finished | Jan 10 02:10:15 PM PST 24 |
| Peak memory | 599436 kb |
| Host | smart-51976784-4423-4896-9f8a-e6b2f21ca6e9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397942560 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2397942560 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.94396813 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 6203699956 ps |
| CPU time | 899.92 seconds |
| Started | Jan 10 01:58:02 PM PST 24 |
| Finished | Jan 10 02:13:15 PM PST 24 |
| Peak memory | 599052 kb |
| Host | smart-f9f69b4c-484f-4449-8b55-e8690b1b2bf4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94396813 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.94396813 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2541523008 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 5661130800 ps |
| CPU time | 976.15 seconds |
| Started | Jan 10 01:56:36 PM PST 24 |
| Finished | Jan 10 02:13:04 PM PST 24 |
| Peak memory | 599132 kb |
| Host | smart-0b79c4c9-d8f6-417d-88c4-d109d93b338a |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541523008 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2541523008 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3805383689 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3144936035 ps |
| CPU time | 322.98 seconds |
| Started | Jan 10 01:56:32 PM PST 24 |
| Finished | Jan 10 02:02:05 PM PST 24 |
| Peak memory | 602388 kb |
| Host | smart-ff903772-0801-4acb-bbe7-e2ea61345387 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805383689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3805383689 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.4215925090 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 11479023624 ps |
| CPU time | 2207.2 seconds |
| Started | Jan 10 01:56:11 PM PST 24 |
| Finished | Jan 10 02:33:00 PM PST 24 |
| Peak memory | 602472 kb |
| Host | smart-0fa57ebf-efdf-48a7-8b4f-f4871c3424df |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4215925090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.4215925090 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.988636612 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2633391140 ps |
| CPU time | 203.46 seconds |
| Started | Jan 10 01:56:42 PM PST 24 |
| Finished | Jan 10 02:00:11 PM PST 24 |
| Peak memory | 601760 kb |
| Host | smart-825cd4f4-7aaa-4a45-8e86-0d98fdf822de |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988636612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.988636612 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2707410511 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4007690012 ps |
| CPU time | 629.14 seconds |
| Started | Jan 10 01:58:18 PM PST 24 |
| Finished | Jan 10 02:08:49 PM PST 24 |
| Peak memory | 602236 kb |
| Host | smart-594c53f2-893b-4318-babf-adf28fd3a769 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270741051 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2707410511 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.484559099 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 18281379622 ps |
| CPU time | 3781.58 seconds |
| Started | Jan 10 01:56:15 PM PST 24 |
| Finished | Jan 10 02:59:18 PM PST 24 |
| Peak memory | 602500 kb |
| Host | smart-03a4975a-0903-49c9-bb43-2e2f476930d3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=484559099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.484559099 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.3167577774 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 2869076376 ps |
| CPU time | 201.89 seconds |
| Started | Jan 10 01:54:01 PM PST 24 |
| Finished | Jan 10 01:57:25 PM PST 24 |
| Peak memory | 601788 kb |
| Host | smart-4eb0d7c3-9b3d-4463-9359-a3c96d3b50ed |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167577774 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3167577774 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.2947450139 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 2628256398 ps |
| CPU time | 151.16 seconds |
| Started | Jan 10 01:54:48 PM PST 24 |
| Finished | Jan 10 01:57:20 PM PST 24 |
| Peak memory | 600968 kb |
| Host | smart-1318ebc2-8e49-4da0-8e10-bcf79e9006cc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947450139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2947450139 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.3351095085 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 6910159532 ps |
| CPU time | 621.8 seconds |
| Started | Jan 10 01:56:19 PM PST 24 |
| Finished | Jan 10 02:06:42 PM PST 24 |
| Peak memory | 614328 kb |
| Host | smart-b8984227-be3b-4912-9030-f462d6bd07b0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351095085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.3351095085 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.2871265478 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 8640421294 ps |
| CPU time | 1677.98 seconds |
| Started | Jan 10 01:59:25 PM PST 24 |
| Finished | Jan 10 02:27:25 PM PST 24 |
| Peak memory | 602624 kb |
| Host | smart-437bb95f-b575-4744-b1f1-a926b80fb171 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871265478 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_asm_init_dev.2871265478 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.3442046375 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 8619266536 ps |
| CPU time | 1800.62 seconds |
| Started | Jan 10 01:58:31 PM PST 24 |
| Finished | Jan 10 02:28:33 PM PST 24 |
| Peak memory | 603252 kb |
| Host | smart-78360c3e-bc20-4281-9e55-4e77cfd9d45a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442046375 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.rom_e2e_asm_init_prod.3442046375 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.370187642 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 8525630910 ps |
| CPU time | 1552.7 seconds |
| Started | Jan 10 01:59:24 PM PST 24 |
| Finished | Jan 10 02:25:18 PM PST 24 |
| Peak memory | 602856 kb |
| Host | smart-06c02252-ead4-4498-9df5-982f85f3ce40 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370187642 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod_end.370187642 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.1614127223 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 8811840815 ps |
| CPU time | 1701.77 seconds |
| Started | Jan 10 01:59:12 PM PST 24 |
| Finished | Jan 10 02:27:35 PM PST 24 |
| Peak memory | 602944 kb |
| Host | smart-6472979f-a591-47be-8559-d4c44a212e81 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614127223 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.rom_e2e_asm_init_rma.1614127223 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2145971099 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 6773688581 ps |
| CPU time | 1293.73 seconds |
| Started | Jan 10 01:57:28 PM PST 24 |
| Finished | Jan 10 02:19:03 PM PST 24 |
| Peak memory | 602944 kb |
| Host | smart-5fa4307a-5996-465e-a933-ff6e8a71c53e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_ flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145971099 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_test_unlocked0.2145971099 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1531057680 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 12312840442 ps |
| CPU time | 2556.08 seconds |
| Started | Jan 10 01:59:16 PM PST 24 |
| Finished | Jan 10 02:41:55 PM PST 24 |
| Peak memory | 602360 kb |
| Host | smart-50a53316-5e2a-4b03-b034-29b3516d9ddb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod:4,rom_with _fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1531057680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1531057680 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2347901094 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 12145534344 ps |
| CPU time | 2494.64 seconds |
| Started | Jan 10 01:59:17 PM PST 24 |
| Finished | Jan 10 02:40:53 PM PST 24 |
| Peak memory | 602728 kb |
| Host | smart-e6e29d65-55c1-435d-bb77-a847a921a495 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2347901094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2347901094 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1127872303 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 11562307118 ps |
| CPU time | 2522.41 seconds |
| Started | Jan 10 02:00:40 PM PST 24 |
| Finished | Jan 10 02:42:44 PM PST 24 |
| Peak memory | 602380 kb |
| Host | smart-84de9fed-22bb-4f19-9cce-9b9a81dae4fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_rma:4,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127872303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1127872303 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4069274118 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 10156803664 ps |
| CPU time | 2026.3 seconds |
| Started | Jan 10 01:59:38 PM PST 24 |
| Finished | Jan 10 02:33:26 PM PST 24 |
| Peak memory | 602400 kb |
| Host | smart-88cea115-0d0f-47ce-b134-47bf01c4f35c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0 :4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4069274118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4069274118 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.904077101 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 8793265096 ps |
| CPU time | 1565.73 seconds |
| Started | Jan 10 01:59:28 PM PST 24 |
| Finished | Jan 10 02:25:36 PM PST 24 |
| Peak memory | 590512 kb |
| Host | smart-56d4620a-9dfd-4078-b5a3-e74f985f0a01 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_dev:4,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904077101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.904077101 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3598683741 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 7940328050 ps |
| CPU time | 1712.21 seconds |
| Started | Jan 10 01:59:24 PM PST 24 |
| Finished | Jan 10 02:27:59 PM PST 24 |
| Peak memory | 602740 kb |
| Host | smart-4bc9a704-b466-42f6-a994-3410118008e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod:4,rom_with _fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3598683741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3598683741 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4148083070 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 9107475900 ps |
| CPU time | 1650.85 seconds |
| Started | Jan 10 01:59:23 PM PST 24 |
| Finished | Jan 10 02:26:55 PM PST 24 |
| Peak memory | 602724 kb |
| Host | smart-2f81e2c2-5881-4e93-ba98-a9d31cefefa7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4148083070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4148083070 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.700973973 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 8293123736 ps |
| CPU time | 1633.8 seconds |
| Started | Jan 10 02:00:40 PM PST 24 |
| Finished | Jan 10 02:27:55 PM PST 24 |
| Peak memory | 590560 kb |
| Host | smart-033ba0d7-09dc-4eb2-8eab-e73363237e49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_rma:4,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700973973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.700973973 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.614801509 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 7234737300 ps |
| CPU time | 1268.01 seconds |
| Started | Jan 10 01:59:32 PM PST 24 |
| Finished | Jan 10 02:20:41 PM PST 24 |
| Peak memory | 602412 kb |
| Host | smart-5abb9e63-2246-424b-8265-05488860ba67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_b inary:signed:fake_rsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0 :4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=614801509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.614801509 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.766209476 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 8939361862 ps |
| CPU time | 1803.2 seconds |
| Started | Jan 10 01:59:39 PM PST 24 |
| Finished | Jan 10 02:29:44 PM PST 24 |
| Peak memory | 590520 kb |
| Host | smart-a354e6c6-fa31-48ad-95ed-54c4a625232b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_dev:4,rom_with_fake_keys: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=766209476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.766209476 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3069166605 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 8887969238 ps |
| CPU time | 1631.59 seconds |
| Started | Jan 10 02:00:54 PM PST 24 |
| Finished | Jan 10 02:28:07 PM PST 24 |
| Peak memory | 590500 kb |
| Host | smart-557485f7-55ea-4aee-bfa0-d9b32812e62a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod:4,rom_with_fake_keys :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3069166605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3069166605 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3293964587 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 9510125292 ps |
| CPU time | 1587.67 seconds |
| Started | Jan 10 01:58:47 PM PST 24 |
| Finished | Jan 10 02:25:25 PM PST 24 |
| Peak memory | 590528 kb |
| Host | smart-5b65a6fd-40db-43f7-8228-3103b84c4d5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,rom_with_fake_ keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3293964587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3293964587 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2149430765 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 8796509386 ps |
| CPU time | 1441.69 seconds |
| Started | Jan 10 01:59:18 PM PST 24 |
| Finished | Jan 10 02:23:21 PM PST 24 |
| Peak memory | 602468 kb |
| Host | smart-1ba3bdf7-6a12-44e1-bea1-ffdf2725fd7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bi nary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_rma:4,rom_with_fake_keys: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2149430765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2149430765 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.571867397 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6810093708 ps |
| CPU time | 1347.17 seconds |
| Started | Jan 10 02:00:16 PM PST 24 |
| Finished | Jan 10 02:22:47 PM PST 24 |
| Peak memory | 602560 kb |
| Host | smart-08057837-718d-4b1f-90fe-84cd389287c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_b inary:signed:fake_rsa_prod_key_0,empty_test_slot_b:2:ot_flash_binary:signed:fake_rsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4,rom_wit h_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=571867397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.571867397 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.4013661195 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 9137062642 ps |
| CPU time | 1675.45 seconds |
| Started | Jan 10 02:03:27 PM PST 24 |
| Finished | Jan 10 02:31:53 PM PST 24 |
| Peak memory | 603196 kb |
| Host | smart-db78e2a9-20fa-4b13-98e1-ba10ef71f469 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:signed:fake_rsa_test_key_0,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4013661195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_exception_c.4013661195 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.1618504348 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 21514702126 ps |
| CPU time | 2470.22 seconds |
| Started | Jan 10 01:59:29 PM PST 24 |
| Finished | Jan 10 02:40:41 PM PST 24 |
| Peak memory | 604652 kb |
| Host | smart-d67b1049-be75-4d53-9e8f-48c637e14638 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bina ry,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618504348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.rom_e2e_shutdown_output.1618504348 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.340045901 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 12149007390 ps |
| CPU time | 2280.56 seconds |
| Started | Jan 10 01:59:19 PM PST 24 |
| Finished | Jan 10 02:37:21 PM PST 24 |
| Peak memory | 590468 kb |
| Host | smart-48d917c4-7aeb-485e-8f7f-e200254bbfa9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sig verify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340045901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_ always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e _sigverify_always_a_bad_b_bad_prod.340045901 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2325844078 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 11634102136 ps |
| CPU time | 2565.26 seconds |
| Started | Jan 10 01:58:37 PM PST 24 |
| Finished | Jan 10 02:41:34 PM PST 24 |
| Peak memory | 590556 kb |
| Host | smart-9baca520-ae3f-4593-908b-223891904a23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sig verify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325844078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigve rify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ro m_e2e_sigverify_always_a_bad_b_bad_prod_end.2325844078 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.39666949 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 11702460942 ps |
| CPU time | 2427.12 seconds |
| Started | Jan 10 01:59:49 PM PST 24 |
| Finished | Jan 10 02:40:25 PM PST 24 |
| Peak memory | 590536 kb |
| Host | smart-fb6ddc35-fd06-43fe-bf4b-6e9ced060ed0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sig verify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39666949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_al ways_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_s igverify_always_a_bad_b_bad_rma.39666949 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3230241422 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 10220233202 ps |
| CPU time | 1882.29 seconds |
| Started | Jan 10 02:00:49 PM PST 24 |
| Finished | Jan 10 02:32:14 PM PST 24 |
| Peak memory | 603088 kb |
| Host | smart-60f16e1f-2b70-45dc-84ee-ed334c07e7cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_si gverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230241422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2 e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3230241422 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.223380087 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 8392421651 ps |
| CPU time | 1503.44 seconds |
| Started | Jan 10 02:00:04 PM PST 24 |
| Finished | Jan 10 02:25:15 PM PST 24 |
| Peak memory | 603384 kb |
| Host | smart-cddde2e6-4996-4af8-a18a-648f851e2254 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_dev_key_0:new_rules,otp_img_sigverify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223380087 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.223380087 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3569496747 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 8232574076 ps |
| CPU time | 1658.12 seconds |
| Started | Jan 10 01:59:17 PM PST 24 |
| Finished | Jan 10 02:26:57 PM PST 24 |
| Peak memory | 602992 kb |
| Host | smart-3b24c4ee-1ce8-4233-b1d2-903b1c46b3be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569496747 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3569496747 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.848983716 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 8534631466 ps |
| CPU time | 1475.38 seconds |
| Started | Jan 10 01:59:12 PM PST 24 |
| Finished | Jan 10 02:23:49 PM PST 24 |
| Peak memory | 603284 kb |
| Host | smart-35584edf-70ea-41b2-abc9-8e01c01cee47 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848983716 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.848983716 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1392488017 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 8514537064 ps |
| CPU time | 1864.03 seconds |
| Started | Jan 10 01:58:41 PM PST 24 |
| Finished | Jan 10 02:29:55 PM PST 24 |
| Peak memory | 603164 kb |
| Host | smart-c7547ea5-45ae-4f69-95fc-9aa54544698e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392488017 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1392488017 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.68221843 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 6936033452 ps |
| CPU time | 1297.98 seconds |
| Started | Jan 10 01:58:28 PM PST 24 |
| Finished | Jan 10 02:20:07 PM PST 24 |
| Peak memory | 603140 kb |
| Host | smart-f24fb70a-2899-4b50-9404-9f5fc4f75337 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68221843 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.68221843 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3796223930 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 8165324565 ps |
| CPU time | 1455.32 seconds |
| Started | Jan 10 01:59:03 PM PST 24 |
| Finished | Jan 10 02:23:19 PM PST 24 |
| Peak memory | 603476 kb |
| Host | smart-b4c38b1f-7eff-4ce4-b78c-0f11fc24e3ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o t_flash_binary:signed:fake_rsa_dev_key_0:new_rules,otp_img_sigverify_always_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796223930 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3796223930 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2843109345 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 8687765178 ps |
| CPU time | 1480.24 seconds |
| Started | Jan 10 02:00:23 PM PST 24 |
| Finished | Jan 10 02:25:05 PM PST 24 |
| Peak memory | 603164 kb |
| Host | smart-7f962b43-45c0-4faa-a35e-84e93dbb3747 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843109345 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2843109345 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2691495251 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 8850078047 ps |
| CPU time | 1406.64 seconds |
| Started | Jan 10 02:00:30 PM PST 24 |
| Finished | Jan 10 02:23:59 PM PST 24 |
| Peak memory | 603168 kb |
| Host | smart-f43e40e6-0bef-4bba-9fd0-c636ff8372f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691495251 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2691495251 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1349198991 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 8308082183 ps |
| CPU time | 1438.27 seconds |
| Started | Jan 10 02:00:53 PM PST 24 |
| Finished | Jan 10 02:24:53 PM PST 24 |
| Peak memory | 602944 kb |
| Host | smart-a69c3d5a-62ba-4ea1-8129-fdf45aa0e663 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1:o t_flash_binary:signed:fake_rsa_prod_key_0:new_rules,otp_img_sigverify_always_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349198991 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1349198991 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2077115620 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 7565167014 ps |
| CPU time | 1207.82 seconds |
| Started | Jan 10 01:59:54 PM PST 24 |
| Finished | Jan 10 02:20:07 PM PST 24 |
| Peak memory | 603360 kb |
| Host | smart-086d95f7-83c1-4fc5-a235-6fe3ee4e1d50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_rsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077115620 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2077115620 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.628678369 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 8561855134 ps |
| CPU time | 1904.05 seconds |
| Started | Jan 10 01:59:56 PM PST 24 |
| Finished | Jan 10 02:31:50 PM PST 24 |
| Peak memory | 602452 kb |
| Host | smart-9861211b-d4a1-4c64-b7e8-0cc8140ea5a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_binary:signed:fake_rsa_test_key_0 ,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=628678369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.628678369 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.1396323207 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 10995039160 ps |
| CPU time | 2147.32 seconds |
| Started | Jan 10 01:58:51 PM PST 24 |
| Finished | Jan 10 02:34:46 PM PST 24 |
| Peak memory | 602972 kb |
| Host | smart-e40077a8-36df-44bf-84eb-b0262b5c7f80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:signed:fake_rsa_test_key_0,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396323207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.1396323207 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.2130932308 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 4130959720 ps |
| CPU time | 446.95 seconds |
| Started | Jan 10 01:59:31 PM PST 24 |
| Finished | Jan 10 02:06:59 PM PST 24 |
| Peak memory | 603192 kb |
| Host | smart-7754c0ce-4bc4-4e12-887a-6f2a94315669 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130932308 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.2130932308 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.2059570620 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 9100987035 ps |
| CPU time | 1449.37 seconds |
| Started | Jan 10 01:57:45 PM PST 24 |
| Finished | Jan 10 02:21:56 PM PST 24 |
| Peak memory | 608832 kb |
| Host | smart-b6181905-d64a-40e3-85a3-89fd9c08b3d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059570620 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.2059570620 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.4049336720 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 11066584482 ps |
| CPU time | 1117.9 seconds |
| Started | Jan 10 01:48:50 PM PST 24 |
| Finished | Jan 10 02:07:40 PM PST 24 |
| Peak memory | 587772 kb |
| Host | smart-7f0b9057-ff6f-443c-ae34-f5018c77faf7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049336720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.4049336720 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.1292651573 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 13781822385 ps |
| CPU time | 1502.76 seconds |
| Started | Jan 10 01:48:35 PM PST 24 |
| Finished | Jan 10 02:13:39 PM PST 24 |
| Peak memory | 587708 kb |
| Host | smart-52857f21-4919-4917-a30c-067b5d85a43f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292651573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.1 292651573 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2424546707 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3753732640 ps |
| CPU time | 399.57 seconds |
| Started | Jan 10 01:56:10 PM PST 24 |
| Finished | Jan 10 02:02:51 PM PST 24 |
| Peak memory | 617176 kb |
| Host | smart-6ee0f5ce-3ac2-424d-a954-dc67dfce5ed4 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 424546707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2424546707 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.4213672527 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 3678279846 ps |
| CPU time | 533.73 seconds |
| Started | Jan 10 02:03:08 PM PST 24 |
| Finished | Jan 10 02:12:25 PM PST 24 |
| Peak memory | 602636 kb |
| Host | smart-ce229388-fcf4-472a-ac16-4992573cfebf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4213672527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.4213672527 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3038762813 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 17983149080 ps |
| CPU time | 506.6 seconds |
| Started | Jan 10 01:55:49 PM PST 24 |
| Finished | Jan 10 02:04:18 PM PST 24 |
| Peak memory | 616516 kb |
| Host | smart-abd8ccf3-d003-46b0-85fa-88766e87a707 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3038762813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3038762813 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.580780357 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 2727465906 ps |
| CPU time | 254.73 seconds |
| Started | Jan 10 01:59:38 PM PST 24 |
| Finished | Jan 10 02:03:54 PM PST 24 |
| Peak memory | 601864 kb |
| Host | smart-700e563f-09c3-4227-83d8-824a393181aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580780357 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.580780357 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2965646633 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2837555477 ps |
| CPU time | 244.64 seconds |
| Started | Jan 10 01:59:34 PM PST 24 |
| Finished | Jan 10 02:03:40 PM PST 24 |
| Peak memory | 602440 kb |
| Host | smart-21af35b6-cf42-4acd-a68e-842db2f1918d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965646633 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2965646633 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1355095961 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 3158875819 ps |
| CPU time | 263.03 seconds |
| Started | Jan 10 02:01:29 PM PST 24 |
| Finished | Jan 10 02:05:58 PM PST 24 |
| Peak memory | 602336 kb |
| Host | smart-b6642e07-20f8-420c-b5bc-e8bb51a55ae7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1355095961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.1355095961 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.3292254792 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2306539200 ps |
| CPU time | 303.47 seconds |
| Started | Jan 10 01:56:35 PM PST 24 |
| Finished | Jan 10 02:01:51 PM PST 24 |
| Peak memory | 602440 kb |
| Host | smart-357206f9-38f5-44bb-a73b-c2f8da6b9555 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292254792 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.3292254792 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.1899605308 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2454231840 ps |
| CPU time | 200.71 seconds |
| Started | Jan 10 01:56:22 PM PST 24 |
| Finished | Jan 10 01:59:44 PM PST 24 |
| Peak memory | 590280 kb |
| Host | smart-979bba5a-6b49-4e3b-a758-ea8940a167c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899605308 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1899605308 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.2991702871 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 3450420647 ps |
| CPU time | 266.57 seconds |
| Started | Jan 10 01:59:32 PM PST 24 |
| Finished | Jan 10 02:03:59 PM PST 24 |
| Peak memory | 603040 kb |
| Host | smart-f3426383-a143-4603-a4a3-d42b41c6b208 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991702871 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.2991702871 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.1269352856 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3136697768 ps |
| CPU time | 235.74 seconds |
| Started | Jan 10 02:03:40 PM PST 24 |
| Finished | Jan 10 02:07:56 PM PST 24 |
| Peak memory | 602316 kb |
| Host | smart-ca0957ee-79e9-4329-9d08-069351679d80 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269352856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.1269352856 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3181836971 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3986943687 ps |
| CPU time | 336.38 seconds |
| Started | Jan 10 01:55:55 PM PST 24 |
| Finished | Jan 10 02:01:33 PM PST 24 |
| Peak memory | 591044 kb |
| Host | smart-c4f9bb6d-e10d-4523-8061-5ad3e44ab332 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3181836971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3181836971 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3094361246 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 6333288048 ps |
| CPU time | 578.67 seconds |
| Started | Jan 10 01:55:18 PM PST 24 |
| Finished | Jan 10 02:04:58 PM PST 24 |
| Peak memory | 608712 kb |
| Host | smart-325255f4-dcbe-4ce2-9f51-8d011c8f070c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3094361246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.3094361246 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1904124322 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5890443796 ps |
| CPU time | 801.21 seconds |
| Started | Jan 10 01:55:33 PM PST 24 |
| Finished | Jan 10 02:08:56 PM PST 24 |
| Peak memory | 602524 kb |
| Host | smart-9275a5fc-ece3-4e7f-9ef8-7e81a1a53a0e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1904124322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.1904124322 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3412850532 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 7264711864 ps |
| CPU time | 1232.37 seconds |
| Started | Jan 10 01:54:53 PM PST 24 |
| Finished | Jan 10 02:15:36 PM PST 24 |
| Peak memory | 602916 kb |
| Host | smart-16377236-f819-494d-bf90-82bede7cb66c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412850532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.3412850532 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3271092405 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3755932888 ps |
| CPU time | 374.83 seconds |
| Started | Jan 10 01:54:55 PM PST 24 |
| Finished | Jan 10 02:01:19 PM PST 24 |
| Peak memory | 633348 kb |
| Host | smart-58dd6d76-7b8d-40e8-ad9d-85854d30ad25 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271092405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.3271092405 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2825677295 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 9283537180 ps |
| CPU time | 1017.8 seconds |
| Started | Jan 10 01:56:38 PM PST 24 |
| Finished | Jan 10 02:13:45 PM PST 24 |
| Peak memory | 603264 kb |
| Host | smart-57c4770e-8266-43b0-be9b-eb01972de6ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825677295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.2825677295 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3562007380 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3499841708 ps |
| CPU time | 366.59 seconds |
| Started | Jan 10 01:57:38 PM PST 24 |
| Finished | Jan 10 02:03:45 PM PST 24 |
| Peak memory | 602688 kb |
| Host | smart-2a452a54-f886-4d9e-b52f-647130a943ef |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3562007380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.3562007380 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2895097425 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 255151720460 ps |
| CPU time | 10569.6 seconds |
| Started | Jan 10 01:55:28 PM PST 24 |
| Finished | Jan 10 04:51:44 PM PST 24 |
| Peak memory | 603020 kb |
| Host | smart-47ea8460-c93e-4ef7-aa4f-af692eb71387 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895097425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2895097425 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.1800663602 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3584929900 ps |
| CPU time | 304.9 seconds |
| Started | Jan 10 01:56:31 PM PST 24 |
| Finished | Jan 10 02:01:38 PM PST 24 |
| Peak memory | 602768 kb |
| Host | smart-c6657b6f-4af5-492c-8aa8-012a7f232da0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800663602 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.1800663602 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.21659062 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3868027144 ps |
| CPU time | 373.06 seconds |
| Started | Jan 10 01:57:27 PM PST 24 |
| Finished | Jan 10 02:03:41 PM PST 24 |
| Peak memory | 602348 kb |
| Host | smart-a2868a15-7c24-40b3-929d-3a9d26171208 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21659062 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.21659062 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3772817436 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 7780062394 ps |
| CPU time | 489.84 seconds |
| Started | Jan 10 01:56:14 PM PST 24 |
| Finished | Jan 10 02:04:25 PM PST 24 |
| Peak memory | 590408 kb |
| Host | smart-b5d31f8f-3f11-49e2-8e05-8e7c45ad1922 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3772817436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3772817436 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1815381207 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 3290480304 ps |
| CPU time | 325.62 seconds |
| Started | Jan 10 01:59:14 PM PST 24 |
| Finished | Jan 10 02:04:42 PM PST 24 |
| Peak memory | 602384 kb |
| Host | smart-322c1aa5-14dc-49b1-af47-56521aa331e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815381207 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.1815381207 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1736197689 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 6076670232 ps |
| CPU time | 602.1 seconds |
| Started | Jan 10 01:59:56 PM PST 24 |
| Finished | Jan 10 02:10:08 PM PST 24 |
| Peak memory | 603268 kb |
| Host | smart-d1e94b0b-f910-4db7-921c-a46730d4d285 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1736197689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1736197689 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1106267011 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 4391271000 ps |
| CPU time | 677.75 seconds |
| Started | Jan 10 01:56:50 PM PST 24 |
| Finished | Jan 10 02:08:11 PM PST 24 |
| Peak memory | 603116 kb |
| Host | smart-6ecc23cd-be83-42d3-8a3e-3bd3674265fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1106267011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1106267011 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3263970644 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 7145495114 ps |
| CPU time | 925.94 seconds |
| Started | Jan 10 02:01:18 PM PST 24 |
| Finished | Jan 10 02:16:52 PM PST 24 |
| Peak memory | 609340 kb |
| Host | smart-3c012625-aece-4718-ac34-efff6d87a9ed |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263970644 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3263970644 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3499282321 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 12139869593 ps |
| CPU time | 612.69 seconds |
| Started | Jan 10 01:57:59 PM PST 24 |
| Finished | Jan 10 02:08:27 PM PST 24 |
| Peak memory | 603740 kb |
| Host | smart-8c78ef9e-0740-48f9-8446-630fe4aa69ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499282321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.3499282321 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2311250275 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 4305347324 ps |
| CPU time | 610.34 seconds |
| Started | Jan 10 01:57:22 PM PST 24 |
| Finished | Jan 10 02:07:33 PM PST 24 |
| Peak memory | 594304 kb |
| Host | smart-3a291357-9a2a-4f6e-af95-64115734afac |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311250275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2311250275 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.918382291 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 3707578104 ps |
| CPU time | 515.3 seconds |
| Started | Jan 10 02:00:34 PM PST 24 |
| Finished | Jan 10 02:09:11 PM PST 24 |
| Peak memory | 594320 kb |
| Host | smart-3843169e-8118-463d-a741-30266bf779ac |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918382291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.918382291 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.301702402 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3761962692 ps |
| CPU time | 604.14 seconds |
| Started | Jan 10 02:01:58 PM PST 24 |
| Finished | Jan 10 02:12:05 PM PST 24 |
| Peak memory | 594328 kb |
| Host | smart-464c8643-725c-4733-92a3-602ad7a53864 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301702402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.301702402 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3944155223 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 5030988326 ps |
| CPU time | 554.29 seconds |
| Started | Jan 10 01:57:00 PM PST 24 |
| Finished | Jan 10 02:06:16 PM PST 24 |
| Peak memory | 595204 kb |
| Host | smart-b687e499-be72-4a33-ac64-94f9500e31a3 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944155223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3944155223 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2543338585 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 4322595284 ps |
| CPU time | 551.81 seconds |
| Started | Jan 10 01:59:52 PM PST 24 |
| Finished | Jan 10 02:09:10 PM PST 24 |
| Peak memory | 595312 kb |
| Host | smart-3280ad75-e692-4133-88bc-c09c6a8b0d03 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543338585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2543338585 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1629085254 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 5353521710 ps |
| CPU time | 647.25 seconds |
| Started | Jan 10 02:00:34 PM PST 24 |
| Finished | Jan 10 02:11:23 PM PST 24 |
| Peak memory | 594320 kb |
| Host | smart-edf4d6b5-9da0-4112-9b79-70e5b67a0b61 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629085254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1629085254 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2404583025 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2641748797 ps |
| CPU time | 272.87 seconds |
| Started | Jan 10 01:58:26 PM PST 24 |
| Finished | Jan 10 02:03:02 PM PST 24 |
| Peak memory | 601992 kb |
| Host | smart-b327dbb4-c6eb-4b15-8e9e-603015522ee8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404583025 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.2404583025 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1974412857 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 3443568040 ps |
| CPU time | 465.8 seconds |
| Started | Jan 10 02:01:18 PM PST 24 |
| Finished | Jan 10 02:09:12 PM PST 24 |
| Peak memory | 602064 kb |
| Host | smart-9551c2c1-9d6b-443e-94ad-93fed80a1360 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974412857 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1974412857 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2990680393 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 2571480706 ps |
| CPU time | 244.51 seconds |
| Started | Jan 10 01:56:07 PM PST 24 |
| Finished | Jan 10 02:00:12 PM PST 24 |
| Peak memory | 602340 kb |
| Host | smart-9f53648e-2d5c-4125-9078-d6b199535b69 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990680393 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.2990680393 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1064474818 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 3773122456 ps |
| CPU time | 468.67 seconds |
| Started | Jan 10 01:55:27 PM PST 24 |
| Finished | Jan 10 02:03:21 PM PST 24 |
| Peak memory | 602920 kb |
| Host | smart-843fafde-9bf3-462f-9c44-d5d62081c583 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064474818 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1064474818 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2895950540 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 5289833252 ps |
| CPU time | 337.27 seconds |
| Started | Jan 10 01:56:59 PM PST 24 |
| Finished | Jan 10 02:02:37 PM PST 24 |
| Peak memory | 602812 kb |
| Host | smart-b49606fb-bbb9-4edd-8e68-184c8fe27274 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895950540 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2895950540 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2903527593 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 5523178112 ps |
| CPU time | 435.5 seconds |
| Started | Jan 10 02:02:23 PM PST 24 |
| Finished | Jan 10 02:09:50 PM PST 24 |
| Peak memory | 603192 kb |
| Host | smart-9288a77e-0224-4cd6-86b6-403e9e609744 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903527593 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.2903527593 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2021355129 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 5099381848 ps |
| CPU time | 509.94 seconds |
| Started | Jan 10 01:56:43 PM PST 24 |
| Finished | Jan 10 02:05:18 PM PST 24 |
| Peak memory | 603244 kb |
| Host | smart-6db9f96c-4b77-48ae-a1a9-12188113038d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021355129 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2021355129 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3757331531 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 12161173600 ps |
| CPU time | 1279.03 seconds |
| Started | Jan 10 01:56:45 PM PST 24 |
| Finished | Jan 10 02:18:08 PM PST 24 |
| Peak memory | 603332 kb |
| Host | smart-b1d78c52-70a4-412b-ba42-344427f3483a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757331531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.3757331531 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2124455624 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 3728762220 ps |
| CPU time | 442.28 seconds |
| Started | Jan 10 02:01:18 PM PST 24 |
| Finished | Jan 10 02:08:49 PM PST 24 |
| Peak memory | 602472 kb |
| Host | smart-f6939e38-18cc-403c-8587-53f520e24c4a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124455624 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2124455624 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1175069104 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 4701659600 ps |
| CPU time | 651.72 seconds |
| Started | Jan 10 02:01:16 PM PST 24 |
| Finished | Jan 10 02:12:18 PM PST 24 |
| Peak memory | 602484 kb |
| Host | smart-bbc97ffc-ef39-452f-b7ae-dce336c99e3f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175069104 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1175069104 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1392101940 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 2397534616 ps |
| CPU time | 250.49 seconds |
| Started | Jan 10 02:01:45 PM PST 24 |
| Finished | Jan 10 02:06:00 PM PST 24 |
| Peak memory | 602320 kb |
| Host | smart-43c92400-e21d-4b59-ac66-0da671baac0b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392101940 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1392101940 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3102196060 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 18145879108 ps |
| CPU time | 3753.13 seconds |
| Started | Jan 10 01:59:06 PM PST 24 |
| Finished | Jan 10 03:01:41 PM PST 24 |
| Peak memory | 603008 kb |
| Host | smart-442ee551-4047-46c7-9ee0-03cc64e9d09b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102196060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.3102196060 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3141691228 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 11449330442 ps |
| CPU time | 1870.55 seconds |
| Started | Jan 10 01:58:26 PM PST 24 |
| Finished | Jan 10 02:29:38 PM PST 24 |
| Peak memory | 602936 kb |
| Host | smart-5d28032f-84ca-4389-85f3-37b3f434a98f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=180_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141691228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _csrng_edn_concurrency_reduced_freq.3141691228 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2403804662 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 4827621692 ps |
| CPU time | 627.06 seconds |
| Started | Jan 10 01:55:15 PM PST 24 |
| Finished | Jan 10 02:05:44 PM PST 24 |
| Peak memory | 603540 kb |
| Host | smart-99b25577-8079-4637-a708-f0a2df0b8e1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24038 04662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.2403804662 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.797334494 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 2301622224 ps |
| CPU time | 215.29 seconds |
| Started | Jan 10 01:55:14 PM PST 24 |
| Finished | Jan 10 01:58:50 PM PST 24 |
| Peak memory | 602536 kb |
| Host | smart-7be58394-79c7-4725-8c4f-4a3fb66191a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797334494 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.797334494 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.598124367 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 6116164504 ps |
| CPU time | 674.3 seconds |
| Started | Jan 10 01:55:51 PM PST 24 |
| Finished | Jan 10 02:07:06 PM PST 24 |
| Peak memory | 603756 kb |
| Host | smart-e90b2d1b-bacd-46cb-9008-fa5a4adcfa81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598124367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrn g_lc_hw_debug_en_test.598124367 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.3474618178 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2811023214 ps |
| CPU time | 211.47 seconds |
| Started | Jan 10 02:00:46 PM PST 24 |
| Finished | Jan 10 02:04:20 PM PST 24 |
| Peak memory | 602328 kb |
| Host | smart-4bf6dd63-9837-4ef1-ad3d-f692827e2ea1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474618178 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.3474618178 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1323306705 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 5483082486 ps |
| CPU time | 618.56 seconds |
| Started | Jan 10 02:03:05 PM PST 24 |
| Finished | Jan 10 02:13:45 PM PST 24 |
| Peak memory | 603836 kb |
| Host | smart-609d999e-577a-4edf-bf8a-1be52aacb608 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1323306705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1323306705 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.1269684112 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 3609725512 ps |
| CPU time | 655.84 seconds |
| Started | Jan 10 01:57:13 PM PST 24 |
| Finished | Jan 10 02:08:10 PM PST 24 |
| Peak memory | 602584 kb |
| Host | smart-be74c2ec-2fb6-4a8d-959f-ccf5cbe7d56a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269684112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.1269684112 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.996838521 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2934821256 ps |
| CPU time | 610.14 seconds |
| Started | Jan 10 01:57:14 PM PST 24 |
| Finished | Jan 10 02:07:26 PM PST 24 |
| Peak memory | 602788 kb |
| Host | smart-d5a9c267-0c2c-4cd9-94a5-23e15f3a623d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996838521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.996838521 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2915511435 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 4681081045 ps |
| CPU time | 601.68 seconds |
| Started | Jan 10 01:55:39 PM PST 24 |
| Finished | Jan 10 02:05:42 PM PST 24 |
| Peak memory | 603192 kb |
| Host | smart-e8d8b4c9-27b0-49f4-a2f4-409717ad25ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915511435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.2915511435 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3119663491 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 2908174808 ps |
| CPU time | 572.3 seconds |
| Started | Jan 10 01:56:40 PM PST 24 |
| Finished | Jan 10 02:06:20 PM PST 24 |
| Peak memory | 608812 kb |
| Host | smart-b14554a0-c77d-433b-9122-4bff0f766f05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119663491 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3119663491 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.3498692174 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 7303693200 ps |
| CPU time | 1300.56 seconds |
| Started | Jan 10 01:55:44 PM PST 24 |
| Finished | Jan 10 02:17:26 PM PST 24 |
| Peak memory | 602280 kb |
| Host | smart-00396c42-17fe-4705-b49c-4b1d263ad840 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498692174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.3498692174 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.108321152 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 3027635328 ps |
| CPU time | 297.39 seconds |
| Started | Jan 10 01:59:54 PM PST 24 |
| Finished | Jan 10 02:04:57 PM PST 24 |
| Peak memory | 602404 kb |
| Host | smart-3b131bd1-2be4-4e61-9ea9-d85c2b8fe7c8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10 8321152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.108321152 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3975163593 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 7862627922 ps |
| CPU time | 1424.7 seconds |
| Started | Jan 10 01:56:42 PM PST 24 |
| Finished | Jan 10 02:20:32 PM PST 24 |
| Peak memory | 603044 kb |
| Host | smart-c3732760-5ed2-4773-b0df-7412d14e6f6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3975163593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3975163593 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_fuse_en_fw_read_test.1130527470 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 4865362616 ps |
| CPU time | 694.98 seconds |
| Started | Jan 10 01:56:37 PM PST 24 |
| Finished | Jan 10 02:08:23 PM PST 24 |
| Peak memory | 603516 kb |
| Host | smart-b63f5349-1611-45bd-9d32-962af99c3b17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18000000 +sw_build_device=sim_dv +sw_images=entropy_src_fuse_en_fw_read_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1130527470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_fuse_en_fw_read_test.1130527470 |
| Directory | /workspace/1.chip_sw_entropy_src_fuse_en_fw_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.904370731 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 2672292760 ps |
| CPU time | 261.8 seconds |
| Started | Jan 10 01:56:20 PM PST 24 |
| Finished | Jan 10 02:00:44 PM PST 24 |
| Peak memory | 602032 kb |
| Host | smart-6e025994-d514-4d0b-9e06-cf6b33ea9fda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904370731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.904370731 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3114938078 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 3883018472 ps |
| CPU time | 355.66 seconds |
| Started | Jan 10 01:59:37 PM PST 24 |
| Finished | Jan 10 02:05:34 PM PST 24 |
| Peak memory | 602380 kb |
| Host | smart-8bb36cd7-4599-45af-bbc3-7f31005d33f1 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3114938078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.3114938078 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.1769556900 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 3285299610 ps |
| CPU time | 319.09 seconds |
| Started | Jan 10 01:59:29 PM PST 24 |
| Finished | Jan 10 02:04:50 PM PST 24 |
| Peak memory | 602468 kb |
| Host | smart-b68e6c36-cd56-41f2-a676-b6dd6e488591 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769556900 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.1769556900 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.3864120678 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 3207333754 ps |
| CPU time | 239.21 seconds |
| Started | Jan 10 01:59:00 PM PST 24 |
| Finished | Jan 10 02:03:02 PM PST 24 |
| Peak memory | 602404 kb |
| Host | smart-a9fc57b1-5680-4de1-b53e-0ec8224d127f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864120678 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.3864120678 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.2342047020 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2251009122 ps |
| CPU time | 199.35 seconds |
| Started | Jan 10 02:00:21 PM PST 24 |
| Finished | Jan 10 02:03:43 PM PST 24 |
| Peak memory | 602308 kb |
| Host | smart-2bd99f1b-cdaf-4b03-9f53-87c811aba7c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342047020 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.2342047020 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.42822993 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2010707224 ps |
| CPU time | 108.9 seconds |
| Started | Jan 10 02:01:35 PM PST 24 |
| Finished | Jan 10 02:03:26 PM PST 24 |
| Peak memory | 601716 kb |
| Host | smart-fa3a2ad0-ee55-41f7-aef0-c7bda2fe6540 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42822993 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_example_rom.42822993 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1074127285 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 61811746040 ps |
| CPU time | 9988.45 seconds |
| Started | Jan 10 01:59:41 PM PST 24 |
| Finished | Jan 10 04:46:11 PM PST 24 |
| Peak memory | 616980 kb |
| Host | smart-7bc2d2bd-04af-4dbd-b0a6-c0495b397a6c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1074127285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.1074127285 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.3487918110 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 5266606150 ps |
| CPU time | 549.82 seconds |
| Started | Jan 10 01:58:19 PM PST 24 |
| Finished | Jan 10 02:07:30 PM PST 24 |
| Peak memory | 604016 kb |
| Host | smart-923fe896-d352-4e3c-b54c-1cc668b0cbe0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3487918110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3487918110 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1752659236 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 6031173208 ps |
| CPU time | 949.93 seconds |
| Started | Jan 10 02:01:42 PM PST 24 |
| Finished | Jan 10 02:17:35 PM PST 24 |
| Peak memory | 602824 kb |
| Host | smart-73f82dce-90fd-4dac-8289-b1d0ed300864 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752659236 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.1752659236 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2725812330 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 5474695729 ps |
| CPU time | 864.24 seconds |
| Started | Jan 10 02:02:00 PM PST 24 |
| Finished | Jan 10 02:16:27 PM PST 24 |
| Peak memory | 602472 kb |
| Host | smart-c6f99ad5-bfe8-4db6-876f-bf5fd7c10406 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725812330 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.2725812330 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3284874036 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 7940678755 ps |
| CPU time | 1031.79 seconds |
| Started | Jan 10 01:57:00 PM PST 24 |
| Finished | Jan 10 02:14:13 PM PST 24 |
| Peak memory | 602872 kb |
| Host | smart-d7829094-0663-4458-ba57-b87537a43698 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284874036 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3284874036 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.317171305 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 6128652705 ps |
| CPU time | 937.96 seconds |
| Started | Jan 10 01:56:47 PM PST 24 |
| Finished | Jan 10 02:12:30 PM PST 24 |
| Peak memory | 602728 kb |
| Host | smart-29fff110-d216-40b5-bd19-1c8172b614f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317171305 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.317171305 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2196023310 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 2789930664 ps |
| CPU time | 399.9 seconds |
| Started | Jan 10 01:56:54 PM PST 24 |
| Finished | Jan 10 02:03:35 PM PST 24 |
| Peak memory | 602188 kb |
| Host | smart-9c6528a5-198e-4ad9-823b-22a8c7199fa1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196023310 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.2196023310 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1278892407 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 4238039608 ps |
| CPU time | 751.59 seconds |
| Started | Jan 10 01:54:43 PM PST 24 |
| Finished | Jan 10 02:07:15 PM PST 24 |
| Peak memory | 602236 kb |
| Host | smart-28640366-782e-4bc2-9f13-7a024ffcaad9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278892407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1278892407 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2183408082 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5091831854 ps |
| CPU time | 843.57 seconds |
| Started | Jan 10 01:55:54 PM PST 24 |
| Finished | Jan 10 02:09:59 PM PST 24 |
| Peak memory | 602532 kb |
| Host | smart-0de5c177-b25a-4c55-a147-3c3257a4c949 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2183408082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2183408082 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.389978946 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 6722171307 ps |
| CPU time | 995.27 seconds |
| Started | Jan 10 01:56:57 PM PST 24 |
| Finished | Jan 10 02:13:33 PM PST 24 |
| Peak memory | 602900 kb |
| Host | smart-b542c350-6936-43e4-abac-ff184e913e6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=389978946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.389978946 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.3611521189 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 17223509742 ps |
| CPU time | 1848.13 seconds |
| Started | Jan 10 01:55:42 PM PST 24 |
| Finished | Jan 10 02:26:33 PM PST 24 |
| Peak memory | 603204 kb |
| Host | smart-d62b9c62-4bb8-4e88-8c1a-dd9d6d22caf5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611521189 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3611521189 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1387943147 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 2540335710 ps |
| CPU time | 163.16 seconds |
| Started | Jan 10 02:01:37 PM PST 24 |
| Finished | Jan 10 02:04:23 PM PST 24 |
| Peak memory | 601952 kb |
| Host | smart-9cfb6f33-d2bc-42b3-9813-375a99b050fc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1387943147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.1387943147 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.3292735295 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3347758920 ps |
| CPU time | 406.58 seconds |
| Started | Jan 10 02:03:03 PM PST 24 |
| Finished | Jan 10 02:10:11 PM PST 24 |
| Peak memory | 603040 kb |
| Host | smart-f22ea35f-e3c9-4db4-a1e3-31d7183f0475 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292735295 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.3292735295 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.1789882757 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 2369566991 ps |
| CPU time | 210.63 seconds |
| Started | Jan 10 02:00:19 PM PST 24 |
| Finished | Jan 10 02:03:52 PM PST 24 |
| Peak memory | 602668 kb |
| Host | smart-97f42014-7807-42c8-a86a-0dc34d33aef1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789882757 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.1789882757 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.586378965 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 2738983570 ps |
| CPU time | 246.44 seconds |
| Started | Jan 10 01:55:13 PM PST 24 |
| Finished | Jan 10 01:59:21 PM PST 24 |
| Peak memory | 602452 kb |
| Host | smart-5b611264-b1a0-4037-8cd2-f347916b1316 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586378965 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.586378965 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.444654451 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 2670275780 ps |
| CPU time | 256.86 seconds |
| Started | Jan 10 01:56:08 PM PST 24 |
| Finished | Jan 10 02:00:26 PM PST 24 |
| Peak memory | 602140 kb |
| Host | smart-1986f84d-41a5-4862-942e-d03a9007ac72 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444654451 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_hmac_enc_idle.444654451 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.745119737 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3278761898 ps |
| CPU time | 295.4 seconds |
| Started | Jan 10 02:02:24 PM PST 24 |
| Finished | Jan 10 02:07:30 PM PST 24 |
| Peak memory | 602132 kb |
| Host | smart-a116b8cd-e0f0-4ec7-94c0-75dbf9a551f2 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745119737 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.745119737 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2684381940 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3360780514 ps |
| CPU time | 250.79 seconds |
| Started | Jan 10 01:56:52 PM PST 24 |
| Finished | Jan 10 02:01:04 PM PST 24 |
| Peak memory | 602480 kb |
| Host | smart-8f8e7ef8-f4ce-44cb-bf80-1ecd20b0e1f5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684381940 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.2684381940 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.4056803888 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 2785857932 ps |
| CPU time | 377.86 seconds |
| Started | Jan 10 02:02:48 PM PST 24 |
| Finished | Jan 10 02:09:39 PM PST 24 |
| Peak memory | 602396 kb |
| Host | smart-397a3c99-790b-4ca7-a503-c6d85b6c0617 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056803888 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.4056803888 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3932526909 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4050572922 ps |
| CPU time | 640.68 seconds |
| Started | Jan 10 02:00:34 PM PST 24 |
| Finished | Jan 10 02:11:16 PM PST 24 |
| Peak memory | 603616 kb |
| Host | smart-99271bbb-0305-418c-9e3a-750b7cf97e73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932526909 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.3932526909 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3331986173 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 4155012080 ps |
| CPU time | 640.76 seconds |
| Started | Jan 10 02:00:21 PM PST 24 |
| Finished | Jan 10 02:11:03 PM PST 24 |
| Peak memory | 602344 kb |
| Host | smart-1e22629e-8c05-4ba3-9e19-e93cbe3817a8 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331986173 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.3331986173 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2941571929 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 5332074792 ps |
| CPU time | 790.8 seconds |
| Started | Jan 10 01:57:22 PM PST 24 |
| Finished | Jan 10 02:10:34 PM PST 24 |
| Peak memory | 602896 kb |
| Host | smart-f9d787ff-0e9f-40ec-aa5c-7ac815983dd1 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941571929 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.2941571929 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1579459425 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 5593126368 ps |
| CPU time | 860.42 seconds |
| Started | Jan 10 02:03:09 PM PST 24 |
| Finished | Jan 10 02:17:52 PM PST 24 |
| Peak memory | 602916 kb |
| Host | smart-303423bd-33ae-4b64-ba57-956faa7e4da8 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579459425 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1579459425 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.588486874 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 67185880102 ps |
| CPU time | 10941.7 seconds |
| Started | Jan 10 01:59:54 PM PST 24 |
| Finished | Jan 10 05:02:23 PM PST 24 |
| Peak memory | 617520 kb |
| Host | smart-53c31df7-7e4e-4690-bb77-5fd4754ad867 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=588486874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.588486874 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2397496814 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 4177481608 ps |
| CPU time | 497.68 seconds |
| Started | Jan 10 01:55:36 PM PST 24 |
| Finished | Jan 10 02:03:54 PM PST 24 |
| Peak memory | 610024 kb |
| Host | smart-68ede907-e5e6-473f-ae41-704458591ee5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397 496814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.2397496814 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.515756867 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 4309465489 ps |
| CPU time | 392.7 seconds |
| Started | Jan 10 01:56:48 PM PST 24 |
| Finished | Jan 10 02:03:25 PM PST 24 |
| Peak memory | 610676 kb |
| Host | smart-da4fe47f-6547-4f4e-a370-6c91535eba53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=515756867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.515756867 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.409304070 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3568921477 ps |
| CPU time | 361.79 seconds |
| Started | Jan 10 01:58:03 PM PST 24 |
| Finished | Jan 10 02:04:16 PM PST 24 |
| Peak memory | 610380 kb |
| Host | smart-c410c558-fbe1-4b6b-89e5-cf842a56d2a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=409304070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.409304070 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2991066942 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 4413464000 ps |
| CPU time | 604.56 seconds |
| Started | Jan 10 01:55:50 PM PST 24 |
| Finished | Jan 10 02:05:56 PM PST 24 |
| Peak memory | 610020 kb |
| Host | smart-05778698-4a55-4c38-9e0e-8504042b6127 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2991066942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2991066942 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1636684123 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 5096355524 ps |
| CPU time | 499.1 seconds |
| Started | Jan 10 01:55:47 PM PST 24 |
| Finished | Jan 10 02:04:08 PM PST 24 |
| Peak memory | 604040 kb |
| Host | smart-c26c50c9-51d8-4bc4-982d-fb951ec5a9eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163668 4123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1636684123 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1209888653 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 3912441972 ps |
| CPU time | 541.85 seconds |
| Started | Jan 10 02:01:58 PM PST 24 |
| Finished | Jan 10 02:11:03 PM PST 24 |
| Peak memory | 591744 kb |
| Host | smart-5e48f71d-b084-4d75-bec5-9d9480142d40 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12098 88653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1209888653 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1031830409 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 13974518288 ps |
| CPU time | 3211.58 seconds |
| Started | Jan 10 01:55:30 PM PST 24 |
| Finished | Jan 10 02:49:06 PM PST 24 |
| Peak memory | 603652 kb |
| Host | smart-9006f92e-8eaf-4d74-b276-1011f552f1ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10318 30409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.1031830409 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2946570538 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2383637090 ps |
| CPU time | 208.64 seconds |
| Started | Jan 10 02:02:24 PM PST 24 |
| Finished | Jan 10 02:06:03 PM PST 24 |
| Peak memory | 602372 kb |
| Host | smart-8eeb128c-4371-4846-89e4-12719f197118 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946570538 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2946570538 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.4055841041 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2418877984 ps |
| CPU time | 278.08 seconds |
| Started | Jan 10 01:55:28 PM PST 24 |
| Finished | Jan 10 02:00:11 PM PST 24 |
| Peak memory | 602348 kb |
| Host | smart-2c1f5397-876b-4ca7-822d-1261012d833e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055841041 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.4055841041 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.1313319258 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2717910526 ps |
| CPU time | 281.5 seconds |
| Started | Jan 10 02:02:04 PM PST 24 |
| Finished | Jan 10 02:06:48 PM PST 24 |
| Peak memory | 602376 kb |
| Host | smart-0f0a30e3-a4b0-4e9c-b564-03b4abf044ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313319258 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1313319258 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.1587229217 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 3114300170 ps |
| CPU time | 309.21 seconds |
| Started | Jan 10 01:55:32 PM PST 24 |
| Finished | Jan 10 02:00:44 PM PST 24 |
| Peak memory | 602080 kb |
| Host | smart-e174382d-2afd-46aa-963a-fbf14dfa698b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587229217 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.1587229217 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1329231616 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3140073936 ps |
| CPU time | 407.04 seconds |
| Started | Jan 10 01:56:29 PM PST 24 |
| Finished | Jan 10 02:03:18 PM PST 24 |
| Peak memory | 590352 kb |
| Host | smart-c0a0bc3a-2ba3-4197-8cf5-4f4c13b24a71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329231616 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1329231616 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.362425479 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 3429688835 ps |
| CPU time | 334.57 seconds |
| Started | Jan 10 02:01:44 PM PST 24 |
| Finished | Jan 10 02:07:21 PM PST 24 |
| Peak memory | 602408 kb |
| Host | smart-880fb255-8c7f-4cc8-a71c-8adca101492f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362425479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.362425479 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.460163747 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 3495538993 ps |
| CPU time | 349.21 seconds |
| Started | Jan 10 01:56:54 PM PST 24 |
| Finished | Jan 10 02:02:44 PM PST 24 |
| Peak memory | 602452 kb |
| Host | smart-73b56d64-7fb6-4418-8580-6d9fd4dd6dca |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46016374 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.460163747 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.1813933068 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3029502220 ps |
| CPU time | 313.48 seconds |
| Started | Jan 10 01:58:04 PM PST 24 |
| Finished | Jan 10 02:03:28 PM PST 24 |
| Peak memory | 590364 kb |
| Host | smart-01bac2b5-0e43-4476-a2a4-0fbb48e53647 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813933068 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.1813933068 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg.3533321481 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 2985724474 ps |
| CPU time | 397.86 seconds |
| Started | Jan 10 01:56:46 PM PST 24 |
| Finished | Jan 10 02:03:28 PM PST 24 |
| Peak memory | 602336 kb |
| Host | smart-5941fc3d-4de4-4f7e-a5e2-e9ada98ea98c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533321481 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg.3533321481 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1650406369 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4437213464 ps |
| CPU time | 609.31 seconds |
| Started | Jan 10 01:58:20 PM PST 24 |
| Finished | Jan 10 02:08:31 PM PST 24 |
| Peak memory | 616880 kb |
| Host | smart-29055806-c532-4e62-94d7-c5dfe4049772 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1650406369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.1650406369 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.391432658 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3250387548 ps |
| CPU time | 185.55 seconds |
| Started | Jan 10 01:55:24 PM PST 24 |
| Finished | Jan 10 01:58:36 PM PST 24 |
| Peak memory | 603696 kb |
| Host | smart-0a8560e0-2521-46f5-ae9f-9e760d8ebb55 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39143265 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.391432658 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.585753588 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 5197755750 ps |
| CPU time | 454.59 seconds |
| Started | Jan 10 01:55:54 PM PST 24 |
| Finished | Jan 10 02:03:29 PM PST 24 |
| Peak memory | 603632 kb |
| Host | smart-f51f72f2-b613-4899-a9bc-6bea45af2b18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585753588 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.585753588 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3953928300 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4938607472 ps |
| CPU time | 268.28 seconds |
| Started | Jan 10 01:56:18 PM PST 24 |
| Finished | Jan 10 02:00:47 PM PST 24 |
| Peak memory | 608628 kb |
| Host | smart-968f9aa7-235c-4ae5-bbe8-829504d6800d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3953928300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3953928300 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.500981594 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 5373488552 ps |
| CPU time | 295.61 seconds |
| Started | Jan 10 01:58:06 PM PST 24 |
| Finished | Jan 10 02:03:10 PM PST 24 |
| Peak memory | 600200 kb |
| Host | smart-f96ec17c-3d24-4a2b-80f3-bb74600100c4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=lc_ctrl_volat ile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500981594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_u nlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_vola tile_raw_unlock_ext_clk_48mhz.500981594 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1209683550 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 9393669231 ps |
| CPU time | 747.39 seconds |
| Started | Jan 10 02:00:20 PM PST 24 |
| Finished | Jan 10 02:12:50 PM PST 24 |
| Peak memory | 608392 kb |
| Host | smart-9a007890-669d-4838-a279-8ae4ee856973 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209683550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1209683550 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2100731449 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 34702795790 ps |
| CPU time | 1807.39 seconds |
| Started | Jan 10 01:55:58 PM PST 24 |
| Finished | Jan 10 02:26:06 PM PST 24 |
| Peak memory | 609880 kb |
| Host | smart-a9e5065c-ca05-4035-8de2-637145768496 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2100731449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.2100731449 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2808488706 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 17590408776 ps |
| CPU time | 2711.32 seconds |
| Started | Jan 10 01:55:37 PM PST 24 |
| Finished | Jan 10 02:40:49 PM PST 24 |
| Peak memory | 602944 kb |
| Host | smart-4ba70526-0476-412c-898a-1b27f54b75b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2808488706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.2808488706 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1854679799 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 18858770308 ps |
| CPU time | 3214.77 seconds |
| Started | Jan 10 01:55:15 PM PST 24 |
| Finished | Jan 10 02:48:51 PM PST 24 |
| Peak memory | 602928 kb |
| Host | smart-f9b7bb09-53b4-4d26-b0ec-02bf7d129617 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1854679799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1854679799 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3369041177 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 24258619716 ps |
| CPU time | 3216.31 seconds |
| Started | Jan 10 01:59:19 PM PST 24 |
| Finished | Jan 10 02:52:57 PM PST 24 |
| Peak memory | 602644 kb |
| Host | smart-817ff578-c7ca-4a6b-b37f-2f258eae55c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369041177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3369041177 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4094302259 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4367380584 ps |
| CPU time | 440.8 seconds |
| Started | Jan 10 01:55:45 PM PST 24 |
| Finished | Jan 10 02:03:07 PM PST 24 |
| Peak memory | 602756 kb |
| Host | smart-30ea1000-4c70-4f9d-a18f-d6eb2c6263ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094302259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.4094302259 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2976247626 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 6010245780 ps |
| CPU time | 530.46 seconds |
| Started | Jan 10 01:56:11 PM PST 24 |
| Finished | Jan 10 02:05:03 PM PST 24 |
| Peak memory | 602984 kb |
| Host | smart-9b8a60ae-a233-4506-8bfd-11e446880fcd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2976247626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2976247626 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.690113330 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 4994362196 ps |
| CPU time | 1038.1 seconds |
| Started | Jan 10 01:58:47 PM PST 24 |
| Finished | Jan 10 02:16:15 PM PST 24 |
| Peak memory | 603060 kb |
| Host | smart-85281216-5902-4519-9367-df289641eec4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690113330 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_smoketest.690113330 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2636016346 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 9283181160 ps |
| CPU time | 1148.03 seconds |
| Started | Jan 10 01:54:48 PM PST 24 |
| Finished | Jan 10 02:13:57 PM PST 24 |
| Peak memory | 603292 kb |
| Host | smart-ecc952aa-7863-42a6-917f-1a2943fc0229 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2636016346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.2636016346 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.19310043 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 7117069190 ps |
| CPU time | 1113.88 seconds |
| Started | Jan 10 01:56:22 PM PST 24 |
| Finished | Jan 10 02:14:56 PM PST 24 |
| Peak memory | 603600 kb |
| Host | smart-d10c4d12-d496-4431-bbc2-bfdcbda39539 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=19310043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.19310043 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1012614141 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 8819602262 ps |
| CPU time | 1014.79 seconds |
| Started | Jan 10 01:56:32 PM PST 24 |
| Finished | Jan 10 02:13:28 PM PST 24 |
| Peak memory | 603488 kb |
| Host | smart-f79fdf65-1257-42ae-8ccb-4076410e7dd3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1012614141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1012614141 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1498366528 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4743597720 ps |
| CPU time | 602.08 seconds |
| Started | Jan 10 01:54:37 PM PST 24 |
| Finished | Jan 10 02:04:40 PM PST 24 |
| Peak memory | 602488 kb |
| Host | smart-727cd0a2-cb4a-4363-bbb8-b75ca8f113c2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1498366528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1498366528 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.15068373 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2195460620 ps |
| CPU time | 229.77 seconds |
| Started | Jan 10 02:02:25 PM PST 24 |
| Finished | Jan 10 02:06:25 PM PST 24 |
| Peak memory | 601996 kb |
| Host | smart-a2aeb620-66ed-4c13-a669-bc4db9d37098 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15068373 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_otp_ctrl_smoketest.15068373 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.3035442488 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2757303812 ps |
| CPU time | 285.26 seconds |
| Started | Jan 10 01:55:39 PM PST 24 |
| Finished | Jan 10 02:00:26 PM PST 24 |
| Peak memory | 590620 kb |
| Host | smart-64d92106-b64d-4b64-b728-9f549d1253c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035442488 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.3035442488 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.3678691929 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 3181870786 ps |
| CPU time | 326.06 seconds |
| Started | Jan 10 01:58:49 PM PST 24 |
| Finished | Jan 10 02:04:24 PM PST 24 |
| Peak memory | 602056 kb |
| Host | smart-49cc8c6f-6f7f-4033-8039-ebcfe6ca488d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678691929 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.3678691929 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.4162294129 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 4823940260 ps |
| CPU time | 538.75 seconds |
| Started | Jan 10 01:58:07 PM PST 24 |
| Finished | Jan 10 02:07:14 PM PST 24 |
| Peak memory | 602672 kb |
| Host | smart-feb981bb-0e34-48d8-b680-07b102da7b92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162294129 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.4162294129 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.3255963118 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4139498036 ps |
| CPU time | 346.01 seconds |
| Started | Jan 10 01:57:21 PM PST 24 |
| Finished | Jan 10 02:03:08 PM PST 24 |
| Peak memory | 602868 kb |
| Host | smart-ca691146-79eb-4e3e-91f0-bca80bd15c40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255963118 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3255963118 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3304011898 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 12766652205 ps |
| CPU time | 1695.56 seconds |
| Started | Jan 10 01:56:07 PM PST 24 |
| Finished | Jan 10 02:24:24 PM PST 24 |
| Peak memory | 593092 kb |
| Host | smart-dbb5c7b0-e0ac-4d88-ade5-c0f5dc4e7222 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304 011898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3304011898 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1684970724 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 22532476696 ps |
| CPU time | 2008.01 seconds |
| Started | Jan 10 01:54:56 PM PST 24 |
| Finished | Jan 10 02:28:32 PM PST 24 |
| Peak memory | 603560 kb |
| Host | smart-a8c89d42-db08-4237-aef5-113b13580cdd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168 4970724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1684970724 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3288756974 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 13273472499 ps |
| CPU time | 1181.9 seconds |
| Started | Jan 10 01:57:12 PM PST 24 |
| Finished | Jan 10 02:16:56 PM PST 24 |
| Peak memory | 592000 kb |
| Host | smart-87604493-c121-43f5-8d76-917ac2e38064 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3288756974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3288756974 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1622676167 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 17577542052 ps |
| CPU time | 1363.77 seconds |
| Started | Jan 10 01:58:50 PM PST 24 |
| Finished | Jan 10 02:21:42 PM PST 24 |
| Peak memory | 603740 kb |
| Host | smart-c3e4ff1f-e30b-4b3a-ab4d-ef1f88e49e0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1622676167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1622676167 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3379902643 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 9665930060 ps |
| CPU time | 786.02 seconds |
| Started | Jan 10 01:55:51 PM PST 24 |
| Finished | Jan 10 02:08:58 PM PST 24 |
| Peak memory | 603476 kb |
| Host | smart-0d9630af-97ee-4d13-b091-81515e79c0a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379902643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3379902643 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2422411648 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 7802144430 ps |
| CPU time | 554.96 seconds |
| Started | Jan 10 01:55:42 PM PST 24 |
| Finished | Jan 10 02:04:58 PM PST 24 |
| Peak memory | 610076 kb |
| Host | smart-41b0b0cd-6d72-4a41-9986-020cef9575da |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2422411648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2422411648 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3302914325 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 7689079762 ps |
| CPU time | 511.67 seconds |
| Started | Jan 10 01:57:36 PM PST 24 |
| Finished | Jan 10 02:06:09 PM PST 24 |
| Peak memory | 603460 kb |
| Host | smart-8a458352-2323-4f4a-ba87-4d168b804806 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302914325 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3302914325 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3183673266 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 4149801340 ps |
| CPU time | 277.32 seconds |
| Started | Jan 10 01:58:39 PM PST 24 |
| Finished | Jan 10 02:03:27 PM PST 24 |
| Peak memory | 609760 kb |
| Host | smart-4704a94b-76cc-48a2-9dcf-09efc7197cba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3183673266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3183673266 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3904896366 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 13150622873 ps |
| CPU time | 1305.4 seconds |
| Started | Jan 10 01:55:13 PM PST 24 |
| Finished | Jan 10 02:16:59 PM PST 24 |
| Peak memory | 603992 kb |
| Host | smart-e55b45a4-4123-4ab9-839a-f66a2ab7cb35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904896366 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3904896366 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.856383099 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 7089560710 ps |
| CPU time | 437.94 seconds |
| Started | Jan 10 01:57:58 PM PST 24 |
| Finished | Jan 10 02:05:32 PM PST 24 |
| Peak memory | 603268 kb |
| Host | smart-dedcc277-0aac-4bc8-8c71-8d5813f3967e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856383099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.856383099 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1574245764 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 21096705564 ps |
| CPU time | 2042.04 seconds |
| Started | Jan 10 01:56:44 PM PST 24 |
| Finished | Jan 10 02:30:50 PM PST 24 |
| Peak memory | 604292 kb |
| Host | smart-b70a2386-7641-4fa1-b30e-be043b230b42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1574245764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1574245764 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2617669036 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 21581208216 ps |
| CPU time | 1424.91 seconds |
| Started | Jan 10 01:58:51 PM PST 24 |
| Finished | Jan 10 02:22:44 PM PST 24 |
| Peak memory | 591504 kb |
| Host | smart-c9b8a09d-434c-428d-8c54-67f12125f093 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2617669036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2617669036 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1760890998 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 42665463804 ps |
| CPU time | 3065.9 seconds |
| Started | Jan 10 01:57:42 PM PST 24 |
| Finished | Jan 10 02:48:49 PM PST 24 |
| Peak memory | 594368 kb |
| Host | smart-26cd9b39-30e8-472e-a361-6d9195c64eb7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760890998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1760890998 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3684740050 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2758093950 ps |
| CPU time | 278.64 seconds |
| Started | Jan 10 01:55:47 PM PST 24 |
| Finished | Jan 10 02:00:26 PM PST 24 |
| Peak memory | 602092 kb |
| Host | smart-c0e9ce6a-58aa-4594-be8b-695001a3dbf0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684740050 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.3684740050 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3097267029 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 6035805897 ps |
| CPU time | 392.51 seconds |
| Started | Jan 10 01:58:11 PM PST 24 |
| Finished | Jan 10 02:04:51 PM PST 24 |
| Peak memory | 609812 kb |
| Host | smart-b3480233-f37c-4545-930b-ce0dff7453eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3097267029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.3097267029 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.4207206275 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 4611973172 ps |
| CPU time | 389.88 seconds |
| Started | Jan 10 01:57:54 PM PST 24 |
| Finished | Jan 10 02:04:26 PM PST 24 |
| Peak memory | 603188 kb |
| Host | smart-efc4b561-10ea-4dea-96b6-27c219c919d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207206275 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.4207206275 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.870978780 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 8153878800 ps |
| CPU time | 1054.41 seconds |
| Started | Jan 10 01:54:55 PM PST 24 |
| Finished | Jan 10 02:12:38 PM PST 24 |
| Peak memory | 591188 kb |
| Host | smart-d63e41cd-5776-442b-ae31-9559a73e3843 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870978780 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.870978780 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.478312648 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 4256457720 ps |
| CPU time | 355.06 seconds |
| Started | Jan 10 01:56:15 PM PST 24 |
| Finished | Jan 10 02:02:10 PM PST 24 |
| Peak memory | 602588 kb |
| Host | smart-fce5b165-a28c-4c47-96cd-076468c8bf58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478312648 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.478312648 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2356844804 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4424193390 ps |
| CPU time | 327.94 seconds |
| Started | Jan 10 01:59:04 PM PST 24 |
| Finished | Jan 10 02:04:33 PM PST 24 |
| Peak memory | 603152 kb |
| Host | smart-4d07a204-3364-4a5e-b885-6709c1a7b02c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356844804 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.2356844804 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.779014697 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 5159705940 ps |
| CPU time | 568.82 seconds |
| Started | Jan 10 01:57:00 PM PST 24 |
| Finished | Jan 10 02:06:30 PM PST 24 |
| Peak memory | 602860 kb |
| Host | smart-5e0dd3eb-9ed3-433d-acf2-c689ce3b264f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779 014697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.779014697 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3132529637 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 8135465040 ps |
| CPU time | 708.4 seconds |
| Started | Jan 10 01:55:40 PM PST 24 |
| Finished | Jan 10 02:07:30 PM PST 24 |
| Peak memory | 606692 kb |
| Host | smart-64df0af9-bdd9-45c3-bf02-7b553c677d7e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132529637 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.3132529637 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3075561430 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 6704382632 ps |
| CPU time | 541.06 seconds |
| Started | Jan 10 01:57:06 PM PST 24 |
| Finished | Jan 10 02:06:08 PM PST 24 |
| Peak memory | 603308 kb |
| Host | smart-431eb32b-c789-49a4-a468-dea3483f0f30 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075561430 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.3075561430 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.4178036575 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5808182286 ps |
| CPU time | 549.96 seconds |
| Started | Jan 10 01:59:41 PM PST 24 |
| Finished | Jan 10 02:08:52 PM PST 24 |
| Peak memory | 634548 kb |
| Host | smart-f52bd8a1-e21c-4499-9644-9d82d75bfdf5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4178036575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.4178036575 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.4141641576 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 2674138526 ps |
| CPU time | 198.41 seconds |
| Started | Jan 10 01:56:57 PM PST 24 |
| Finished | Jan 10 02:00:17 PM PST 24 |
| Peak memory | 602060 kb |
| Host | smart-e4c1ee98-215a-425e-9c4c-4ad3887a402a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141641576 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.4141641576 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2505473342 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 3973146000 ps |
| CPU time | 408.04 seconds |
| Started | Jan 10 01:55:55 PM PST 24 |
| Finished | Jan 10 02:02:44 PM PST 24 |
| Peak memory | 602548 kb |
| Host | smart-1b45f17b-9112-4b92-978b-a0fefbc3fc8f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505473342 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.2505473342 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.22974475 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 3245123550 ps |
| CPU time | 239.58 seconds |
| Started | Jan 10 01:55:13 PM PST 24 |
| Finished | Jan 10 01:59:14 PM PST 24 |
| Peak memory | 602200 kb |
| Host | smart-a1547e91-333e-4cf4-a91f-5b7c8a0fc521 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22974475 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.22974475 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2138631329 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3427239920 ps |
| CPU time | 324.48 seconds |
| Started | Jan 10 01:57:12 PM PST 24 |
| Finished | Jan 10 02:02:38 PM PST 24 |
| Peak memory | 602092 kb |
| Host | smart-1ef95a19-28a0-42ab-958d-74311e19b771 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2138631329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.2138631329 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.373913871 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 2888876405 ps |
| CPU time | 254.94 seconds |
| Started | Jan 10 01:58:06 PM PST 24 |
| Finished | Jan 10 02:02:30 PM PST 24 |
| Peak memory | 602060 kb |
| Host | smart-0afe15d2-bc50-47a9-9063-a1a23a47ef78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373913871 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.373913871 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2584913211 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4524697448 ps |
| CPU time | 724.8 seconds |
| Started | Jan 10 01:55:36 PM PST 24 |
| Finished | Jan 10 02:07:42 PM PST 24 |
| Peak memory | 602732 kb |
| Host | smart-213c233c-7390-4cef-9d0d-2ddadf3644bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25849 13211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2584913211 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3453174258 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4911812056 ps |
| CPU time | 1043.33 seconds |
| Started | Jan 10 01:55:05 PM PST 24 |
| Finished | Jan 10 02:12:33 PM PST 24 |
| Peak memory | 602636 kb |
| Host | smart-07c4a8a3-7a06-4571-9d4a-3f430d1fa859 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3453174258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3453174258 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1472042636 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 6282565762 ps |
| CPU time | 612.15 seconds |
| Started | Jan 10 01:56:11 PM PST 24 |
| Finished | Jan 10 02:06:24 PM PST 24 |
| Peak memory | 617096 kb |
| Host | smart-32263d0c-c92a-4066-b27a-d0fc2138daa2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472042636 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1472042636 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3898320874 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 5961616870 ps |
| CPU time | 437.81 seconds |
| Started | Jan 10 01:56:08 PM PST 24 |
| Finished | Jan 10 02:03:27 PM PST 24 |
| Peak memory | 616432 kb |
| Host | smart-e19bf922-3496-4d3c-9651-6217a2e428b5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup:1:new_rules,test_rom:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898320874 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.3898320874 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.716459507 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 4133678440 ps |
| CPU time | 457.19 seconds |
| Started | Jan 10 01:58:09 PM PST 24 |
| Finished | Jan 10 02:05:52 PM PST 24 |
| Peak memory | 616540 kb |
| Host | smart-3479e0c2-5dc2-4c65-88e0-c75563c987c5 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716459507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.716459507 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2705590814 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2837613608 ps |
| CPU time | 177.13 seconds |
| Started | Jan 10 01:56:19 PM PST 24 |
| Finished | Jan 10 01:59:17 PM PST 24 |
| Peak memory | 602056 kb |
| Host | smart-bc28fed1-1767-4630-8c3a-d2c6c85c72e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705590814 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2705590814 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.4275068747 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3022809560 ps |
| CPU time | 217.87 seconds |
| Started | Jan 10 01:55:16 PM PST 24 |
| Finished | Jan 10 01:58:55 PM PST 24 |
| Peak memory | 602376 kb |
| Host | smart-6a2f095c-0305-4822-80b9-625475e3ccf6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275068747 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.4275068747 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2070106481 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 2510753862 ps |
| CPU time | 204.01 seconds |
| Started | Jan 10 02:03:50 PM PST 24 |
| Finished | Jan 10 02:07:27 PM PST 24 |
| Peak memory | 602028 kb |
| Host | smart-171f95b9-6b81-473f-bab4-ac13b8194990 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070106481 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2070106481 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4157280623 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 9383213864 ps |
| CPU time | 925.44 seconds |
| Started | Jan 10 01:56:43 PM PST 24 |
| Finished | Jan 10 02:12:13 PM PST 24 |
| Peak memory | 603276 kb |
| Host | smart-813baeab-c55a-43ac-88c2-45dd9758d0f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41572806 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.4157280623 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4271222668 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3028645549 ps |
| CPU time | 256.02 seconds |
| Started | Jan 10 01:56:31 PM PST 24 |
| Finished | Jan 10 02:00:49 PM PST 24 |
| Peak memory | 603232 kb |
| Host | smart-f9786fc8-2a18-4bf8-8c4e-0f1bbcab3fa8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271222 668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.4271222668 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1449460917 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4101042900 ps |
| CPU time | 328.08 seconds |
| Started | Jan 10 02:00:13 PM PST 24 |
| Finished | Jan 10 02:05:46 PM PST 24 |
| Peak memory | 602508 kb |
| Host | smart-ced766d3-57ed-48b7-9a77-b3ce6c9ed1a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449460917 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.1449460917 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4163555562 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 8622837152 ps |
| CPU time | 1053.78 seconds |
| Started | Jan 10 02:03:03 PM PST 24 |
| Finished | Jan 10 02:20:58 PM PST 24 |
| Peak memory | 591316 kb |
| Host | smart-fb64b721-61b5-4884-85f9-5add98f2c20f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163555562 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.4163555562 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1276395822 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 6672828588 ps |
| CPU time | 676.87 seconds |
| Started | Jan 10 01:56:36 PM PST 24 |
| Finished | Jan 10 02:08:04 PM PST 24 |
| Peak memory | 603284 kb |
| Host | smart-344884e2-922b-48af-9543-9688141f263f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276395822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.1276395822 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.461613079 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 6696135048 ps |
| CPU time | 611.78 seconds |
| Started | Jan 10 01:56:42 PM PST 24 |
| Finished | Jan 10 02:06:59 PM PST 24 |
| Peak memory | 592160 kb |
| Host | smart-4bd74df3-0545-4455-9a0a-bcf5ef055c29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461613079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_ sram_ret_contents_scramble.461613079 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2290313813 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 6878737414 ps |
| CPU time | 640.49 seconds |
| Started | Jan 10 01:57:39 PM PST 24 |
| Finished | Jan 10 02:08:20 PM PST 24 |
| Peak memory | 618128 kb |
| Host | smart-c25df64d-6751-4ce1-a0a8-47c7f27b5d73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290313813 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.2290313813 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.988543156 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4115481089 ps |
| CPU time | 454.32 seconds |
| Started | Jan 10 01:58:30 PM PST 24 |
| Finished | Jan 10 02:06:05 PM PST 24 |
| Peak memory | 618120 kb |
| Host | smart-1ad729d4-417d-4c40-89fe-f550bf290434 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988543156 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.988543156 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.2565923794 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 3212695886 ps |
| CPU time | 395.34 seconds |
| Started | Jan 10 01:55:06 PM PST 24 |
| Finished | Jan 10 02:01:45 PM PST 24 |
| Peak memory | 616512 kb |
| Host | smart-cea38a38-42e9-44c2-a970-8a8ca36d7c9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565923794 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.2565923794 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tx_rx.1133947614 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 2453820768 ps |
| CPU time | 371.2 seconds |
| Started | Jan 10 01:58:18 PM PST 24 |
| Finished | Jan 10 02:04:31 PM PST 24 |
| Peak memory | 608372 kb |
| Host | smart-fde73b11-ed55-4740-9307-d9e6f9956e2e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133947614 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_spi_device_tx_rx.1133947614 |
| Directory | /workspace/1.chip_sw_spi_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1026132211 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3453358956 ps |
| CPU time | 294.58 seconds |
| Started | Jan 10 01:57:48 PM PST 24 |
| Finished | Jan 10 02:02:44 PM PST 24 |
| Peak memory | 602916 kb |
| Host | smart-ed2159de-2ffd-42c7-9083-36595ffcdd6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026132211 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1026132211 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3679330070 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 8742042328 ps |
| CPU time | 562.4 seconds |
| Started | Jan 10 01:55:59 PM PST 24 |
| Finished | Jan 10 02:05:23 PM PST 24 |
| Peak memory | 590260 kb |
| Host | smart-773811a3-16e2-4956-a6d6-b72fa22fe967 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679330070 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3679330070 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1347966957 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5900996712 ps |
| CPU time | 548.74 seconds |
| Started | Jan 10 02:02:16 PM PST 24 |
| Finished | Jan 10 02:11:36 PM PST 24 |
| Peak memory | 603164 kb |
| Host | smart-c79a17df-241a-4af5-a92d-d15d4cce2b44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347966957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.1347966957 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.715746882 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 4320571178 ps |
| CPU time | 613.41 seconds |
| Started | Jan 10 02:01:49 PM PST 24 |
| Finished | Jan 10 02:12:04 PM PST 24 |
| Peak memory | 603040 kb |
| Host | smart-f2b19e28-4f9f-47db-a578-34311feb8885 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715746882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.715746882 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1956509874 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 3602880548 ps |
| CPU time | 477.88 seconds |
| Started | Jan 10 01:57:49 PM PST 24 |
| Finished | Jan 10 02:05:50 PM PST 24 |
| Peak memory | 602720 kb |
| Host | smart-72987f1e-0c4c-4ceb-b738-41da0251f973 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956509874 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1956509874 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.846897967 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 3253848410 ps |
| CPU time | 308.67 seconds |
| Started | Jan 10 02:01:30 PM PST 24 |
| Finished | Jan 10 02:06:44 PM PST 24 |
| Peak memory | 602000 kb |
| Host | smart-79eced45-b568-4dd1-b119-be9d709dc84f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846897967 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_sram_ctrl_smoketest.846897967 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3976485530 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 20603377504 ps |
| CPU time | 2732.79 seconds |
| Started | Jan 10 01:54:19 PM PST 24 |
| Finished | Jan 10 02:39:53 PM PST 24 |
| Peak memory | 603152 kb |
| Host | smart-c05d2cb9-118a-4087-8a18-a74c4fe0ce8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976485530 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3976485530 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2264473556 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4287355777 ps |
| CPU time | 595.29 seconds |
| Started | Jan 10 01:54:53 PM PST 24 |
| Finished | Jan 10 02:05:00 PM PST 24 |
| Peak memory | 602648 kb |
| Host | smart-67ac1870-fee9-442a-8b87-1aca5c8541d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264473556 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.2264473556 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3071087392 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2704631587 ps |
| CPU time | 286.69 seconds |
| Started | Jan 10 01:57:29 PM PST 24 |
| Finished | Jan 10 02:02:18 PM PST 24 |
| Peak memory | 602376 kb |
| Host | smart-49951311-9f01-4f9f-a08d-c1fc3aa9769c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071087392 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3071087392 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1725801346 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 3880976320 ps |
| CPU time | 484.01 seconds |
| Started | Jan 10 01:56:41 PM PST 24 |
| Finished | Jan 10 02:04:52 PM PST 24 |
| Peak memory | 602392 kb |
| Host | smart-02691eb1-eda8-4fba-9ad7-a2ccda5df37a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725801346 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.1725801346 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.22384789 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 23594359704 ps |
| CPU time | 1486.61 seconds |
| Started | Jan 10 01:55:55 PM PST 24 |
| Finished | Jan 10 02:20:43 PM PST 24 |
| Peak memory | 603836 kb |
| Host | smart-dae73d4c-281c-440b-8850-d13fecd650c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22384789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.22384789 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1017639523 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 4926654432 ps |
| CPU time | 446.6 seconds |
| Started | Jan 10 01:56:38 PM PST 24 |
| Finished | Jan 10 02:04:15 PM PST 24 |
| Peak memory | 603204 kb |
| Host | smart-aad4ddb3-6f16-4262-85f2-bd68f25c3c3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017639523 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1017639523 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.521825875 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 22905614256 ps |
| CPU time | 3772.47 seconds |
| Started | Jan 10 01:59:01 PM PST 24 |
| Finished | Jan 10 03:01:56 PM PST 24 |
| Peak memory | 598592 kb |
| Host | smart-ef865b65-1e1b-4d64-be2f-28ac49f6cbd7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=521825875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.521825875 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.3428037793 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2711497976 ps |
| CPU time | 270.34 seconds |
| Started | Jan 10 01:59:06 PM PST 24 |
| Finished | Jan 10 02:03:38 PM PST 24 |
| Peak memory | 590360 kb |
| Host | smart-00b19fb7-a312-4791-b4f9-8474d003eea2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428037793 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.3428037793 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest_signed.1523995763 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 9297638700 ps |
| CPU time | 1674.11 seconds |
| Started | Jan 10 02:05:30 PM PST 24 |
| Finished | Jan 10 02:33:27 PM PST 24 |
| Peak memory | 590492 kb |
| Host | smart-60030392-94f2-4dea-8c9c-d68e6c2d8949 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=uart_smoketest_signed:1:signed:fake_rsa_test_key_0,rom_with_fa ke_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1523995763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_smoketest_signed.1523995763 |
| Directory | /workspace/1.chip_sw_uart_smoketest_signed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.209124327 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 5335414900 ps |
| CPU time | 911.94 seconds |
| Started | Jan 10 01:55:19 PM PST 24 |
| Finished | Jan 10 02:10:33 PM PST 24 |
| Peak memory | 598596 kb |
| Host | smart-4ef164e8-89e3-45bd-bed9-367860239564 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209124327 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.209124327 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2916600828 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 4868758616 ps |
| CPU time | 779.88 seconds |
| Started | Jan 10 01:54:36 PM PST 24 |
| Finished | Jan 10 02:07:37 PM PST 24 |
| Peak memory | 599140 kb |
| Host | smart-968d6117-9f58-4022-951d-f5c32d391997 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916600828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_r x_alt_clk_freq.2916600828 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3278497972 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 12992410366 ps |
| CPU time | 1384.25 seconds |
| Started | Jan 10 01:57:35 PM PST 24 |
| Finished | Jan 10 02:20:41 PM PST 24 |
| Peak memory | 599208 kb |
| Host | smart-18343399-307f-4329-921f-9f37f335e4a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278497972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_r x_alt_clk_freq_low_speed.3278497972 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3865198776 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 73018514050 ps |
| CPU time | 12189 seconds |
| Started | Jan 10 01:54:18 PM PST 24 |
| Finished | Jan 10 05:17:29 PM PST 24 |
| Peak memory | 610980 kb |
| Host | smart-846a9472-f717-483a-bc3f-edd1701a8cac |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3865198776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.3865198776 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1122376560 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 5342388260 ps |
| CPU time | 815 seconds |
| Started | Jan 10 01:56:03 PM PST 24 |
| Finished | Jan 10 02:09:38 PM PST 24 |
| Peak memory | 599028 kb |
| Host | smart-a102240a-0982-412f-929f-3a0d7b89d3e0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122376560 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1122376560 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4045768554 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 4967510280 ps |
| CPU time | 789.16 seconds |
| Started | Jan 10 01:54:45 PM PST 24 |
| Finished | Jan 10 02:07:55 PM PST 24 |
| Peak memory | 598772 kb |
| Host | smart-ab9f0bc1-f0b8-4133-8f69-e14597424362 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045768554 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.4045768554 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.469652124 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5692861982 ps |
| CPU time | 847.87 seconds |
| Started | Jan 10 01:58:55 PM PST 24 |
| Finished | Jan 10 02:13:08 PM PST 24 |
| Peak memory | 598784 kb |
| Host | smart-3eceea9f-18ac-4184-8c26-47da1a86176f |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469652124 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.469652124 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.2151738416 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 11871003934 ps |
| CPU time | 1122.51 seconds |
| Started | Jan 10 01:56:57 PM PST 24 |
| Finished | Jan 10 02:15:40 PM PST 24 |
| Peak memory | 615412 kb |
| Host | smart-27eee8a5-6abd-4976-9e7c-6f81c4f5d127 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2151738416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.2151738416 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.2336252645 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 5811206883 ps |
| CPU time | 491.8 seconds |
| Started | Jan 10 01:55:48 PM PST 24 |
| Finished | Jan 10 02:04:01 PM PST 24 |
| Peak memory | 601940 kb |
| Host | smart-8aa812bf-e8b7-46c7-8c22-f2095803c3ee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336252645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.2336252645 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.1959661759 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 2297191314 ps |
| CPU time | 160.68 seconds |
| Started | Jan 10 01:57:03 PM PST 24 |
| Finished | Jan 10 01:59:45 PM PST 24 |
| Peak memory | 615344 kb |
| Host | smart-a10435e2-a46e-464e-8e34-6bfd8b38d607 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959661759 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1959661759 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.2524018338 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8846555513 ps |
| CPU time | 894.5 seconds |
| Started | Jan 10 01:55:51 PM PST 24 |
| Finished | Jan 10 02:10:46 PM PST 24 |
| Peak memory | 615368 kb |
| Host | smart-e2780b44-020c-4245-abff-1478c1915ff7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524018338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2524018338 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.858186680 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 9493344855 ps |
| CPU time | 1660.61 seconds |
| Started | Jan 10 02:05:19 PM PST 24 |
| Finished | Jan 10 02:33:02 PM PST 24 |
| Peak memory | 602904 kb |
| Host | smart-daa0af73-8397-4055-ab58-bbf47a70e27c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858186680 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_dev.858186680 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.2522581966 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 8824711772 ps |
| CPU time | 1558.76 seconds |
| Started | Jan 10 02:02:29 PM PST 24 |
| Finished | Jan 10 02:29:07 PM PST 24 |
| Peak memory | 590736 kb |
| Host | smart-ff2c49d0-380b-4102-b0f4-2876627dadfc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522581966 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.rom_e2e_asm_init_prod.2522581966 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2682609269 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 8888163825 ps |
| CPU time | 1769.02 seconds |
| Started | Jan 10 02:02:06 PM PST 24 |
| Finished | Jan 10 02:31:45 PM PST 24 |
| Peak memory | 602924 kb |
| Host | smart-49cecf11-db13-4d24-9ad0-2d3d74af580c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682609269 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod_end.2682609269 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.2949134583 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 9243570072 ps |
| CPU time | 1705.62 seconds |
| Started | Jan 10 02:01:26 PM PST 24 |
| Finished | Jan 10 02:29:59 PM PST 24 |
| Peak memory | 602920 kb |
| Host | smart-aecd4af2-f6df-4aaf-a39b-ff53cd2d8399 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949134583 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.rom_e2e_asm_init_rma.2949134583 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1239450224 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 6486513554 ps |
| CPU time | 1141.77 seconds |
| Started | Jan 10 02:00:39 PM PST 24 |
| Finished | Jan 10 02:19:42 PM PST 24 |
| Peak memory | 590796 kb |
| Host | smart-9a7b2d22-e167-49e3-8904-54bf227212f5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_ flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239450224 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_test_unlocked0.1239450224 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.485456702 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 8556911067 ps |
| CPU time | 1434.37 seconds |
| Started | Jan 10 02:01:08 PM PST 24 |
| Finished | Jan 10 02:25:04 PM PST 24 |
| Peak memory | 603132 kb |
| Host | smart-c23f6439-e27f-4eb8-8a72-965bc6bcda50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:signed:fake_rsa_test_key_0,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=485456702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_exception_c.485456702 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.167771770 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 19653635725 ps |
| CPU time | 2112.62 seconds |
| Started | Jan 10 02:00:51 PM PST 24 |
| Finished | Jan 10 02:36:05 PM PST 24 |
| Peak memory | 604680 kb |
| Host | smart-4b841d67-bfd3-40c8-8330-315084b602ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bina ry,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167771770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.167771770 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.3154188813 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 8471984500 ps |
| CPU time | 1470.65 seconds |
| Started | Jan 10 01:56:28 PM PST 24 |
| Finished | Jan 10 02:21:00 PM PST 24 |
| Peak memory | 602704 kb |
| Host | smart-96dde631-65bd-475d-8ce4-9ad246df0a1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_binary:signed:fake_rsa_test_key_0 ,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3154188813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3154188813 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.1715034370 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 9988596736 ps |
| CPU time | 1713.54 seconds |
| Started | Jan 10 01:59:50 PM PST 24 |
| Finished | Jan 10 02:28:31 PM PST 24 |
| Peak memory | 590576 kb |
| Host | smart-261e316c-6d30-42ca-ad92-78cf198378dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:signed:fake_rsa_test_key_0,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715034370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.1715034370 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.1073261440 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 5226254600 ps |
| CPU time | 519.67 seconds |
| Started | Jan 10 02:00:29 PM PST 24 |
| Finished | Jan 10 02:09:12 PM PST 24 |
| Peak memory | 603400 kb |
| Host | smart-c211bd36-b042-4999-9799-9f8f1f255cb1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073261440 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1073261440 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.3317412388 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 15581210559 ps |
| CPU time | 1955.65 seconds |
| Started | Jan 10 01:58:00 PM PST 24 |
| Finished | Jan 10 02:30:50 PM PST 24 |
| Peak memory | 608772 kb |
| Host | smart-4816990e-bf41-46b2-b056-2f51ad370457 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3317412388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.3317412388 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.4269254033 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9939427882 ps |
| CPU time | 1519.8 seconds |
| Started | Jan 10 01:58:34 PM PST 24 |
| Finished | Jan 10 02:24:04 PM PST 24 |
| Peak memory | 608836 kb |
| Host | smart-28233cbc-d6f4-4de1-882b-1bb013bd7254 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269254033 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.4269254033 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.3615599509 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4432153124 ps |
| CPU time | 457.68 seconds |
| Started | Jan 10 02:01:59 PM PST 24 |
| Finished | Jan 10 02:09:39 PM PST 24 |
| Peak memory | 608828 kb |
| Host | smart-9c143628-f8d8-4abc-be5a-ae53f1d4afeb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3615599509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.3615599509 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3091296655 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 11453125675 ps |
| CPU time | 846.64 seconds |
| Started | Jan 10 02:02:04 PM PST 24 |
| Finished | Jan 10 02:16:13 PM PST 24 |
| Peak memory | 604812 kb |
| Host | smart-7fb3d691-0d54-4e22-b74e-00bea757a84d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091296655 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3091296655 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.4024159539 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 22942001994 ps |
| CPU time | 3364.42 seconds |
| Started | Jan 10 02:02:38 PM PST 24 |
| Finished | Jan 10 02:59:26 PM PST 24 |
| Peak memory | 598620 kb |
| Host | smart-7718c784-2d45-4fef-8229-be72b3d2369d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4024159539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.4024159539 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.778613162 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 10642216762 ps |
| CPU time | 731.93 seconds |
| Started | Jan 10 02:01:12 PM PST 24 |
| Finished | Jan 10 02:13:27 PM PST 24 |
| Peak memory | 604792 kb |
| Host | smart-7e581d59-8d44-4159-afe2-9c7fd0f8494e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778613162 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.778613162 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.659610866 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 23507041456 ps |
| CPU time | 3767.25 seconds |
| Started | Jan 10 02:06:40 PM PST 24 |
| Finished | Jan 10 03:09:30 PM PST 24 |
| Peak memory | 598268 kb |
| Host | smart-fce8fc8d-a399-44a7-ac74-cfb19299490d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=659610866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.659610866 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.858902502 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 13525277805 ps |
| CPU time | 875.11 seconds |
| Started | Jan 10 02:02:24 PM PST 24 |
| Finished | Jan 10 02:17:10 PM PST 24 |
| Peak memory | 603568 kb |
| Host | smart-31ca5880-8035-4a79-8d2e-06b5052c17f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858902502 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.858902502 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3722534855 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 23751901750 ps |
| CPU time | 3492.57 seconds |
| Started | Jan 10 02:02:17 PM PST 24 |
| Finished | Jan 10 03:00:42 PM PST 24 |
| Peak memory | 599144 kb |
| Host | smart-aa236c9e-29b0-49df-aee1-98f447f61be1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3722534855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3722534855 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1655305269 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 5779221768 ps |
| CPU time | 531.54 seconds |
| Started | Jan 10 02:00:38 PM PST 24 |
| Finished | Jan 10 02:09:32 PM PST 24 |
| Peak memory | 603876 kb |
| Host | smart-fccb8eb7-73df-4e4f-9ee2-146efb26719e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655305269 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.1655305269 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2284549671 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 4858704904 ps |
| CPU time | 925.22 seconds |
| Started | Jan 10 02:01:49 PM PST 24 |
| Finished | Jan 10 02:17:16 PM PST 24 |
| Peak memory | 601528 kb |
| Host | smart-f164730d-6c4b-4028-898f-c7368d953615 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2284549671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.2284549671 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1525932021 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12106200078 ps |
| CPU time | 780.65 seconds |
| Started | Jan 10 02:01:06 PM PST 24 |
| Finished | Jan 10 02:14:08 PM PST 24 |
| Peak memory | 604676 kb |
| Host | smart-79f11b22-3b74-4599-beb3-333ea41c44db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525932021 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.1525932021 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1102288437 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 13545699844 ps |
| CPU time | 1989.97 seconds |
| Started | Jan 10 02:00:26 PM PST 24 |
| Finished | Jan 10 02:33:40 PM PST 24 |
| Peak memory | 599436 kb |
| Host | smart-483f1850-fca0-47bf-9972-b7cec57f8bd2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1102288437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1102288437 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.569959942 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 5329962904 ps |
| CPU time | 586.73 seconds |
| Started | Jan 10 02:06:44 PM PST 24 |
| Finished | Jan 10 02:16:34 PM PST 24 |
| Peak memory | 608876 kb |
| Host | smart-11e472f5-e9ea-42c0-814a-17491368871f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 569959942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.569959942 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.162609661 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 5383523160 ps |
| CPU time | 896.52 seconds |
| Started | Jan 10 02:02:14 PM PST 24 |
| Finished | Jan 10 02:17:21 PM PST 24 |
| Peak memory | 598596 kb |
| Host | smart-026e4665-c5c8-46d8-ae62-bec0493a0a3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=162609661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.162609661 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3825346799 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 3607682880 ps |
| CPU time | 375.01 seconds |
| Started | Jan 10 02:02:30 PM PST 24 |
| Finished | Jan 10 02:09:20 PM PST 24 |
| Peak memory | 608880 kb |
| Host | smart-d8ed6f59-4e5c-40ed-8202-b3dfd179da70 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825346799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3825346799 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3661267811 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3227729124 ps |
| CPU time | 296.08 seconds |
| Started | Jan 10 02:03:18 PM PST 24 |
| Finished | Jan 10 02:08:47 PM PST 24 |
| Peak memory | 629040 kb |
| Host | smart-f0cb410b-a9f7-40c3-b0cb-278eb6d8d7f2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661267811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3661267811 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3289694999 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 14107841144 ps |
| CPU time | 2558.75 seconds |
| Started | Jan 10 02:07:23 PM PST 24 |
| Finished | Jan 10 02:50:11 PM PST 24 |
| Peak memory | 599252 kb |
| Host | smart-aefb3a54-3414-4a19-80d5-1f5796cb5a16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3289694999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3289694999 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1100204626 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 23013602246 ps |
| CPU time | 3713.72 seconds |
| Started | Jan 10 02:07:25 PM PST 24 |
| Finished | Jan 10 03:09:29 PM PST 24 |
| Peak memory | 599244 kb |
| Host | smart-855aeed7-04e2-464f-950c-1662834ac7ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1100204626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.1100204626 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.200482512 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 14392010360 ps |
| CPU time | 2663.05 seconds |
| Started | Jan 10 02:07:23 PM PST 24 |
| Finished | Jan 10 02:51:56 PM PST 24 |
| Peak memory | 599536 kb |
| Host | smart-0979aed3-7ccf-45f0-970f-6d63491ccd26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=200482512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.200482512 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.1227118337 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 13814022522 ps |
| CPU time | 1278.45 seconds |
| Started | Jan 10 01:52:12 PM PST 24 |
| Finished | Jan 10 02:13:42 PM PST 24 |
| Peak memory | 596436 kb |
| Host | smart-b1391dec-ca81-4db3-92c9-5e84e2b02b9d |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227118337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.1 227118337 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4127300242 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4734667816 ps |
| CPU time | 410.01 seconds |
| Started | Jan 10 01:59:51 PM PST 24 |
| Finished | Jan 10 02:06:48 PM PST 24 |
| Peak memory | 617408 kb |
| Host | smart-65c05d3d-3d96-4e10-a24f-d6a8b35f7054 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4 127300242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.4127300242 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.1366493839 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 4114785928 ps |
| CPU time | 371.25 seconds |
| Started | Jan 10 01:59:05 PM PST 24 |
| Finished | Jan 10 02:05:18 PM PST 24 |
| Peak memory | 602224 kb |
| Host | smart-5609e80a-5285-455e-87f5-9ebaceb0618e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1366493839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.1366493839 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3412970937 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 18453791592 ps |
| CPU time | 667.78 seconds |
| Started | Jan 10 02:00:42 PM PST 24 |
| Finished | Jan 10 02:11:53 PM PST 24 |
| Peak memory | 616476 kb |
| Host | smart-f2d3b510-843f-40f7-857b-0f432c541e7a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3412970937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3412970937 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.110595450 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 2443994102 ps |
| CPU time | 261.59 seconds |
| Started | Jan 10 02:01:18 PM PST 24 |
| Finished | Jan 10 02:05:48 PM PST 24 |
| Peak memory | 602368 kb |
| Host | smart-ebc5fda3-bad9-4faa-a647-3e53527f503e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110595450 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.110595450 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2863591790 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 3030647884 ps |
| CPU time | 243.55 seconds |
| Started | Jan 10 02:02:13 PM PST 24 |
| Finished | Jan 10 02:06:26 PM PST 24 |
| Peak memory | 602292 kb |
| Host | smart-14a67b84-508a-4cc9-90bf-b7f74089708b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863591790 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2863591790 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1748009362 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 2998921788 ps |
| CPU time | 220.86 seconds |
| Started | Jan 10 02:05:23 PM PST 24 |
| Finished | Jan 10 02:09:08 PM PST 24 |
| Peak memory | 602340 kb |
| Host | smart-7f464afc-81cf-4b74-b086-d66104c5bf90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1748009362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1748009362 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.2329423211 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2932736292 ps |
| CPU time | 217.98 seconds |
| Started | Jan 10 02:00:09 PM PST 24 |
| Finished | Jan 10 02:03:54 PM PST 24 |
| Peak memory | 602144 kb |
| Host | smart-ffecf9af-66a9-4656-b1f6-78fc048b688f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329423211 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.2329423211 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.1677946071 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 2102575962 ps |
| CPU time | 194.56 seconds |
| Started | Jan 10 01:59:56 PM PST 24 |
| Finished | Jan 10 02:03:21 PM PST 24 |
| Peak memory | 602260 kb |
| Host | smart-7d89a841-0819-4feb-9d8e-5420d3a5ecf1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677946071 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1677946071 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.2711028847 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2956331176 ps |
| CPU time | 335.08 seconds |
| Started | Jan 10 02:00:34 PM PST 24 |
| Finished | Jan 10 02:06:11 PM PST 24 |
| Peak memory | 603020 kb |
| Host | smart-9df600cd-5ce6-4ea5-8ea0-54c2bd2db73d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711028847 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2711028847 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.3860628124 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 2335955204 ps |
| CPU time | 274.37 seconds |
| Started | Jan 10 02:04:32 PM PST 24 |
| Finished | Jan 10 02:09:10 PM PST 24 |
| Peak memory | 602320 kb |
| Host | smart-ddfb032d-6a84-4959-b810-35aff415d695 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860628124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.3860628124 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.1967305423 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3375359158 ps |
| CPU time | 327.29 seconds |
| Started | Jan 10 01:59:59 PM PST 24 |
| Finished | Jan 10 02:05:36 PM PST 24 |
| Peak memory | 602260 kb |
| Host | smart-21471737-cd86-4ba4-9058-ff662ec69544 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1967305423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1967305423 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.68658791 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4465777800 ps |
| CPU time | 346.99 seconds |
| Started | Jan 10 02:03:01 PM PST 24 |
| Finished | Jan 10 02:09:10 PM PST 24 |
| Peak memory | 608732 kb |
| Host | smart-b2dccbd7-f5ca-4bb7-8c91-ed2cfdb87a29 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=68658791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.68658791 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.131502761 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 8870854616 ps |
| CPU time | 1732.67 seconds |
| Started | Jan 10 01:58:55 PM PST 24 |
| Finished | Jan 10 02:27:52 PM PST 24 |
| Peak memory | 602864 kb |
| Host | smart-258c5a0c-bb62-4cb5-bba6-b0dc7b31690b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=131502761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.131502761 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.363628811 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 6871223930 ps |
| CPU time | 1279.58 seconds |
| Started | Jan 10 01:59:32 PM PST 24 |
| Finished | Jan 10 02:20:53 PM PST 24 |
| Peak memory | 602848 kb |
| Host | smart-fd6f0dd3-ab9a-4193-9c41-3a1811d4e420 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363628811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.363628811 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2393232699 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 9320521322 ps |
| CPU time | 933.18 seconds |
| Started | Jan 10 01:59:17 PM PST 24 |
| Finished | Jan 10 02:14:52 PM PST 24 |
| Peak memory | 603632 kb |
| Host | smart-1d0c6f1a-20d1-4d5b-b4bc-44fe3f725f1d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393232699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.2393232699 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3100016816 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 3717235474 ps |
| CPU time | 364.95 seconds |
| Started | Jan 10 01:59:03 PM PST 24 |
| Finished | Jan 10 02:05:09 PM PST 24 |
| Peak memory | 602268 kb |
| Host | smart-05b9280f-f98f-47f4-b22b-1dea63ea9504 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3100016816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3100016816 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1925839354 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 255018768262 ps |
| CPU time | 10383.4 seconds |
| Started | Jan 10 01:59:17 PM PST 24 |
| Finished | Jan 10 04:52:23 PM PST 24 |
| Peak memory | 603468 kb |
| Host | smart-24fb8cb3-ee03-498a-af41-5e157e6e8ab0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1925839354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1925839354 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.3334199182 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3489557036 ps |
| CPU time | 342.04 seconds |
| Started | Jan 10 01:59:08 PM PST 24 |
| Finished | Jan 10 02:04:52 PM PST 24 |
| Peak memory | 602796 kb |
| Host | smart-c573f656-b0e2-4e49-a6fb-7e07877c1c34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334199182 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.3334199182 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.1436880249 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 4801814440 ps |
| CPU time | 536.09 seconds |
| Started | Jan 10 01:58:00 PM PST 24 |
| Finished | Jan 10 02:07:10 PM PST 24 |
| Peak memory | 608856 kb |
| Host | smart-f1cc32ec-b9b0-4cd6-a1a8-7b4a60a121fd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1436880249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1436880249 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.3264877509 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 3813771966 ps |
| CPU time | 394.97 seconds |
| Started | Jan 10 02:00:36 PM PST 24 |
| Finished | Jan 10 02:07:13 PM PST 24 |
| Peak memory | 602024 kb |
| Host | smart-82122245-3692-4b8c-9ff9-dee5e84134d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264877509 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3264877509 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.270071295 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 6856261166 ps |
| CPU time | 469.13 seconds |
| Started | Jan 10 02:05:05 PM PST 24 |
| Finished | Jan 10 02:12:58 PM PST 24 |
| Peak memory | 603140 kb |
| Host | smart-85f7a0ad-3902-4f22-9aea-3049e235af3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=270071295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.270071295 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.350047236 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 2601192412 ps |
| CPU time | 281.92 seconds |
| Started | Jan 10 01:59:41 PM PST 24 |
| Finished | Jan 10 02:04:24 PM PST 24 |
| Peak memory | 602384 kb |
| Host | smart-8d303567-7884-49b7-b1d9-8724db78ed8a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350047236 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_aon_timer_smoketest.350047236 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.359754193 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 8834936950 ps |
| CPU time | 665.01 seconds |
| Started | Jan 10 02:04:48 PM PST 24 |
| Finished | Jan 10 02:16:03 PM PST 24 |
| Peak memory | 603220 kb |
| Host | smart-c8d3e646-28c3-4743-978b-7dba4f86e884 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 359754193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.359754193 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2494527406 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4689814122 ps |
| CPU time | 520.25 seconds |
| Started | Jan 10 02:03:46 PM PST 24 |
| Finished | Jan 10 02:12:42 PM PST 24 |
| Peak memory | 603396 kb |
| Host | smart-21214793-0495-428f-9d5e-cfc34e719bbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2494527406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2494527406 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.487206720 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 8005195042 ps |
| CPU time | 787.51 seconds |
| Started | Jan 10 01:58:57 PM PST 24 |
| Finished | Jan 10 02:12:08 PM PST 24 |
| Peak memory | 609832 kb |
| Host | smart-0369ea8a-9040-4b78-921f-3bec16451263 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487206720 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.487206720 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.329361089 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 10136712362 ps |
| CPU time | 769.12 seconds |
| Started | Jan 10 01:59:10 PM PST 24 |
| Finished | Jan 10 02:12:01 PM PST 24 |
| Peak memory | 604784 kb |
| Host | smart-449cc9ea-a525-44cc-ba50-1433725423ad |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=329361089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.329361089 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2923806422 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3964062472 ps |
| CPU time | 661.22 seconds |
| Started | Jan 10 01:59:52 PM PST 24 |
| Finished | Jan 10 02:10:59 PM PST 24 |
| Peak memory | 595256 kb |
| Host | smart-6bfdfa50-2bdc-4ca6-b36a-0b8b6261fdbd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923806422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2923806422 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3666325867 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 3492848016 ps |
| CPU time | 685.29 seconds |
| Started | Jan 10 01:58:37 PM PST 24 |
| Finished | Jan 10 02:10:14 PM PST 24 |
| Peak memory | 595320 kb |
| Host | smart-affb2e50-e91d-4923-a625-4045dffd0311 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666325867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3666325867 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3380376328 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4164475364 ps |
| CPU time | 533.34 seconds |
| Started | Jan 10 01:58:50 PM PST 24 |
| Finished | Jan 10 02:07:52 PM PST 24 |
| Peak memory | 595384 kb |
| Host | smart-a666925e-1de5-44de-a672-98737661953b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380376328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3380376328 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3051335295 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 5313920134 ps |
| CPU time | 642.58 seconds |
| Started | Jan 10 01:59:02 PM PST 24 |
| Finished | Jan 10 02:09:46 PM PST 24 |
| Peak memory | 595380 kb |
| Host | smart-d821f188-ba34-4ec9-880c-a126947cf868 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051335295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3051335295 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3953182966 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 4952058564 ps |
| CPU time | 536.34 seconds |
| Started | Jan 10 01:59:06 PM PST 24 |
| Finished | Jan 10 02:08:04 PM PST 24 |
| Peak memory | 595436 kb |
| Host | smart-f80a5404-dd27-4bbe-92ae-959b0899068c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953182966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3953182966 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1535611639 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 4924090344 ps |
| CPU time | 585.15 seconds |
| Started | Jan 10 01:59:27 PM PST 24 |
| Finished | Jan 10 02:09:14 PM PST 24 |
| Peak memory | 595260 kb |
| Host | smart-4093366a-d714-4ce3-8077-3bd079f0cd03 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535611639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1535611639 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2571870490 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 3088966092 ps |
| CPU time | 246.2 seconds |
| Started | Jan 10 02:01:22 PM PST 24 |
| Finished | Jan 10 02:05:34 PM PST 24 |
| Peak memory | 602060 kb |
| Host | smart-c125d936-ed01-44d2-b18c-81d8e65d4423 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571870490 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.2571870490 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2552652508 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3861722336 ps |
| CPU time | 458.87 seconds |
| Started | Jan 10 02:00:06 PM PST 24 |
| Finished | Jan 10 02:07:53 PM PST 24 |
| Peak memory | 602536 kb |
| Host | smart-e74bb4c4-f6d0-4916-9735-d2f270e02261 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552652508 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.2552652508 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2500347926 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 2791662502 ps |
| CPU time | 182.52 seconds |
| Started | Jan 10 02:00:28 PM PST 24 |
| Finished | Jan 10 02:03:35 PM PST 24 |
| Peak memory | 602080 kb |
| Host | smart-631875c4-2c3d-4170-a269-565b3a141470 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500347926 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2500347926 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2253804101 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 4873885560 ps |
| CPU time | 550.08 seconds |
| Started | Jan 10 01:58:32 PM PST 24 |
| Finished | Jan 10 02:07:45 PM PST 24 |
| Peak memory | 603256 kb |
| Host | smart-18350c9f-1069-416a-8f91-f6f7ca582655 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253804101 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2253804101 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.436523667 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 4772734838 ps |
| CPU time | 400.81 seconds |
| Started | Jan 10 01:59:49 PM PST 24 |
| Finished | Jan 10 02:06:38 PM PST 24 |
| Peak memory | 602864 kb |
| Host | smart-3242b012-90c1-4764-a409-a1558ca85337 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436523667 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.436523667 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3287497951 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 4371601740 ps |
| CPU time | 480.55 seconds |
| Started | Jan 10 01:58:59 PM PST 24 |
| Finished | Jan 10 02:07:02 PM PST 24 |
| Peak memory | 602832 kb |
| Host | smart-889fe75f-ef78-4ce4-8811-eaba707a16c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287497951 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.3287497951 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.56274909 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 6132354520 ps |
| CPU time | 561.1 seconds |
| Started | Jan 10 01:59:06 PM PST 24 |
| Finished | Jan 10 02:08:28 PM PST 24 |
| Peak memory | 603128 kb |
| Host | smart-dc95e43e-d0a6-4adf-a4f6-bfb523ab7e58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56274909 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.56274909 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.706793172 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 12914505624 ps |
| CPU time | 1139.47 seconds |
| Started | Jan 10 01:59:46 PM PST 24 |
| Finished | Jan 10 02:18:52 PM PST 24 |
| Peak memory | 603292 kb |
| Host | smart-78b1b768-fb92-4564-9973-62cf592fa47f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706793172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.706793172 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3409800566 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 3078816952 ps |
| CPU time | 416.28 seconds |
| Started | Jan 10 02:00:16 PM PST 24 |
| Finished | Jan 10 02:07:15 PM PST 24 |
| Peak memory | 602628 kb |
| Host | smart-74e941bc-15a4-4ee0-a42f-24d735ba582c |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409800566 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3409800566 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.4016503723 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 4551781160 ps |
| CPU time | 520.19 seconds |
| Started | Jan 10 02:00:08 PM PST 24 |
| Finished | Jan 10 02:08:56 PM PST 24 |
| Peak memory | 602884 kb |
| Host | smart-0798c757-eab0-4b55-b208-6be5b4455ff0 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016503723 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.4016503723 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.326232118 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 2992501980 ps |
| CPU time | 204.23 seconds |
| Started | Jan 10 02:00:00 PM PST 24 |
| Finished | Jan 10 02:03:33 PM PST 24 |
| Peak memory | 590368 kb |
| Host | smart-8d0e51d4-ff37-45f0-b6ce-6eeb914840ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326232118 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_clkmgr_smoketest.326232118 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1351200494 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 7418369790 ps |
| CPU time | 1654.63 seconds |
| Started | Jan 10 01:58:34 PM PST 24 |
| Finished | Jan 10 02:26:19 PM PST 24 |
| Peak memory | 602972 kb |
| Host | smart-7152b6a6-f62f-43d1-acf5-06b7fd969d7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351200494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1351200494 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3214687368 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 4844495880 ps |
| CPU time | 411.58 seconds |
| Started | Jan 10 01:59:49 PM PST 24 |
| Finished | Jan 10 02:06:49 PM PST 24 |
| Peak memory | 603656 kb |
| Host | smart-c73caa82-dff2-4d88-8032-60629441d8db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146 87368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3214687368 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.1514762 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2633172680 ps |
| CPU time | 208.13 seconds |
| Started | Jan 10 02:02:03 PM PST 24 |
| Finished | Jan 10 02:05:34 PM PST 24 |
| Peak memory | 602436 kb |
| Host | smart-2720aa20-2459-4978-8fa9-a63ada02d79b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.1514762 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2223241757 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 7144221000 ps |
| CPU time | 607.72 seconds |
| Started | Jan 10 01:59:36 PM PST 24 |
| Finished | Jan 10 02:09:45 PM PST 24 |
| Peak memory | 603892 kb |
| Host | smart-f84e4c97-d5b7-475f-87c3-52c4ce90e88f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223241757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.2223241757 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.3485619366 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 3171235686 ps |
| CPU time | 204.68 seconds |
| Started | Jan 10 02:00:11 PM PST 24 |
| Finished | Jan 10 02:03:42 PM PST 24 |
| Peak memory | 602420 kb |
| Host | smart-b38bc7dc-1300-40dd-858a-e681022dc226 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485619366 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.3485619366 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3338209382 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 4075225544 ps |
| CPU time | 609.07 seconds |
| Started | Jan 10 01:58:49 PM PST 24 |
| Finished | Jan 10 02:09:07 PM PST 24 |
| Peak memory | 602580 kb |
| Host | smart-330068dd-dfe4-47ae-b541-f93a677c6d78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338209382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3338209382 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.3994902463 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3080123888 ps |
| CPU time | 464.44 seconds |
| Started | Jan 10 01:59:16 PM PST 24 |
| Finished | Jan 10 02:07:02 PM PST 24 |
| Peak memory | 602752 kb |
| Host | smart-0fe1e7d4-32ec-4a54-859e-ac6b4ca8a2ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994902463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.3994902463 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1387825872 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4167090100 ps |
| CPU time | 582.41 seconds |
| Started | Jan 10 01:58:57 PM PST 24 |
| Finished | Jan 10 02:08:43 PM PST 24 |
| Peak memory | 602660 kb |
| Host | smart-f36fdd96-711f-4fc5-aace-1a53349dc84b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1387825872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1387825872 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2393937885 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 5585796203 ps |
| CPU time | 873.63 seconds |
| Started | Jan 10 02:01:48 PM PST 24 |
| Finished | Jan 10 02:16:23 PM PST 24 |
| Peak memory | 602888 kb |
| Host | smart-c6cc5880-1aa4-46c3-a59b-6a2c5dddae68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393937885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2393937885 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.3872705852 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3515568438 ps |
| CPU time | 627.57 seconds |
| Started | Jan 10 01:59:12 PM PST 24 |
| Finished | Jan 10 02:09:41 PM PST 24 |
| Peak memory | 608524 kb |
| Host | smart-e37658ce-b5a5-47f3-9ec9-564b1e62d89d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872705852 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.3872705852 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.4006478378 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 5022989170 ps |
| CPU time | 901.93 seconds |
| Started | Jan 10 02:00:08 PM PST 24 |
| Finished | Jan 10 02:15:18 PM PST 24 |
| Peak memory | 602712 kb |
| Host | smart-7c858abb-adef-436c-ab86-76bb1960e633 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006478378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.4006478378 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2759262912 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 2256690866 ps |
| CPU time | 165.08 seconds |
| Started | Jan 10 01:59:58 PM PST 24 |
| Finished | Jan 10 02:02:53 PM PST 24 |
| Peak memory | 602324 kb |
| Host | smart-5a45ae92-be57-440b-8be0-09c2f840ed89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27 59262912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2759262912 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3866312044 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8150163016 ps |
| CPU time | 1432.69 seconds |
| Started | Jan 10 02:00:10 PM PST 24 |
| Finished | Jan 10 02:24:10 PM PST 24 |
| Peak memory | 603096 kb |
| Host | smart-af2cba5b-93bf-4e96-9b48-092cbaf33aa4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3866312044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.3866312044 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_fuse_en_fw_read_test.3734917758 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 4355720270 ps |
| CPU time | 463.52 seconds |
| Started | Jan 10 01:59:45 PM PST 24 |
| Finished | Jan 10 02:07:31 PM PST 24 |
| Peak memory | 603108 kb |
| Host | smart-2f27679a-d628-4994-bb91-be8d7acfec6c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18000000 +sw_build_device=sim_dv +sw_images=entropy_src_fuse_en_fw_read_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3734917758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_fuse_en_fw_read_test.3734917758 |
| Directory | /workspace/2.chip_sw_entropy_src_fuse_en_fw_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.4209371989 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 3017877400 ps |
| CPU time | 205.05 seconds |
| Started | Jan 10 01:59:46 PM PST 24 |
| Finished | Jan 10 02:03:12 PM PST 24 |
| Peak memory | 602432 kb |
| Host | smart-88f50887-96d8-4aea-9880-8c08731d55f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209371989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.4209371989 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2696484703 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 3816851144 ps |
| CPU time | 394.61 seconds |
| Started | Jan 10 01:59:59 PM PST 24 |
| Finished | Jan 10 02:06:43 PM PST 24 |
| Peak memory | 602396 kb |
| Host | smart-138f3d59-2831-4d95-b0a4-be3ca4438401 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2696484703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2696484703 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.696285925 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2780742408 ps |
| CPU time | 241.04 seconds |
| Started | Jan 10 02:02:21 PM PST 24 |
| Finished | Jan 10 02:06:33 PM PST 24 |
| Peak memory | 602404 kb |
| Host | smart-7ef4f750-2b3c-4163-8085-216f4ff0d3c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696285925 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_concurrency.696285925 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.3624388769 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2676286824 ps |
| CPU time | 200.69 seconds |
| Started | Jan 10 01:55:46 PM PST 24 |
| Finished | Jan 10 01:59:08 PM PST 24 |
| Peak memory | 602408 kb |
| Host | smart-b1333210-27f6-4ac4-ac78-94203c6246db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624388769 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.3624388769 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.1373196247 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2867488480 ps |
| CPU time | 237.28 seconds |
| Started | Jan 10 01:57:06 PM PST 24 |
| Finished | Jan 10 02:01:05 PM PST 24 |
| Peak memory | 601932 kb |
| Host | smart-07fbbcba-24af-4daa-ae09-9f6b1a4861df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373196247 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.1373196247 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.628147744 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 2109001360 ps |
| CPU time | 121.53 seconds |
| Started | Jan 10 01:59:35 PM PST 24 |
| Finished | Jan 10 02:01:37 PM PST 24 |
| Peak memory | 601300 kb |
| Host | smart-c4501ee6-0fb1-424a-b4d3-86f880d58138 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628147744 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_example_rom.628147744 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1382095195 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 60711327561 ps |
| CPU time | 9775.09 seconds |
| Started | Jan 10 02:02:12 PM PST 24 |
| Finished | Jan 10 04:45:18 PM PST 24 |
| Peak memory | 616888 kb |
| Host | smart-374ecd80-9c0b-466c-8b4d-fbc797cf99de |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1382095195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1382095195 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.348782366 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 5953109040 ps |
| CPU time | 472.59 seconds |
| Started | Jan 10 02:00:52 PM PST 24 |
| Finished | Jan 10 02:08:47 PM PST 24 |
| Peak memory | 604020 kb |
| Host | smart-667c795f-d759-4e23-88c7-a4745280ef4e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=348782366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.348782366 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1012942621 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 5673893452 ps |
| CPU time | 1039.95 seconds |
| Started | Jan 10 02:03:44 PM PST 24 |
| Finished | Jan 10 02:21:21 PM PST 24 |
| Peak memory | 602356 kb |
| Host | smart-b99a8a67-411c-4182-90ec-b8b07c616b27 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012942621 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.1012942621 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3213243636 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 5682049679 ps |
| CPU time | 869.21 seconds |
| Started | Jan 10 02:02:40 PM PST 24 |
| Finished | Jan 10 02:17:59 PM PST 24 |
| Peak memory | 602852 kb |
| Host | smart-3a4bd6dd-0f84-44c6-a9f1-22094dbf6347 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213243636 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.3213243636 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1739472392 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 7429803041 ps |
| CPU time | 853.49 seconds |
| Started | Jan 10 02:00:44 PM PST 24 |
| Finished | Jan 10 02:14:59 PM PST 24 |
| Peak memory | 602868 kb |
| Host | smart-77a396e2-7ff6-4ef9-a5b3-3bc46ebdff99 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739472392 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1739472392 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3719293479 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 5887485822 ps |
| CPU time | 908.74 seconds |
| Started | Jan 10 01:56:40 PM PST 24 |
| Finished | Jan 10 02:11:56 PM PST 24 |
| Peak memory | 602396 kb |
| Host | smart-100b7bb0-cb67-4973-9b15-9c8f842cd981 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719293479 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.3719293479 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.4166155247 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 3239691680 ps |
| CPU time | 421.06 seconds |
| Started | Jan 10 02:04:49 PM PST 24 |
| Finished | Jan 10 02:12:00 PM PST 24 |
| Peak memory | 602372 kb |
| Host | smart-5925471c-1d7f-4a4d-9f64-7a528eb66a1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166155247 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.4166155247 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3129520481 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5643867903 ps |
| CPU time | 561.95 seconds |
| Started | Jan 10 02:04:53 PM PST 24 |
| Finished | Jan 10 02:14:23 PM PST 24 |
| Peak memory | 603116 kb |
| Host | smart-41d4b913-fb45-4ee6-bc34-024880df6fa0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31 29520481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.3129520481 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3852519995 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 5589312404 ps |
| CPU time | 793.43 seconds |
| Started | Jan 10 01:57:04 PM PST 24 |
| Finished | Jan 10 02:10:18 PM PST 24 |
| Peak memory | 602784 kb |
| Host | smart-385eddc3-fd24-4a45-98fa-6d24aab194d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852519995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.3852519995 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.673799477 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 5430675574 ps |
| CPU time | 686.6 seconds |
| Started | Jan 10 01:58:27 PM PST 24 |
| Finished | Jan 10 02:09:55 PM PST 24 |
| Peak memory | 602992 kb |
| Host | smart-56e7f8dd-3fc5-4beb-a31d-744c95235f7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=673799477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.673799477 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2155993285 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 5927047955 ps |
| CPU time | 716.55 seconds |
| Started | Jan 10 02:05:01 PM PST 24 |
| Finished | Jan 10 02:17:04 PM PST 24 |
| Peak memory | 602836 kb |
| Host | smart-80b71497-229b-4b0d-bd4b-cc8996480ebd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2155993285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2155993285 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.1273368448 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 25303300100 ps |
| CPU time | 1559.55 seconds |
| Started | Jan 10 02:03:26 PM PST 24 |
| Finished | Jan 10 02:29:57 PM PST 24 |
| Peak memory | 603088 kb |
| Host | smart-ab7222ed-b409-4c68-92c7-ff4fa8e2b10c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273368448 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.1273368448 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3197901225 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2375251062 ps |
| CPU time | 156.19 seconds |
| Started | Jan 10 02:08:19 PM PST 24 |
| Finished | Jan 10 02:10:58 PM PST 24 |
| Peak memory | 601980 kb |
| Host | smart-a258d911-b641-4c76-b9f3-08603231bf53 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3197901225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.3197901225 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.1291043824 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 2937505309 ps |
| CPU time | 201.42 seconds |
| Started | Jan 10 01:59:14 PM PST 24 |
| Finished | Jan 10 02:02:38 PM PST 24 |
| Peak memory | 602740 kb |
| Host | smart-ce740446-e017-429d-87a6-4822a167b457 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291043824 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.1291043824 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.3846190235 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 3008657246 ps |
| CPU time | 261.58 seconds |
| Started | Jan 10 02:00:30 PM PST 24 |
| Finished | Jan 10 02:04:54 PM PST 24 |
| Peak memory | 602428 kb |
| Host | smart-0373634f-bb35-4638-a2fe-1269f8901aea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846190235 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3846190235 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2397112609 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2980097800 ps |
| CPU time | 190.24 seconds |
| Started | Jan 10 02:00:23 PM PST 24 |
| Finished | Jan 10 02:03:34 PM PST 24 |
| Peak memory | 602048 kb |
| Host | smart-475f113d-32e5-4f42-94b1-4bb1206b56dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397112609 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.2397112609 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.137776109 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 2655576481 ps |
| CPU time | 254.53 seconds |
| Started | Jan 10 02:00:00 PM PST 24 |
| Finished | Jan 10 02:04:24 PM PST 24 |
| Peak memory | 602540 kb |
| Host | smart-c3997b4f-1d3f-4673-a37a-a8dcec90c4b0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137776109 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.137776109 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.268252342 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3119428872 ps |
| CPU time | 269.9 seconds |
| Started | Jan 10 02:04:51 PM PST 24 |
| Finished | Jan 10 02:09:31 PM PST 24 |
| Peak memory | 602472 kb |
| Host | smart-cf62b1bc-8516-40bb-b59d-e67b261a6f89 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268252342 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.268252342 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.658525505 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 3246753846 ps |
| CPU time | 369.23 seconds |
| Started | Jan 10 02:05:26 PM PST 24 |
| Finished | Jan 10 02:11:39 PM PST 24 |
| Peak memory | 602128 kb |
| Host | smart-8ab7bca4-50bf-4915-ad3e-832aa471d626 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658525505 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_smoketest.658525505 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2199302690 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4296067884 ps |
| CPU time | 601.55 seconds |
| Started | Jan 10 02:02:57 PM PST 24 |
| Finished | Jan 10 02:13:24 PM PST 24 |
| Peak memory | 603236 kb |
| Host | smart-b70a5876-36ff-48b8-8a8c-dd2583744cab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199302690 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2199302690 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.150860010 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4583173544 ps |
| CPU time | 799.95 seconds |
| Started | Jan 10 02:02:55 PM PST 24 |
| Finished | Jan 10 02:16:42 PM PST 24 |
| Peak memory | 602904 kb |
| Host | smart-a0974f78-3e61-410f-a43a-5ebfafd45fc8 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150860010 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.150860010 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1912228861 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 5098531200 ps |
| CPU time | 749.14 seconds |
| Started | Jan 10 02:02:14 PM PST 24 |
| Finished | Jan 10 02:14:53 PM PST 24 |
| Peak memory | 602516 kb |
| Host | smart-90ddc3f9-ae5a-49b0-80bd-f22bbfbc5f2b |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912228861 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.1912228861 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2713413947 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 5310954162 ps |
| CPU time | 806.26 seconds |
| Started | Jan 10 01:58:05 PM PST 24 |
| Finished | Jan 10 02:11:41 PM PST 24 |
| Peak memory | 602608 kb |
| Host | smart-32c8c054-d5f2-4bb8-81db-5622744b4b0f |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713413947 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.2713413947 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2022231371 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 67414280768 ps |
| CPU time | 11169.5 seconds |
| Started | Jan 10 01:56:38 PM PST 24 |
| Finished | Jan 10 05:02:58 PM PST 24 |
| Peak memory | 617420 kb |
| Host | smart-60fd4698-4ec3-481b-a35c-507f0f9e0ff1 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2022231371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2022231371 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2519535156 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4251003978 ps |
| CPU time | 440.97 seconds |
| Started | Jan 10 02:00:07 PM PST 24 |
| Finished | Jan 10 02:07:36 PM PST 24 |
| Peak memory | 610200 kb |
| Host | smart-7c5d931b-2024-4362-a70d-063f5b969eb6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519 535156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2519535156 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2949629248 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3960229454 ps |
| CPU time | 391.09 seconds |
| Started | Jan 10 02:00:08 PM PST 24 |
| Finished | Jan 10 02:06:47 PM PST 24 |
| Peak memory | 610536 kb |
| Host | smart-534220ab-1e09-4d53-a350-29744e4f028f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2949629248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2949629248 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2144959221 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 5702914481 ps |
| CPU time | 506.03 seconds |
| Started | Jan 10 02:00:54 PM PST 24 |
| Finished | Jan 10 02:09:22 PM PST 24 |
| Peak memory | 610384 kb |
| Host | smart-b0efaa2b-b78d-472c-9949-4fb1ae0c95ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2144959221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2144959221 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.4209459210 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 3210868174 ps |
| CPU time | 413.42 seconds |
| Started | Jan 10 01:59:49 PM PST 24 |
| Finished | Jan 10 02:06:51 PM PST 24 |
| Peak memory | 610152 kb |
| Host | smart-0186bb8c-b088-4967-89fe-a0e75e824e1f |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4209459210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.4209459210 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1459860532 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 4050294508 ps |
| CPU time | 483.47 seconds |
| Started | Jan 10 01:59:47 PM PST 24 |
| Finished | Jan 10 02:07:59 PM PST 24 |
| Peak memory | 603736 kb |
| Host | smart-d84dcfa3-6237-499d-83dd-39d7eba2d5d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145986 0532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1459860532 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1403398641 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 4361370370 ps |
| CPU time | 468.93 seconds |
| Started | Jan 10 01:58:52 PM PST 24 |
| Finished | Jan 10 02:06:48 PM PST 24 |
| Peak memory | 604196 kb |
| Host | smart-7a05a8d0-2bf0-478b-989f-b4a64143609e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14033 98641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.1403398641 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2890338860 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 10599419922 ps |
| CPU time | 2370.78 seconds |
| Started | Jan 10 02:03:52 PM PST 24 |
| Finished | Jan 10 02:43:35 PM PST 24 |
| Peak memory | 603712 kb |
| Host | smart-6261161d-4136-4e85-b968-c06023679511 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28903 38860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2890338860 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.1943115480 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2342358530 ps |
| CPU time | 261.77 seconds |
| Started | Jan 10 02:01:22 PM PST 24 |
| Finished | Jan 10 02:05:50 PM PST 24 |
| Peak memory | 602060 kb |
| Host | smart-51cf7e21-5b3e-426e-9334-69f7f9c12fa3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943115480 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.1943115480 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.558804547 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 3394823480 ps |
| CPU time | 294.46 seconds |
| Started | Jan 10 01:57:34 PM PST 24 |
| Finished | Jan 10 02:02:30 PM PST 24 |
| Peak memory | 602008 kb |
| Host | smart-f3d1f322-e2fc-4650-b55b-b313734a8e89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558804547 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_entropy.558804547 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.2895204994 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 2972783848 ps |
| CPU time | 313.53 seconds |
| Started | Jan 10 02:02:08 PM PST 24 |
| Finished | Jan 10 02:07:32 PM PST 24 |
| Peak memory | 590364 kb |
| Host | smart-c9f621d2-75de-4c7d-b4af-aa9086bfdda6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895204994 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.2895204994 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.289530723 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 2889889382 ps |
| CPU time | 192.01 seconds |
| Started | Jan 10 02:03:15 PM PST 24 |
| Finished | Jan 10 02:06:59 PM PST 24 |
| Peak memory | 602456 kb |
| Host | smart-766403d4-d63f-43a9-ad0e-d6b6af873720 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289530723 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_kmac_mode_cshake.289530723 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2258756245 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2829876040 ps |
| CPU time | 275.41 seconds |
| Started | Jan 10 02:02:12 PM PST 24 |
| Finished | Jan 10 02:06:57 PM PST 24 |
| Peak memory | 602084 kb |
| Host | smart-49cd27e6-5bf5-4611-aeb4-cb72ef80b471 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258756245 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.2258756245 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2442388856 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 2645792679 ps |
| CPU time | 271.69 seconds |
| Started | Jan 10 02:00:17 PM PST 24 |
| Finished | Jan 10 02:04:51 PM PST 24 |
| Peak memory | 602432 kb |
| Host | smart-d6955bb2-e483-463a-a1a5-b6661fb0cb6a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442388856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.2442388856 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2444370109 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 3339843926 ps |
| CPU time | 261.95 seconds |
| Started | Jan 10 02:04:21 PM PST 24 |
| Finished | Jan 10 02:08:46 PM PST 24 |
| Peak memory | 602364 kb |
| Host | smart-1dd383b1-a030-41d2-b486-f672ebd67d10 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24443701 09 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2444370109 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.2966655276 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2668041434 ps |
| CPU time | 215.53 seconds |
| Started | Jan 10 01:59:50 PM PST 24 |
| Finished | Jan 10 02:03:33 PM PST 24 |
| Peak memory | 602416 kb |
| Host | smart-010149de-38f7-4e2e-ae6e-0e0d2a910cc9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966655276 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.2966655276 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg.4258808010 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2721930588 ps |
| CPU time | 229.63 seconds |
| Started | Jan 10 02:04:21 PM PST 24 |
| Finished | Jan 10 02:08:13 PM PST 24 |
| Peak memory | 602304 kb |
| Host | smart-6de594dc-ae94-4b7c-8629-90e4fcef9db9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258808010 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg.4258808010 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.326756700 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 5133240040 ps |
| CPU time | 464.34 seconds |
| Started | Jan 10 02:00:09 PM PST 24 |
| Finished | Jan 10 02:08:00 PM PST 24 |
| Peak memory | 616456 kb |
| Host | smart-86fa82c9-2d76-4cca-9767-e8730dfe2aa3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=326756700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.326756700 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4081641000 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3274066425 ps |
| CPU time | 146.26 seconds |
| Started | Jan 10 01:57:12 PM PST 24 |
| Finished | Jan 10 01:59:40 PM PST 24 |
| Peak memory | 602716 kb |
| Host | smart-b5af0f6e-cb9f-4234-87da-8aba7394013f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40816410 00 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.4081641000 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1182374882 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 6046337583 ps |
| CPU time | 386.06 seconds |
| Started | Jan 10 02:03:29 PM PST 24 |
| Finished | Jan 10 02:10:24 PM PST 24 |
| Peak memory | 603752 kb |
| Host | smart-13a1fff8-d435-4dab-8195-67125f2c51da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182374882 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.1182374882 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2528480836 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 4577295666 ps |
| CPU time | 278.64 seconds |
| Started | Jan 10 02:04:11 PM PST 24 |
| Finished | Jan 10 02:08:52 PM PST 24 |
| Peak memory | 608552 kb |
| Host | smart-e242d81a-f80b-4697-8fef-92ad8ccf06f4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2528480836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.2528480836 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1707401789 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 3896087623 ps |
| CPU time | 240.54 seconds |
| Started | Jan 10 02:04:17 PM PST 24 |
| Finished | Jan 10 02:08:20 PM PST 24 |
| Peak memory | 601596 kb |
| Host | smart-9f0e5a8e-993e-4413-9bf7-5f4e438ce9da |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=lc_ctrl_volat ile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707401789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_ unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_vol atile_raw_unlock_ext_clk_48mhz.1707401789 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2131332309 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 26260728032 ps |
| CPU time | 1868.01 seconds |
| Started | Jan 10 02:04:51 PM PST 24 |
| Finished | Jan 10 02:36:09 PM PST 24 |
| Peak memory | 602576 kb |
| Host | smart-e3e835b7-3e24-453a-8f9f-328399628f32 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2131332309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.2131332309 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.345614157 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 16988849882 ps |
| CPU time | 2823.22 seconds |
| Started | Jan 10 01:58:37 PM PST 24 |
| Finished | Jan 10 02:45:52 PM PST 24 |
| Peak memory | 602620 kb |
| Host | smart-d69e0574-32e0-4532-9df9-c5de5c09dc41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=345614157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.345614157 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3832165983 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 18867890823 ps |
| CPU time | 3079.71 seconds |
| Started | Jan 10 02:00:03 PM PST 24 |
| Finished | Jan 10 02:51:30 PM PST 24 |
| Peak memory | 602876 kb |
| Host | smart-e9d781fe-143b-412c-bb78-cb019183bb0e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3832165983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3832165983 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.222993116 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 4294723816 ps |
| CPU time | 402.48 seconds |
| Started | Jan 10 01:58:31 PM PST 24 |
| Finished | Jan 10 02:05:15 PM PST 24 |
| Peak memory | 602800 kb |
| Host | smart-7c1c4704-6e94-41f4-9295-41b51c9c08fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222993116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.222993116 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.2368633908 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 5831205672 ps |
| CPU time | 518.06 seconds |
| Started | Jan 10 02:00:01 PM PST 24 |
| Finished | Jan 10 02:08:48 PM PST 24 |
| Peak memory | 590440 kb |
| Host | smart-3057f9ac-53d0-42bd-96d7-3770b767c52a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2368633908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.2368633908 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.923112850 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 10032895600 ps |
| CPU time | 1926.95 seconds |
| Started | Jan 10 02:00:08 PM PST 24 |
| Finished | Jan 10 02:32:23 PM PST 24 |
| Peak memory | 602876 kb |
| Host | smart-62987beb-970b-4aee-afc3-2033f7b4ac8b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923112850 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_smoketest.923112850 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.846953677 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 7345109888 ps |
| CPU time | 983.23 seconds |
| Started | Jan 10 02:04:57 PM PST 24 |
| Finished | Jan 10 02:21:26 PM PST 24 |
| Peak memory | 603428 kb |
| Host | smart-039364cd-4820-4826-8193-25913910fb80 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=846953677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.846953677 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3955375476 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 9762068132 ps |
| CPU time | 1169.54 seconds |
| Started | Jan 10 02:02:22 PM PST 24 |
| Finished | Jan 10 02:22:03 PM PST 24 |
| Peak memory | 603184 kb |
| Host | smart-8b00ef52-9b48-42ae-9327-279cd6b23f95 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3955375476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.3955375476 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.492582744 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 7423679962 ps |
| CPU time | 952.79 seconds |
| Started | Jan 10 02:03:22 PM PST 24 |
| Finished | Jan 10 02:19:48 PM PST 24 |
| Peak memory | 603568 kb |
| Host | smart-624b9583-fd7d-4f3c-99d5-489ec55c8ad7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=492582744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.492582744 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.781849009 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 4367890072 ps |
| CPU time | 568.44 seconds |
| Started | Jan 10 02:04:53 PM PST 24 |
| Finished | Jan 10 02:14:30 PM PST 24 |
| Peak memory | 602828 kb |
| Host | smart-21c0eb1c-3a4d-4031-a409-efb3cb207cbb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=781849009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.781849009 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.870025392 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 3319378420 ps |
| CPU time | 314.15 seconds |
| Started | Jan 10 01:59:21 PM PST 24 |
| Finished | Jan 10 02:04:36 PM PST 24 |
| Peak memory | 602452 kb |
| Host | smart-c7b3cbd6-b973-4f49-8839-2e14c329e7bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870025392 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_otp_ctrl_smoketest.870025392 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.4072042927 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 3040070972 ps |
| CPU time | 219.17 seconds |
| Started | Jan 10 01:59:53 PM PST 24 |
| Finished | Jan 10 02:03:37 PM PST 24 |
| Peak memory | 602036 kb |
| Host | smart-d92de0b3-4aa0-4d2a-a139-09cc44966573 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072042927 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.4072042927 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.188490722 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 4076630080 ps |
| CPU time | 652.25 seconds |
| Started | Jan 10 01:58:33 PM PST 24 |
| Finished | Jan 10 02:09:28 PM PST 24 |
| Peak memory | 602844 kb |
| Host | smart-72db7f26-7a8d-49b6-baa7-5d9f1ebfdeb1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188490722 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.188490722 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.2552361466 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4662770608 ps |
| CPU time | 470.03 seconds |
| Started | Jan 10 02:01:38 PM PST 24 |
| Finished | Jan 10 02:09:32 PM PST 24 |
| Peak memory | 603208 kb |
| Host | smart-767a8a18-fdec-4f2d-908e-f821fe63c644 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552361466 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.2552361466 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1435845758 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 10945968952 ps |
| CPU time | 1535.88 seconds |
| Started | Jan 10 02:03:52 PM PST 24 |
| Finished | Jan 10 02:29:40 PM PST 24 |
| Peak memory | 604180 kb |
| Host | smart-3f66f387-49fd-40d4-af0b-a99786f02abd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435 845758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1435845758 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2393420888 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 22359240196 ps |
| CPU time | 2339.64 seconds |
| Started | Jan 10 01:58:35 PM PST 24 |
| Finished | Jan 10 02:37:44 PM PST 24 |
| Peak memory | 603208 kb |
| Host | smart-4bbaf9df-990a-4603-acd7-6d366640661c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239 3420888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2393420888 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1622421233 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 13786912699 ps |
| CPU time | 1133.84 seconds |
| Started | Jan 10 02:04:30 PM PST 24 |
| Finished | Jan 10 02:23:28 PM PST 24 |
| Peak memory | 604108 kb |
| Host | smart-850e1648-52dd-44a4-a0ae-e6f6ca0c3ea5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1622421233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1622421233 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.792685096 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 21136777492 ps |
| CPU time | 1166 seconds |
| Started | Jan 10 01:59:27 PM PST 24 |
| Finished | Jan 10 02:18:55 PM PST 24 |
| Peak memory | 591504 kb |
| Host | smart-3087aca0-9f0d-48cf-b963-b2ad00b66639 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 792685096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.792685096 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1219647156 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 9629150552 ps |
| CPU time | 830.4 seconds |
| Started | Jan 10 02:03:36 PM PST 24 |
| Finished | Jan 10 02:17:50 PM PST 24 |
| Peak memory | 603540 kb |
| Host | smart-8ae3e60c-835d-4e9c-9f60-00912b5db736 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219647156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.1219647156 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3577995627 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 5533869426 ps |
| CPU time | 562.65 seconds |
| Started | Jan 10 02:03:22 PM PST 24 |
| Finished | Jan 10 02:13:17 PM PST 24 |
| Peak memory | 609744 kb |
| Host | smart-83b2b189-5098-4702-a947-65e13ca069be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3577995627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3577995627 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2458277261 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 10131356522 ps |
| CPU time | 477.2 seconds |
| Started | Jan 10 02:03:20 PM PST 24 |
| Finished | Jan 10 02:11:50 PM PST 24 |
| Peak memory | 603552 kb |
| Host | smart-b9677f45-45a3-48e5-b734-61264d021e37 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458277261 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.2458277261 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.939271122 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 3068649495 ps |
| CPU time | 290.54 seconds |
| Started | Jan 10 02:04:10 PM PST 24 |
| Finished | Jan 10 02:09:03 PM PST 24 |
| Peak memory | 609668 kb |
| Host | smart-8121a337-ccd8-40c6-bcfb-df533490e6f5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=939271122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.939271122 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1540579646 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 13404165038 ps |
| CPU time | 1159.48 seconds |
| Started | Jan 10 01:56:28 PM PST 24 |
| Finished | Jan 10 02:15:48 PM PST 24 |
| Peak memory | 592092 kb |
| Host | smart-15bdbb2b-9613-47b2-8475-7b6000669fdd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540579646 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1540579646 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3867164085 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 7285890688 ps |
| CPU time | 395.38 seconds |
| Started | Jan 10 01:59:13 PM PST 24 |
| Finished | Jan 10 02:05:51 PM PST 24 |
| Peak memory | 603004 kb |
| Host | smart-e78cd213-9724-418d-a306-cabbb87a25e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867164085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3867164085 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3623377131 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 6252536064 ps |
| CPU time | 506.81 seconds |
| Started | Jan 10 02:03:53 PM PST 24 |
| Finished | Jan 10 02:12:31 PM PST 24 |
| Peak memory | 591276 kb |
| Host | smart-94c81382-af6f-4edf-b6ad-6eb05ed4a130 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623377131 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3623377131 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3862382308 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 23450688904 ps |
| CPU time | 2039.48 seconds |
| Started | Jan 10 02:04:26 PM PST 24 |
| Finished | Jan 10 02:38:28 PM PST 24 |
| Peak memory | 603840 kb |
| Host | smart-6c2fe55a-e9b2-44c1-8e1b-491896162d4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3862382308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3862382308 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3834319490 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 25380630130 ps |
| CPU time | 1678.29 seconds |
| Started | Jan 10 02:00:32 PM PST 24 |
| Finished | Jan 10 02:28:32 PM PST 24 |
| Peak memory | 603660 kb |
| Host | smart-8c57add4-219c-4d41-9d70-d636bdc20ea8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3834319490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3834319490 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2023133923 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 35755764837 ps |
| CPU time | 2875.54 seconds |
| Started | Jan 10 02:04:54 PM PST 24 |
| Finished | Jan 10 02:52:57 PM PST 24 |
| Peak memory | 604572 kb |
| Host | smart-6b3b6ef8-45ea-4499-be67-b7bd731e3913 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023133923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2023133923 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.237371450 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2875309800 ps |
| CPU time | 298.41 seconds |
| Started | Jan 10 02:00:07 PM PST 24 |
| Finished | Jan 10 02:05:14 PM PST 24 |
| Peak memory | 602004 kb |
| Host | smart-cb5dc0b9-4448-4a54-9391-2ada29a403a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237371450 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.237371450 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1748643958 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 4046485260 ps |
| CPU time | 424.01 seconds |
| Started | Jan 10 02:04:48 PM PST 24 |
| Finished | Jan 10 02:12:02 PM PST 24 |
| Peak memory | 609736 kb |
| Host | smart-79ae0552-e95b-43d4-83c8-0d5ff80296ff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1748643958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1748643958 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3880983532 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 5310963592 ps |
| CPU time | 396.9 seconds |
| Started | Jan 10 01:58:52 PM PST 24 |
| Finished | Jan 10 02:05:36 PM PST 24 |
| Peak memory | 602592 kb |
| Host | smart-07eaaea6-079e-4f5c-94aa-4272dea795b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809835 32 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3880983532 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.582517419 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 6011738758 ps |
| CPU time | 446.13 seconds |
| Started | Jan 10 02:00:45 PM PST 24 |
| Finished | Jan 10 02:08:13 PM PST 24 |
| Peak memory | 603224 kb |
| Host | smart-43465765-b7eb-4fc2-aae7-4da23f5e47f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582517419 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.582517419 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2813291768 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 7800138310 ps |
| CPU time | 871.48 seconds |
| Started | Jan 10 02:04:52 PM PST 24 |
| Finished | Jan 10 02:19:33 PM PST 24 |
| Peak memory | 603264 kb |
| Host | smart-bc375edd-fc9a-4746-bac0-325694f37061 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813291768 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2813291768 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2639298376 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3788510770 ps |
| CPU time | 365.48 seconds |
| Started | Jan 10 02:05:00 PM PST 24 |
| Finished | Jan 10 02:11:13 PM PST 24 |
| Peak memory | 602896 kb |
| Host | smart-79935c88-68b5-499e-a6c9-553b0171edf5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639298376 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2639298376 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1466101056 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 5590247912 ps |
| CPU time | 352.89 seconds |
| Started | Jan 10 01:59:55 PM PST 24 |
| Finished | Jan 10 02:05:55 PM PST 24 |
| Peak memory | 603140 kb |
| Host | smart-5c63a1d4-9c73-4afe-9c95-42cad1b88f79 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466101056 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1466101056 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1943333064 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 4950420560 ps |
| CPU time | 498.17 seconds |
| Started | Jan 10 02:05:04 PM PST 24 |
| Finished | Jan 10 02:13:27 PM PST 24 |
| Peak memory | 603164 kb |
| Host | smart-c4f80e8b-bb56-4e61-bf03-498a5d5f21b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194 3333064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1943333064 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2923538283 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 9677840421 ps |
| CPU time | 357.7 seconds |
| Started | Jan 10 01:59:30 PM PST 24 |
| Finished | Jan 10 02:05:29 PM PST 24 |
| Peak memory | 606624 kb |
| Host | smart-c41d8014-6e90-49eb-b0c1-628472e0a88a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923538283 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2923538283 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3943026265 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 13185814776 ps |
| CPU time | 1326.04 seconds |
| Started | Jan 10 01:58:21 PM PST 24 |
| Finished | Jan 10 02:20:28 PM PST 24 |
| Peak memory | 603712 kb |
| Host | smart-3d6325b8-2168-4127-bad7-1979c23bbcd9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3943026265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.3943026265 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.822394573 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 6135871514 ps |
| CPU time | 476.21 seconds |
| Started | Jan 10 02:04:09 PM PST 24 |
| Finished | Jan 10 02:12:08 PM PST 24 |
| Peak memory | 603260 kb |
| Host | smart-0cef3c18-233f-4d9d-a8f1-7204a52fe9ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822394573 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_rstmgr_cpu_info.822394573 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1929279060 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 4641587220 ps |
| CPU time | 566.66 seconds |
| Started | Jan 10 01:57:49 PM PST 24 |
| Finished | Jan 10 02:07:18 PM PST 24 |
| Peak memory | 634588 kb |
| Host | smart-7bc4bfa4-1925-4515-8baa-d6a0d7c9a617 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1929279060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1929279060 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1279493935 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 2092224380 ps |
| CPU time | 187.33 seconds |
| Started | Jan 10 02:01:06 PM PST 24 |
| Finished | Jan 10 02:04:14 PM PST 24 |
| Peak memory | 602328 kb |
| Host | smart-8d29f156-da92-40f2-996a-7ecb0bcc81b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279493935 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1279493935 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.165868497 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 3482767400 ps |
| CPU time | 331.13 seconds |
| Started | Jan 10 02:03:31 PM PST 24 |
| Finished | Jan 10 02:09:30 PM PST 24 |
| Peak memory | 602464 kb |
| Host | smart-bef7c00f-864e-43e4-83e5-6201320a35ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165868497 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rstmgr_sw_req.165868497 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1374582088 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2476121764 ps |
| CPU time | 163.28 seconds |
| Started | Jan 10 02:04:10 PM PST 24 |
| Finished | Jan 10 02:06:55 PM PST 24 |
| Peak memory | 602392 kb |
| Host | smart-d341b6b5-b2d7-48bc-a6ae-4edb474d3878 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374582088 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.1374582088 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2254276883 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3041765944 ps |
| CPU time | 217.26 seconds |
| Started | Jan 10 02:00:12 PM PST 24 |
| Finished | Jan 10 02:03:54 PM PST 24 |
| Peak memory | 602408 kb |
| Host | smart-e0e3de28-d7e0-47f2-9d0d-05b8c55a73eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2254276883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2254276883 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.319774705 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 3036789544 ps |
| CPU time | 217.05 seconds |
| Started | Jan 10 02:00:46 PM PST 24 |
| Finished | Jan 10 02:04:24 PM PST 24 |
| Peak memory | 590408 kb |
| Host | smart-74d6e8f2-5a4f-4070-a810-933cc985a5b1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319774705 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.319774705 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2802498803 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2139019458 ps |
| CPU time | 166.67 seconds |
| Started | Jan 10 02:05:22 PM PST 24 |
| Finished | Jan 10 02:08:11 PM PST 24 |
| Peak memory | 601488 kb |
| Host | smart-8394ec21-45b8-456f-8d60-f93f07e10a79 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802498803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.2802498803 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3679858506 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 5149768372 ps |
| CPU time | 817.12 seconds |
| Started | Jan 10 02:00:57 PM PST 24 |
| Finished | Jan 10 02:14:36 PM PST 24 |
| Peak memory | 602432 kb |
| Host | smart-b24b88ee-282a-4bdc-b679-8d898810a448 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36798 58506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3679858506 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.746924053 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 5756417030 ps |
| CPU time | 779.36 seconds |
| Started | Jan 10 01:59:54 PM PST 24 |
| Finished | Jan 10 02:12:58 PM PST 24 |
| Peak memory | 602644 kb |
| Host | smart-34dc1fb4-1947-4f6a-b52e-bd5a390db3c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=746924053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.746924053 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.317087627 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 5064414098 ps |
| CPU time | 495.87 seconds |
| Started | Jan 10 01:59:34 PM PST 24 |
| Finished | Jan 10 02:07:51 PM PST 24 |
| Peak memory | 616912 kb |
| Host | smart-506392ea-8398-4b91-b4eb-0e6ae91931a4 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317087627 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.317087627 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3514300032 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 6082599480 ps |
| CPU time | 363.52 seconds |
| Started | Jan 10 01:59:33 PM PST 24 |
| Finished | Jan 10 02:05:37 PM PST 24 |
| Peak memory | 617108 kb |
| Host | smart-96f79480-7d19-4bef-a416-e2e7e7855263 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup:1:new_rules,test_rom:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514300032 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3514300032 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2880295475 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3787233590 ps |
| CPU time | 386.94 seconds |
| Started | Jan 10 01:59:33 PM PST 24 |
| Finished | Jan 10 02:06:01 PM PST 24 |
| Peak memory | 617264 kb |
| Host | smart-6c07164b-e2f8-41b6-bfd1-b191e24e2997 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880295475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2880295475 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4247984158 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 2795696626 ps |
| CPU time | 299.1 seconds |
| Started | Jan 10 02:04:21 PM PST 24 |
| Finished | Jan 10 02:09:22 PM PST 24 |
| Peak memory | 602444 kb |
| Host | smart-b231444f-ecc7-4d41-98b8-f50bb5dbd6e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247984158 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.4247984158 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.2662462952 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 3133278580 ps |
| CPU time | 267.57 seconds |
| Started | Jan 10 02:04:54 PM PST 24 |
| Finished | Jan 10 02:09:29 PM PST 24 |
| Peak memory | 602208 kb |
| Host | smart-0ec937e8-0d87-4945-ad21-0f5dad6e9e4d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662462952 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.2662462952 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.967455841 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 2309265168 ps |
| CPU time | 204.67 seconds |
| Started | Jan 10 02:00:02 PM PST 24 |
| Finished | Jan 10 02:03:34 PM PST 24 |
| Peak memory | 602376 kb |
| Host | smart-24f69dd9-0833-4651-b20e-df740f460726 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967455841 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_smoketest.967455841 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2069365095 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 7156688376 ps |
| CPU time | 607.35 seconds |
| Started | Jan 10 02:00:55 PM PST 24 |
| Finished | Jan 10 02:11:04 PM PST 24 |
| Peak memory | 603296 kb |
| Host | smart-a462a9da-9ea0-4910-862a-89d8dcef5491 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20693650 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.2069365095 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3371385730 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3315571727 ps |
| CPU time | 337.99 seconds |
| Started | Jan 10 02:00:55 PM PST 24 |
| Finished | Jan 10 02:06:34 PM PST 24 |
| Peak memory | 603244 kb |
| Host | smart-bf7b5b73-ad65-4bb4-9b48-91cceb319536 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371385 730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3371385730 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2392506227 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3813149964 ps |
| CPU time | 361.31 seconds |
| Started | Jan 10 01:58:43 PM PST 24 |
| Finished | Jan 10 02:04:53 PM PST 24 |
| Peak memory | 602852 kb |
| Host | smart-5dde0a51-a2af-4686-8545-2150ecfdf649 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392506227 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.2392506227 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.299983310 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 7463367880 ps |
| CPU time | 611.55 seconds |
| Started | Jan 10 01:59:37 PM PST 24 |
| Finished | Jan 10 02:09:50 PM PST 24 |
| Peak memory | 603432 kb |
| Host | smart-ba9e0265-65f8-4ede-9585-731c661b1f29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299983310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sle ep_sram_ret_contents_no_scramble.299983310 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.462045554 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 8424147180 ps |
| CPU time | 645.15 seconds |
| Started | Jan 10 01:59:31 PM PST 24 |
| Finished | Jan 10 02:10:17 PM PST 24 |
| Peak memory | 603428 kb |
| Host | smart-101abe43-feca-48c5-b88f-df2a1fd3d463 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462045554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.462045554 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3855447036 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 6614081590 ps |
| CPU time | 617.71 seconds |
| Started | Jan 10 02:00:27 PM PST 24 |
| Finished | Jan 10 02:10:49 PM PST 24 |
| Peak memory | 618108 kb |
| Host | smart-1cb0b73a-2e91-4dee-8124-9f9bb80c9ece |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855447036 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3855447036 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3595006295 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 4534528595 ps |
| CPU time | 637.18 seconds |
| Started | Jan 10 02:02:24 PM PST 24 |
| Finished | Jan 10 02:13:12 PM PST 24 |
| Peak memory | 618052 kb |
| Host | smart-458d88dd-f5c2-4d58-bd7a-7be14d5d0969 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595006295 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3595006295 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.3276841734 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 3667298061 ps |
| CPU time | 386.45 seconds |
| Started | Jan 10 01:57:53 PM PST 24 |
| Finished | Jan 10 02:04:23 PM PST 24 |
| Peak memory | 616920 kb |
| Host | smart-ae99c8ea-d066-4ed3-9aef-2b246f8a0178 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276841734 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3276841734 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tx_rx.1313185403 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3646729530 ps |
| CPU time | 387.75 seconds |
| Started | Jan 10 01:56:56 PM PST 24 |
| Finished | Jan 10 02:03:25 PM PST 24 |
| Peak memory | 601700 kb |
| Host | smart-23ca0496-df15-47a9-a588-8ddaa8604188 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313185403 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_spi_device_tx_rx.1313185403 |
| Directory | /workspace/2.chip_sw_spi_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1872399940 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2686608784 ps |
| CPU time | 188.47 seconds |
| Started | Jan 10 01:56:21 PM PST 24 |
| Finished | Jan 10 01:59:31 PM PST 24 |
| Peak memory | 602476 kb |
| Host | smart-aec300c3-21de-45d5-99ef-4b0f8c65ff68 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872399940 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.1872399940 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3456516961 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 5645534091 ps |
| CPU time | 494.06 seconds |
| Started | Jan 10 01:59:47 PM PST 24 |
| Finished | Jan 10 02:08:11 PM PST 24 |
| Peak memory | 603488 kb |
| Host | smart-b0eda38e-664a-437c-b984-16debccc2ba2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456516961 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3456516961 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1345596516 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 3950092508 ps |
| CPU time | 493.94 seconds |
| Started | Jan 10 02:02:07 PM PST 24 |
| Finished | Jan 10 02:10:32 PM PST 24 |
| Peak memory | 590568 kb |
| Host | smart-260956d9-f013-422a-9356-96baf06810b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345596516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.1345596516 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.686545654 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4781250368 ps |
| CPU time | 432.15 seconds |
| Started | Jan 10 01:58:32 PM PST 24 |
| Finished | Jan 10 02:05:46 PM PST 24 |
| Peak memory | 602820 kb |
| Host | smart-cee3691c-c7f5-479f-be45-ada7ae66bb99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686545654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.686545654 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4283249370 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 5185547615 ps |
| CPU time | 599.93 seconds |
| Started | Jan 10 02:01:48 PM PST 24 |
| Finished | Jan 10 02:11:50 PM PST 24 |
| Peak memory | 603000 kb |
| Host | smart-f7d0f515-9319-4a6f-a477-4bf889ffa063 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283249370 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4283249370 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3917238595 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 2629149808 ps |
| CPU time | 206.64 seconds |
| Started | Jan 10 02:03:29 PM PST 24 |
| Finished | Jan 10 02:07:24 PM PST 24 |
| Peak memory | 602044 kb |
| Host | smart-b32633bc-271d-461d-af73-0f73adcf8e8f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917238595 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3917238595 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1055757648 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 20758311519 ps |
| CPU time | 2963.09 seconds |
| Started | Jan 10 01:56:06 PM PST 24 |
| Finished | Jan 10 02:45:32 PM PST 24 |
| Peak memory | 603604 kb |
| Host | smart-cd8ccd5c-8c99-4dec-9ac0-3d473c7fe630 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055757648 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.1055757648 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.53335977 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 4857401378 ps |
| CPU time | 675.42 seconds |
| Started | Jan 10 02:03:49 PM PST 24 |
| Finished | Jan 10 02:15:19 PM PST 24 |
| Peak memory | 603220 kb |
| Host | smart-bd2e765c-4573-410e-907c-98fd0463eb67 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53335977 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.53335977 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3783641644 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 2757255701 ps |
| CPU time | 333.15 seconds |
| Started | Jan 10 02:04:40 PM PST 24 |
| Finished | Jan 10 02:10:17 PM PST 24 |
| Peak memory | 602792 kb |
| Host | smart-77323d49-929a-4947-af40-2263fc8334c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783641644 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.3783641644 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2951450747 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3076254112 ps |
| CPU time | 306.48 seconds |
| Started | Jan 10 02:04:44 PM PST 24 |
| Finished | Jan 10 02:09:55 PM PST 24 |
| Peak memory | 602688 kb |
| Host | smart-c4d39b31-c69b-4e6f-82f3-1a54326f8a03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951450747 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.2951450747 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.325380828 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 22647402640 ps |
| CPU time | 1487.98 seconds |
| Started | Jan 10 02:04:27 PM PST 24 |
| Finished | Jan 10 02:29:19 PM PST 24 |
| Peak memory | 603560 kb |
| Host | smart-3841f4b2-5e5a-4d42-a30b-c3ba2cd199c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32538082 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.325380828 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3242879019 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 6150287856 ps |
| CPU time | 612.55 seconds |
| Started | Jan 10 02:04:36 PM PST 24 |
| Finished | Jan 10 02:14:51 PM PST 24 |
| Peak memory | 603176 kb |
| Host | smart-c1d3e276-842e-4249-b70d-dd02b645b66e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242879019 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3242879019 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1381197654 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 13994488700 ps |
| CPU time | 2644.56 seconds |
| Started | Jan 10 01:56:15 PM PST 24 |
| Finished | Jan 10 02:40:21 PM PST 24 |
| Peak memory | 598472 kb |
| Host | smart-ad90890c-9eed-4af7-b136-cb16c0355a32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1381197654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.1381197654 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.1200280430 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2670086960 ps |
| CPU time | 223.24 seconds |
| Started | Jan 10 02:00:15 PM PST 24 |
| Finished | Jan 10 02:04:02 PM PST 24 |
| Peak memory | 590276 kb |
| Host | smart-c2d58b28-baf4-49ce-88bb-28118d9fa962 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200280430 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.1200280430 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest_signed.263950069 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 9165509510 ps |
| CPU time | 1558.75 seconds |
| Started | Jan 10 02:04:30 PM PST 24 |
| Finished | Jan 10 02:30:32 PM PST 24 |
| Peak memory | 590556 kb |
| Host | smart-dc17ce96-5fca-4595-b87a-90a68dc8b2b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=uart_smoketest_signed:1:signed:fake_rsa_test_key_0,rom_with_fa ke_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=263950069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_smoketest_signed.263950069 |
| Directory | /workspace/2.chip_sw_uart_smoketest_signed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.636934115 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 5660194284 ps |
| CPU time | 830.11 seconds |
| Started | Jan 10 01:55:52 PM PST 24 |
| Finished | Jan 10 02:09:43 PM PST 24 |
| Peak memory | 599168 kb |
| Host | smart-1a74a146-83af-4d2e-87eb-739f03f0c5f9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636934115 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.636934115 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1820573468 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4443563946 ps |
| CPU time | 678.18 seconds |
| Started | Jan 10 02:02:18 PM PST 24 |
| Finished | Jan 10 02:13:47 PM PST 24 |
| Peak memory | 598812 kb |
| Host | smart-b160db86-b646-4ec6-b19e-54dc4467d9ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820573468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_r x_alt_clk_freq.1820573468 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3835199054 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 13206396978 ps |
| CPU time | 1631.14 seconds |
| Started | Jan 10 01:56:50 PM PST 24 |
| Finished | Jan 10 02:24:05 PM PST 24 |
| Peak memory | 598496 kb |
| Host | smart-4ea78db5-bb81-479a-9eb1-a5786ec4c341 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835199054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_r x_alt_clk_freq_low_speed.3835199054 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.236729611 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 72689437779 ps |
| CPU time | 12018.6 seconds |
| Started | Jan 10 02:02:53 PM PST 24 |
| Finished | Jan 10 05:23:42 PM PST 24 |
| Peak memory | 612908 kb |
| Host | smart-b09b5967-8994-41f9-863c-1215a890806e |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=80_000_000 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=236729611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.236729611 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2762068010 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 5812494788 ps |
| CPU time | 874.67 seconds |
| Started | Jan 10 01:57:41 PM PST 24 |
| Finished | Jan 10 02:12:17 PM PST 24 |
| Peak memory | 599400 kb |
| Host | smart-649e6b08-6b24-4c44-853b-15d4a04d42d9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762068010 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2762068010 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.919674320 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 5750894732 ps |
| CPU time | 799.05 seconds |
| Started | Jan 10 01:57:33 PM PST 24 |
| Finished | Jan 10 02:10:55 PM PST 24 |
| Peak memory | 599384 kb |
| Host | smart-e681fdeb-2f9f-4cac-8cf8-a04d83cc9a25 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919674320 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.919674320 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2097723758 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 5872196280 ps |
| CPU time | 767.9 seconds |
| Started | Jan 10 01:58:08 PM PST 24 |
| Finished | Jan 10 02:11:03 PM PST 24 |
| Peak memory | 599424 kb |
| Host | smart-319aaa3a-979b-4e90-b3a3-7b7503fdaea1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097723758 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.2097723758 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.2520174085 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2520235603 ps |
| CPU time | 144.14 seconds |
| Started | Jan 10 01:58:57 PM PST 24 |
| Finished | Jan 10 02:01:25 PM PST 24 |
| Peak memory | 613968 kb |
| Host | smart-39499cf0-dcc0-4f85-b3b3-31c32edd05d8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2520174085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2520174085 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.750143693 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 7263940699 ps |
| CPU time | 645.27 seconds |
| Started | Jan 10 01:59:19 PM PST 24 |
| Finished | Jan 10 02:10:06 PM PST 24 |
| Peak memory | 615396 kb |
| Host | smart-348200fc-876d-4690-9fd0-6267c5bffad3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750143693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.750143693 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.962140139 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6472059001 ps |
| CPU time | 529.31 seconds |
| Started | Jan 10 01:58:38 PM PST 24 |
| Finished | Jan 10 02:07:38 PM PST 24 |
| Peak memory | 600904 kb |
| Host | smart-8ed3880b-5770-440a-a213-27a3ba834141 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962140139 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.962140139 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.4254108038 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7347286885 ps |
| CPU time | 578.12 seconds |
| Started | Jan 10 02:02:27 PM PST 24 |
| Finished | Jan 10 02:12:14 PM PST 24 |
| Peak memory | 614344 kb |
| Host | smart-8d1b9df1-14db-4d9e-9f7e-4b6a0c98131e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254108038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.4254108038 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.3342840444 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 8621682365 ps |
| CPU time | 1648.68 seconds |
| Started | Jan 10 02:05:01 PM PST 24 |
| Finished | Jan 10 02:32:37 PM PST 24 |
| Peak memory | 602896 kb |
| Host | smart-05a4c38e-3b2c-4745-a5f9-c2d93d093288 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_dev:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342840444 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.rom_e2e_asm_init_dev.3342840444 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.2049802487 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 8699714995 ps |
| CPU time | 1652.53 seconds |
| Started | Jan 10 02:05:12 PM PST 24 |
| Finished | Jan 10 02:32:46 PM PST 24 |
| Peak memory | 602868 kb |
| Host | smart-519393e2-95ff-4d86-88cb-96bc3f888724 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049802487 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.rom_e2e_asm_init_prod.2049802487 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1442357737 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 8927407740 ps |
| CPU time | 1834.04 seconds |
| Started | Jan 10 02:03:32 PM PST 24 |
| Finished | Jan 10 02:34:33 PM PST 24 |
| Peak memory | 602604 kb |
| Host | smart-c5ee7b96-18af-4b37-8c55-8cae67c3248b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_prod_end:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442357737 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod_end.1442357737 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.703901942 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 8948055628 ps |
| CPU time | 1579.83 seconds |
| Started | Jan 10 02:04:57 PM PST 24 |
| Finished | Jan 10 02:31:22 PM PST 24 |
| Peak memory | 602904 kb |
| Host | smart-a5c99093-0664-44ee-b07d-e79a5ea459b5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_fla sh_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_rma:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703901942 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_rma.703901942 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.434694927 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 6794736197 ps |
| CPU time | 1284.85 seconds |
| Started | Jan 10 02:02:53 PM PST 24 |
| Finished | Jan 10 02:24:47 PM PST 24 |
| Peak memory | 603132 kb |
| Host | smart-eeaaaf8e-0306-4881-884a-3ed6b941d0cf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:ot_ flash_binary:fake_rsa_prod_key_0,otp_img_e2e_bootstrap_entry_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434694927 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_test_unlocked0.434694927 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3633859101 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 8534465812 ps |
| CPU time | 1577.25 seconds |
| Started | Jan 10 02:04:37 PM PST 24 |
| Finished | Jan 10 02:30:57 PM PST 24 |
| Peak memory | 603388 kb |
| Host | smart-1e065404-b660-4a8b-9373-faf33827d2d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:signed:fake_rsa_test_key_0,rom_ with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3633859101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutdown_exception_c_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_exception_c.3633859101 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.869992137 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 24534285778 ps |
| CPU time | 2599.77 seconds |
| Started | Jan 10 02:04:01 PM PST 24 |
| Finished | Jan 10 02:47:28 PM PST 24 |
| Peak memory | 604352 kb |
| Host | smart-4b21c11b-a09b-4007-a986-dd416f4c857f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_bina ry,otp_img_shutdown_output_test_unlocked0:4,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869992137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.869992137 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.2681687939 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 8390477832 ps |
| CPU time | 1860.84 seconds |
| Started | Jan 10 02:00:24 PM PST 24 |
| Finished | Jan 10 02:31:30 PM PST 24 |
| Peak memory | 602712 kb |
| Host | smart-a55fd177-5060-4ae7-95e9-8d0c670ced48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:ot_flash_binary:signed:fake_rsa_test_key_0 ,rom_with_fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2681687939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.2681687939 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.4158051761 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 10574768100 ps |
| CPU time | 1772.96 seconds |
| Started | Jan 10 02:02:35 PM PST 24 |
| Finished | Jan 10 02:32:55 PM PST 24 |
| Peak memory | 602884 kb |
| Host | smart-1e735446-c376-4cad-974a-1c33d9762138 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:signed:fake_rsa_test_key_0,rom_with_ fake_keys:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158051761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.4158051761 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.3344820949 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 3517597650 ps |
| CPU time | 358.64 seconds |
| Started | Jan 10 02:00:47 PM PST 24 |
| Finished | Jan 10 02:06:48 PM PST 24 |
| Peak memory | 602820 kb |
| Host | smart-00fa08fe-f3b6-4100-9989-4cbfdf8b4bc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344820949 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3344820949 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.3615063490 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 15071922606 ps |
| CPU time | 1647.13 seconds |
| Started | Jan 10 02:03:58 PM PST 24 |
| Finished | Jan 10 02:31:34 PM PST 24 |
| Peak memory | 608828 kb |
| Host | smart-b081a24e-2c02-411b-a174-284018c08992 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3615063490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.3615063490 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.534854942 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 9659528696 ps |
| CPU time | 1412.11 seconds |
| Started | Jan 10 02:04:11 PM PST 24 |
| Finished | Jan 10 02:27:45 PM PST 24 |
| Peak memory | 608524 kb |
| Host | smart-c6a5656a-690f-4f20-849d-b75306875d5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a:1:signed:fake_rsa_test_key_0:ot_flash_binary,rom_with_fake_keys:0 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534854942 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.534854942 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.2759372961 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 5593174840 ps |
| CPU time | 555.26 seconds |
| Started | Jan 10 02:02:50 PM PST 24 |
| Finished | Jan 10 02:12:45 PM PST 24 |
| Peak memory | 634652 kb |
| Host | smart-3a3ca9c2-3f02-4562-b8ea-6a9711787c94 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2759372961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.2759372961 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.1592218820 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4978636792 ps |
| CPU time | 677.25 seconds |
| Started | Jan 10 02:02:48 PM PST 24 |
| Finished | Jan 10 02:14:43 PM PST 24 |
| Peak memory | 634332 kb |
| Host | smart-e8b9dbb5-e115-450e-84f9-21b842741e5b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1592218820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1592218820 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.3631713541 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4684118424 ps |
| CPU time | 527.43 seconds |
| Started | Jan 10 02:09:54 PM PST 24 |
| Finished | Jan 10 02:18:43 PM PST 24 |
| Peak memory | 635036 kb |
| Host | smart-0eccbc4e-d2dd-460a-9004-015ea7c20ae0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3631713541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.3631713541 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.3839402028 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 6365628326 ps |
| CPU time | 550.54 seconds |
| Started | Jan 10 02:03:23 PM PST 24 |
| Finished | Jan 10 02:13:06 PM PST 24 |
| Peak memory | 634496 kb |
| Host | smart-7ad10cb7-6da8-4144-8ad6-40e96714df0a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3839402028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3839402028 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.4116426874 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4687706360 ps |
| CPU time | 521.73 seconds |
| Started | Jan 10 02:05:01 PM PST 24 |
| Finished | Jan 10 02:13:50 PM PST 24 |
| Peak memory | 631204 kb |
| Host | smart-494f8fac-5d95-41dd-9ee7-dfaa5abcee8a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4116426874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.4116426874 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444031358 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 3457770686 ps |
| CPU time | 355.12 seconds |
| Started | Jan 10 02:03:06 PM PST 24 |
| Finished | Jan 10 02:09:24 PM PST 24 |
| Peak memory | 629112 kb |
| Host | smart-77158b38-edac-40eb-8b7c-af06d5feffcd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444031358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1444031358 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2845502458 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3553156992 ps |
| CPU time | 389.38 seconds |
| Started | Jan 10 02:01:49 PM PST 24 |
| Finished | Jan 10 02:08:20 PM PST 24 |
| Peak memory | 633124 kb |
| Host | smart-79cd1e04-5487-4c47-92d2-01114ed2664c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845502458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2845502458 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4134007157 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 7389145426 ps |
| CPU time | 465.42 seconds |
| Started | Jan 10 02:01:02 PM PST 24 |
| Finished | Jan 10 02:08:49 PM PST 24 |
| Peak memory | 603176 kb |
| Host | smart-7ea66f91-2931-464a-a4b2-eb91bd56ac09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4134007157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4134007157 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.4158749364 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5216934664 ps |
| CPU time | 643.97 seconds |
| Started | Jan 10 02:00:57 PM PST 24 |
| Finished | Jan 10 02:11:43 PM PST 24 |
| Peak memory | 603836 kb |
| Host | smart-3edf9d5d-8a9e-4f98-82b4-5f2acee94001 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4158749364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.4158749364 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1576820268 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 8611179023 ps |
| CPU time | 570.18 seconds |
| Started | Jan 10 02:00:58 PM PST 24 |
| Finished | Jan 10 02:10:30 PM PST 24 |
| Peak memory | 604756 kb |
| Host | smart-4ca0a85d-aa08-479c-9206-57311635c9fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576820268 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1576820268 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3741109920 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 6644120200 ps |
| CPU time | 905.67 seconds |
| Started | Jan 10 02:00:28 PM PST 24 |
| Finished | Jan 10 02:15:37 PM PST 24 |
| Peak memory | 603216 kb |
| Host | smart-70c34827-bb37-48fd-9108-df883f725505 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37411099 20 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3741109920 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3762857446 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 5873985654 ps |
| CPU time | 683.34 seconds |
| Started | Jan 10 01:59:21 PM PST 24 |
| Finished | Jan 10 02:10:45 PM PST 24 |
| Peak memory | 599472 kb |
| Host | smart-116c8626-32d0-4908-a1f5-f9d1be9736a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3762857446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3762857446 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1950732315 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 5588152424 ps |
| CPU time | 907.62 seconds |
| Started | Jan 10 02:04:48 PM PST 24 |
| Finished | Jan 10 02:20:06 PM PST 24 |
| Peak memory | 598804 kb |
| Host | smart-8f5fd007-60a3-494d-915c-61cebf74a581 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950732315 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1950732315 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3852327294 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 6039191322 ps |
| CPU time | 896.93 seconds |
| Started | Jan 10 02:06:14 PM PST 24 |
| Finished | Jan 10 02:21:13 PM PST 24 |
| Peak memory | 599464 kb |
| Host | smart-86af5922-0917-44cf-aa66-ba4a0fcdfe56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852327294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_r x_alt_clk_freq.3852327294 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4151037947 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 5387064494 ps |
| CPU time | 575.38 seconds |
| Started | Jan 10 02:00:59 PM PST 24 |
| Finished | Jan 10 02:10:37 PM PST 24 |
| Peak memory | 599468 kb |
| Host | smart-554e3066-f6a9-4d5d-b644-ee4d7d79bcd8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151037947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_r x_alt_clk_freq_low_speed.4151037947 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3887959582 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5860908528 ps |
| CPU time | 969.99 seconds |
| Started | Jan 10 02:03:23 PM PST 24 |
| Finished | Jan 10 02:20:06 PM PST 24 |
| Peak memory | 599376 kb |
| Host | smart-b5f0f85a-0803-443a-b4ea-59c72d906a7d |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887959582 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.3887959582 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1354755055 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 5032771076 ps |
| CPU time | 769.75 seconds |
| Started | Jan 10 01:59:52 PM PST 24 |
| Finished | Jan 10 02:12:47 PM PST 24 |
| Peak memory | 599104 kb |
| Host | smart-1240ed6b-52c0-4caa-99fb-9c7c0c32c8a9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354755055 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.1354755055 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2074781750 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 5574603672 ps |
| CPU time | 746.79 seconds |
| Started | Jan 10 02:00:19 PM PST 24 |
| Finished | Jan 10 02:12:48 PM PST 24 |
| Peak memory | 599132 kb |
| Host | smart-6cab741a-33c0-448a-a14b-65936d328de3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074781750 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2074781750 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1317371872 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2435712971 ps |
| CPU time | 144.66 seconds |
| Started | Jan 10 02:01:01 PM PST 24 |
| Finished | Jan 10 02:03:27 PM PST 24 |
| Peak memory | 600960 kb |
| Host | smart-9dd0193b-791a-4e30-92d9-b2784050447e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1317371872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1317371872 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.2188723442 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12473673570 ps |
| CPU time | 1280.14 seconds |
| Started | Jan 10 02:02:08 PM PST 24 |
| Finished | Jan 10 02:23:40 PM PST 24 |
| Peak memory | 601980 kb |
| Host | smart-5f8a7e50-054a-425d-b374-3ed95ab4ddad |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188723442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.2188723442 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.2945867757 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4704200922 ps |
| CPU time | 466.34 seconds |
| Started | Jan 10 02:04:48 PM PST 24 |
| Finished | Jan 10 02:12:44 PM PST 24 |
| Peak memory | 615320 kb |
| Host | smart-df007abf-fdfd-4d80-a4ab-622befe93a36 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945867757 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2945867757 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.1686839752 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4417898618 ps |
| CPU time | 277.06 seconds |
| Started | Jan 10 02:00:02 PM PST 24 |
| Finished | Jan 10 02:04:47 PM PST 24 |
| Peak memory | 601876 kb |
| Host | smart-0194ca36-0a60-4487-aab4-80fb51316f48 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686839752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.1686839752 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1941403715 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3691784696 ps |
| CPU time | 326.71 seconds |
| Started | Jan 10 02:04:26 PM PST 24 |
| Finished | Jan 10 02:09:55 PM PST 24 |
| Peak memory | 633360 kb |
| Host | smart-49af3903-0f4f-4283-b6fd-d74284c20530 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941403715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1941403715 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187959050 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 4044928240 ps |
| CPU time | 369.82 seconds |
| Started | Jan 10 02:04:28 PM PST 24 |
| Finished | Jan 10 02:10:40 PM PST 24 |
| Peak memory | 633400 kb |
| Host | smart-b9a92dcd-e0fa-4d07-930d-08fb54131706 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187959050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4187959050 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2561005783 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3346098316 ps |
| CPU time | 329.5 seconds |
| Started | Jan 10 02:02:23 PM PST 24 |
| Finished | Jan 10 02:08:04 PM PST 24 |
| Peak memory | 633576 kb |
| Host | smart-3eb3ea91-2b70-4936-a55e-554ba5cbdebc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561005783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2561005783 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909382617 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 3612421920 ps |
| CPU time | 319.52 seconds |
| Started | Jan 10 02:02:08 PM PST 24 |
| Finished | Jan 10 02:07:38 PM PST 24 |
| Peak memory | 633444 kb |
| Host | smart-abfc70e6-c1a5-498b-ae2a-64ea3f0b6383 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909382617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2909382617 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.882428515 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 4980599230 ps |
| CPU time | 487.36 seconds |
| Started | Jan 10 02:02:37 PM PST 24 |
| Finished | Jan 10 02:11:32 PM PST 24 |
| Peak memory | 608856 kb |
| Host | smart-ead99d80-4235-43e8-b305-1ebed097ed25 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 882428515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.882428515 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1287508698 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2966837388 ps |
| CPU time | 319.58 seconds |
| Started | Jan 10 02:02:48 PM PST 24 |
| Finished | Jan 10 02:08:42 PM PST 24 |
| Peak memory | 633556 kb |
| Host | smart-1cda6b66-c8a2-4e15-b346-2cea928ea95c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287508698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1287508698 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3631050121 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 3989172420 ps |
| CPU time | 361 seconds |
| Started | Jan 10 02:01:05 PM PST 24 |
| Finished | Jan 10 02:07:08 PM PST 24 |
| Peak memory | 633504 kb |
| Host | smart-2f619f7e-ada6-4335-b08a-62428ff485e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631050121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.3631050121 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.3420495476 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 5086447984 ps |
| CPU time | 708.16 seconds |
| Started | Jan 10 02:05:47 PM PST 24 |
| Finished | Jan 10 02:17:40 PM PST 24 |
| Peak memory | 634404 kb |
| Host | smart-4c4f227b-58fd-4832-87c9-03c950d07e82 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3420495476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3420495476 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3801849970 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 7184407936 ps |
| CPU time | 397.5 seconds |
| Started | Jan 10 02:00:40 PM PST 24 |
| Finished | Jan 10 02:07:18 PM PST 24 |
| Peak memory | 590988 kb |
| Host | smart-64df7250-da91-48fa-9728-9bf7d813e3ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3801849970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3801849970 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3568838698 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 4705556678 ps |
| CPU time | 362.22 seconds |
| Started | Jan 10 02:05:41 PM PST 24 |
| Finished | Jan 10 02:11:45 PM PST 24 |
| Peak memory | 604816 kb |
| Host | smart-32e62634-8b68-4801-9737-42b447d61e59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568838698 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.3568838698 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2746336452 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 6131224806 ps |
| CPU time | 815.58 seconds |
| Started | Jan 10 02:05:51 PM PST 24 |
| Finished | Jan 10 02:19:31 PM PST 24 |
| Peak memory | 598212 kb |
| Host | smart-b7dd3a3d-1f42-48a8-b460-d4bcbf85d883 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2746336452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2746336452 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.1111268376 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4697258418 ps |
| CPU time | 880.09 seconds |
| Started | Jan 10 02:02:02 PM PST 24 |
| Finished | Jan 10 02:16:44 PM PST 24 |
| Peak memory | 599112 kb |
| Host | smart-62f769d3-2da8-4829-a59b-9c86814e596d |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111268376 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.1111268376 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2500327116 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 23124617752 ps |
| CPU time | 3588.56 seconds |
| Started | Jan 10 02:00:17 PM PST 24 |
| Finished | Jan 10 03:00:09 PM PST 24 |
| Peak memory | 598708 kb |
| Host | smart-a6c6e19e-ff71-401c-875c-ce2f306dc8f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500327116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_r x_alt_clk_freq.2500327116 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1833337371 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 5630126231 ps |
| CPU time | 743.31 seconds |
| Started | Jan 10 02:05:56 PM PST 24 |
| Finished | Jan 10 02:18:24 PM PST 24 |
| Peak memory | 599180 kb |
| Host | smart-4628df4d-3af1-4ccb-8db4-5c5417d5b659 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833337371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_r x_alt_clk_freq_low_speed.1833337371 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.695064618 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 5074756950 ps |
| CPU time | 960.11 seconds |
| Started | Jan 10 02:00:43 PM PST 24 |
| Finished | Jan 10 02:16:45 PM PST 24 |
| Peak memory | 599148 kb |
| Host | smart-3d6f2fa3-f008-4294-87f9-a93d03c1bfdd |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695064618 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.695064618 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.856192236 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 5591018412 ps |
| CPU time | 836.99 seconds |
| Started | Jan 10 02:05:51 PM PST 24 |
| Finished | Jan 10 02:19:53 PM PST 24 |
| Peak memory | 598808 kb |
| Host | smart-7a1732ad-2ca5-46a7-b72b-151cba622c92 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856192236 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.856192236 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1971670840 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 5922792100 ps |
| CPU time | 840.39 seconds |
| Started | Jan 10 01:59:32 PM PST 24 |
| Finished | Jan 10 02:13:33 PM PST 24 |
| Peak memory | 599052 kb |
| Host | smart-9e5b4bd3-58c1-449f-9d29-e41a286e4b7d |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971670840 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1971670840 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.2063856068 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 11107537723 ps |
| CPU time | 1083.59 seconds |
| Started | Jan 10 02:05:20 PM PST 24 |
| Finished | Jan 10 02:23:27 PM PST 24 |
| Peak memory | 615420 kb |
| Host | smart-d902fa6b-5527-4dce-a955-3d5e70aa9ae9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2063856068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.2063856068 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.669522638 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 7054200213 ps |
| CPU time | 776.65 seconds |
| Started | Jan 10 02:01:52 PM PST 24 |
| Finished | Jan 10 02:14:52 PM PST 24 |
| Peak memory | 601596 kb |
| Host | smart-cd1675a5-5b7e-49fb-8fe8-978e9363c508 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669522638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.669522638 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.1690515688 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 4827050957 ps |
| CPU time | 453.34 seconds |
| Started | Jan 10 02:00:42 PM PST 24 |
| Finished | Jan 10 02:08:17 PM PST 24 |
| Peak memory | 614424 kb |
| Host | smart-59d8af98-c585-459b-9343-e280ab4b101f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690515688 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1690515688 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.2047990813 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 10151029704 ps |
| CPU time | 1092.55 seconds |
| Started | Jan 10 02:01:49 PM PST 24 |
| Finished | Jan 10 02:20:05 PM PST 24 |
| Peak memory | 614376 kb |
| Host | smart-a2cd6417-caef-4ae1-8893-3eb82030e00d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047990813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.2047990813 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2017504024 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 3801204940 ps |
| CPU time | 351.01 seconds |
| Started | Jan 10 02:05:25 PM PST 24 |
| Finished | Jan 10 02:11:20 PM PST 24 |
| Peak memory | 633448 kb |
| Host | smart-e5a54f3a-6530-4660-afcf-68ced2c30506 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017504024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2017504024 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911061398 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 3143926796 ps |
| CPU time | 241 seconds |
| Started | Jan 10 02:05:26 PM PST 24 |
| Finished | Jan 10 02:09:30 PM PST 24 |
| Peak memory | 633360 kb |
| Host | smart-e5ee453c-141f-4d85-98d4-32973b61bc25 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911061398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1911061398 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.2587260671 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 5983879350 ps |
| CPU time | 607.56 seconds |
| Started | Jan 10 02:04:56 PM PST 24 |
| Finished | Jan 10 02:15:09 PM PST 24 |
| Peak memory | 608440 kb |
| Host | smart-530fe9fb-6ea9-46e6-95f2-b391505043e0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2587260671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2587260671 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.2658929120 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 4204482280 ps |
| CPU time | 511.35 seconds |
| Started | Jan 10 02:05:16 PM PST 24 |
| Finished | Jan 10 02:13:50 PM PST 24 |
| Peak memory | 634728 kb |
| Host | smart-7c39cc57-2380-4c36-b91f-2290a2d77603 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2658929120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.2658929120 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.112020731 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3480927692 ps |
| CPU time | 394.71 seconds |
| Started | Jan 10 02:05:05 PM PST 24 |
| Finished | Jan 10 02:11:44 PM PST 24 |
| Peak memory | 633356 kb |
| Host | smart-3201e40e-a08b-4c89-b0d8-ccc2ee06d99e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112020731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_s w_alert_handler_lpg_sleep_mode_alerts.112020731 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.209612087 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3641140312 ps |
| CPU time | 309.66 seconds |
| Started | Jan 10 02:05:08 PM PST 24 |
| Finished | Jan 10 02:10:20 PM PST 24 |
| Peak memory | 633496 kb |
| Host | smart-f86c8477-72ab-413e-93ff-c177088d8f1d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209612087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_s w_alert_handler_lpg_sleep_mode_alerts.209612087 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.666716348 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2970858320 ps |
| CPU time | 273.56 seconds |
| Started | Jan 10 02:04:48 PM PST 24 |
| Finished | Jan 10 02:09:31 PM PST 24 |
| Peak memory | 633476 kb |
| Host | smart-e1382cc5-ce50-48a8-8af4-2b2b3e0335c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666716348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_s w_alert_handler_lpg_sleep_mode_alerts.666716348 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.3697255573 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 6171939504 ps |
| CPU time | 604.63 seconds |
| Started | Jan 10 02:05:11 PM PST 24 |
| Finished | Jan 10 02:15:18 PM PST 24 |
| Peak memory | 608860 kb |
| Host | smart-1a8dfb5a-f126-4d67-be18-4cafe9d60cf2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3697255573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3697255573 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1695626004 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 4244249268 ps |
| CPU time | 382.39 seconds |
| Started | Jan 10 02:05:12 PM PST 24 |
| Finished | Jan 10 02:11:36 PM PST 24 |
| Peak memory | 633428 kb |
| Host | smart-a3353195-b2a3-4fce-925d-dbeda49c5757 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695626004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1695626004 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2385027804 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 5014858204 ps |
| CPU time | 457.86 seconds |
| Started | Jan 10 02:05:32 PM PST 24 |
| Finished | Jan 10 02:13:13 PM PST 24 |
| Peak memory | 603744 kb |
| Host | smart-dca8abca-bc27-4376-9b15-ece59401f6ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2385027804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2385027804 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.65794958 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3629302200 ps |
| CPU time | 325.93 seconds |
| Started | Jan 10 02:05:27 PM PST 24 |
| Finished | Jan 10 02:10:56 PM PST 24 |
| Peak memory | 633648 kb |
| Host | smart-1ef93f8e-7372-43dd-a581-9666ff2be201 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65794958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw _alert_handler_lpg_sleep_mode_alerts.65794958 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.3237337122 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 5410041950 ps |
| CPU time | 580.44 seconds |
| Started | Jan 10 02:05:32 PM PST 24 |
| Finished | Jan 10 02:15:15 PM PST 24 |
| Peak memory | 608836 kb |
| Host | smart-4f2dad7f-3aa2-4116-8d79-2b4b6fda4125 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3237337122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.3237337122 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1863578714 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3429455510 ps |
| CPU time | 284.85 seconds |
| Started | Jan 10 02:06:22 PM PST 24 |
| Finished | Jan 10 02:11:08 PM PST 24 |
| Peak memory | 628984 kb |
| Host | smart-49863cbb-7945-406f-bc55-f617936ed987 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863578714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1863578714 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.4173062422 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 4548037616 ps |
| CPU time | 454.86 seconds |
| Started | Jan 10 02:05:35 PM PST 24 |
| Finished | Jan 10 02:13:12 PM PST 24 |
| Peak memory | 608584 kb |
| Host | smart-b21e69d7-f444-481e-be7d-1e09641f27d5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4173062422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.4173062422 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2205841302 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 3379049182 ps |
| CPU time | 400.51 seconds |
| Started | Jan 10 02:02:58 PM PST 24 |
| Finished | Jan 10 02:10:07 PM PST 24 |
| Peak memory | 633620 kb |
| Host | smart-1875f171-1b21-4f24-8478-7a3b43f056d4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205841302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.2205841302 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.2540537871 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5361596472 ps |
| CPU time | 488.41 seconds |
| Started | Jan 10 02:05:56 PM PST 24 |
| Finished | Jan 10 02:14:10 PM PST 24 |
| Peak memory | 634444 kb |
| Host | smart-5b3d1582-b41f-4aa1-a55f-d0369db59037 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2540537871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2540537871 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1283464249 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 5966942550 ps |
| CPU time | 513.8 seconds |
| Started | Jan 10 02:00:36 PM PST 24 |
| Finished | Jan 10 02:09:11 PM PST 24 |
| Peak memory | 603824 kb |
| Host | smart-3ffda1a0-c317-4a38-aafb-063969284868 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1283464249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.1283464249 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3232995889 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 11688576461 ps |
| CPU time | 992.24 seconds |
| Started | Jan 10 02:02:20 PM PST 24 |
| Finished | Jan 10 02:19:03 PM PST 24 |
| Peak memory | 604800 kb |
| Host | smart-8b9637a0-44ed-4279-a7a0-8820452e704d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232995889 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.3232995889 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3638074538 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 4764260150 ps |
| CPU time | 662.65 seconds |
| Started | Jan 10 02:01:41 PM PST 24 |
| Finished | Jan 10 02:12:46 PM PST 24 |
| Peak memory | 598868 kb |
| Host | smart-3f1f43c9-11a2-4b0d-9263-689812e0fc52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3638074538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3638074538 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2951528749 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 4256918680 ps |
| CPU time | 356.53 seconds |
| Started | Jan 10 02:05:18 PM PST 24 |
| Finished | Jan 10 02:11:17 PM PST 24 |
| Peak memory | 633040 kb |
| Host | smart-9a927221-9a69-47f5-acf8-dac665a981b8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951528749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2951528749 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.2331615811 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 5911307970 ps |
| CPU time | 448.75 seconds |
| Started | Jan 10 02:04:47 PM PST 24 |
| Finished | Jan 10 02:12:26 PM PST 24 |
| Peak memory | 634360 kb |
| Host | smart-6ce2db5d-5eba-49f7-a067-738350e7d2de |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2331615811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.2331615811 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.943126244 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 4331454040 ps |
| CPU time | 457.41 seconds |
| Started | Jan 10 02:05:00 PM PST 24 |
| Finished | Jan 10 02:12:45 PM PST 24 |
| Peak memory | 634836 kb |
| Host | smart-549b29a3-a433-40fb-80b6-fabbe9ea209f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 943126244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.943126244 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383684836 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3892173688 ps |
| CPU time | 355.59 seconds |
| Started | Jan 10 02:06:47 PM PST 24 |
| Finished | Jan 10 02:12:47 PM PST 24 |
| Peak memory | 633120 kb |
| Host | smart-7f14c4e5-c47a-49ee-8bd3-7507014a1b3c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383684836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2383684836 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.707018085 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 6676034080 ps |
| CPU time | 654.61 seconds |
| Started | Jan 10 02:06:05 PM PST 24 |
| Finished | Jan 10 02:17:02 PM PST 24 |
| Peak memory | 630284 kb |
| Host | smart-364bccb9-cf53-4825-addb-8bd9185ba581 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 707018085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.707018085 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.508057308 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3666105440 ps |
| CPU time | 367.94 seconds |
| Started | Jan 10 02:05:31 PM PST 24 |
| Finished | Jan 10 02:11:41 PM PST 24 |
| Peak memory | 633736 kb |
| Host | smart-4d0ca07d-dc7f-485e-b7b0-7b38a818cb12 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508057308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_s w_alert_handler_lpg_sleep_mode_alerts.508057308 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.932199917 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 5340668980 ps |
| CPU time | 548.84 seconds |
| Started | Jan 10 02:06:15 PM PST 24 |
| Finished | Jan 10 02:15:26 PM PST 24 |
| Peak memory | 608888 kb |
| Host | smart-e606e676-f061-4c3f-b88d-c4c0a59a3f38 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 932199917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.932199917 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3407012107 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3554479160 ps |
| CPU time | 308.23 seconds |
| Started | Jan 10 02:06:01 PM PST 24 |
| Finished | Jan 10 02:11:13 PM PST 24 |
| Peak memory | 628992 kb |
| Host | smart-7611118b-4720-4859-aba7-0a7e9c198a84 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407012107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3407012107 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.3284456670 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 4105679240 ps |
| CPU time | 406.31 seconds |
| Started | Jan 10 02:06:02 PM PST 24 |
| Finished | Jan 10 02:12:52 PM PST 24 |
| Peak memory | 634772 kb |
| Host | smart-d363127f-ce4b-4894-baac-508c9a2c5c34 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3284456670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3284456670 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.952527005 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 4008457608 ps |
| CPU time | 372.38 seconds |
| Started | Jan 10 02:06:27 PM PST 24 |
| Finished | Jan 10 02:12:43 PM PST 24 |
| Peak memory | 628816 kb |
| Host | smart-f34b7066-a30a-4fed-8123-bc996db6b8f8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952527005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_s w_alert_handler_lpg_sleep_mode_alerts.952527005 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.3699301460 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 5431811272 ps |
| CPU time | 445.21 seconds |
| Started | Jan 10 02:05:31 PM PST 24 |
| Finished | Jan 10 02:12:59 PM PST 24 |
| Peak memory | 634864 kb |
| Host | smart-119acdb7-1fb0-4ca1-9f56-c75c6e44dd27 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3699301460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3699301460 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099890333 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 3851854804 ps |
| CPU time | 343.95 seconds |
| Started | Jan 10 02:05:51 PM PST 24 |
| Finished | Jan 10 02:11:40 PM PST 24 |
| Peak memory | 633492 kb |
| Host | smart-f1d1619e-69c8-411e-b08b-1ae4acc374a0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099890333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4099890333 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2798326136 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 2973569784 ps |
| CPU time | 327.51 seconds |
| Started | Jan 10 02:06:07 PM PST 24 |
| Finished | Jan 10 02:11:36 PM PST 24 |
| Peak memory | 633116 kb |
| Host | smart-9e476600-87fb-4247-9668-44c5c8bd89e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798326136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2798326136 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2343092892 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4212664580 ps |
| CPU time | 410.83 seconds |
| Started | Jan 10 02:01:37 PM PST 24 |
| Finished | Jan 10 02:08:30 PM PST 24 |
| Peak memory | 628940 kb |
| Host | smart-f0f5a849-c317-4e43-b405-8ab62bff441c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343092892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.2343092892 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1812623677 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 5288938284 ps |
| CPU time | 355.98 seconds |
| Started | Jan 10 02:01:33 PM PST 24 |
| Finished | Jan 10 02:07:32 PM PST 24 |
| Peak memory | 604172 kb |
| Host | smart-f5164531-89fd-4eec-bf18-cefc66141792 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812623677 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.1812623677 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2718519503 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 12665247138 ps |
| CPU time | 1939.73 seconds |
| Started | Jan 10 02:00:34 PM PST 24 |
| Finished | Jan 10 02:32:56 PM PST 24 |
| Peak memory | 601464 kb |
| Host | smart-3a6ed587-1773-4da7-8ea3-e329ae68b219 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2718519503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2718519503 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.1441410952 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5224430152 ps |
| CPU time | 646.46 seconds |
| Started | Jan 10 02:06:14 PM PST 24 |
| Finished | Jan 10 02:17:03 PM PST 24 |
| Peak memory | 634484 kb |
| Host | smart-83f9bf66-4325-4bdc-8380-aa2c96c36a96 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1441410952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.1441410952 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.3264216078 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 4774241258 ps |
| CPU time | 593.37 seconds |
| Started | Jan 10 02:06:16 PM PST 24 |
| Finished | Jan 10 02:16:11 PM PST 24 |
| Peak memory | 608808 kb |
| Host | smart-7a366999-d1a5-41f8-b3a7-8e175244b4fc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3264216078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3264216078 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800871349 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 3779419364 ps |
| CPU time | 381.56 seconds |
| Started | Jan 10 02:06:00 PM PST 24 |
| Finished | Jan 10 02:12:26 PM PST 24 |
| Peak memory | 626928 kb |
| Host | smart-cc92f448-324b-4138-a5a3-4ea2f4f92c18 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800871349 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2800871349 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.4226260601 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 4983540770 ps |
| CPU time | 456.26 seconds |
| Started | Jan 10 02:05:43 PM PST 24 |
| Finished | Jan 10 02:13:23 PM PST 24 |
| Peak memory | 608908 kb |
| Host | smart-b91ab589-37e7-4f2e-a899-ed497c14ec3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4226260601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.4226260601 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1593681401 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3169487584 ps |
| CPU time | 327.91 seconds |
| Started | Jan 10 02:06:01 PM PST 24 |
| Finished | Jan 10 02:11:33 PM PST 24 |
| Peak memory | 633148 kb |
| Host | smart-11b7fe10-5672-4f68-bf58-601b5a5ffbc4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593681401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1593681401 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.905887909 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 5896910380 ps |
| CPU time | 461.93 seconds |
| Started | Jan 10 02:05:38 PM PST 24 |
| Finished | Jan 10 02:13:21 PM PST 24 |
| Peak memory | 634868 kb |
| Host | smart-fc38fc8c-8c4f-46a1-9de7-639cb3cd3a3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 905887909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.905887909 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1455645042 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 3767344940 ps |
| CPU time | 278.7 seconds |
| Started | Jan 10 02:06:15 PM PST 24 |
| Finished | Jan 10 02:10:56 PM PST 24 |
| Peak memory | 633716 kb |
| Host | smart-b79c239e-86ee-4845-aa82-ee5c74b3428c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455645042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1455645042 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.2281541371 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 5180444720 ps |
| CPU time | 601.4 seconds |
| Started | Jan 10 02:05:28 PM PST 24 |
| Finished | Jan 10 02:15:33 PM PST 24 |
| Peak memory | 601380 kb |
| Host | smart-60bfc074-7bdb-4457-bbcd-83345d240326 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2281541371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.2281541371 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2182453823 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3905884908 ps |
| CPU time | 309.36 seconds |
| Started | Jan 10 02:05:52 PM PST 24 |
| Finished | Jan 10 02:11:06 PM PST 24 |
| Peak memory | 628936 kb |
| Host | smart-46b0b278-6276-4772-bbba-04be8232024d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182453823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2182453823 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2551046564 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 5935653836 ps |
| CPU time | 469.65 seconds |
| Started | Jan 10 02:00:58 PM PST 24 |
| Finished | Jan 10 02:08:50 PM PST 24 |
| Peak memory | 604772 kb |
| Host | smart-3efc115f-0c8e-4b12-b538-e4eb9f99f60a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551046564 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2551046564 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3067509940 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 22596803240 ps |
| CPU time | 4006.8 seconds |
| Started | Jan 10 02:04:08 PM PST 24 |
| Finished | Jan 10 03:10:59 PM PST 24 |
| Peak memory | 599248 kb |
| Host | smart-ee4790e1-bde7-482f-9404-1af49eedbf15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3067509940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3067509940 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930497578 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3849198460 ps |
| CPU time | 378.76 seconds |
| Started | Jan 10 02:06:27 PM PST 24 |
| Finished | Jan 10 02:12:50 PM PST 24 |
| Peak memory | 633768 kb |
| Host | smart-ceb049b6-06de-42cb-b253-b9103b665974 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930497578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1930497578 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2081830164 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 3699916148 ps |
| CPU time | 280.45 seconds |
| Started | Jan 10 02:06:29 PM PST 24 |
| Finished | Jan 10 02:11:13 PM PST 24 |
| Peak memory | 633456 kb |
| Host | smart-be862bc7-3d9e-4456-911d-e0cf4a5509cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081830164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2081830164 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.3423183961 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 5714738712 ps |
| CPU time | 544.36 seconds |
| Started | Jan 10 02:06:12 PM PST 24 |
| Finished | Jan 10 02:15:18 PM PST 24 |
| Peak memory | 634880 kb |
| Host | smart-5d736477-6c8c-4172-8f9d-96ada6abc474 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3423183961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3423183961 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2052508595 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 4401990010 ps |
| CPU time | 313.19 seconds |
| Started | Jan 10 02:05:42 PM PST 24 |
| Finished | Jan 10 02:10:58 PM PST 24 |
| Peak memory | 633736 kb |
| Host | smart-fc933d94-d70d-42fe-a40a-ce9683882e11 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052508595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2052508595 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.1075504240 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 4679111526 ps |
| CPU time | 673.83 seconds |
| Started | Jan 10 02:05:45 PM PST 24 |
| Finished | Jan 10 02:17:01 PM PST 24 |
| Peak memory | 634840 kb |
| Host | smart-87c0d123-7e51-4120-8cf9-e0514b062792 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1075504240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.1075504240 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.4187923161 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 5232618670 ps |
| CPU time | 525.82 seconds |
| Started | Jan 10 02:06:23 PM PST 24 |
| Finished | Jan 10 02:15:13 PM PST 24 |
| Peak memory | 634804 kb |
| Host | smart-d9a7b9a9-a512-48e5-ba3b-e673216bd4fe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4187923161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.4187923161 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.669255902 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4050049508 ps |
| CPU time | 382.66 seconds |
| Started | Jan 10 02:08:00 PM PST 24 |
| Finished | Jan 10 02:14:30 PM PST 24 |
| Peak memory | 633172 kb |
| Host | smart-4de0a5d4-f9e5-4db9-b10f-4277a2326859 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669255902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_s w_alert_handler_lpg_sleep_mode_alerts.669255902 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.2477744673 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 4412845000 ps |
| CPU time | 509.44 seconds |
| Started | Jan 10 02:06:43 PM PST 24 |
| Finished | Jan 10 02:15:16 PM PST 24 |
| Peak memory | 634508 kb |
| Host | smart-a6888bd5-205a-40aa-9b8d-285e64b863f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2477744673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2477744673 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.510142304 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3922281208 ps |
| CPU time | 341.07 seconds |
| Started | Jan 10 02:06:12 PM PST 24 |
| Finished | Jan 10 02:11:54 PM PST 24 |
| Peak memory | 628964 kb |
| Host | smart-a9c6cc93-74fb-49b4-b47f-72251d451144 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510142304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_s w_alert_handler_lpg_sleep_mode_alerts.510142304 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2671924335 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 4215790614 ps |
| CPU time | 465.48 seconds |
| Started | Jan 10 02:06:39 PM PST 24 |
| Finished | Jan 10 02:14:26 PM PST 24 |
| Peak memory | 634448 kb |
| Host | smart-d291a96b-175e-4a41-bea0-1301c1ef9c3e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2671924335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2671924335 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3704122390 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3266467632 ps |
| CPU time | 325.32 seconds |
| Started | Jan 10 02:06:21 PM PST 24 |
| Finished | Jan 10 02:11:48 PM PST 24 |
| Peak memory | 633376 kb |
| Host | smart-eba9b9f5-0516-4ec9-be60-ac729a127a84 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704122390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3704122390 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.1595710958 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 4619413288 ps |
| CPU time | 584.81 seconds |
| Started | Jan 10 02:06:13 PM PST 24 |
| Finished | Jan 10 02:15:59 PM PST 24 |
| Peak memory | 603728 kb |
| Host | smart-abe38fe9-8fef-4dee-81b3-4441fbcbcddc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1595710958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1595710958 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3307499950 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 4131270752 ps |
| CPU time | 428.99 seconds |
| Started | Jan 10 02:06:42 PM PST 24 |
| Finished | Jan 10 02:13:54 PM PST 24 |
| Peak memory | 633500 kb |
| Host | smart-857aeadc-db85-4490-af34-f9d6ea2bfafd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307499950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3307499950 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.1305619639 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 5378528642 ps |
| CPU time | 431.78 seconds |
| Started | Jan 10 02:05:35 PM PST 24 |
| Finished | Jan 10 02:12:49 PM PST 24 |
| Peak memory | 634856 kb |
| Host | smart-15795f5c-c244-4428-b2a5-9aac5bde5391 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1305619639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1305619639 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.756571218 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 6103747052 ps |
| CPU time | 544.13 seconds |
| Started | Jan 10 02:06:21 PM PST 24 |
| Finished | Jan 10 02:15:27 PM PST 24 |
| Peak memory | 634520 kb |
| Host | smart-77f60530-405d-4fa9-97bb-effa72363d4c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 756571218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.756571218 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4131484111 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3316640188 ps |
| CPU time | 377.49 seconds |
| Started | Jan 10 02:07:35 PM PST 24 |
| Finished | Jan 10 02:14:07 PM PST 24 |
| Peak memory | 633436 kb |
| Host | smart-735e8d81-65da-4bac-8be9-3465bc837372 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131484111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4131484111 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3606662552 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3913049246 ps |
| CPU time | 359.62 seconds |
| Started | Jan 10 02:01:37 PM PST 24 |
| Finished | Jan 10 02:07:39 PM PST 24 |
| Peak memory | 633432 kb |
| Host | smart-6c53dd2d-51c8-4566-98bc-42b569d80908 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606662552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.3606662552 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.3171742368 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 5461509580 ps |
| CPU time | 585.4 seconds |
| Started | Jan 10 02:07:23 PM PST 24 |
| Finished | Jan 10 02:17:17 PM PST 24 |
| Peak memory | 634796 kb |
| Host | smart-fc6bd5f8-6798-4fbb-b05a-16d5bfba6763 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3171742368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3171742368 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3884360437 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4642791777 ps |
| CPU time | 318.03 seconds |
| Started | Jan 10 02:01:33 PM PST 24 |
| Finished | Jan 10 02:06:54 PM PST 24 |
| Peak memory | 604720 kb |
| Host | smart-71e63a02-2ef5-4471-a997-6df582c57ff2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884360437 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3884360437 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3161005120 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 3487633598 ps |
| CPU time | 327.9 seconds |
| Started | Jan 10 02:06:35 PM PST 24 |
| Finished | Jan 10 02:12:06 PM PST 24 |
| Peak memory | 633068 kb |
| Host | smart-a67ab7b9-381b-4184-a0c7-777ff0e0ec20 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161005120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3161005120 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.4110639602 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 3834109136 ps |
| CPU time | 376.71 seconds |
| Started | Jan 10 02:06:32 PM PST 24 |
| Finished | Jan 10 02:12:53 PM PST 24 |
| Peak memory | 633748 kb |
| Host | smart-983f30ec-c1bf-4344-a602-6e5906cafa28 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110639602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4110639602 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.1123324651 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4880433484 ps |
| CPU time | 637.03 seconds |
| Started | Jan 10 02:06:35 PM PST 24 |
| Finished | Jan 10 02:17:15 PM PST 24 |
| Peak memory | 634324 kb |
| Host | smart-ca6c9199-096e-402f-9e1e-07b31a8eaaf5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1123324651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.1123324651 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1146902521 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 4279918320 ps |
| CPU time | 368.99 seconds |
| Started | Jan 10 02:06:56 PM PST 24 |
| Finished | Jan 10 02:13:07 PM PST 24 |
| Peak memory | 632980 kb |
| Host | smart-3a3ffef1-eb58-46b1-a2d9-4fcdceac3bd6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146902521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1146902521 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.4166176520 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4942748988 ps |
| CPU time | 543.02 seconds |
| Started | Jan 10 02:08:11 PM PST 24 |
| Finished | Jan 10 02:17:20 PM PST 24 |
| Peak memory | 634792 kb |
| Host | smart-ad39d94c-4ede-45b5-8b31-5ace878698e8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4166176520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.4166176520 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2913692241 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3857499236 ps |
| CPU time | 394.04 seconds |
| Started | Jan 10 02:06:13 PM PST 24 |
| Finished | Jan 10 02:12:49 PM PST 24 |
| Peak memory | 633492 kb |
| Host | smart-23a0da05-d981-42b9-b2d8-4579a675a92d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913692241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2913692241 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.4139310227 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 4884688540 ps |
| CPU time | 572.75 seconds |
| Started | Jan 10 02:06:22 PM PST 24 |
| Finished | Jan 10 02:15:57 PM PST 24 |
| Peak memory | 634388 kb |
| Host | smart-2f3d996d-cafd-49c4-912d-b9976a582624 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4139310227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.4139310227 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.4203565777 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 6250537236 ps |
| CPU time | 622.62 seconds |
| Started | Jan 10 02:06:54 PM PST 24 |
| Finished | Jan 10 02:17:19 PM PST 24 |
| Peak memory | 634892 kb |
| Host | smart-eaeaa356-d016-4a01-9234-54c233c5d3fe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4203565777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.4203565777 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.758803092 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3815691036 ps |
| CPU time | 335.17 seconds |
| Started | Jan 10 02:08:12 PM PST 24 |
| Finished | Jan 10 02:13:53 PM PST 24 |
| Peak memory | 633400 kb |
| Host | smart-f548f02f-9cb5-404d-ae34-71b644b90620 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758803092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_s w_alert_handler_lpg_sleep_mode_alerts.758803092 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3625799091 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3791731052 ps |
| CPU time | 266.52 seconds |
| Started | Jan 10 02:06:05 PM PST 24 |
| Finished | Jan 10 02:10:34 PM PST 24 |
| Peak memory | 633508 kb |
| Host | smart-d6c20f53-2cea-44a5-beab-b6a9ddc09a1b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625799091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3625799091 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.901688124 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6106199700 ps |
| CPU time | 540.56 seconds |
| Started | Jan 10 02:06:48 PM PST 24 |
| Finished | Jan 10 02:15:53 PM PST 24 |
| Peak memory | 634624 kb |
| Host | smart-eaa99b19-313b-4589-9d2a-8d2a0c694746 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 901688124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.901688124 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2157289589 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 3558157188 ps |
| CPU time | 341.19 seconds |
| Started | Jan 10 02:06:42 PM PST 24 |
| Finished | Jan 10 02:12:27 PM PST 24 |
| Peak memory | 628976 kb |
| Host | smart-a2e99a60-58fb-4176-ba1c-3b3b8e0bf930 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157289589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2157289589 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.3791855414 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4484573948 ps |
| CPU time | 551.21 seconds |
| Started | Jan 10 02:08:16 PM PST 24 |
| Finished | Jan 10 02:17:31 PM PST 24 |
| Peak memory | 634856 kb |
| Host | smart-a9172147-db17-4576-90a2-f40a2e6fd78f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3791855414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3791855414 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1697380657 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4045882056 ps |
| CPU time | 319.85 seconds |
| Started | Jan 10 02:06:58 PM PST 24 |
| Finished | Jan 10 02:12:22 PM PST 24 |
| Peak memory | 633120 kb |
| Host | smart-29b860f8-617a-4dfb-a946-de5e1adaa2af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697380657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1697380657 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.749444189 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 5034088968 ps |
| CPU time | 562.45 seconds |
| Started | Jan 10 02:06:52 PM PST 24 |
| Finished | Jan 10 02:16:18 PM PST 24 |
| Peak memory | 603388 kb |
| Host | smart-aba28262-d6e5-4d4d-be6e-033ac9f0b745 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 749444189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.749444189 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1601939113 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3534948600 ps |
| CPU time | 417.82 seconds |
| Started | Jan 10 02:07:10 PM PST 24 |
| Finished | Jan 10 02:14:16 PM PST 24 |
| Peak memory | 633392 kb |
| Host | smart-fd87793f-aa76-4531-a9d5-bc8869c1cd10 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601939113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1601939113 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2743520614 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4789664800 ps |
| CPU time | 463.02 seconds |
| Started | Jan 10 02:06:45 PM PST 24 |
| Finished | Jan 10 02:14:33 PM PST 24 |
| Peak memory | 634392 kb |
| Host | smart-5bece5ff-cf73-4ad4-879b-887426032baf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2743520614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2743520614 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2759325887 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 3882886110 ps |
| CPU time | 325.13 seconds |
| Started | Jan 10 02:01:27 PM PST 24 |
| Finished | Jan 10 02:06:59 PM PST 24 |
| Peak memory | 633428 kb |
| Host | smart-b89afb32-8044-496a-aafc-a9f22a8b38ec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759325887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.2759325887 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.2897432172 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 5102462092 ps |
| CPU time | 463.26 seconds |
| Started | Jan 10 02:02:11 PM PST 24 |
| Finished | Jan 10 02:10:02 PM PST 24 |
| Peak memory | 631648 kb |
| Host | smart-395331a7-0929-4710-9812-b404a29c3966 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2897432172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.2897432172 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2247481194 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 10145126819 ps |
| CPU time | 961.5 seconds |
| Started | Jan 10 02:01:40 PM PST 24 |
| Finished | Jan 10 02:17:44 PM PST 24 |
| Peak memory | 604788 kb |
| Host | smart-2128cde6-77b0-4231-8226-072bbbffc8c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247481194 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.2247481194 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3934593963 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 13314270998 ps |
| CPU time | 2251.02 seconds |
| Started | Jan 10 02:06:42 PM PST 24 |
| Finished | Jan 10 02:44:17 PM PST 24 |
| Peak memory | 599572 kb |
| Host | smart-c4558c11-fa0b-4054-9c80-73da5180c6cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart0_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3934593963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3934593963 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.1769027135 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5031401014 ps |
| CPU time | 586.62 seconds |
| Started | Jan 10 02:09:13 PM PST 24 |
| Finished | Jan 10 02:19:04 PM PST 24 |
| Peak memory | 634900 kb |
| Host | smart-589b279a-6343-413b-a882-df8350f50d1b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1769027135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1769027135 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2283271106 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 5455929888 ps |
| CPU time | 580.44 seconds |
| Started | Jan 10 02:06:10 PM PST 24 |
| Finished | Jan 10 02:15:52 PM PST 24 |
| Peak memory | 634496 kb |
| Host | smart-3cc64769-7e0d-456b-8e35-4cfea7f2d868 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2283271106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2283271106 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.839731654 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 6028388300 ps |
| CPU time | 609.55 seconds |
| Started | Jan 10 02:09:29 PM PST 24 |
| Finished | Jan 10 02:19:41 PM PST 24 |
| Peak memory | 634508 kb |
| Host | smart-2d3bc390-2e66-461f-b8dd-708fa392d479 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 839731654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.839731654 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.1014288319 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 5525381672 ps |
| CPU time | 537.17 seconds |
| Started | Jan 10 02:07:01 PM PST 24 |
| Finished | Jan 10 02:16:03 PM PST 24 |
| Peak memory | 634932 kb |
| Host | smart-c4bbaf9f-5c14-4805-883d-d0ff61b3c998 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1014288319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1014288319 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.1733231074 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 6424815290 ps |
| CPU time | 580.87 seconds |
| Started | Jan 10 02:06:54 PM PST 24 |
| Finished | Jan 10 02:16:38 PM PST 24 |
| Peak memory | 634620 kb |
| Host | smart-8c283986-057d-434b-ada0-4c0580f3fde2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1733231074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1733231074 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.1406187302 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 4926173160 ps |
| CPU time | 549.07 seconds |
| Started | Jan 10 02:06:33 PM PST 24 |
| Finished | Jan 10 02:15:46 PM PST 24 |
| Peak memory | 598920 kb |
| Host | smart-950eb26c-a71b-47a8-9f16-0586ed1d249b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1406187302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.1406187302 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1678040822 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 5093790828 ps |
| CPU time | 224.69 seconds |
| Started | Jan 10 01:46:46 PM PST 24 |
| Finished | Jan 10 01:50:34 PM PST 24 |
| Peak memory | 619152 kb |
| Host | smart-6537ac1a-7e19-46c6-9b6b-1a8ef4d874b5 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678040822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.1678040822 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2416125383 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 5153780713 ps |
| CPU time | 263.81 seconds |
| Started | Jan 10 01:47:06 PM PST 24 |
| Finished | Jan 10 01:51:32 PM PST 24 |
| Peak memory | 630788 kb |
| Host | smart-922d9bc3-f22f-47d5-8c08-c221105d9060 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416125383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.2416125383 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2497588686 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4534844480 ps |
| CPU time | 169.57 seconds |
| Started | Jan 10 01:47:14 PM PST 24 |
| Finished | Jan 10 01:50:06 PM PST 24 |
| Peak memory | 626312 kb |
| Host | smart-6b44c311-63c5-4dc3-b059-44a36cda4c64 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497588686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.2497588686 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1527266314 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 4247963574 ps |
| CPU time | 231.79 seconds |
| Started | Jan 10 01:47:10 PM PST 24 |
| Finished | Jan 10 01:51:05 PM PST 24 |
| Peak memory | 629168 kb |
| Host | smart-e0e8fa39-8139-4ca4-8b42-cd41d3009ce6 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527266314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1527266314 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3428476304 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4392436284 ps |
| CPU time | 217.88 seconds |
| Started | Jan 10 01:47:01 PM PST 24 |
| Finished | Jan 10 01:50:43 PM PST 24 |
| Peak memory | 634164 kb |
| Host | smart-c0ad19e1-fdb9-48f0-961c-7858482bfb19 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428476304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.3428476304 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1736231198 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 4502007112 ps |
| CPU time | 212.19 seconds |
| Started | Jan 10 01:47:05 PM PST 24 |
| Finished | Jan 10 01:50:39 PM PST 24 |
| Peak memory | 634176 kb |
| Host | smart-9b526a20-3cbb-4cd7-b07a-d61866c2821a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736231198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1736231198 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3633895954 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3411976492 ps |
| CPU time | 167.54 seconds |
| Started | Jan 10 01:47:16 PM PST 24 |
| Finished | Jan 10 01:50:06 PM PST 24 |
| Peak memory | 628708 kb |
| Host | smart-834b11f2-26bf-4540-abc0-77c82d13275d |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633895954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.3633895954 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1013248740 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 5367555434 ps |
| CPU time | 257.2 seconds |
| Started | Jan 10 01:47:23 PM PST 24 |
| Finished | Jan 10 01:51:42 PM PST 24 |
| Peak memory | 628352 kb |
| Host | smart-d9d6e7ee-29ea-4a2b-add3-4b06e8713ca6 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013248740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.1013248740 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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