Unified Coverage Report :: Module :: tlul_cmd_intg_chk

Module : tlul_cmd_intg_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk	100.00	100.00					100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.39	99.61	69.95			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.17	100.00	76.67			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.37	100.00	69.98			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.64	99.44	69.97			97.14	100.00	u_reg_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_tlul_data_integ_dec	100.00	100.00

Line Coverage for Module : tlul_cmd_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Module : tlul_cmd_intg_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	3832	3832	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	3832	3832	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T23	4	4	0	0
T49	4	4	0	0
T65	4	4	0	0
T66	4	4	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	958	958	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	958	958	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	958	958	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	22	1	1	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	49	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
22	1	1
44		unreachable
49	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	958	958	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0