Unified Coverage Report :: Module :: sensor_ctrl_reg_top

Module : sensor_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	100.00	76.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg	94.17	100.00	76.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.17	100.00	76.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.86	91.85	89.95			93.64	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.64	91.78	83.05	93.39		100.00	100.00	u_sensor_ctrl_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_alert_trig_val_0	100.00	100.00	100.00			100.00
u_alert_trig_val_1	100.00	100.00	100.00			100.00
u_alert_trig_val_10	100.00	100.00	100.00			100.00
u_alert_trig_val_2	100.00	100.00	100.00			100.00
u_alert_trig_val_3	100.00	100.00	100.00			100.00
u_alert_trig_val_4	100.00	100.00	100.00			100.00
u_alert_trig_val_5	100.00	100.00	100.00			100.00
u_alert_trig_val_6	100.00	100.00	100.00			100.00
u_alert_trig_val_7	100.00	100.00	100.00			100.00
u_alert_trig_val_8	100.00	100.00	100.00			100.00
u_alert_trig_val_9	100.00	100.00	100.00			100.00
u_cfg_regwen	89.63	88.89	80.00			100.00
u_chk	100.00	100.00					100.00
u_fatal_alert_en_val_0	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_1	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_10	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_2	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_3	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_4	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_5	96.30	88.89	100.00			100.00
u_fatal_alert_en_val_6	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_7	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_8	100.00	100.00	100.00			100.00
u_fatal_alert_en_val_9	100.00	100.00	100.00			100.00
u_fatal_alert_val_0	96.30	88.89	100.00			100.00
u_fatal_alert_val_1	47.78	33.33	50.00			60.00
u_fatal_alert_val_10	47.78	33.33	50.00			60.00
u_fatal_alert_val_11	96.30	88.89	100.00			100.00
u_fatal_alert_val_2	96.30	88.89	100.00			100.00
u_fatal_alert_val_3	96.30	88.89	100.00			100.00
u_fatal_alert_val_4	96.30	88.89	100.00			100.00
u_fatal_alert_val_5	47.78	33.33	50.00			60.00
u_fatal_alert_val_6	96.30	88.89	100.00			100.00
u_fatal_alert_val_7	47.78	33.33	50.00			60.00
u_fatal_alert_val_8	47.78	33.33	50.00			60.00
u_fatal_alert_val_9	47.78	33.33	50.00			60.00
u_intr_enable_init_status_change	100.00	100.00	100.00			100.00
u_intr_enable_io_status_change	100.00	100.00	100.00			100.00
u_intr_state_init_status_change	100.00	100.00	100.00			100.00
u_intr_state_io_status_change	100.00	100.00	100.00			100.00
u_intr_test_init_status_change	100.00	100.00
u_intr_test_io_status_change	100.00	100.00
u_prim_reg_we_check	100.00	100.00
u_recov_alert_val_0	100.00	100.00	100.00			100.00
u_recov_alert_val_1	100.00	100.00	100.00			100.00
u_recov_alert_val_10	100.00	100.00	100.00			100.00
u_recov_alert_val_2	100.00	100.00	100.00			100.00
u_recov_alert_val_3	100.00	100.00	100.00			100.00
u_recov_alert_val_4	100.00	100.00	100.00			100.00
u_recov_alert_val_5	100.00	100.00	100.00			100.00
u_recov_alert_val_6	100.00	100.00	100.00			100.00
u_recov_alert_val_7	100.00	100.00	100.00			100.00
u_recov_alert_val_8	100.00	100.00	100.00			100.00
u_recov_alert_val_9	100.00	100.00	100.00			100.00
u_reg_if	83.13	85.71	74.07			72.73	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_ast_init_done	62.59	77.78	50.00			60.00
u_status_io_pok	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		150	150	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
ALWAYS	1734	11	11	100.00
CONT_ASSIGN	1747	1	1	100.00
ALWAYS	1751	1	1	100.00
CONT_ASSIGN	1765	1	1	100.00
CONT_ASSIGN	1767	1	1	100.00
CONT_ASSIGN	1769	1	1	100.00
CONT_ASSIGN	1770	1	1	100.00
CONT_ASSIGN	1772	1	1	100.00
CONT_ASSIGN	1774	1	1	100.00
CONT_ASSIGN	1775	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1780	1	1	100.00
CONT_ASSIGN	1782	1	1	100.00
CONT_ASSIGN	1784	1	1	100.00
CONT_ASSIGN	1785	1	1	100.00
CONT_ASSIGN	1787	1	1	100.00
CONT_ASSIGN	1788	1	1	100.00
CONT_ASSIGN	1790	1	1	100.00
CONT_ASSIGN	1792	1	1	100.00
CONT_ASSIGN	1794	1	1	100.00
CONT_ASSIGN	1796	1	1	100.00
CONT_ASSIGN	1798	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1804	1	1	100.00
CONT_ASSIGN	1806	1	1	100.00
CONT_ASSIGN	1808	1	1	100.00
CONT_ASSIGN	1810	1	1	100.00
CONT_ASSIGN	1811	1	1	100.00
CONT_ASSIGN	1813	1	1	100.00
CONT_ASSIGN	1815	1	1	100.00
CONT_ASSIGN	1817	1	1	100.00
CONT_ASSIGN	1819	1	1	100.00
CONT_ASSIGN	1821	1	1	100.00
CONT_ASSIGN	1823	1	1	100.00
CONT_ASSIGN	1825	1	1	100.00
CONT_ASSIGN	1827	1	1	100.00
CONT_ASSIGN	1829	1	1	100.00
CONT_ASSIGN	1831	1	1	100.00
CONT_ASSIGN	1833	1	1	100.00
CONT_ASSIGN	1834	1	1	100.00
CONT_ASSIGN	1836	1	1	100.00
CONT_ASSIGN	1838	1	1	100.00
CONT_ASSIGN	1840	1	1	100.00
CONT_ASSIGN	1842	1	1	100.00
CONT_ASSIGN	1844	1	1	100.00
CONT_ASSIGN	1846	1	1	100.00
CONT_ASSIGN	1848	1	1	100.00
CONT_ASSIGN	1850	1	1	100.00
CONT_ASSIGN	1852	1	1	100.00
CONT_ASSIGN	1854	1	1	100.00
CONT_ASSIGN	1856	1	1	100.00
ALWAYS	1860	11	11	100.00
ALWAYS	1875	58	58	100.00
CONT_ASSIGN	1974	0	0
CONT_ASSIGN	1982	1	1	100.00
CONT_ASSIGN	1983	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
346	1	1
361	1	1
377	1	1
383	1	1
398	1	1
414	1	1
749	1	1
1734	1	1
1735	1	1
1736	1	1
1737	1	1
1738	1	1
1739	1	1
1740	1	1
1741	1	1
1742	1	1
1743	1	1
1744	1	1
1747	1	1
1751	1	1
1765	1	1
1767	1	1
1769	1	1
1770	1	1
1772	1	1
1774	1	1
1775	1	1
1777	1	1
1779	1	1
1780	1	1
1782	1	1
1784	1	1
1785	1	1
1787	1	1
1788	1	1
1790	1	1
1792	1	1
1794	1	1
1796	1	1
1798	1	1
1800	1	1
1802	1	1
1804	1	1
1806	1	1
1808	1	1
1810	1	1
1811	1	1
1813	1	1
1815	1	1
1817	1	1
1819	1	1
1821	1	1
1823	1	1
1825	1	1
1827	1	1
1829	1	1
1831	1	1
1833	1	1
1834	1	1
1836	1	1
1838	1	1
1840	1	1
1842	1	1
1844	1	1
1846	1	1
1848	1	1
1850	1	1
1852	1	1
1854	1	1
1856	1	1
1860	1	1
1861	1	1
1862	1	1
1863	1	1
1864	1	1
1865	1	1
1866	1	1
1867	1	1
1868	1	1
1869	1	1
1870	1	1
1875	1	1
1876	1	1
1878	1	1
1879	1	1
1883	1	1
1884	1	1
1888	1	1
1889	1	1
1893	1	1
1894	1	1
1898	1	1
1902	1	1
1903	1	1
1904	1	1
1905	1	1
1906	1	1
1907	1	1
1908	1	1
1909	1	1
1910	1	1
1911	1	1
1912	1	1
1916	1	1
1917	1	1
1918	1	1
1919	1	1
1920	1	1
1921	1	1
1922	1	1
1923	1	1
1924	1	1
1925	1	1
1926	1	1
1930	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1953	1	1
1954	1	1
1955	1	1
1959	1	1
1960	1	1
1974		unreachable
1982	1	1
1983	1	1

---

Cond Coverage for Module : sensor_ctrl_reg_top

	Total	Covered	Percent
Conditions	120	92	76.67
Logical	120	92	76.67
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T35,T104,T143

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T342,T344,T256
1	0	Not Covered

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T342,T344,T256
0	1	0	Not Covered
1	0	0	Covered	T342,T344,T256

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       749
 EXPRESSION (fatal_alert_en_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T104,T116,T88

 LINE       1735
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1736
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1737
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1738
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1739
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_CFG_REGWEN_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1740
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_ALERT_TRIG_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1741
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_EN_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1742
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_RECOV_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1743
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_FATAL_ALERT_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1744
 EXPRESSION (reg_addr == sensor_ctrl_reg_pkg::SENSOR_CTRL_STATUS_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1747
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1747
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T35,T104,T143
1	0	Covered	T1,T2,T3

 LINE       1751
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T35,T104,T143
1	1	Not Covered

 LINE       1751
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	Status	Tests
0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	1	Not Covered
0	0	0	0	0	0	0	0	1	0	Covered	T10,T11,T12
0	0	0	0	0	0	0	1	0	0	Covered	T10,T11,T12
0	0	0	0	0	0	1	0	0	0	Covered	T10,T11,T12
0	0	0	0	0	1	0	0	0	0	Covered	T10,T11,T12
0	0	0	0	1	0	0	0	0	0	Not Covered
0	0	0	1	0	0	0	0	0	0	Not Covered
0	0	1	0	0	0	0	0	0	0	Not Covered
0	1	0	0	0	0	0	0	0	0	Not Covered
1	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3

 LINE       1751
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1751
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1751
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1751
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1751
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1751
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T11,T12

 LINE       1751
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T11,T12

 LINE       1751
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T11,T12

 LINE       1751
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T11,T12

 LINE       1751
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       1765
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T104,T143
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T143,T98,T322

 LINE       1770
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T104,T143
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T143,T88,T98

 LINE       1775
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T104,T143
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T143,T166,T167

 LINE       1780
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T104,T143,T116
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T35,T88,T36

 LINE       1785
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T104,T143
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T88

 LINE       1788
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T104,T143
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T104,T116,T117

 LINE       1811
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T104,T143
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T104,T116,T88

 LINE       1834
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T104,T143
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T104,T116,T88

---

Branch Coverage for Module : sensor_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
TERNARY	1747	2	2	100.00
IF	71	3	3	100.00
CASE	1876	11	11	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv' or '../src/lowrisc_systems_sensor_ctrl_reg_0.1/rtl/sensor_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1747	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T342,T344,T256
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1876	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : sensor_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	99927493	2346	0	0
reAfterRv	99927493	2346	0	0
rePulse	99927493	2032	0	0
wePulse	99927493	314	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	99927493	2346	0	0
T1	26915	1	0	0
T2	36556	1	0	0
T3	59784	1	0	0
T16	108004	3	0	0
T17	60701	2	0	0
T18	46406	2	0	0
T23	211526	0	0	0
T44	0	2	0	0
T49	42405	1	0	0
T65	67768	1	0	0
T66	18213	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	99927493	2346	0	0
T1	26915	1	0	0
T2	36556	1	0	0
T3	59784	1	0	0
T16	108004	3	0	0
T17	60701	2	0	0
T18	46406	2	0	0
T23	211526	0	0	0
T44	0	2	0	0
T49	42405	1	0	0
T65	67768	1	0	0
T66	18213	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	99927493	2032	0	0
T1	26915	1	0	0
T2	36556	1	0	0
T3	59784	1	0	0
T16	108004	3	0	0
T17	60701	2	0	0
T18	46406	2	0	0
T23	211526	0	0	0
T44	0	2	0	0
T49	42405	1	0	0
T65	67768	1	0	0
T66	18213	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	99927493	314	0	0
T35	29137	2	0	0
T36	0	2	0	0
T86	153757	0	0	0
T88	0	7	0	0
T98	0	12	0	0
T104	0	24	0	0
T116	0	21	0	0
T117	0	33	0	0
T120	0	14	0	0
T137	61638	0	0	0
T143	0	8	0	0
T146	30333	0	0	0
T197	63806	0	0	0
T206	119860	0	0	0
T214	43491	0	0	0
T235	27577	0	0	0
T322	0	12	0	0
T350	42163	0	0	0
T351	22738	0	0	0