Unified Coverage Report :: Module :: tlul_adapter_host

Module : tlul_adapter_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.09	91.11	75.79			89.44	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex	87.26	90.91	69.23			88.89	100.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex	90.91	91.30	82.35			90.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.26	90.91	69.23			88.89	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.90	90.48	72.22			88.89	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.43	96.47	89.29	87.72		100.00	73.68	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_intg_gen	94.12	88.24					100.00
u_rsp_chk	93.33	100.00	80.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.91	91.30	82.35			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.79	95.35	81.82			90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.43	96.47	89.29	87.72		100.00	73.68	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmd_intg_gen	100.00	100.00					100.00
u_rsp_chk	93.33	100.00	80.00				100.00

Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
90.91	91.30

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Line No.	Total	Covered	Percent
TOTAL		23	21	91.30
ALWAYS	69	3	3	100.00
ALWAYS	77	5	5	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	131	4	3	75.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	0	0
ALWAYS	176	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
72	1	1
77	1	1
79	1	1
80	1	1
81	1	1
83	1	1
			MISSING_ELSE
88	1	1
93	1	1
95	1	1
115	1	1
117	1	1
118	1	1
119	1	1
131	1	1
132	1	1
133	1	1
134	0	1
			MISSING_ELSE
140	1	1
144	1	1
148	0	1
152	1	1
166		unreachable
168		unreachable
169		unreachable
170		unreachable
171		unreachable
			==> MISSING_ELSE
176		unreachable
177		unreachable
179		unreachable

---

Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
87.26	90.91

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
ALWAYS	69	3	3	100.00
ALWAYS	77	5	5	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	131	4	3	75.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	0	0
ALWAYS	176	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
72	1	1
77	1	1
79	1	1
80	1	1
81	1	1
83	1	1
			MISSING_ELSE
88	1	1
93		unreachable
95	1	1
115	1	1
117	1	1
118	1	1
119	1	1
131	1	1
132	1	1
133	1	1
134	0	1
			MISSING_ELSE
140	1	1
144	1	1
148	0	1
152	1	1
166		unreachable
168		unreachable
169		unreachable
170		unreachable
171		unreachable
			==> MISSING_ELSE
176		unreachable
177		unreachable
179		unreachable

---

Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
87.26	69.23

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       95
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       140
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T47,T55

 LINE       144
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.91	82.35

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Total	Covered	Percent
Conditions	17	14	82.35
Logical	17	14	82.35
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       95
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T47,T48

 LINE       144
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
90.91	90.00

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	93	2	2	100.00
IF	131	3	2	66.67
IF	69	2	2	100.00
IF	79	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	93	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	131	if ((!rst_ni))
-2-:	133	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	79	if ((req_i && gnt_o))
-2-:	80	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
87.26	88.89

tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
TERNARY	93	1	1	100.00
IF	131	3	2	66.67
IF	69	2	2	100.00
IF	79	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	93	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	131	if ((!rst_ni))
-2-:	133	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	79	if ((req_i && gnt_o))
-2-:	80	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_host

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	801514482	80106221	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes	Failures	Incomplete
Total	801514482	80106221	0	0
T1	221130	24296	0	0
T2	301454	30336	0	0
T3	495018	48322	0	0
T16	890496	78868	0	0
T17	499486	38060	0	0
T18	380382	39040	0	0
T23	1759430	251415	0	0
T49	350198	3929	0	0
T65	561552	59464	0	0
T66	148612	12039	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
ALWAYS	69	3	3	100.00
ALWAYS	77	5	5	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	131	4	3	75.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	0	0
ALWAYS	176	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
72	1	1
77	1	1
79	1	1
80	1	1
81	1	1
83	1	1
			MISSING_ELSE
88	1	1
93		unreachable
95	1	1
115	1	1
117	1	1
118	1	1
119	1	1
131	1	1
132	1	1
133	1	1
134	0	1
			MISSING_ELSE
140	1	1
144	1	1
148	0	1
152	1	1
166		unreachable
168		unreachable
169		unreachable
170		unreachable
171		unreachable
			==> MISSING_ELSE
176		unreachable
177		unreachable
179		unreachable

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Total	Covered	Percent
Conditions	13	9	69.23
Logical	13	9	69.23
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       95
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       140
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T47,T55

 LINE       144
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
TERNARY	93	1	1	100.00
IF	131	3	2	66.67
IF	69	2	2	100.00
IF	79	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	93	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	131	if ((!rst_ni))
-2-:	133	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	79	if ((req_i && gnt_o))
-2-:	80	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	400757241	46022109	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	46022109	0	0
T1	110565	14036	0	0
T2	150727	21437	0	0
T3	247509	30583	0	0
T16	445248	55535	0	0
T17	249743	25412	0	0
T18	190191	25149	0	0
T23	879715	101432	0	0
T49	175099	3464	0	0
T65	280776	34021	0	0
T66	74306	7435	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Line No.	Total	Covered	Percent
TOTAL		23	21	91.30
ALWAYS	69	3	3	100.00
ALWAYS	77	5	5	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
ALWAYS	131	4	3	75.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	152	1	1	100.00
ALWAYS	166	0	0
ALWAYS	176	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
72	1	1
77	1	1
79	1	1
80	1	1
81	1	1
83	1	1
			MISSING_ELSE
88	1	1
93	1	1
95	1	1
115	1	1
117	1	1
118	1	1
119	1	1
131	1	1
132	1	1
133	1	1
134	0	1
			MISSING_ELSE
140	1	1
144	1	1
148	0	1
152	1	1
166		unreachable
168		unreachable
169		unreachable
170		unreachable
171		unreachable
			==> MISSING_ELSE
176		unreachable
177		unreachable
179		unreachable

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Total	Covered	Percent
Conditions	17	14	82.35
Logical	17	14	82.35
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (req_i && gnt_o)
             --1--    --2--

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       95
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T47,T48

 LINE       144
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	93	2	2	100.00
IF	131	3	2	66.67
IF	69	2	2	100.00
IF	79	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	93	((~we_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	131	if ((!rst_ni))
-2-:	133	if (intg_err)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	79	if ((req_i && gnt_o))
-2-:	80	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DontExceeedMaxReqs	400757241	34084112	0	0

DontExceeedMaxReqs

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	34084112	0	0
T1	110565	10260	0	0
T2	150727	8899	0	0
T3	247509	17739	0	0
T16	445248	23333	0	0
T17	249743	12648	0	0
T18	190191	13891	0	0
T23	879715	149983	0	0
T49	175099	465	0	0
T65	280776	25443	0	0
T66	74306	4604	0	0