Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.22	96.47	89.29	86.64		100.00	73.68

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	89.43	96.47	89.29	87.72		100.00	73.68

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.43	96.47	89.29	87.72		100.00	73.68

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.57	96.36	80.95	90.86		96.27	93.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.74	90.68		90.55			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	91.79	95.35	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.63			96.63
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	96.36	100.00	92.59			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	93.19	96.39	79.74			96.64	100.00
u_sim_win_rsp	80.88	77.55	68.18			77.78	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	725	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
ALWAYS	789	11	11	100.00
ALWAYS	805	7	7	100.00
CONT_ASSIGN	816	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	837	1	1	100.00
CONT_ASSIGN	840	1	0	0.00
CONT_ASSIGN	844	0	0
CONT_ASSIGN	883	1	1	100.00
ALWAYS	936	0	0
CONT_ASSIGN	977	1	0	0.00
CONT_ASSIGN	979	1	0	0.00
CONT_ASSIGN	981	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	985	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
699	2	2
700	2	2
701	2	2
705	2	2
706	2	2
707	2	2
714	1	1
715	1	1
716	1	1
719	1	1
721	1	1
723	1	1
725	1	1
732	1	1
734	1	1
736	1	1
738	1	1
748	1	1
749	1	1
750	1	1
751	1	1
754	1	1
757	1	1
789	1	1
790	1	1
791	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
			MISSING_ELSE
805	1	1
806	1	1
807	1	1
808	1	1
810	1	1
811	1	1
812	1	1
816	1	1
835	1	1
836	1	1
837	1	1
840	0	1
844		unreachable
883	1	1
936		unreachable
937		unreachable
938		unreachable
939		unreachable
			==> MISSING_ELSE
977	0	1
979	0	1
981	1	1
983	1	1
985	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T215,T105,T76
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T216,T217
1	0	Covered	T4,T151,T97

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T4,T151

 LINE       732
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T139,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T35,T36,T218

 LINE       734
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T218
1	0	Covered	T1,T2,T3
1	1	Covered	T35,T139,T26

 LINE       736
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T139,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T35,T36,T218

 LINE       738
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T139,T219
1	0	Covered	T1,T2,T3
1	1	Covered	T35,T26,T36

 LINE       750
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T17,T4,T151
0	1	0	Covered	T215,T105,T76
1	0	0	Covered	T2,T220,T221

 LINE       797
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	91	75.21
Total Bits	1624	1407	86.64
Total Bits 0->1	812	704	86.70
Total Bits 1->0	812	703	86.58

Ports	121	91	75.21
Port Bits	1624	1407	86.64
Port Bits 0->1	812	704	86.70
Port Bits 1->0	812	703	86.58

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T222,T223,T224	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	*T21,*T225,*T226	Yes	T21,T225,T226	OUTPUT
corei_tl_h_o.a_address[30]	No	No		No		OUTPUT
corei_tl_h_o.a_address[31]	Yes	Yes	T227,T228,T229	Yes	T227,T228,T229	OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T17,T47,T55	Yes	T17,T47,T55	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T17,*T47,*T55	Yes	T17,T47,T55	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T19,T126,T127	Yes	T19,T126,T127	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T19,T126,T127	Yes	T19,T126,T127	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T17,T47,T48	Yes	T17,T47,T48	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T230,T231,T232	Yes	T230,T231,T232	INPUT
irq_timer_i	Yes	Yes	T233,T143,T234	Yes	T233,T143,T234	INPUT
irq_external_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_n	Yes	Yes	T2,T17,T47	Yes	T2,T17,T47	INPUT
esc_tx_i.esc_p	Yes	Yes	T2,T17,T47	Yes	T2,T17,T47	INPUT
esc_rx_o.resp_n	Yes	Yes	T2,T17,T47	Yes	T2,T17,T47	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T2,T17,T47	Yes	T2,T17,T47	OUTPUT
nmi_wdog_i	Yes	Yes	T235,T236,T237	Yes	T235,T236,T237	INPUT
debug_req_i	Yes	Yes	T55,T128,T129	Yes	T55,T128,T129	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T2,T16,T17	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T26,*T1,*T2	Yes	T26,T1,T2	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T26	Yes	T26	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T26,*T1,*T2	Yes	T26,T1,T2	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T2,T16,T17	Yes	T1,T2,T16	INPUT
edn_i.edn_fips	Yes	Yes	T156,T113,T83	Yes	T156,T113,T83	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T238,T227,T239	Yes	T238,T227,T239	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T1,T2,T3	Yes	T3,T16,T65	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T3,T16,T65	Yes	T3,T16,T65	INPUT
icache_otp_key_i.ack	Yes	Yes	T238,T227,T239	Yes	T238,T227,T239	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T35,T61,T160	Yes	T35,T61,T160	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T2,T17,T215	Yes	T2,T17,T215	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T61,T62,T63	Yes	T61,T63,T64	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T61,T63,T64	Yes	T61,T62,T63	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T35,T61,T26	Yes	T35,T61,T26	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T61,T240,T62	Yes	T61,T63,T64	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T61,T63,T64	Yes	T61,T240,T62	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T35,T61,T160	Yes	T35,T61,T160	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T2,T17,T215	Yes	T2,T17,T215	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T35,T61,T26	Yes	T35,T61,T26	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	793	3	3	100.00
IF	805	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T4,T151
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T17,T216,T217
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	793	if (reg2hw.rnd_data.re)
-2-:	797	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	805	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	14	73.68
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	14	73.68

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	400757241	4	0	0
FpvSecCmIbexFetchEnable1_A	400757241	23100191	0	80
FpvSecCmIbexFetchEnable2_A	400757241	60869626	0	86
FpvSecCmIbexFetchEnable3Rev_A	400757241	335149981	0	1896
FpvSecCmIbexFetchEnable3_A	400757241	335151697	0	1808
FpvSecCmIbexInstrIntgErrCheck_A	400757241	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	400757241	588	0	0
FpvSecCmIbexPcMismatchCheck_A	400757241	0	0	0
FpvSecCmIbexRfEccErrCheck_A	400757241	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	400757241	0	0	0
FpvSecCmRegWeOnehotCheck_A	400757241	7	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	400757241	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	958	958	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	958	958	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	958	958	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	958	958	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	958	958	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	400757241	147	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	400757241	197	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	4	0	0
T4	632780	0	0	0
T17	249743	1	0	0
T18	190191	0	0	0
T23	879715	0	0	0
T28	147051	0	0	0
T44	144270	0	0	0
T47	221161	0	0	0
T48	258383	0	0	0
T49	175099	0	0	0
T66	74306	0	0	0
T216	0	1	0	0
T217	0	1	0	0
T241	0	1	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	23100191	0	80
T1	110565	9595	0	0
T2	150727	9587	0	0
T3	247509	9599	0	0
T4	0	0	0	2
T10	0	0	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	445248	28769	0	0
T17	249743	40448	0	0
T18	190191	19190	0	0
T19	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T23	879715	9587	0	0
T45	0	0	0	2
T49	175099	9591	0	0
T65	280776	9595	0	0
T66	74306	9599	0	0
T79	0	0	0	2
T183	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	60869626	0	86
T1	110565	34775	0	0
T2	150727	38307	0	0
T3	247509	34775	0	0
T4	0	0	0	2
T10	0	0	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	445248	104330	0	0
T17	249743	69555	0	0
T18	190191	69555	0	0
T19	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T23	879715	34775	0	0
T45	0	0	0	2
T49	175099	34775	0	0
T65	280776	34775	0	0
T66	74306	34775	0	0
T79	0	0	0	2
T183	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	335149981	0	1896
T1	110565	75729	0	2
T2	150727	112366	0	2
T3	247509	212673	0	2
T16	445248	340749	0	2
T17	249743	118805	0	2
T18	190191	120510	0	2
T23	879715	844886	0	2
T49	175099	140266	0	2
T65	280776	245936	0	2
T66	74306	39466	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	335151697	0	1808
T1	110565	75730	0	2
T2	150727	112367	0	2
T3	247509	212674	0	2
T16	445248	340751	0	2
T17	249743	118807	0	2
T18	190191	120512	0	2
T23	879715	844887	0	2
T49	175099	140267	0	2
T65	280776	245937	0	2
T66	74306	39467	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	588	0	0
T24	665494	0	0	0
T76	0	100	0	0
T94	346219	0	0	0
T105	186551	31	0	0
T111	206202	0	0	0
T157	0	31	0	0
T180	229781	0	0	0
T186	429823	0	0	0
T215	152673	99	0	0
T226	0	1	0	0
T242	0	1	0	0
T243	0	31	0	0
T244	0	32	0	0
T245	0	1	0	0
T246	0	1	0	0
T247	210047	0	0	0
T248	79292	0	0	0
T249	383635	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	7	0	0
T2	150727	1	0	0
T3	247509	0	0	0
T16	445248	0	0	0
T17	249743	0	0	0
T18	190191	0	0	0
T23	879715	0	0	0
T44	144270	0	0	0
T49	175099	0	0	0
T65	280776	0	0	0
T66	74306	0	0	0
T220	0	1	0	0
T221	0	1	0	0
T250	0	1	0	0
T251	0	1	0	0
T252	0	1	0	0
T253	0	1	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	147	0	0
T227	83002	17	0	0
T228	0	18	0	0
T229	0	18	0	0
T238	102469	37	0	0
T239	0	28	0	0
T254	0	29	0	0
T255	261751	0	0	0
T256	287260	0	0	0
T257	344789	0	0	0
T258	162609	0	0	0
T259	283975	0	0	0
T260	77381	0	0	0
T261	145960	0	0	0
T262	151157	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	197	0	0
T158	0	16	0	0
T159	0	16	0	0
T227	83002	42	0	0
T228	0	42	0	0
T229	0	42	0	0
T238	102469	9	0	0
T239	0	7	0	0
T254	0	7	0	0
T255	261751	0	0	0
T256	287260	0	0	0
T257	344789	0	0	0
T258	162609	0	0	0
T259	283975	0	0	0
T260	77381	0	0	0
T261	145960	0	0	0
T262	151157	0	0	0
T263	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	725	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
ALWAYS	789	11	11	100.00
ALWAYS	805	7	7	100.00
CONT_ASSIGN	816	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	837	1	1	100.00
CONT_ASSIGN	840	1	0	0.00
CONT_ASSIGN	844	0	0
CONT_ASSIGN	883	1	1	100.00
ALWAYS	936	0	0
CONT_ASSIGN	977	1	0	0.00
CONT_ASSIGN	979	1	0	0.00
CONT_ASSIGN	981	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	985	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
699	2	2
700	2	2
701	2	2
705	2	2
706	2	2
707	2	2
714	1	1
715	1	1
716	1	1
719	1	1
721	1	1
723	1	1
725	1	1
732	1	1
734	1	1
736	1	1
738	1	1
748	1	1
749	1	1
750	1	1
751	1	1
754	1	1
757	1	1
789	1	1
790	1	1
791	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
			MISSING_ELSE
805	1	1
806	1	1
807	1	1
808	1	1
810	1	1
811	1	1
812	1	1
816	1	1
835	1	1
836	1	1
837	1	1
840	0	1
844		unreachable
883	1	1
936		unreachable
937		unreachable
938		unreachable
939		unreachable
			==> MISSING_ELSE
977	0	1
979	0	1
981	1	1
983	1	1
985	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T215,T105,T76
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T216,T217
1	0	Covered	T4,T151,T97

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T4,T151

 LINE       732
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T139,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T35,T36,T218

 LINE       734
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T218
1	0	Covered	T1,T2,T3
1	1	Covered	T35,T139,T26

 LINE       736
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T139,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T35,T36,T218

 LINE       738
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T35,T139,T219
1	0	Covered	T1,T2,T3
1	1	Covered	T35,T26,T36

 LINE       750
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T17,T4,T151
0	1	0	Covered	T215,T105,T76
1	0	0	Covered	T2,T220,T221

 LINE       797
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	91	77.78
Total Bits	1604	1407	87.72
Total Bits 0->1	802	704	87.78
Total Bits 1->0	802	703	87.66

Ports	117	91	77.78
Port Bits	1604	1407	87.72
Port Bits 0->1	802	704	87.78
Port Bits 1->0	802	703	87.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
rst_cpu_n_o	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	No	No		No		OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	No	No		No		OUTPUT
corei_tl_h_o.a_mask[3:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_address[16:2]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_address[18:17]	No	No		No		OUTPUT
corei_tl_h_o.a_address[19]	No	No		Yes	T222,T223,T224	OUTPUT
corei_tl_h_o.a_address[27:20]	No	No		No		OUTPUT
corei_tl_h_o.a_address[29:28]	Yes	Yes	*T21,*T225,*T226	Yes	T21,T225,T226	OUTPUT
corei_tl_h_o.a_address[30]	No	No		No		OUTPUT
corei_tl_h_o.a_address[31]	Yes	Yes	T227,T228,T229	Yes	T227,T228,T229	OUTPUT
corei_tl_h_o.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_o.a_source[5:3]	No	No		No		OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	No	No		No		OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	No	No		No		OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_error	Yes	Yes	T17,T47,T55	Yes	T17,T47,T55	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T17,*T47,*T55	Yes	T17,T47,T55	INPUT
corei_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_sink	No	No		No		INPUT
corei_tl_h_i.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_source[5:3]	No	No		No		INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[0]	No	No		No		INPUT
corei_tl_h_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T19,T126,T127	Yes	T19,T126,T127	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T19,T126,T127	Yes	T19,T126,T127	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_opcode[1]	No	No		No		OUTPUT
cored_tl_h_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_error	Yes	Yes	T17,T47,T48	Yes	T17,T47,T48	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_user.rsp_intg[6]	No	No		No		INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_sink	No	No		No		INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
irq_software_i	Yes	Yes	T230,T231,T232	Yes	T230,T231,T232	INPUT
irq_timer_i	Yes	Yes	T233,T143,T234	Yes	T233,T143,T234	INPUT
irq_external_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_tx_i.esc_n	Yes	Yes	T2,T17,T47	Yes	T2,T17,T47	INPUT
esc_tx_i.esc_p	Yes	Yes	T2,T17,T47	Yes	T2,T17,T47	INPUT
esc_rx_o.resp_n	Yes	Yes	T2,T17,T47	Yes	T2,T17,T47	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T2,T17,T47	Yes	T2,T17,T47	OUTPUT
nmi_wdog_i	Yes	Yes	T235,T236,T237	Yes	T235,T236,T237	INPUT
debug_req_i	Yes	Yes	T55,T128,T129	Yes	T55,T128,T129	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T2,T16,T17	Yes	T1,T2,T3	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.cmd_intg[1]	No	No		No		INPUT
cfg_tl_d_i.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.instr_type[2:1]	No	No		No		INPUT
cfg_tl_d_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_address[7:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[1:0]	Yes	Yes	*T26,*T1,*T2	Yes	T26,T1,T2	INPUT
cfg_tl_d_i.a_source[5:2]	No	No		No		INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[0]	No	No		No		INPUT
cfg_tl_d_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[1:0]	No	No		No		INPUT
cfg_tl_d_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T26	Yes	T26	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[2:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
cfg_tl_d_o.d_user.rsp_intg[5:4]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_sink	No	No		No		OUTPUT
cfg_tl_d_o.d_source[1:0]	Yes	Yes	*T26,*T1,*T2	Yes	T26,T1,T2	OUTPUT
cfg_tl_d_o.d_source[5:2]	No	No		No		OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[0]	No	No		No		OUTPUT
cfg_tl_d_o.d_size[1]	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T2,T16,T17	Yes	T1,T2,T16	INPUT
edn_i.edn_fips	Yes	Yes	T156,T113,T83	Yes	T156,T113,T83	INPUT
edn_i.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
icache_otp_key_o.req	Yes	Yes	T238,T227,T239	Yes	T238,T227,T239	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T16,T17,T18	Yes	T1,T2,T3	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T1,T2,T3	Yes	T3,T16,T65	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T3,T16,T65	Yes	T3,T16,T65	INPUT
icache_otp_key_i.ack	Yes	Yes	T238,T227,T239	Yes	T238,T227,T239	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T35,T61,T160	Yes	T35,T61,T160	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T61,T160,T62	Yes	T61,T160,T62	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T2,T17,T215	Yes	T2,T17,T215	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T61,T62,T63	Yes	T61,T63,T64	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T61,T63,T64	Yes	T61,T62,T63	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T35,T61,T26	Yes	T35,T61,T26	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T61,T240,T62	Yes	T61,T63,T64	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T61,T63,T64	Yes	T61,T240,T62	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T35,T61,T160	Yes	T35,T61,T160	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T35,T61,T139	Yes	T35,T61,T139	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T2,T17,T215	Yes	T2,T17,T215	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T35,T61,T26	Yes	T35,T61,T26	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	793	3	3	100.00
IF	805	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T4,T151
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T17,T216,T217
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	793	if (reg2hw.rnd_data.re)
-2-:	797	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	805	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	14	73.68
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	14	73.68

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	400757241	4	0	0
FpvSecCmIbexFetchEnable1_A	400757241	23100191	0	80
FpvSecCmIbexFetchEnable2_A	400757241	60869626	0	86
FpvSecCmIbexFetchEnable3Rev_A	400757241	335149981	0	1896
FpvSecCmIbexFetchEnable3_A	400757241	335151697	0	1808
FpvSecCmIbexInstrIntgErrCheck_A	400757241	0	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	400757241	588	0	0
FpvSecCmIbexPcMismatchCheck_A	400757241	0	0	0
FpvSecCmIbexRfEccErrCheck_A	400757241	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	400757241	0	0	0
FpvSecCmRegWeOnehotCheck_A	400757241	7	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	400757241	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	958	958	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	958	958	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	958	958	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	958	958	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	958	958	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	400757241	147	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	400757241	197	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	4	0	0
T4	632780	0	0	0
T17	249743	1	0	0
T18	190191	0	0	0
T23	879715	0	0	0
T28	147051	0	0	0
T44	144270	0	0	0
T47	221161	0	0	0
T48	258383	0	0	0
T49	175099	0	0	0
T66	74306	0	0	0
T216	0	1	0	0
T217	0	1	0	0
T241	0	1	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	23100191	0	80
T1	110565	9595	0	0
T2	150727	9587	0	0
T3	247509	9599	0	0
T4	0	0	0	2
T10	0	0	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	445248	28769	0	0
T17	249743	40448	0	0
T18	190191	19190	0	0
T19	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T23	879715	9587	0	0
T45	0	0	0	2
T49	175099	9591	0	0
T65	280776	9595	0	0
T66	74306	9599	0	0
T79	0	0	0	2
T183	0	0	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	60869626	0	86
T1	110565	34775	0	0
T2	150727	38307	0	0
T3	247509	34775	0	0
T4	0	0	0	2
T10	0	0	0	2
T11	0	0	0	2
T12	0	0	0	2
T16	445248	104330	0	0
T17	249743	69555	0	0
T18	190191	69555	0	0
T19	0	0	0	2
T21	0	0	0	2
T22	0	0	0	2
T23	879715	34775	0	0
T45	0	0	0	2
T49	175099	34775	0	0
T65	280776	34775	0	0
T66	74306	34775	0	0
T79	0	0	0	2
T183	0	0	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	335149981	0	1896
T1	110565	75729	0	2
T2	150727	112366	0	2
T3	247509	212673	0	2
T16	445248	340749	0	2
T17	249743	118805	0	2
T18	190191	120510	0	2
T23	879715	844886	0	2
T49	175099	140266	0	2
T65	280776	245936	0	2
T66	74306	39466	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	335151697	0	1808
T1	110565	75730	0	2
T2	150727	112367	0	2
T3	247509	212674	0	2
T16	445248	340751	0	2
T17	249743	118807	0	2
T18	190191	120512	0	2
T23	879715	844887	0	2
T49	175099	140267	0	2
T65	280776	245937	0	2
T66	74306	39467	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	588	0	0
T24	665494	0	0	0
T76	0	100	0	0
T94	346219	0	0	0
T105	186551	31	0	0
T111	206202	0	0	0
T157	0	31	0	0
T180	229781	0	0	0
T186	429823	0	0	0
T215	152673	99	0	0
T226	0	1	0	0
T242	0	1	0	0
T243	0	31	0	0
T244	0	32	0	0
T245	0	1	0	0
T246	0	1	0	0
T247	210047	0	0	0
T248	79292	0	0	0
T249	383635	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	7	0	0
T2	150727	1	0	0
T3	247509	0	0	0
T16	445248	0	0	0
T17	249743	0	0	0
T18	190191	0	0	0
T23	879715	0	0	0
T44	144270	0	0	0
T49	175099	0	0	0
T65	280776	0	0	0
T66	74306	0	0	0
T220	0	1	0	0
T221	0	1	0	0
T250	0	1	0	0
T251	0	1	0	0
T252	0	1	0	0
T253	0	1	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	147	0	0
T227	83002	17	0	0
T228	0	18	0	0
T229	0	18	0	0
T238	102469	37	0	0
T239	0	28	0	0
T254	0	29	0	0
T255	261751	0	0	0
T256	287260	0	0	0
T257	344789	0	0	0
T258	162609	0	0	0
T259	283975	0	0	0
T260	77381	0	0	0
T261	145960	0	0	0
T262	151157	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	197	0	0
T158	0	16	0	0
T159	0	16	0	0
T227	83002	42	0	0
T228	0	42	0	0
T229	0	42	0	0
T238	102469	9	0	0
T239	0	7	0	0
T254	0	7	0	0
T255	261751	0	0	0
T256	287260	0	0	0
T257	344789	0	0	0
T258	162609	0	0	0
T259	283975	0	0	0
T260	77381	0	0	0
T261	145960	0	0	0
T262	151157	0	0	0
T263	0	16	0	0