| T663 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.941528324 |
|
|
Jan 17 05:07:03 PM PST 24 |
Jan 17 05:15:06 PM PST 24 |
5743684790 ps |
| T640 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3670147986 |
|
|
Jan 17 04:57:00 PM PST 24 |
Jan 17 05:13:24 PM PST 24 |
5225463878 ps |
| T964 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3906370346 |
|
|
Jan 17 04:57:50 PM PST 24 |
Jan 17 05:18:26 PM PST 24 |
6319909964 ps |
| T157 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4204834430 |
|
|
Jan 17 04:40:00 PM PST 24 |
Jan 17 04:50:44 PM PST 24 |
7722118282 ps |
| T238 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3811065190 |
|
|
Jan 17 05:11:56 PM PST 24 |
Jan 17 05:17:10 PM PST 24 |
3579494040 ps |
| T242 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1628326345 |
|
|
Jan 17 05:07:12 PM PST 24 |
Jan 17 05:13:40 PM PST 24 |
3566194960 ps |
| T702 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.116390445 |
|
|
Jan 17 05:10:00 PM PST 24 |
Jan 17 05:18:07 PM PST 24 |
5793339192 ps |
| T965 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4028584240 |
|
|
Jan 17 05:03:27 PM PST 24 |
Jan 17 05:07:00 PM PST 24 |
2403569944 ps |
| T966 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.4210297979 |
|
|
Jan 17 04:46:56 PM PST 24 |
Jan 17 04:52:46 PM PST 24 |
3313746169 ps |
| T967 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1474197585 |
|
|
Jan 17 04:40:58 PM PST 24 |
Jan 17 04:53:09 PM PST 24 |
4262293550 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3798565815 |
|
|
Jan 17 05:02:35 PM PST 24 |
Jan 17 05:06:44 PM PST 24 |
2915025452 ps |
| T968 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.267531707 |
|
|
Jan 17 04:59:26 PM PST 24 |
Jan 17 05:07:26 PM PST 24 |
4097973062 ps |
| T969 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3868093702 |
|
|
Jan 17 04:45:22 PM PST 24 |
Jan 17 05:12:25 PM PST 24 |
7532222264 ps |
| T970 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1340964104 |
|
|
Jan 17 04:41:58 PM PST 24 |
Jan 17 04:46:49 PM PST 24 |
3272603598 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.43908539 |
|
|
Jan 17 04:40:33 PM PST 24 |
Jan 17 04:45:07 PM PST 24 |
2585323734 ps |
| T972 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1040267569 |
|
|
Jan 17 04:44:31 PM PST 24 |
Jan 17 05:03:17 PM PST 24 |
5946300424 ps |
| T298 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2595663934 |
|
|
Jan 17 04:49:14 PM PST 24 |
Jan 17 04:59:31 PM PST 24 |
8559485413 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.601862576 |
|
|
Jan 17 04:54:37 PM PST 24 |
Jan 17 05:55:00 PM PST 24 |
23340509040 ps |
| T974 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1136021633 |
|
|
Jan 17 04:47:40 PM PST 24 |
Jan 17 05:22:49 PM PST 24 |
8449743720 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.856304678 |
|
|
Jan 17 04:48:21 PM PST 24 |
Jan 17 04:52:49 PM PST 24 |
2702489283 ps |
| T976 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3484242146 |
|
|
Jan 17 05:02:16 PM PST 24 |
Jan 17 05:06:26 PM PST 24 |
2907433000 ps |
| T977 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.965086877 |
|
|
Jan 17 04:57:39 PM PST 24 |
Jan 17 05:25:22 PM PST 24 |
7466967133 ps |
| T978 |
/workspace/coverage/default/0.chip_sw_edn_kat.4101745878 |
|
|
Jan 17 04:39:41 PM PST 24 |
Jan 17 04:48:20 PM PST 24 |
2910759200 ps |
| T286 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3483565432 |
|
|
Jan 17 05:02:00 PM PST 24 |
Jan 17 05:15:34 PM PST 24 |
6417277960 ps |
| T979 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1614444608 |
|
|
Jan 17 04:46:47 PM PST 24 |
Jan 17 05:44:00 PM PST 24 |
19037529782 ps |
| T980 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1697332570 |
|
|
Jan 17 04:55:28 PM PST 24 |
Jan 17 05:15:03 PM PST 24 |
12303190603 ps |
| T688 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1932863434 |
|
|
Jan 17 05:07:12 PM PST 24 |
Jan 17 05:12:05 PM PST 24 |
3577367008 ps |
| T193 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.2512361683 |
|
|
Jan 17 04:39:51 PM PST 24 |
Jan 17 04:46:17 PM PST 24 |
4160640000 ps |
| T698 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3022888089 |
|
|
Jan 17 05:04:45 PM PST 24 |
Jan 17 05:13:22 PM PST 24 |
4277866042 ps |
| T121 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.40819099 |
|
|
Jan 17 04:39:19 PM PST 24 |
Jan 17 04:47:30 PM PST 24 |
4247601226 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3392498326 |
|
|
Jan 17 04:58:00 PM PST 24 |
Jan 17 05:12:11 PM PST 24 |
4555785368 ps |
| T129 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.866799714 |
|
|
Jan 17 04:55:20 PM PST 24 |
Jan 17 05:01:27 PM PST 24 |
3050738725 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.371033291 |
|
|
Jan 17 04:46:42 PM PST 24 |
Jan 17 05:17:21 PM PST 24 |
14383060204 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2299270567 |
|
|
Jan 17 04:57:02 PM PST 24 |
Jan 17 05:05:54 PM PST 24 |
6000008772 ps |
| T111 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.2346312452 |
|
|
Jan 17 04:38:07 PM PST 24 |
Jan 17 05:23:27 PM PST 24 |
12083025116 ps |
| T984 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.142007922 |
|
|
Jan 17 04:47:32 PM PST 24 |
Jan 17 05:28:49 PM PST 24 |
11862584388 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1690576180 |
|
|
Jan 17 04:56:51 PM PST 24 |
Jan 17 05:06:56 PM PST 24 |
4412521212 ps |
| T986 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.1077343954 |
|
|
Jan 17 04:40:25 PM PST 24 |
Jan 17 07:43:46 PM PST 24 |
66742285367 ps |
| T987 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2373179472 |
|
|
Jan 17 04:48:29 PM PST 24 |
Jan 17 05:14:36 PM PST 24 |
7108475120 ps |
| T165 |
/workspace/coverage/default/1.chip_sival_flash_info_access.199189928 |
|
|
Jan 17 04:45:35 PM PST 24 |
Jan 17 04:53:30 PM PST 24 |
3285981400 ps |
| T309 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.1833388620 |
|
|
Jan 17 04:58:29 PM PST 24 |
Jan 17 05:03:59 PM PST 24 |
2574439240 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1173939991 |
|
|
Jan 17 04:46:22 PM PST 24 |
Jan 17 04:49:48 PM PST 24 |
2904871816 ps |
| T67 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.778933221 |
|
|
Jan 17 05:10:33 PM PST 24 |
Jan 17 05:20:58 PM PST 24 |
6425730532 ps |
| T689 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.2161626667 |
|
|
Jan 17 05:03:49 PM PST 24 |
Jan 17 05:13:45 PM PST 24 |
5559102822 ps |
| T989 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.4292824782 |
|
|
Jan 17 04:47:34 PM PST 24 |
Jan 17 05:04:41 PM PST 24 |
5398420798 ps |
| T990 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3951823314 |
|
|
Jan 17 05:02:57 PM PST 24 |
Jan 17 05:14:34 PM PST 24 |
11551541814 ps |
| T9 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2569696540 |
|
|
Jan 17 04:45:19 PM PST 24 |
Jan 17 04:53:56 PM PST 24 |
5622804966 ps |
| T991 |
/workspace/coverage/default/2.chip_jtag_mem_access.2218965843 |
|
|
Jan 17 04:51:13 PM PST 24 |
Jan 17 05:14:54 PM PST 24 |
13197084928 ps |
| T992 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1598426498 |
|
|
Jan 17 04:47:00 PM PST 24 |
Jan 17 05:23:08 PM PST 24 |
8245442144 ps |
| T993 |
/workspace/coverage/default/2.chip_sw_power_idle_load.1187786411 |
|
|
Jan 17 04:58:56 PM PST 24 |
Jan 17 05:11:18 PM PST 24 |
4307202922 ps |
| T994 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3579201101 |
|
|
Jan 17 04:50:35 PM PST 24 |
Jan 17 05:02:02 PM PST 24 |
7383567148 ps |
| T995 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1140592779 |
|
|
Jan 17 05:03:15 PM PST 24 |
Jan 17 05:14:56 PM PST 24 |
5469966920 ps |
| T687 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.990998296 |
|
|
Jan 17 05:07:46 PM PST 24 |
Jan 17 05:17:03 PM PST 24 |
4219735000 ps |
| T996 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1574708194 |
|
|
Jan 17 04:41:10 PM PST 24 |
Jan 17 04:46:18 PM PST 24 |
2860328652 ps |
| T997 |
/workspace/coverage/default/2.rom_keymgr_functest.2453351961 |
|
|
Jan 17 05:00:30 PM PST 24 |
Jan 17 05:09:51 PM PST 24 |
5090610700 ps |
| T998 |
/workspace/coverage/default/1.rom_keymgr_functest.4236616481 |
|
|
Jan 17 04:53:33 PM PST 24 |
Jan 17 05:00:48 PM PST 24 |
4830341440 ps |
| T999 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3960571807 |
|
|
Jan 17 04:53:13 PM PST 24 |
Jan 17 05:06:37 PM PST 24 |
10402963048 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2419978394 |
|
|
Jan 17 04:47:44 PM PST 24 |
Jan 17 04:51:42 PM PST 24 |
3119554682 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3143239797 |
|
|
Jan 17 04:49:05 PM PST 24 |
Jan 17 05:19:33 PM PST 24 |
8631111614 ps |
| T1002 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.196514514 |
|
|
Jan 17 05:04:02 PM PST 24 |
Jan 17 05:16:26 PM PST 24 |
5053384600 ps |
| T1003 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2492360346 |
|
|
Jan 17 04:55:59 PM PST 24 |
Jan 17 05:19:28 PM PST 24 |
13250209455 ps |
| T1004 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.715364422 |
|
|
Jan 17 04:38:42 PM PST 24 |
Jan 17 07:25:29 PM PST 24 |
61422690580 ps |
| T1005 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1571891585 |
|
|
Jan 17 04:48:05 PM PST 24 |
Jan 17 05:18:36 PM PST 24 |
8633973623 ps |
| T700 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2408257000 |
|
|
Jan 17 05:07:08 PM PST 24 |
Jan 17 05:20:03 PM PST 24 |
4862832406 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3690961425 |
|
|
Jan 17 04:43:49 PM PST 24 |
Jan 17 04:49:04 PM PST 24 |
2961909352 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1764351474 |
|
|
Jan 17 04:38:38 PM PST 24 |
Jan 17 04:55:41 PM PST 24 |
5742720512 ps |
| T1008 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3283324800 |
|
|
Jan 17 04:39:43 PM PST 24 |
Jan 17 04:47:22 PM PST 24 |
4692158112 ps |
| T604 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2524440599 |
|
|
Jan 17 04:56:38 PM PST 24 |
Jan 17 05:02:30 PM PST 24 |
3019981217 ps |
| T681 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3650169024 |
|
|
Jan 17 05:04:15 PM PST 24 |
Jan 17 05:10:10 PM PST 24 |
3460128836 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.827899933 |
|
|
Jan 17 04:54:45 PM PST 24 |
Jan 17 08:00:50 PM PST 24 |
67113986750 ps |
| T1010 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3676676203 |
|
|
Jan 17 04:54:26 PM PST 24 |
Jan 17 04:57:13 PM PST 24 |
2381887330 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2642029387 |
|
|
Jan 17 04:59:11 PM PST 24 |
Jan 17 05:03:15 PM PST 24 |
2864207697 ps |
| T141 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3550074736 |
|
|
Jan 17 04:40:26 PM PST 24 |
Jan 17 04:42:50 PM PST 24 |
2272901393 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_alert_test.873897206 |
|
|
Jan 17 04:40:38 PM PST 24 |
Jan 17 04:44:52 PM PST 24 |
2735137536 ps |
| T1012 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3570575379 |
|
|
Jan 17 04:46:41 PM PST 24 |
Jan 17 05:39:27 PM PST 24 |
12484266911 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3545155585 |
|
|
Jan 17 04:58:25 PM PST 24 |
Jan 17 05:06:14 PM PST 24 |
5093284254 ps |
| T314 |
/workspace/coverage/default/2.chip_sw_entropy_src_fuse_en_fw_read_test.2015937368 |
|
|
Jan 17 04:57:35 PM PST 24 |
Jan 17 05:05:57 PM PST 24 |
4871367420 ps |
| T266 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1670121177 |
|
|
Jan 17 04:56:00 PM PST 24 |
Jan 17 05:09:05 PM PST 24 |
5637060680 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.150009397 |
|
|
Jan 17 04:47:31 PM PST 24 |
Jan 17 05:43:03 PM PST 24 |
20507259271 ps |
| T1015 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4107947460 |
|
|
Jan 17 04:57:32 PM PST 24 |
Jan 17 05:07:02 PM PST 24 |
9142336424 ps |
| T675 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.3528426509 |
|
|
Jan 17 05:06:28 PM PST 24 |
Jan 17 05:16:37 PM PST 24 |
4839049448 ps |
| T731 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.983495070 |
|
|
Jan 17 04:56:54 PM PST 24 |
Jan 17 05:03:58 PM PST 24 |
3843539452 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2244886701 |
|
|
Jan 17 04:50:36 PM PST 24 |
Jan 17 05:02:42 PM PST 24 |
5691687064 ps |
| T1017 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2135991521 |
|
|
Jan 17 04:47:09 PM PST 24 |
Jan 17 04:53:00 PM PST 24 |
2913155525 ps |
| T1018 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3699245745 |
|
|
Jan 17 04:57:15 PM PST 24 |
Jan 17 05:06:57 PM PST 24 |
6048304570 ps |
| T267 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1919097541 |
|
|
Jan 17 05:03:37 PM PST 24 |
Jan 17 05:12:56 PM PST 24 |
5128113804 ps |
| T1019 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.612812668 |
|
|
Jan 17 04:57:35 PM PST 24 |
Jan 17 05:10:37 PM PST 24 |
5030999124 ps |
| T273 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.402484788 |
|
|
Jan 17 04:53:50 PM PST 24 |
Jan 17 05:08:13 PM PST 24 |
4659554408 ps |
| T275 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2408146119 |
|
|
Jan 17 05:06:26 PM PST 24 |
Jan 17 05:18:11 PM PST 24 |
5052053600 ps |
| T262 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2537477320 |
|
|
Jan 17 04:41:02 PM PST 24 |
Jan 17 05:24:11 PM PST 24 |
9225247468 ps |
| T276 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3770048281 |
|
|
Jan 17 05:08:47 PM PST 24 |
Jan 17 05:15:35 PM PST 24 |
3868479102 ps |
| T277 |
/workspace/coverage/default/0.chip_sival_flash_info_access.570538622 |
|
|
Jan 17 04:40:15 PM PST 24 |
Jan 17 04:48:01 PM PST 24 |
3418345870 ps |
| T278 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.428540156 |
|
|
Jan 17 05:04:08 PM PST 24 |
Jan 17 05:13:48 PM PST 24 |
4832178880 ps |
| T279 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.2271657426 |
|
|
Jan 17 04:54:54 PM PST 24 |
Jan 17 05:31:26 PM PST 24 |
9736315046 ps |
| T280 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.129666399 |
|
|
Jan 17 05:05:09 PM PST 24 |
Jan 17 05:10:50 PM PST 24 |
3737706420 ps |
| T281 |
/workspace/coverage/default/1.chip_sw_aes_idle.175076643 |
|
|
Jan 17 04:47:52 PM PST 24 |
Jan 17 04:51:09 PM PST 24 |
2397580730 ps |
| T104 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.826561734 |
|
|
Jan 17 04:58:01 PM PST 24 |
Jan 17 05:06:22 PM PST 24 |
4753719192 ps |
| T1020 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.602687373 |
|
|
Jan 17 04:44:07 PM PST 24 |
Jan 17 04:51:37 PM PST 24 |
3913419902 ps |
| T85 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2743617137 |
|
|
Jan 17 04:56:22 PM PST 24 |
Jan 17 05:06:40 PM PST 24 |
17740313150 ps |
| T1021 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.993380296 |
|
|
Jan 17 04:41:33 PM PST 24 |
Jan 17 04:46:01 PM PST 24 |
2945887740 ps |
| T195 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3375251359 |
|
|
Jan 17 04:39:31 PM PST 24 |
Jan 17 05:20:19 PM PST 24 |
12380919378 ps |
| T694 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.763059820 |
|
|
Jan 17 05:08:47 PM PST 24 |
Jan 17 05:15:59 PM PST 24 |
3349920298 ps |
| T718 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2910815809 |
|
|
Jan 17 05:10:15 PM PST 24 |
Jan 17 05:17:16 PM PST 24 |
4527017614 ps |
| T130 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.1168872131 |
|
|
Jan 17 04:45:26 PM PST 24 |
Jan 17 04:51:01 PM PST 24 |
3236382476 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.110836401 |
|
|
Jan 17 04:39:55 PM PST 24 |
Jan 17 05:13:51 PM PST 24 |
24908046356 ps |
| T582 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.416033313 |
|
|
Jan 17 04:40:20 PM PST 24 |
Jan 17 04:49:01 PM PST 24 |
2708342800 ps |
| T191 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.181362105 |
|
|
Jan 17 04:40:23 PM PST 24 |
Jan 17 04:51:54 PM PST 24 |
3891807552 ps |
| T1023 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.395237372 |
|
|
Jan 17 04:42:18 PM PST 24 |
Jan 17 04:48:07 PM PST 24 |
3629771141 ps |
| T173 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.230216148 |
|
|
Jan 17 04:47:20 PM PST 24 |
Jan 17 05:19:26 PM PST 24 |
12667736930 ps |
| T583 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.3598617716 |
|
|
Jan 17 04:47:41 PM PST 24 |
Jan 17 04:56:23 PM PST 24 |
3091539656 ps |
| T659 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3538602767 |
|
|
Jan 17 05:09:28 PM PST 24 |
Jan 17 05:15:19 PM PST 24 |
3556029374 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1742981399 |
|
|
Jan 17 04:51:42 PM PST 24 |
Jan 17 05:09:01 PM PST 24 |
5697987620 ps |
| T1025 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2836965476 |
|
|
Jan 17 04:47:32 PM PST 24 |
Jan 17 04:55:45 PM PST 24 |
7215741858 ps |
| T738 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2025673575 |
|
|
Jan 17 05:05:29 PM PST 24 |
Jan 17 05:14:09 PM PST 24 |
5825594424 ps |
| T1026 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4115573487 |
|
|
Jan 17 04:44:17 PM PST 24 |
Jan 17 05:12:41 PM PST 24 |
14261438369 ps |
| T581 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1926936699 |
|
|
Jan 17 04:39:45 PM PST 24 |
Jan 17 05:00:56 PM PST 24 |
5396665768 ps |
| T1027 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.3098200748 |
|
|
Jan 17 04:53:52 PM PST 24 |
Jan 17 05:00:00 PM PST 24 |
3483587480 ps |
| T10 |
/workspace/coverage/default/1.chip_jtag_csr_rw.337480184 |
|
|
Jan 17 04:44:00 PM PST 24 |
Jan 17 05:07:07 PM PST 24 |
12025015180 ps |
| T1028 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1855909688 |
|
|
Jan 17 04:40:28 PM PST 24 |
Jan 17 04:48:00 PM PST 24 |
4918678754 ps |
| T1029 |
/workspace/coverage/default/1.chip_sw_example_flash.14361461 |
|
|
Jan 17 04:45:18 PM PST 24 |
Jan 17 04:48:21 PM PST 24 |
2149185690 ps |
| T219 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.4135800194 |
|
|
Jan 17 04:45:46 PM PST 24 |
Jan 17 05:02:00 PM PST 24 |
5229131664 ps |
| T1030 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4166647578 |
|
|
Jan 17 04:42:30 PM PST 24 |
Jan 17 04:54:25 PM PST 24 |
6935441870 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3241180160 |
|
|
Jan 17 04:46:49 PM PST 24 |
Jan 17 04:53:35 PM PST 24 |
4243584616 ps |
| T287 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1120851433 |
|
|
Jan 17 04:50:23 PM PST 24 |
Jan 17 05:01:51 PM PST 24 |
4726841790 ps |
| T709 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.579169957 |
|
|
Jan 17 05:04:24 PM PST 24 |
Jan 17 05:10:40 PM PST 24 |
3126442282 ps |
| T1032 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1215444425 |
|
|
Jan 17 05:10:16 PM PST 24 |
Jan 17 05:19:32 PM PST 24 |
5750166152 ps |
| T288 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.289216866 |
|
|
Jan 17 04:46:34 PM PST 24 |
Jan 17 04:55:42 PM PST 24 |
3682712180 ps |
| T184 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1492720117 |
|
|
Jan 17 04:45:56 PM PST 24 |
Jan 17 05:05:27 PM PST 24 |
5575210028 ps |
| T196 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3236851078 |
|
|
Jan 17 05:04:08 PM PST 24 |
Jan 17 05:17:45 PM PST 24 |
4137345934 ps |
| T1033 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2605735785 |
|
|
Jan 17 04:46:48 PM PST 24 |
Jan 17 05:40:47 PM PST 24 |
37250841176 ps |
| T68 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.4113459293 |
|
|
Jan 17 05:08:15 PM PST 24 |
Jan 17 05:14:40 PM PST 24 |
3764228972 ps |
| T1034 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1472823594 |
|
|
Jan 17 04:47:06 PM PST 24 |
Jan 17 05:11:42 PM PST 24 |
6781832450 ps |
| T609 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1129411549 |
|
|
Jan 17 05:05:53 PM PST 24 |
Jan 17 05:16:29 PM PST 24 |
5373036156 ps |
| T612 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.580992634 |
|
|
Jan 17 04:41:36 PM PST 24 |
Jan 17 04:46:10 PM PST 24 |
3050804420 ps |
| T185 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2303448739 |
|
|
Jan 17 04:55:00 PM PST 24 |
Jan 17 05:10:26 PM PST 24 |
5534990810 ps |
| T613 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3056281029 |
|
|
Jan 17 04:54:31 PM PST 24 |
Jan 17 05:16:05 PM PST 24 |
7688799000 ps |
| T614 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.4293149673 |
|
|
Jan 17 04:45:28 PM PST 24 |
Jan 17 05:07:36 PM PST 24 |
8183353720 ps |
| T615 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2577397976 |
|
|
Jan 17 05:08:04 PM PST 24 |
Jan 17 05:17:48 PM PST 24 |
4361029550 ps |
| T616 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1674185457 |
|
|
Jan 17 05:04:38 PM PST 24 |
Jan 17 05:15:43 PM PST 24 |
5930925496 ps |
| T617 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3169946157 |
|
|
Jan 17 04:55:30 PM PST 24 |
Jan 17 05:30:39 PM PST 24 |
23490626785 ps |
| T618 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.4284218368 |
|
|
Jan 17 04:40:07 PM PST 24 |
Jan 17 05:49:18 PM PST 24 |
18476799708 ps |
| T619 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1070005233 |
|
|
Jan 17 05:01:45 PM PST 24 |
Jan 17 05:12:22 PM PST 24 |
4666775199 ps |
| T1035 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2464112324 |
|
|
Jan 17 04:39:45 PM PST 24 |
Jan 17 04:55:37 PM PST 24 |
5515467344 ps |
| T1036 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3157476525 |
|
|
Jan 17 05:08:35 PM PST 24 |
Jan 17 05:18:15 PM PST 24 |
5112777060 ps |
| T172 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.602131144 |
|
|
Jan 17 04:58:03 PM PST 24 |
Jan 17 05:17:42 PM PST 24 |
5922593308 ps |
| T69 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.4006530548 |
|
|
Jan 17 05:05:55 PM PST 24 |
Jan 17 05:16:33 PM PST 24 |
5090286006 ps |
| T1037 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3407465515 |
|
|
Jan 17 04:50:03 PM PST 24 |
Jan 17 05:14:57 PM PST 24 |
9666656144 ps |
| T1038 |
/workspace/coverage/default/1.chip_jtag_mem_access.3495120245 |
|
|
Jan 17 04:43:57 PM PST 24 |
Jan 17 05:09:04 PM PST 24 |
13733870435 ps |
| T1039 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.1130718470 |
|
|
Jan 17 04:43:17 PM PST 24 |
Jan 17 05:14:05 PM PST 24 |
7861708236 ps |
| T633 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2724791220 |
|
|
Jan 17 04:40:43 PM PST 24 |
Jan 17 04:52:26 PM PST 24 |
19289878240 ps |
| T217 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2960315180 |
|
|
Jan 17 04:39:31 PM PST 24 |
Jan 17 04:42:56 PM PST 24 |
2695965240 ps |
| T1040 |
/workspace/coverage/default/4.chip_tap_straps_prod.2665568890 |
|
|
Jan 17 05:01:33 PM PST 24 |
Jan 17 05:04:36 PM PST 24 |
2654021696 ps |
| T1041 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1916149058 |
|
|
Jan 17 04:40:40 PM PST 24 |
Jan 17 04:44:38 PM PST 24 |
2957453300 ps |
| T1042 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.1128264877 |
|
|
Jan 17 04:40:49 PM PST 24 |
Jan 17 04:45:50 PM PST 24 |
2674449160 ps |
| T1043 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.196208017 |
|
|
Jan 17 05:06:49 PM PST 24 |
Jan 17 05:15:27 PM PST 24 |
4965266464 ps |
| T1044 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.528485276 |
|
|
Jan 17 04:44:59 PM PST 24 |
Jan 17 05:08:21 PM PST 24 |
7752385632 ps |
| T1045 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.932123729 |
|
|
Jan 17 04:46:56 PM PST 24 |
Jan 17 04:58:29 PM PST 24 |
4979033462 ps |
| T1046 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg.2628935852 |
|
|
Jan 17 04:45:39 PM PST 24 |
Jan 17 04:51:17 PM PST 24 |
2395352280 ps |
| T218 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3886253349 |
|
|
Jan 17 04:51:18 PM PST 24 |
Jan 17 04:55:32 PM PST 24 |
2951889220 ps |
| T1047 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2175632873 |
|
|
Jan 17 04:43:01 PM PST 24 |
Jan 17 05:43:14 PM PST 24 |
30921193000 ps |
| T1048 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3778913555 |
|
|
Jan 17 04:58:19 PM PST 24 |
Jan 17 05:08:34 PM PST 24 |
4417275740 ps |
| T733 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.893008431 |
|
|
Jan 17 05:03:31 PM PST 24 |
Jan 17 05:08:54 PM PST 24 |
3665991134 ps |
| T1049 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.300034772 |
|
|
Jan 17 04:39:47 PM PST 24 |
Jan 17 04:57:02 PM PST 24 |
5773212956 ps |
| T1050 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.914296611 |
|
|
Jan 17 04:57:35 PM PST 24 |
Jan 17 05:13:36 PM PST 24 |
5211972232 ps |
| T1051 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.377789940 |
|
|
Jan 17 04:39:05 PM PST 24 |
Jan 17 04:56:02 PM PST 24 |
9333018900 ps |
| T1052 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.201883426 |
|
|
Jan 17 04:57:50 PM PST 24 |
Jan 17 05:07:07 PM PST 24 |
6498124080 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_aes_enc.2053071198 |
|
|
Jan 17 04:41:16 PM PST 24 |
Jan 17 04:46:21 PM PST 24 |
3592338260 ps |
| T105 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2011391697 |
|
|
Jan 17 04:41:33 PM PST 24 |
Jan 17 04:49:11 PM PST 24 |
5247331240 ps |
| T299 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2833776124 |
|
|
Jan 17 04:42:24 PM PST 24 |
Jan 17 04:58:56 PM PST 24 |
8007825264 ps |
| T142 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3628745362 |
|
|
Jan 17 04:55:14 PM PST 24 |
Jan 17 04:56:50 PM PST 24 |
1784104240 ps |
| T12 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3064242440 |
|
|
Jan 17 04:43:36 PM PST 24 |
Jan 17 04:48:04 PM PST 24 |
4170567752 ps |
| T636 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3748102502 |
|
|
Jan 17 05:04:09 PM PST 24 |
Jan 17 05:12:59 PM PST 24 |
5425650804 ps |
| T576 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.825981763 |
|
|
Jan 17 04:42:32 PM PST 24 |
Jan 17 04:54:27 PM PST 24 |
11722493392 ps |
| T1054 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.657998992 |
|
|
Jan 17 04:38:42 PM PST 24 |
Jan 17 04:57:15 PM PST 24 |
10606143157 ps |
| T1055 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2927599311 |
|
|
Jan 17 04:50:17 PM PST 24 |
Jan 17 04:58:21 PM PST 24 |
3418870136 ps |
| T657 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1065437837 |
|
|
Jan 17 05:09:59 PM PST 24 |
Jan 17 05:15:23 PM PST 24 |
3158637430 ps |
| T1056 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3717510427 |
|
|
Jan 17 05:03:42 PM PST 24 |
Jan 17 05:20:42 PM PST 24 |
9172651966 ps |
| T1057 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.561002727 |
|
|
Jan 17 05:01:33 PM PST 24 |
Jan 17 05:08:36 PM PST 24 |
4915952388 ps |
| T679 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1014199855 |
|
|
Jan 17 05:10:10 PM PST 24 |
Jan 17 05:18:13 PM PST 24 |
5575772044 ps |
| T5 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1274868665 |
|
|
Jan 17 04:40:10 PM PST 24 |
Jan 17 04:46:00 PM PST 24 |
3736175051 ps |
| T1058 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1438161493 |
|
|
Jan 17 04:58:21 PM PST 24 |
Jan 17 05:02:38 PM PST 24 |
2740279544 ps |
| T715 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1627914011 |
|
|
Jan 17 05:09:19 PM PST 24 |
Jan 17 05:14:42 PM PST 24 |
3363168564 ps |
| T719 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1744235992 |
|
|
Jan 17 05:04:41 PM PST 24 |
Jan 17 05:10:36 PM PST 24 |
3374497176 ps |
| T1059 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3664139290 |
|
|
Jan 17 04:39:35 PM PST 24 |
Jan 17 04:47:22 PM PST 24 |
3830581924 ps |
| T710 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3665191656 |
|
|
Jan 17 05:07:45 PM PST 24 |
Jan 17 05:16:26 PM PST 24 |
4221861032 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1569338089 |
|
|
Jan 17 04:39:47 PM PST 24 |
Jan 17 04:58:30 PM PST 24 |
5481242504 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.658634378 |
|
|
Jan 17 04:48:49 PM PST 24 |
Jan 17 05:03:51 PM PST 24 |
7780395532 ps |
| T1062 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1443707714 |
|
|
Jan 17 04:42:02 PM PST 24 |
Jan 17 04:51:43 PM PST 24 |
4067020728 ps |
| T1063 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3837014781 |
|
|
Jan 17 04:48:32 PM PST 24 |
Jan 17 04:56:30 PM PST 24 |
3994963200 ps |
| T1064 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.638266142 |
|
|
Jan 17 05:09:53 PM PST 24 |
Jan 17 05:18:15 PM PST 24 |
4544073668 ps |
| T1065 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1398139194 |
|
|
Jan 17 04:49:12 PM PST 24 |
Jan 17 04:54:55 PM PST 24 |
3005657120 ps |
| T1066 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2458623763 |
|
|
Jan 17 04:57:57 PM PST 24 |
Jan 17 05:09:37 PM PST 24 |
4225731816 ps |
| T1067 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1417601424 |
|
|
Jan 17 04:49:12 PM PST 24 |
Jan 17 05:46:58 PM PST 24 |
14337593384 ps |
| T691 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2428387454 |
|
|
Jan 17 05:07:27 PM PST 24 |
Jan 17 05:14:45 PM PST 24 |
3688821922 ps |
| T1068 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.213210052 |
|
|
Jan 17 04:48:26 PM PST 24 |
Jan 17 05:04:50 PM PST 24 |
10395725566 ps |
| T1069 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2769843666 |
|
|
Jan 17 04:58:54 PM PST 24 |
Jan 17 05:14:31 PM PST 24 |
6446223904 ps |
| T1070 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.566826990 |
|
|
Jan 17 04:39:38 PM PST 24 |
Jan 17 05:07:23 PM PST 24 |
7985349624 ps |
| T1071 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.222238567 |
|
|
Jan 17 04:57:29 PM PST 24 |
Jan 17 05:19:47 PM PST 24 |
6730581352 ps |
| T258 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1000874120 |
|
|
Jan 17 04:58:26 PM PST 24 |
Jan 17 05:07:26 PM PST 24 |
4017230020 ps |
| T1072 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1195464883 |
|
|
Jan 17 04:53:41 PM PST 24 |
Jan 17 05:04:03 PM PST 24 |
5928862300 ps |
| T1073 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.2825070885 |
|
|
Jan 17 04:46:22 PM PST 24 |
Jan 17 04:51:27 PM PST 24 |
2720104990 ps |
| T1074 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3870447160 |
|
|
Jan 17 04:47:06 PM PST 24 |
Jan 17 04:56:16 PM PST 24 |
5599929320 ps |
| T239 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.3184162106 |
|
|
Jan 17 05:05:14 PM PST 24 |
Jan 17 05:16:06 PM PST 24 |
5289849718 ps |
| T243 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3184588667 |
|
|
Jan 17 05:10:05 PM PST 24 |
Jan 17 05:20:22 PM PST 24 |
5032421736 ps |
| T188 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1762953225 |
|
|
Jan 17 04:44:56 PM PST 24 |
Jan 17 05:03:33 PM PST 24 |
5794240300 ps |
| T244 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.33313900 |
|
|
Jan 17 04:48:30 PM PST 24 |
Jan 17 04:56:25 PM PST 24 |
3446723748 ps |
| T1075 |
/workspace/coverage/default/1.rom_e2e_static_critical.1138563108 |
|
|
Jan 17 04:56:00 PM PST 24 |
Jan 17 05:33:22 PM PST 24 |
10535704836 ps |
| T1076 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.1757206057 |
|
|
Jan 17 04:39:07 PM PST 24 |
Jan 17 04:45:37 PM PST 24 |
3875657813 ps |
| T1077 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3391740402 |
|
|
Jan 17 04:39:27 PM PST 24 |
Jan 17 04:51:25 PM PST 24 |
6334326496 ps |
| T1078 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2155592374 |
|
|
Jan 17 05:08:58 PM PST 24 |
Jan 17 05:15:45 PM PST 24 |
3669627234 ps |
| T1079 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1155475756 |
|
|
Jan 17 04:44:48 PM PST 24 |
Jan 17 04:51:54 PM PST 24 |
3582377040 ps |
| T14 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3687680842 |
|
|
Jan 17 04:54:46 PM PST 24 |
Jan 17 05:00:56 PM PST 24 |
3877487132 ps |
| T1080 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1284548983 |
|
|
Jan 17 04:40:52 PM PST 24 |
Jan 17 04:50:23 PM PST 24 |
7161451510 ps |
| T591 |
/workspace/coverage/default/2.chip_tap_straps_dev.1888487932 |
|
|
Jan 17 04:58:33 PM PST 24 |
Jan 17 05:27:42 PM PST 24 |
16898704683 ps |
| T1081 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3634784297 |
|
|
Jan 17 04:50:10 PM PST 24 |
Jan 17 05:00:53 PM PST 24 |
5156254350 ps |
| T1082 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2601573564 |
|
|
Jan 17 05:10:13 PM PST 24 |
Jan 17 05:16:04 PM PST 24 |
3659435880 ps |
| T1083 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.414250226 |
|
|
Jan 17 04:57:24 PM PST 24 |
Jan 17 05:31:22 PM PST 24 |
9480215000 ps |
| T661 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1709652788 |
|
|
Jan 17 05:10:08 PM PST 24 |
Jan 17 05:18:06 PM PST 24 |
3911732744 ps |
| T1084 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.776696050 |
|
|
Jan 17 05:02:01 PM PST 24 |
Jan 17 05:13:32 PM PST 24 |
4738107065 ps |
| T1085 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.536365779 |
|
|
Jan 17 05:00:21 PM PST 24 |
Jan 17 05:04:57 PM PST 24 |
3215166062 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.861779123 |
|
|
Jan 17 04:40:21 PM PST 24 |
Jan 17 04:47:02 PM PST 24 |
3525989692 ps |
| T235 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2592292824 |
|
|
Jan 17 04:50:08 PM PST 24 |
Jan 17 05:09:31 PM PST 24 |
8966725060 ps |
| T1087 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3355751261 |
|
|
Jan 17 04:51:14 PM PST 24 |
Jan 17 05:05:22 PM PST 24 |
4483456190 ps |
| T1088 |
/workspace/coverage/default/1.chip_sw_aes_entropy.2300892874 |
|
|
Jan 17 04:48:53 PM PST 24 |
Jan 17 04:53:09 PM PST 24 |
2524851750 ps |
| T313 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.495196109 |
|
|
Jan 17 04:59:54 PM PST 24 |
Jan 17 05:05:19 PM PST 24 |
2498085240 ps |
| T1089 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4223596972 |
|
|
Jan 17 05:09:07 PM PST 24 |
Jan 17 05:18:12 PM PST 24 |
4410765010 ps |
| T1090 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3388491149 |
|
|
Jan 17 04:52:48 PM PST 24 |
Jan 17 05:03:29 PM PST 24 |
11464971111 ps |
| T713 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.885375767 |
|
|
Jan 17 05:03:40 PM PST 24 |
Jan 17 05:10:38 PM PST 24 |
3553726688 ps |
| T1091 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1022967505 |
|
|
Jan 17 04:46:42 PM PST 24 |
Jan 17 04:52:39 PM PST 24 |
3979817732 ps |
| T153 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3467381574 |
|
|
Jan 17 04:57:03 PM PST 24 |
Jan 17 06:16:09 PM PST 24 |
45342520984 ps |
| T291 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3488095986 |
|
|
Jan 17 05:04:57 PM PST 24 |
Jan 17 05:13:07 PM PST 24 |
6039258290 ps |
| T594 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3685614709 |
|
|
Jan 17 04:39:30 PM PST 24 |
Jan 17 04:41:34 PM PST 24 |
3278810907 ps |
| T1092 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1025201259 |
|
|
Jan 17 05:08:34 PM PST 24 |
Jan 17 05:14:48 PM PST 24 |
3278054820 ps |
| T11 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3886195446 |
|
|
Jan 17 04:44:03 PM PST 24 |
Jan 17 04:48:41 PM PST 24 |
3459997832 ps |
| T1093 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1581838775 |
|
|
Jan 17 04:44:14 PM PST 24 |
Jan 17 04:55:59 PM PST 24 |
4562402104 ps |
| T1094 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4120847828 |
|
|
Jan 17 04:41:56 PM PST 24 |
Jan 17 04:56:22 PM PST 24 |
4509842788 ps |
| T1095 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2074529800 |
|
|
Jan 17 04:57:00 PM PST 24 |
Jan 17 05:05:03 PM PST 24 |
3704838006 ps |
| T1096 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.908434195 |
|
|
Jan 17 04:58:13 PM PST 24 |
Jan 17 05:27:32 PM PST 24 |
22589601882 ps |
| T189 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2055778230 |
|
|
Jan 17 04:38:44 PM PST 24 |
Jan 17 04:48:53 PM PST 24 |
3973176602 ps |
| T1097 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.4117309645 |
|
|
Jan 17 04:39:58 PM PST 24 |
Jan 17 04:46:52 PM PST 24 |
5115121480 ps |
| T1098 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.2239980020 |
|
|
Jan 17 04:54:58 PM PST 24 |
Jan 17 05:11:29 PM PST 24 |
5706410432 ps |
| T1099 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.771469594 |
|
|
Jan 17 05:02:02 PM PST 24 |
Jan 17 05:15:45 PM PST 24 |
4639045126 ps |
| T1100 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2553729075 |
|
|
Jan 17 04:46:32 PM PST 24 |
Jan 17 05:25:08 PM PST 24 |
35394753888 ps |
| T240 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1814509093 |
|
|
Jan 17 05:11:12 PM PST 24 |
Jan 17 05:18:28 PM PST 24 |
3918689030 ps |
| T245 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3387094145 |
|
|
Jan 17 04:49:03 PM PST 24 |
Jan 17 05:03:19 PM PST 24 |
4625948704 ps |
| T246 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.80616626 |
|
|
Jan 17 05:04:49 PM PST 24 |
Jan 17 05:11:35 PM PST 24 |
3913522920 ps |
| T1101 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.680540584 |
|
|
Jan 17 04:42:25 PM PST 24 |
Jan 17 05:11:27 PM PST 24 |
7297474328 ps |
| T1102 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.247723197 |
|
|
Jan 17 05:01:57 PM PST 24 |
Jan 17 05:08:08 PM PST 24 |
3575069220 ps |
| T1103 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.244655336 |
|
|
Jan 17 04:57:57 PM PST 24 |
Jan 17 05:04:13 PM PST 24 |
3179183460 ps |
| T1104 |
/workspace/coverage/default/0.chip_sw_example_concurrency.3432897301 |
|
|
Jan 17 04:38:33 PM PST 24 |
Jan 17 04:42:05 PM PST 24 |
2470611672 ps |