| T771 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3852123523 |
|
|
Jan 21 04:36:11 PM PST 24 |
Jan 21 05:12:36 PM PST 24 |
24524753418 ps |
| T172 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.89655676 |
|
|
Jan 21 05:49:50 PM PST 24 |
Jan 21 06:08:30 PM PST 24 |
13010692984 ps |
| T274 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3779526693 |
|
|
Jan 21 06:12:11 PM PST 24 |
Jan 21 06:40:05 PM PST 24 |
7636104384 ps |
| T101 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4033287438 |
|
|
Jan 21 06:07:06 PM PST 24 |
Jan 21 07:05:51 PM PST 24 |
14362528350 ps |
| T258 |
/workspace/coverage/default/2.chip_sw_gpio.4177890045 |
|
|
Jan 21 04:48:35 PM PST 24 |
Jan 21 04:58:08 PM PST 24 |
3520927208 ps |
| T978 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1755551113 |
|
|
Jan 21 04:24:26 PM PST 24 |
Jan 21 04:36:33 PM PST 24 |
6320002736 ps |
| T315 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.680707428 |
|
|
Jan 21 04:52:27 PM PST 24 |
Jan 21 04:56:29 PM PST 24 |
3297740328 ps |
| T794 |
/workspace/coverage/default/2.chip_sw_edn_kat.1348521863 |
|
|
Jan 21 04:54:09 PM PST 24 |
Jan 21 05:05:26 PM PST 24 |
3402772050 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2634791125 |
|
|
Jan 21 05:26:32 PM PST 24 |
Jan 21 05:57:59 PM PST 24 |
12616806106 ps |
| T401 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2197621566 |
|
|
Jan 21 04:40:43 PM PST 24 |
Jan 21 04:53:56 PM PST 24 |
4245660860 ps |
| T26 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3000959441 |
|
|
Jan 21 06:46:46 PM PST 24 |
Jan 21 06:52:08 PM PST 24 |
4060389512 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1147090168 |
|
|
Jan 21 04:36:02 PM PST 24 |
Jan 21 04:53:52 PM PST 24 |
7727388667 ps |
| T180 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1781827833 |
|
|
Jan 21 05:09:49 PM PST 24 |
Jan 21 05:24:21 PM PST 24 |
4751248366 ps |
| T207 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3367253710 |
|
|
Jan 21 04:23:45 PM PST 24 |
Jan 21 04:28:46 PM PST 24 |
2651454172 ps |
| T208 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.684285658 |
|
|
Jan 21 04:50:11 PM PST 24 |
Jan 21 04:56:35 PM PST 24 |
4266439193 ps |
| T51 |
/workspace/coverage/default/1.chip_tap_straps_rma.1566079786 |
|
|
Jan 21 05:00:07 PM PST 24 |
Jan 21 05:05:44 PM PST 24 |
3706963514 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3368730041 |
|
|
Jan 21 04:24:48 PM PST 24 |
Jan 21 04:28:46 PM PST 24 |
2929335720 ps |
| T210 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2300750869 |
|
|
Jan 21 04:38:57 PM PST 24 |
Jan 21 04:44:02 PM PST 24 |
3457636060 ps |
| T152 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2625462717 |
|
|
Jan 21 04:25:22 PM PST 24 |
Jan 21 04:39:11 PM PST 24 |
4498658888 ps |
| T181 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1388436937 |
|
|
Jan 21 04:50:06 PM PST 24 |
Jan 21 04:59:43 PM PST 24 |
4829284342 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4188889315 |
|
|
Jan 21 04:58:49 PM PST 24 |
Jan 21 05:19:10 PM PST 24 |
7455208595 ps |
| T136 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1381325506 |
|
|
Jan 21 04:47:32 PM PST 24 |
Jan 21 05:00:16 PM PST 24 |
4165848402 ps |
| T212 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.930541043 |
|
|
Jan 21 05:09:20 PM PST 24 |
Jan 21 05:15:42 PM PST 24 |
3466259710 ps |
| T173 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.884164153 |
|
|
Jan 21 04:19:36 PM PST 24 |
Jan 21 04:22:19 PM PST 24 |
2991609892 ps |
| T53 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.1304334496 |
|
|
Jan 21 04:18:34 PM PST 24 |
Jan 21 05:16:24 PM PST 24 |
12431269086 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1753160171 |
|
|
Jan 21 04:58:55 PM PST 24 |
Jan 21 05:06:48 PM PST 24 |
4710267712 ps |
| T982 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.663497919 |
|
|
Jan 21 04:59:01 PM PST 24 |
Jan 21 05:10:28 PM PST 24 |
4482574420 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_hmac_enc.1051416631 |
|
|
Jan 21 04:39:58 PM PST 24 |
Jan 21 04:46:02 PM PST 24 |
3156840376 ps |
| T179 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1493058847 |
|
|
Jan 21 05:04:53 PM PST 24 |
Jan 21 05:16:28 PM PST 24 |
8987826557 ps |
| T248 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3490501336 |
|
|
Jan 21 05:19:01 PM PST 24 |
Jan 21 05:23:02 PM PST 24 |
2626974800 ps |
| T249 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.2048920854 |
|
|
Jan 21 05:01:39 PM PST 24 |
Jan 21 06:08:37 PM PST 24 |
26256112485 ps |
| T250 |
/workspace/coverage/default/1.chip_sw_flash_init.781021732 |
|
|
Jan 21 04:35:08 PM PST 24 |
Jan 21 05:13:12 PM PST 24 |
22776911760 ps |
| T251 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3169683715 |
|
|
Jan 21 06:15:18 PM PST 24 |
Jan 21 06:22:38 PM PST 24 |
3251213376 ps |
| T185 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1960081313 |
|
|
Jan 21 05:45:32 PM PST 24 |
Jan 21 05:56:59 PM PST 24 |
5614529049 ps |
| T252 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335399154 |
|
|
Jan 21 05:17:13 PM PST 24 |
Jan 21 05:24:05 PM PST 24 |
3506679640 ps |
| T253 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3218670743 |
|
|
Jan 21 04:20:40 PM PST 24 |
Jan 21 04:25:25 PM PST 24 |
3412237380 ps |
| T254 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1238901679 |
|
|
Jan 21 05:39:18 PM PST 24 |
Jan 21 05:45:33 PM PST 24 |
3539817588 ps |
| T255 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.386538946 |
|
|
Jan 21 04:49:39 PM PST 24 |
Jan 21 04:56:22 PM PST 24 |
4581244032 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.4162511034 |
|
|
Jan 21 05:28:55 PM PST 24 |
Jan 21 05:35:07 PM PST 24 |
5687976548 ps |
| T123 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3838106984 |
|
|
Jan 21 05:32:56 PM PST 24 |
Jan 21 05:37:58 PM PST 24 |
3046997399 ps |
| T174 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2851308217 |
|
|
Jan 21 04:35:19 PM PST 24 |
Jan 21 04:38:48 PM PST 24 |
3809398847 ps |
| T983 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.1949950658 |
|
|
Jan 21 05:21:42 PM PST 24 |
Jan 21 05:31:43 PM PST 24 |
5150505624 ps |
| T316 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1785871975 |
|
|
Jan 21 05:19:17 PM PST 24 |
Jan 21 06:08:21 PM PST 24 |
9647157384 ps |
| T64 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.2375924295 |
|
|
Jan 21 05:07:05 PM PST 24 |
Jan 21 05:19:26 PM PST 24 |
5420083162 ps |
| T77 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.4028221564 |
|
|
Jan 21 04:37:25 PM PST 24 |
Jan 21 04:47:00 PM PST 24 |
3705232688 ps |
| T78 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3134023834 |
|
|
Jan 21 05:54:28 PM PST 24 |
Jan 21 06:16:03 PM PST 24 |
7635756360 ps |
| T79 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.638351497 |
|
|
Jan 21 04:34:00 PM PST 24 |
Jan 21 05:11:31 PM PST 24 |
9061435788 ps |
| T80 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.414041510 |
|
|
Jan 21 05:19:30 PM PST 24 |
Jan 21 05:36:27 PM PST 24 |
5240538920 ps |
| T81 |
/workspace/coverage/default/1.chip_sw_example_rom.3105099005 |
|
|
Jan 21 04:33:33 PM PST 24 |
Jan 21 04:35:45 PM PST 24 |
2378047086 ps |
| T46 |
/workspace/coverage/default/3.chip_tap_straps_rma.2223701475 |
|
|
Jan 21 05:20:25 PM PST 24 |
Jan 21 05:36:09 PM PST 24 |
8805997434 ps |
| T82 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.3872041668 |
|
|
Jan 21 05:25:00 PM PST 24 |
Jan 21 05:30:44 PM PST 24 |
2696853626 ps |
| T83 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2810615111 |
|
|
Jan 21 05:05:45 PM PST 24 |
Jan 21 05:21:04 PM PST 24 |
5108375046 ps |
| T84 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2347773854 |
|
|
Jan 21 04:20:40 PM PST 24 |
Jan 21 04:24:57 PM PST 24 |
4005727940 ps |
| T984 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3223758134 |
|
|
Jan 21 04:36:21 PM PST 24 |
Jan 21 04:43:12 PM PST 24 |
3636156734 ps |
| T265 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1653259673 |
|
|
Jan 21 04:18:10 PM PST 24 |
Jan 21 04:32:35 PM PST 24 |
4830300354 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3297697743 |
|
|
Jan 21 04:50:28 PM PST 24 |
Jan 21 05:11:15 PM PST 24 |
6704180199 ps |
| T986 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.633698468 |
|
|
Jan 21 04:33:39 PM PST 24 |
Jan 21 05:12:37 PM PST 24 |
9534280350 ps |
| T116 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1256071652 |
|
|
Jan 21 05:02:48 PM PST 24 |
Jan 21 05:18:01 PM PST 24 |
7689363336 ps |
| T305 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.1261161091 |
|
|
Jan 21 05:06:06 PM PST 24 |
Jan 21 05:15:50 PM PST 24 |
4964620590 ps |
| T391 |
/workspace/coverage/default/0.chip_sw_power_idle_load.1188767576 |
|
|
Jan 21 04:27:54 PM PST 24 |
Jan 21 04:39:47 PM PST 24 |
3908698456 ps |
| T987 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.818309465 |
|
|
Jan 21 04:51:38 PM PST 24 |
Jan 21 06:03:01 PM PST 24 |
16759021616 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg.3934482316 |
|
|
Jan 21 04:18:31 PM PST 24 |
Jan 21 04:24:08 PM PST 24 |
2936163804 ps |
| T783 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2725759012 |
|
|
Jan 21 05:12:35 PM PST 24 |
Jan 21 05:19:13 PM PST 24 |
3933765942 ps |
| T989 |
/workspace/coverage/default/1.rom_raw_unlock.3647480781 |
|
|
Jan 21 04:45:16 PM PST 24 |
Jan 21 05:22:32 PM PST 24 |
16219029458 ps |
| T990 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.1216371536 |
|
|
Jan 21 05:01:41 PM PST 24 |
Jan 21 05:33:33 PM PST 24 |
9829438233 ps |
| T201 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.395949380 |
|
|
Jan 21 05:05:07 PM PST 24 |
Jan 21 05:11:07 PM PST 24 |
3509998736 ps |
| T177 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2393143007 |
|
|
Jan 21 04:55:32 PM PST 24 |
Jan 21 06:51:48 PM PST 24 |
42286150032 ps |
| T991 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.1233612006 |
|
|
Jan 21 04:46:31 PM PST 24 |
Jan 21 04:50:55 PM PST 24 |
2854625680 ps |
| T11 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2993874582 |
|
|
Jan 21 04:42:30 PM PST 24 |
Jan 21 04:47:33 PM PST 24 |
4518505036 ps |
| T380 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3452998217 |
|
|
Jan 21 05:21:56 PM PST 24 |
Jan 21 05:35:47 PM PST 24 |
4623729028 ps |
| T381 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4155084898 |
|
|
Jan 21 04:20:30 PM PST 24 |
Jan 21 04:54:11 PM PST 24 |
11396124982 ps |
| T382 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1312266832 |
|
|
Jan 21 05:34:21 PM PST 24 |
Jan 21 05:50:44 PM PST 24 |
10777291495 ps |
| T383 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.732766906 |
|
|
Jan 21 04:26:38 PM PST 24 |
Jan 21 04:37:38 PM PST 24 |
4006715100 ps |
| T384 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.4086297576 |
|
|
Jan 21 05:27:10 PM PST 24 |
Jan 21 05:57:58 PM PST 24 |
6823709572 ps |
| T385 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1840814344 |
|
|
Jan 21 04:23:13 PM PST 24 |
Jan 21 04:27:22 PM PST 24 |
2476899447 ps |
| T386 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1035047629 |
|
|
Jan 21 05:20:27 PM PST 24 |
Jan 21 05:27:47 PM PST 24 |
3917626776 ps |
| T387 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.3820770632 |
|
|
Jan 21 04:34:08 PM PST 24 |
Jan 21 04:46:43 PM PST 24 |
5405380200 ps |
| T388 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.63888715 |
|
|
Jan 21 04:32:38 PM PST 24 |
Jan 21 05:29:13 PM PST 24 |
23184346244 ps |
| T992 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.2824432698 |
|
|
Jan 21 04:24:12 PM PST 24 |
Jan 21 04:51:13 PM PST 24 |
7581652924 ps |
| T793 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3173010845 |
|
|
Jan 21 05:10:37 PM PST 24 |
Jan 21 05:17:54 PM PST 24 |
3329959784 ps |
| T319 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1167862057 |
|
|
Jan 21 05:17:15 PM PST 24 |
Jan 21 05:23:22 PM PST 24 |
3618432570 ps |
| T740 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4031127866 |
|
|
Jan 21 05:09:24 PM PST 24 |
Jan 21 05:17:23 PM PST 24 |
3635370760 ps |
| T295 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3882313324 |
|
|
Jan 21 05:18:37 PM PST 24 |
Jan 21 05:32:28 PM PST 24 |
4892637558 ps |
| T196 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3006567912 |
|
|
Jan 21 06:20:16 PM PST 24 |
Jan 21 06:29:06 PM PST 24 |
4133679796 ps |
| T223 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1196220501 |
|
|
Jan 21 04:17:51 PM PST 24 |
Jan 21 04:32:27 PM PST 24 |
4829876240 ps |
| T4 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.987019770 |
|
|
Jan 21 05:21:19 PM PST 24 |
Jan 21 05:27:01 PM PST 24 |
2501722913 ps |
| T117 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3893075083 |
|
|
Jan 21 04:56:42 PM PST 24 |
Jan 21 05:06:31 PM PST 24 |
5906245708 ps |
| T993 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3124573020 |
|
|
Jan 21 04:33:32 PM PST 24 |
Jan 21 04:37:19 PM PST 24 |
2336838616 ps |
| T994 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3429220157 |
|
|
Jan 21 05:19:11 PM PST 24 |
Jan 21 05:30:45 PM PST 24 |
4846250312 ps |
| T763 |
/workspace/coverage/default/1.chip_sw_power_idle_load.302029197 |
|
|
Jan 21 04:42:59 PM PST 24 |
Jan 21 04:55:44 PM PST 24 |
4746021522 ps |
| T995 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1860050788 |
|
|
Jan 21 04:40:46 PM PST 24 |
Jan 21 05:28:39 PM PST 24 |
20272001618 ps |
| T996 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2022198056 |
|
|
Jan 21 05:26:55 PM PST 24 |
Jan 21 05:45:40 PM PST 24 |
5535829754 ps |
| T997 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1370524391 |
|
|
Jan 21 04:51:25 PM PST 24 |
Jan 21 05:01:29 PM PST 24 |
4838765160 ps |
| T998 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3094125530 |
|
|
Jan 21 04:51:32 PM PST 24 |
Jan 21 04:59:52 PM PST 24 |
3973852616 ps |
| T143 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.896003493 |
|
|
Jan 21 04:48:15 PM PST 24 |
Jan 21 04:54:51 PM PST 24 |
3117222796 ps |
| T999 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.430877953 |
|
|
Jan 21 05:12:07 PM PST 24 |
Jan 21 05:19:43 PM PST 24 |
4047216560 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_edn_kat.4110230570 |
|
|
Jan 21 05:27:26 PM PST 24 |
Jan 21 05:40:08 PM PST 24 |
3326916912 ps |
| T788 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305980147 |
|
|
Jan 21 07:10:27 PM PST 24 |
Jan 21 07:17:00 PM PST 24 |
3334937828 ps |
| T8 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2924064111 |
|
|
Jan 21 05:37:43 PM PST 24 |
Jan 21 05:42:13 PM PST 24 |
3165768056 ps |
| T85 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.293428493 |
|
|
Jan 21 05:16:11 PM PST 24 |
Jan 21 05:23:43 PM PST 24 |
3093986936 ps |
| T86 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2150573131 |
|
|
Jan 21 04:58:49 PM PST 24 |
Jan 21 05:03:40 PM PST 24 |
2675410284 ps |
| T87 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2900615383 |
|
|
Jan 21 04:37:52 PM PST 24 |
Jan 21 04:48:27 PM PST 24 |
5214106939 ps |
| T88 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2937824150 |
|
|
Jan 21 04:42:01 PM PST 24 |
Jan 21 05:00:10 PM PST 24 |
6298045536 ps |
| T89 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1619006336 |
|
|
Jan 21 05:55:19 PM PST 24 |
Jan 21 06:04:28 PM PST 24 |
4373695960 ps |
| T90 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2433020827 |
|
|
Jan 21 04:43:39 PM PST 24 |
Jan 21 05:01:38 PM PST 24 |
6423627366 ps |
| T91 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2566951830 |
|
|
Jan 21 05:17:36 PM PST 24 |
Jan 21 05:32:02 PM PST 24 |
6120962312 ps |
| T92 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.80194034 |
|
|
Jan 21 06:10:57 PM PST 24 |
Jan 21 06:19:19 PM PST 24 |
4033411120 ps |
| T93 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1439368555 |
|
|
Jan 21 05:10:20 PM PST 24 |
Jan 21 05:21:54 PM PST 24 |
5922651120 ps |
| T244 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1982937140 |
|
|
Jan 21 05:39:09 PM PST 24 |
Jan 21 05:44:44 PM PST 24 |
3420628498 ps |
| T245 |
/workspace/coverage/default/2.chip_sw_hmac_enc.3883141839 |
|
|
Jan 21 04:55:26 PM PST 24 |
Jan 21 05:02:00 PM PST 24 |
3352129508 ps |
| T118 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3690755631 |
|
|
Jan 21 05:28:21 PM PST 24 |
Jan 21 05:37:36 PM PST 24 |
5205001010 ps |
| T790 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3578268410 |
|
|
Jan 21 05:20:25 PM PST 24 |
Jan 21 05:27:52 PM PST 24 |
3704065664 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1985332128 |
|
|
Jan 21 04:41:20 PM PST 24 |
Jan 21 04:51:56 PM PST 24 |
4961022992 ps |
| T292 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.2074311487 |
|
|
Jan 21 04:45:52 PM PST 24 |
Jan 21 04:50:09 PM PST 24 |
2761232284 ps |
| T308 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2139029425 |
|
|
Jan 21 05:52:15 PM PST 24 |
Jan 21 06:00:43 PM PST 24 |
4504421752 ps |
| T1002 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.2531112633 |
|
|
Jan 21 04:17:20 PM PST 24 |
Jan 21 04:21:38 PM PST 24 |
2985884118 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_alert_test.270335254 |
|
|
Jan 21 04:22:54 PM PST 24 |
Jan 21 04:27:41 PM PST 24 |
2623848200 ps |
| T1003 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1395253866 |
|
|
Jan 21 04:41:44 PM PST 24 |
Jan 21 04:49:32 PM PST 24 |
5648158920 ps |
| T1004 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.319427225 |
|
|
Jan 21 04:34:59 PM PST 24 |
Jan 21 04:58:37 PM PST 24 |
8834373976 ps |
| T347 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2428208700 |
|
|
Jan 21 05:31:04 PM PST 24 |
Jan 21 05:32:00 PM PST 24 |
1176125814 ps |
| T1005 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4132899751 |
|
|
Jan 21 05:03:25 PM PST 24 |
Jan 21 05:22:19 PM PST 24 |
5975769316 ps |
| T73 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2378457426 |
|
|
Jan 21 05:13:15 PM PST 24 |
Jan 21 05:26:12 PM PST 24 |
5622182480 ps |
| T1006 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3169825614 |
|
|
Jan 21 05:08:59 PM PST 24 |
Jan 21 05:20:20 PM PST 24 |
5608267504 ps |
| T1007 |
/workspace/coverage/default/2.rom_e2e_smoke.1965244188 |
|
|
Jan 21 05:14:10 PM PST 24 |
Jan 21 05:55:50 PM PST 24 |
8545446320 ps |
| T47 |
/workspace/coverage/default/4.chip_tap_straps_rma.3279190859 |
|
|
Jan 21 05:29:44 PM PST 24 |
Jan 21 05:44:37 PM PST 24 |
7678005100 ps |
| T1008 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3773945751 |
|
|
Jan 21 06:49:55 PM PST 24 |
Jan 21 07:10:49 PM PST 24 |
11713773387 ps |
| T789 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1762011552 |
|
|
Jan 21 05:57:15 PM PST 24 |
Jan 21 06:05:01 PM PST 24 |
3339305532 ps |
| T1009 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2260291555 |
|
|
Jan 21 04:31:27 PM PST 24 |
Jan 21 04:48:20 PM PST 24 |
5335818830 ps |
| T1010 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.624004528 |
|
|
Jan 21 07:14:34 PM PST 24 |
Jan 21 07:21:23 PM PST 24 |
3671980956 ps |
| T819 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2068163245 |
|
|
Jan 21 05:13:11 PM PST 24 |
Jan 21 05:24:30 PM PST 24 |
4590393538 ps |
| T1011 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2146012641 |
|
|
Jan 21 04:45:57 PM PST 24 |
Jan 21 04:51:23 PM PST 24 |
3256745324 ps |
| T1012 |
/workspace/coverage/default/0.rom_raw_unlock.3174842526 |
|
|
Jan 21 04:33:07 PM PST 24 |
Jan 21 05:08:58 PM PST 24 |
15572066144 ps |
| T1013 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2262031977 |
|
|
Jan 21 06:32:47 PM PST 24 |
Jan 21 07:18:23 PM PST 24 |
13091757234 ps |
| T1014 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3924299386 |
|
|
Jan 21 04:33:35 PM PST 24 |
Jan 21 05:13:53 PM PST 24 |
8465460120 ps |
| T778 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2096391055 |
|
|
Jan 21 06:41:56 PM PST 24 |
Jan 21 06:48:37 PM PST 24 |
4152746144 ps |
| T1015 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4134002764 |
|
|
Jan 21 08:12:04 PM PST 24 |
Jan 21 08:21:43 PM PST 24 |
4629926492 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.353248551 |
|
|
Jan 21 04:39:38 PM PST 24 |
Jan 21 05:22:35 PM PST 24 |
10209842856 ps |
| T12 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1209588764 |
|
|
Jan 21 04:26:57 PM PST 24 |
Jan 21 04:36:29 PM PST 24 |
4934764122 ps |
| T296 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1315300312 |
|
|
Jan 21 05:12:18 PM PST 24 |
Jan 21 05:21:36 PM PST 24 |
5453735708 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.3711667011 |
|
|
Jan 21 05:02:19 PM PST 24 |
Jan 21 05:23:13 PM PST 24 |
5572845150 ps |
| T186 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1798964179 |
|
|
Jan 21 04:20:59 PM PST 24 |
Jan 21 04:50:04 PM PST 24 |
11235079440 ps |
| T1018 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1173592400 |
|
|
Jan 21 05:06:07 PM PST 24 |
Jan 21 05:13:52 PM PST 24 |
6527515408 ps |
| T102 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.124362 |
|
|
Jan 21 04:59:44 PM PST 24 |
Jan 21 05:52:30 PM PST 24 |
14161687667 ps |
| T1019 |
/workspace/coverage/default/2.chip_sw_aes_enc.4025574307 |
|
|
Jan 21 04:53:05 PM PST 24 |
Jan 21 04:59:24 PM PST 24 |
3031635188 ps |
| T402 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.4117566259 |
|
|
Jan 21 06:25:11 PM PST 24 |
Jan 21 06:44:12 PM PST 24 |
5132493240 ps |
| T1020 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3935873494 |
|
|
Jan 21 05:43:08 PM PST 24 |
Jan 21 05:49:16 PM PST 24 |
2987946406 ps |
| T1021 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3452907249 |
|
|
Jan 21 07:09:03 PM PST 24 |
Jan 21 07:45:59 PM PST 24 |
12640453160 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.348501603 |
|
|
Jan 21 04:18:45 PM PST 24 |
Jan 21 04:23:29 PM PST 24 |
3442151508 ps |
| T124 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.4119477956 |
|
|
Jan 21 04:48:42 PM PST 24 |
Jan 21 05:00:44 PM PST 24 |
8206882506 ps |
| T10 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.785205753 |
|
|
Jan 21 04:18:23 PM PST 24 |
Jan 21 04:25:04 PM PST 24 |
4712462112 ps |
| T22 |
/workspace/coverage/default/2.chip_sw_alert_test.1052161870 |
|
|
Jan 21 05:16:50 PM PST 24 |
Jan 21 05:21:56 PM PST 24 |
2848307224 ps |
| T363 |
/workspace/coverage/default/2.chip_tap_straps_rma.3390257820 |
|
|
Jan 21 04:59:46 PM PST 24 |
Jan 21 05:05:42 PM PST 24 |
3578954381 ps |
| T23 |
/workspace/coverage/default/1.chip_sw_alert_test.4148184007 |
|
|
Jan 21 04:39:20 PM PST 24 |
Jan 21 04:45:01 PM PST 24 |
2596509780 ps |
| T364 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1055693906 |
|
|
Jan 21 04:21:07 PM PST 24 |
Jan 21 04:39:49 PM PST 24 |
9413593748 ps |
| T365 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.340331169 |
|
|
Jan 21 06:35:34 PM PST 24 |
Jan 21 06:43:10 PM PST 24 |
3765049750 ps |
| T95 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1113930314 |
|
|
Jan 21 06:51:37 PM PST 24 |
Jan 21 06:58:11 PM PST 24 |
17971217004 ps |
| T366 |
/workspace/coverage/default/0.chip_sw_edn_kat.2057871517 |
|
|
Jan 21 04:21:52 PM PST 24 |
Jan 21 04:31:49 PM PST 24 |
3803670980 ps |
| T5 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3830412685 |
|
|
Jan 21 04:35:10 PM PST 24 |
Jan 21 04:39:50 PM PST 24 |
2700496193 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.522770623 |
|
|
Jan 21 04:23:01 PM PST 24 |
Jan 21 04:29:51 PM PST 24 |
3744390228 ps |
| T726 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.3556785840 |
|
|
Jan 21 04:23:16 PM PST 24 |
Jan 21 04:37:57 PM PST 24 |
4014879802 ps |
| T768 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4016358401 |
|
|
Jan 21 05:40:36 PM PST 24 |
Jan 21 05:53:55 PM PST 24 |
4277313880 ps |
| T1023 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1476349046 |
|
|
Jan 21 05:00:14 PM PST 24 |
Jan 21 05:03:54 PM PST 24 |
2827518670 ps |
| T1024 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.215048656 |
|
|
Jan 21 04:26:44 PM PST 24 |
Jan 21 04:29:54 PM PST 24 |
2702113120 ps |
| T404 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1177101281 |
|
|
Jan 21 06:18:22 PM PST 24 |
Jan 21 06:27:11 PM PST 24 |
5604335584 ps |
| T1025 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.2889273712 |
|
|
Jan 21 06:59:49 PM PST 24 |
Jan 21 11:25:11 PM PST 24 |
65440824577 ps |
| T1026 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.580486373 |
|
|
Jan 21 04:52:06 PM PST 24 |
Jan 21 05:21:42 PM PST 24 |
6537482064 ps |
| T1027 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1260341903 |
|
|
Jan 21 04:32:27 PM PST 24 |
Jan 21 04:36:39 PM PST 24 |
2880959688 ps |
| T344 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1926055532 |
|
|
Jan 21 04:34:31 PM PST 24 |
Jan 21 05:27:13 PM PST 24 |
9971304172 ps |
| T1028 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1695655541 |
|
|
Jan 21 04:35:48 PM PST 24 |
Jan 21 05:14:44 PM PST 24 |
8181334123 ps |
| T297 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2362232132 |
|
|
Jan 21 05:05:44 PM PST 24 |
Jan 21 05:18:47 PM PST 24 |
4887622100 ps |
| T340 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.1734522485 |
|
|
Jan 21 05:53:51 PM PST 24 |
Jan 21 06:04:36 PM PST 24 |
3245511240 ps |
| T1029 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1758440982 |
|
|
Jan 21 04:57:05 PM PST 24 |
Jan 21 05:08:11 PM PST 24 |
4600158588 ps |
| T405 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1989072967 |
|
|
Jan 21 04:55:50 PM PST 24 |
Jan 21 05:07:47 PM PST 24 |
5406189120 ps |
| T1030 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1607801972 |
|
|
Jan 21 05:04:03 PM PST 24 |
Jan 21 05:12:36 PM PST 24 |
4880916960 ps |
| T822 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.422973316 |
|
|
Jan 21 05:17:20 PM PST 24 |
Jan 21 05:24:13 PM PST 24 |
3809718380 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1122094306 |
|
|
Jan 21 05:36:23 PM PST 24 |
Jan 21 05:43:47 PM PST 24 |
3526798384 ps |
| T1032 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3921659859 |
|
|
Jan 21 04:56:34 PM PST 24 |
Jan 21 05:10:51 PM PST 24 |
7337317750 ps |
| T1033 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3053632614 |
|
|
Jan 21 04:55:19 PM PST 24 |
Jan 21 05:29:36 PM PST 24 |
8091987068 ps |
| T1034 |
/workspace/coverage/default/0.chip_sw_aes_idle.3308378773 |
|
|
Jan 21 04:21:26 PM PST 24 |
Jan 21 04:25:46 PM PST 24 |
3431549986 ps |
| T806 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.635755925 |
|
|
Jan 21 05:19:29 PM PST 24 |
Jan 21 05:27:03 PM PST 24 |
3374327170 ps |
| T1035 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3754838230 |
|
|
Jan 21 05:58:31 PM PST 24 |
Jan 21 06:10:46 PM PST 24 |
4470890628 ps |
| T213 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1015811718 |
|
|
Jan 21 05:03:42 PM PST 24 |
Jan 21 05:15:56 PM PST 24 |
6087732056 ps |
| T219 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3976604983 |
|
|
Jan 21 04:55:50 PM PST 24 |
Jan 21 05:12:08 PM PST 24 |
5139923223 ps |
| T220 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3423409274 |
|
|
Jan 21 07:14:20 PM PST 24 |
Jan 21 07:26:00 PM PST 24 |
5338193696 ps |
| T221 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2346933110 |
|
|
Jan 21 05:08:25 PM PST 24 |
Jan 21 05:15:20 PM PST 24 |
3693406948 ps |
| T214 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2017103364 |
|
|
Jan 21 04:34:02 PM PST 24 |
Jan 21 04:45:30 PM PST 24 |
5234229700 ps |
| T798 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.2699118686 |
|
|
Jan 21 06:24:30 PM PST 24 |
Jan 21 06:35:46 PM PST 24 |
5479250488 ps |
| T801 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2953920069 |
|
|
Jan 21 05:17:38 PM PST 24 |
Jan 21 05:29:38 PM PST 24 |
5231261640 ps |
| T1036 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.2390761539 |
|
|
Jan 21 05:05:54 PM PST 24 |
Jan 21 05:42:11 PM PST 24 |
8488205978 ps |
| T224 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3560465124 |
|
|
Jan 21 04:22:56 PM PST 24 |
Jan 21 04:31:07 PM PST 24 |
3862904460 ps |
| T182 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2649960630 |
|
|
Jan 21 05:19:15 PM PST 24 |
Jan 21 05:31:52 PM PST 24 |
6075058228 ps |
| T1037 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2309594696 |
|
|
Jan 21 04:45:15 PM PST 24 |
Jan 21 04:49:26 PM PST 24 |
3029159200 ps |
| T199 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4075922695 |
|
|
Jan 21 04:27:41 PM PST 24 |
Jan 21 04:31:36 PM PST 24 |
3324884681 ps |
| T1038 |
/workspace/coverage/default/2.chip_sw_example_rom.3627026413 |
|
|
Jan 21 04:45:38 PM PST 24 |
Jan 21 04:48:00 PM PST 24 |
2603525640 ps |
| T854 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3969369233 |
|
|
Jan 21 05:16:38 PM PST 24 |
Jan 21 05:28:12 PM PST 24 |
5492029428 ps |
| T1039 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3428542000 |
|
|
Jan 21 05:02:26 PM PST 24 |
Jan 21 05:21:32 PM PST 24 |
5619243800 ps |
| T1040 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.1803799792 |
|
|
Jan 21 04:17:54 PM PST 24 |
Jan 21 04:34:47 PM PST 24 |
4950631224 ps |
| T846 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3376529316 |
|
|
Jan 21 05:33:19 PM PST 24 |
Jan 21 05:41:07 PM PST 24 |
3664837280 ps |
| T1041 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3763386669 |
|
|
Jan 21 06:10:52 PM PST 24 |
Jan 21 06:18:14 PM PST 24 |
6170954914 ps |
| T406 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1823135543 |
|
|
Jan 21 04:55:46 PM PST 24 |
Jan 21 06:24:31 PM PST 24 |
15882647800 ps |
| T1042 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1685933667 |
|
|
Jan 21 04:21:01 PM PST 24 |
Jan 21 04:32:20 PM PST 24 |
4350198760 ps |
| T1043 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.4052595707 |
|
|
Jan 21 04:45:40 PM PST 24 |
Jan 21 04:49:41 PM PST 24 |
2894686770 ps |
| T1044 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2172379285 |
|
|
Jan 21 04:20:03 PM PST 24 |
Jan 21 04:38:30 PM PST 24 |
5985767195 ps |
| T163 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3441961830 |
|
|
Jan 21 05:19:36 PM PST 24 |
Jan 21 05:32:13 PM PST 24 |
5451853180 ps |
| T1045 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3550865655 |
|
|
Jan 21 04:37:15 PM PST 24 |
Jan 21 05:37:45 PM PST 24 |
38756887140 ps |
| T13 |
/workspace/coverage/default/2.chip_jtag_csr_rw.1963250990 |
|
|
Jan 21 04:51:20 PM PST 24 |
Jan 21 05:38:02 PM PST 24 |
20181624580 ps |
| T367 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.906436341 |
|
|
Jan 21 06:39:50 PM PST 24 |
Jan 21 06:51:57 PM PST 24 |
6430210712 ps |
| T368 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2597531067 |
|
|
Jan 21 05:03:02 PM PST 24 |
Jan 21 05:08:30 PM PST 24 |
2993603348 ps |
| T369 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2835548583 |
|
|
Jan 21 04:41:00 PM PST 24 |
Jan 21 04:52:46 PM PST 24 |
7410963479 ps |
| T370 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3459407422 |
|
|
Jan 21 05:07:44 PM PST 24 |
Jan 21 05:21:15 PM PST 24 |
4920171546 ps |
| T371 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3212093146 |
|
|
Jan 21 07:05:49 PM PST 24 |
Jan 21 07:14:26 PM PST 24 |
3639846322 ps |
| T372 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.383203119 |
|
|
Jan 21 04:37:13 PM PST 24 |
Jan 21 05:01:53 PM PST 24 |
12812227539 ps |
| T225 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3517157613 |
|
|
Jan 21 04:37:56 PM PST 24 |
Jan 21 04:46:37 PM PST 24 |
3375171368 ps |
| T373 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.526237504 |
|
|
Jan 21 05:22:13 PM PST 24 |
Jan 21 05:43:11 PM PST 24 |
6697030456 ps |
| T374 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3129751027 |
|
|
Jan 21 04:28:03 PM PST 24 |
Jan 21 05:45:34 PM PST 24 |
24597379185 ps |
| T1046 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.544846392 |
|
|
Jan 21 04:43:04 PM PST 24 |
Jan 21 04:49:17 PM PST 24 |
5333316052 ps |
| T226 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3922190222 |
|
|
Jan 21 04:51:49 PM PST 24 |
Jan 21 05:03:11 PM PST 24 |
4129255000 ps |
| T864 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.11997759 |
|
|
Jan 21 05:12:37 PM PST 24 |
Jan 21 05:22:30 PM PST 24 |
5040782828 ps |
| T1047 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2015426292 |
|
|
Jan 21 04:25:27 PM PST 24 |
Jan 21 04:28:49 PM PST 24 |
2229723320 ps |
| T769 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1185091167 |
|
|
Jan 21 05:24:56 PM PST 24 |
Jan 21 05:39:44 PM PST 24 |
5556106088 ps |
| T867 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.3816115590 |
|
|
Jan 21 05:02:46 PM PST 24 |
Jan 21 05:14:04 PM PST 24 |
3923544696 ps |
| T257 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.155374364 |
|
|
Jan 21 04:54:19 PM PST 24 |
Jan 21 05:14:51 PM PST 24 |
6369648902 ps |
| T96 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.3968360717 |
|
|
Jan 21 05:00:32 PM PST 24 |
Jan 21 05:06:38 PM PST 24 |
4283541928 ps |
| T1048 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4104867228 |
|
|
Jan 21 04:47:52 PM PST 24 |
Jan 21 04:50:58 PM PST 24 |
2138869376 ps |
| T773 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3766331754 |
|
|
Jan 21 04:52:08 PM PST 24 |
Jan 21 04:59:17 PM PST 24 |
3198695610 ps |
| T758 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.45007525 |
|
|
Jan 21 07:14:45 PM PST 24 |
Jan 21 07:24:00 PM PST 24 |
4112749756 ps |
| T1049 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2409311017 |
|
|
Jan 21 05:24:05 PM PST 24 |
Jan 21 05:34:14 PM PST 24 |
4761286438 ps |
| T202 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4190963003 |
|
|
Jan 21 06:09:54 PM PST 24 |
Jan 21 06:19:19 PM PST 24 |
5583635060 ps |
| T1050 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3886217961 |
|
|
Jan 21 04:46:26 PM PST 24 |
Jan 21 04:50:31 PM PST 24 |
2264191652 ps |
| T848 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2900288474 |
|
|
Jan 21 06:50:15 PM PST 24 |
Jan 21 07:03:47 PM PST 24 |
5906507332 ps |
| T1051 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2277991012 |
|
|
Jan 21 05:05:52 PM PST 24 |
Jan 21 05:48:36 PM PST 24 |
8903619493 ps |
| T1052 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.766999679 |
|
|
Jan 21 05:07:15 PM PST 24 |
Jan 21 05:27:00 PM PST 24 |
5358069446 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3072279918 |
|
|
Jan 21 04:37:06 PM PST 24 |
Jan 21 04:54:14 PM PST 24 |
5814295738 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2420843889 |
|
|
Jan 21 04:23:04 PM PST 24 |
Jan 21 04:35:03 PM PST 24 |
4467979524 ps |
| T1054 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1126045118 |
|
|
Jan 21 04:57:46 PM PST 24 |
Jan 21 05:10:42 PM PST 24 |
3606460444 ps |
| T1055 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1334790275 |
|
|
Jan 21 04:34:02 PM PST 24 |
Jan 21 05:13:45 PM PST 24 |
9652212736 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1341247170 |
|
|
Jan 21 04:39:56 PM PST 24 |
Jan 21 04:43:46 PM PST 24 |
2832918058 ps |
| T1056 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.562241246 |
|
|
Jan 21 06:09:39 PM PST 24 |
Jan 21 06:21:14 PM PST 24 |
6684798510 ps |
| T836 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2374293549 |
|
|
Jan 21 06:53:51 PM PST 24 |
Jan 21 07:00:52 PM PST 24 |
4047012478 ps |
| T74 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1528550914 |
|
|
Jan 21 05:06:15 PM PST 24 |
Jan 21 05:13:45 PM PST 24 |
3858515988 ps |
| T1057 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.2416878202 |
|
|
Jan 21 04:45:54 PM PST 24 |
Jan 21 05:19:34 PM PST 24 |
8591465646 ps |
| T1058 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1247312076 |
|
|
Jan 21 04:35:28 PM PST 24 |
Jan 21 05:11:33 PM PST 24 |
9423928648 ps |
| T1059 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.877662789 |
|
|
Jan 21 05:42:19 PM PST 24 |
Jan 21 06:56:08 PM PST 24 |
50103326368 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.657493212 |
|
|
Jan 21 04:48:26 PM PST 24 |
Jan 21 04:52:33 PM PST 24 |
1968544280 ps |
| T190 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.949923009 |
|
|
Jan 21 04:23:51 PM PST 24 |
Jan 21 04:28:19 PM PST 24 |
2953065000 ps |
| T394 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1729284803 |
|
|
Jan 21 04:58:43 PM PST 24 |
Jan 21 05:37:58 PM PST 24 |
21926110508 ps |
| T1061 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.112163240 |
|
|
Jan 21 04:24:34 PM PST 24 |
Jan 21 05:09:52 PM PST 24 |
20563476464 ps |
| T1062 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2709246925 |
|
|
Jan 21 05:23:45 PM PST 24 |
Jan 21 05:34:19 PM PST 24 |
6101896002 ps |
| T164 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.294356818 |
|
|
Jan 21 04:57:39 PM PST 24 |
Jan 21 05:08:57 PM PST 24 |
5312393762 ps |
| T1063 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3907686138 |
|
|
Jan 21 04:23:21 PM PST 24 |
Jan 21 04:35:06 PM PST 24 |
4328511734 ps |