CHIP Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.321m	2.217ms	3	3	100.00
		chip_sw_example_rom	2.275m	2.604ms	3	3	100.00
		chip_sw_example_manufacturer	5.360m	2.537ms	3	3	100.00
		chip_sw_example_concurrency	4.762m	2.915ms	3	3	100.00
		chip_sw_uart_smoketest_signed	42.131m	9.249ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.565m	6.746ms	5	5	100.00
V1	csr_rw	chip_csr_rw	13.983m	6.491ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.861h	93.030ms	4	5	80.00
V1	csr_aliasing	chip_csr_aliasing	1.905h	38.133ms	2	5	40.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	8.223m	9.823ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.905h	38.133ms	2	5	40.00
		chip_csr_rw	13.983m	6.491ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.730s	267.438us	99	100	99.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.534m	3.521ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.534m	3.521ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.534m	3.521ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	20.299m	5.920ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	20.299m	5.920ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	19.058m	5.782ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	19.247m	5.898ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	19.345m	5.307ms	5	5	100.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.698h	22.941ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	59.470m	14.308ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.158m	5.834ms	3	5	60.00
V1		TOTAL			216	223	96.86
V2	chip_pin_mux	chip_padctrl_attributes	5.164m	5.342ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.164m	5.342ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.662m	2.502ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.657m	4.712ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.832m	4.441ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	39.296m	17.984ms	5	5	100.00
		chip_tap_straps_testunlock0	8.873m	4.686ms	5	5	100.00
		chip_tap_straps_rma	15.729m	8.806ms	5	5	100.00
		chip_tap_straps_prod	39.502m	16.420ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.454m	2.894ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.439m	8.078ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	16.128m	6.115ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	16.128m	6.115ms	6	6	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.110m	2.988ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	7.139m	3.199ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.152m	4.333ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	32.404m	22.035ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_sysrst_ctrl_reset	32.404m	22.035ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	32.404m	22.035ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.201h	21.004ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.201h	21.004ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	11.720m	6.465ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.707m	19.680ms	3	3	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	21.553m	7.636ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	14.853m	12.010ms	3	3	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	17.118m	5.814ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.225m	6.542ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.360h	18.222ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.391m	2.441ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.993m	5.132ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.221m	3.502ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.677m	5.726ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.842m	3.476ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.966m	3.982ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.498m	2.635ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.431m	2.939ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	15.203m	7.689ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	15.203m	7.689ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.798m	5.906ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.260m	3.249ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.798m	5.906ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.753m	3.183ms	3	3	100.00
		chip_sw_aes_smoketest	5.160m	2.576ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.220m	3.540ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.708m	3.020ms	3	3	100.00
		chip_sw_csrng_smoketest	5.718m	2.697ms	3	3	100.00
		chip_sw_entropy_src_smoketest	12.098m	3.814ms	3	3	100.00
		chip_sw_gpio_smoketest	4.233m	2.494ms	3	3	100.00
		chip_sw_hmac_smoketest	7.618m	3.426ms	3	3	100.00
		chip_sw_kmac_smoketest	4.876m	3.285ms	3	3	100.00
		chip_sw_otbn_smoketest	49.040m	9.647ms	2	3	66.67
		chip_sw_otp_ctrl_smoketest	5.183m	2.645ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.265m	6.056ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	10.187m	5.198ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.384m	2.759ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.342m	2.707ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.451m	2.994ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.318m	3.114ms	3	3	100.00
		chip_sw_uart_smoketest	4.920m	3.205ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.578m	4.844ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	42.131m	9.249ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap			0	3	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.842m	8.545ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	40.974m	15.750ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.805m	4.194ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	10.787m	10.794ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap			0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	4.747h	67.207ms	2	3	66.67
V2	tl_d_oob_addr_access	chip_tl_errors	13.657m	5.573ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	13.657m	5.573ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.905h	38.133ms	2	5	40.00
		chip_same_csr_outstanding	1.405h	32.911ms	20	20	100.00
		chip_csr_hw_reset	6.565m	6.746ms	5	5	100.00
		chip_csr_rw	13.983m	6.491ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.905h	38.133ms	2	5	40.00
		chip_same_csr_outstanding	1.405h	32.911ms	20	20	100.00
		chip_csr_hw_reset	6.565m	6.746ms	5	5	100.00
		chip_csr_rw	13.983m	6.491ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.986m	2.810ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.550s	53.937us	100	100	100.00
		xbar_smoke_large_delays	2.077m	10.762ms	100	100	100.00
		xbar_smoke_slow_rsp	2.021m	6.586ms	100	100	100.00
		xbar_random_zero_delays	1.044m	608.601us	100	100	100.00
		xbar_random_large_delays	22.837m	114.326ms	100	100	100.00
		xbar_random_slow_rsp	20.519m	67.937ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.103m	1.366ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.004m	1.308ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.783m	2.589ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.004m	1.308ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.029m	3.848ms	100	100	100.00
		xbar_access_same_device_slow_rsp	47.331m	151.039ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.495m	2.647ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.346m	21.268ms	100	100	100.00
		xbar_stress_all_with_error	12.549m	18.852ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.967m	10.689ms	100	100	100.00
		xbar_stress_all_with_reset_error	23.261m	32.605ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.842m	8.545ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	1.138h	23.959ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.731m	8.841ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	29.254m	6.986ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	37.503m	9.061ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	38.962m	9.534ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.683m	9.652ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.023m	8.189ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	27.424m	6.890ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	40.278m	8.465ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	41.323m	8.574ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	41.410m	8.643ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	52.687m	9.971ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.010h	11.808ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.114h	11.993ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	59.943m	11.530ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.152h	11.707ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	48.602m	9.748ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.000h	12.618ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	57.052m	11.815ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	58.581m	12.204ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.044h	11.837ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	31.427m	7.019ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	37.842m	9.013ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	40.207m	8.457ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	37.664m	8.321ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	41.195m	9.012ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	29.769m	6.717ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	38.204m	8.571ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	36.360m	8.939ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	38.892m	8.181ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	36.047m	9.424ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.947m	6.978ms	3	3	100.00
		rom_e2e_asm_init_dev	38.616m	8.494ms	3	3	100.00
		rom_e2e_asm_init_prod	42.053m	8.860ms	3	3	100.00
		rom_e2e_asm_init_prod_end	43.850m	9.150ms	3	3	100.00
		rom_e2e_asm_init_rma	39.204m	8.577ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	58.282m	10.600ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.269m	3.032ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.391m	2.441ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.775m	2.419ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.459m	2.994ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.932m	4.284ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.707m	19.680ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.707m	19.680ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.795m	3.924ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.265m	6.056ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.795m	3.924ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.226m	9.650ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.226m	9.650ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.393m	6.913ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.940m	4.468ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	11.193m	5.993ms	3	3	100.00
		chip_sw_aes_idle	4.459m	2.994ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.065m	2.437ms	3	3	100.00
		chip_sw_kmac_idle	5.023m	3.503ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.588m	4.961ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.861m	4.963ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.222m	4.164ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	10.555m	6.102ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	29.097m	13.238ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.469m	4.463ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.482m	4.781ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.270m	3.727ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.554m	4.541ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.317m	4.066ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.420m	5.236ms	3	3	100.00
		chip_sw_ast_clk_outputs	21.553m	7.636ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	20.159m	13.950ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.270m	3.727ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.554m	4.541ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	17.118m	5.814ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.225m	6.542ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.360h	18.222ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.391m	2.441ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.993m	5.132ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.221m	3.502ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.677m	5.726ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.842m	3.476ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.966m	3.982ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.498m	2.635ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.750m	3.057ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	19.051m	6.009ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	22.464m	7.689ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.373h	24.846ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.129m	3.397ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	4.728m	3.052ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.366m	4.204ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.726m	3.564ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.162m	5.283ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	39.148m	21.926ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.379h	21.976ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	21.553m	7.636ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.424m	4.483ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	9.082m	3.485ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.300m	5.108ms	95	100	95.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	34.016m	7.580ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	34.323m	7.373ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	7.923m	4.042ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	13.203m	7.460ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.941m	2.895ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.501h	14.941ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.673m	2.682ms	3	3	100.00
		chip_sw_edn_entropy_reqs	20.589m	6.050ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.673m	2.682ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	34.323m	7.373ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test	11.788m	4.684ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	5.526m	3.421ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	41.273m	24.081ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.265m	4.827ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.225m	6.542ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	19.889m	4.759ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	17.118m	5.814ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.937h	42.286ms	1	3	33.33
V2	chip_sw_flash_scramble	chip_sw_flash_init	41.273m	24.081ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.356m	3.527ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	11.706m	4.329ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.133m	5.608ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.937h	42.286ms	1	3	33.33
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.133m	5.608ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.133m	5.608ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	10.133m	5.608ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.133m	5.608ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.300m	5.108ms	95	100	95.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	9.972m	9.939ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	22.509m	5.640ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.912m	5.353ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.555m	3.352ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.221m	3.502ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.065m	2.437ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.493m	6.167ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	20.295m	5.571ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	20.387m	5.525ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.034m	3.779ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	11.706m	4.329ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.677m	5.726ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	11.922m	5.406ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.932m	4.284ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.673h	15.966ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.994m	3.004ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.070m	3.087ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.842m	3.476ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	11.706m	4.329ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	18.644m	13.011ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.436m	3.422ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.078m	2.779ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.023m	3.503ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.673m	5.434ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	39.296m	17.984ms	5	5	100.00
		chip_tap_straps_rma	15.729m	8.806ms	5	5	100.00
		chip_tap_straps_prod	39.502m	16.420ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	6.191m	2.797ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	18.644m	13.011ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	18.644m	13.011ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	18.644m	13.011ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.691m	4.689ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	10.133m	5.608ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.937h	42.286ms	1	3	33.33
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.481m	4.791ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.416m	7.736ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.142m	8.850ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.523m	8.522ms	3	3	100.00
		chip_sw_lc_ctrl_transition	18.644m	13.011ms	15	15	100.00
		chip_sw_keymgr_key_derivation	11.706m	4.329ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	10.586m	9.739ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	20.760m	9.454ms	3	3	100.00
		chip_prim_tl_access	9.972m	9.939ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	20.159m	13.950ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.469m	4.463ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.482m	4.781ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.270m	3.727ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.554m	4.541ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.317m	4.066ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.420m	5.236ms	3	3	100.00
		chip_tap_straps_dev	39.296m	17.984ms	5	5	100.00
		chip_tap_straps_rma	15.729m	8.806ms	5	5	100.00
		chip_tap_straps_prod	39.502m	16.420ms	5	5	100.00
		chip_rv_dm_lc_disabled	10.103m	12.943ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.659m	3.271ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.538m	3.015ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.752m	3.772ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.465m	3.809ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	38.331m	34.446ms	3	3	100.00
		chip_rv_dm_lc_disabled	10.103m	12.943ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	2.007h	50.108ms	1	3	33.33
		chip_sw_lc_walkthrough_prod			0	3	0.00
		chip_sw_lc_walkthrough_prodend	17.812m	7.727ms	3	3	100.00
		chip_sw_lc_walkthrough_rma			0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	38.331m	34.446ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	5.965m	3.902ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	5.984m	4.964ms	3	3	100.00
		rom_volatile_raw_unlock	33.652m	8.591ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	18.644m	13.011ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	41.273m	24.081ms	3	3	100.00
		chip_sw_otbn_mem_scramble	11.359m	4.129ms	3	3	100.00
		chip_sw_keymgr_key_derivation	11.706m	4.329ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.445m	3.464ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.803m	2.513ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	41.273m	24.081ms	3	3	100.00
		chip_sw_otbn_mem_scramble	11.359m	4.129ms	3	3	100.00
		chip_sw_keymgr_key_derivation	11.706m	4.329ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.445m	3.464ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.803m	2.513ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	18.644m	13.011ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.262m	5.312ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	6.191m	2.797ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.481m	4.791ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.416m	7.736ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	24.142m	8.850ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	24.523m	8.522ms	3	3	100.00
		chip_sw_lc_ctrl_transition	18.644m	13.011ms	15	15	100.00
		chip_prim_tl_access	9.972m	9.939ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.972m	9.939ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	12.014m	8.207ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	9.734m	8.657ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.156m	6.045ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	9.904m	16.235ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	14.034m	17.576ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.848m	10.286ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	31.395m	17.991ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.226m	9.650ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	31.392m	12.617ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	8.823m	4.513ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	12.014m	8.207ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.841m	3.636ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.228h	50.103ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.738m	5.811ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.576m	5.214ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	49.378m	24.589ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.717m	6.704ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	33.626m	11.396ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	47.844m	20.272ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.385m	3.109ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.300m	5.108ms	95	100	95.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.586m	9.739ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.586m	9.739ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	33.626m	11.396ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	49.378m	24.589ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	8.823m	4.513ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.265m	6.056ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	9.512m	4.935ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	14.540m	7.345ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.569m	3.705ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	40.486m	15.269ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.641m	3.412ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.300m	5.108ms	95	100	95.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	39.141m	8.020ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.875m	6.151ms	3	3	100.00
		chip_plic_all_irqs_10	12.580m	4.833ms	2	3	66.67
		chip_plic_all_irqs_20	16.328m	4.459ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.515m	3.457ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.728m	2.632ms	3	3	100.00
V2	chip_sw_spi_device_tx_rx	chip_sw_spi_device_tx_rx	7.836m	3.887ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap			0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	17.167m	7.116ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	12.725m	4.166ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.744m	3.784ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.092m	3.529ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.445m	3.464ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.966m	3.982ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	16.395m	8.579ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.270m	7.337ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	20.760m	9.454ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.300m	5.108ms	95	100	95.00
		chip_sw_data_integrity_escalation	16.128m	6.115ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.021m	3.298ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.241m	3.488ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup			0	0	--
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	11.245m	3.793ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	0	--
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.737h	31.909ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	57.793m	12.431ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.676m	2.597ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.673m	5.434ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.300m	5.108ms	95	100	95.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.178m	3.949ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	40.486m	15.269ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.416m	4.504ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.054m	4.374ms	87	90	96.67
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	27.002m	11.963ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	34.016m	7.580ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	39.141m	8.020ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep			0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	49.008m	18.130ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.505m	13.237ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	9.512m	4.935ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.990m	4.877ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.715m	6.182ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	15.729m	8.806ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.103m	12.943ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2577	2661	96.84
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.250m	2.900ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.233m	4.683ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.836m	1.928ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.750m	2.023ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.323m	2.259ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.424h	50.966ms	0	1	0.00
		rom_e2e_jtag_inject_dev	2.000h	60.000ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.485h	50.971ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	50.568m	10.141ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.108m	3.878ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_combo_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.717m	6.704ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	32.404m	22.035ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_input	chip_sw_sysrst_ctrl_inputs	6.110m	2.988ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_input_interrupt	chip_sw_sysrst_ctrl_in_irq	10.152m	4.333ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_ulp_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	11.720m	6.465ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.737m	3.246ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	17.066m	4.693ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	42.923m	10.210ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.680m	3.327ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.046m	5.770ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.307m	2.825ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	13.581m	13.020ms	0	1	0.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	10.088m	5.831ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.317m	5.552ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	33.626m	11.396ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.300m	5.108ms	95	100	95.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_watermarks			0	0	--
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.557h	18.961ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.836m	1.928ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.750m	2.023ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.323m	2.259ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.896m	5.785ms	3	3	100.00
V3		TOTAL			31	48	64.58
	Unmapped tests	chip_sival_flash_info_access	8.890m	3.754ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.364m	4.603ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.344h	16.726ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	19.845m	5.573ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	14.785m	5.556ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.246m	3.407ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.631m	2.828ms	3	3	100.00
		TOTAL			2848	2956	96.35

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	7	7	7	100.00
V1	19	19	15	78.95
V2	290	276	245	84.48
V2S	1	1	1	100.00
V3	92	22	11	11.96

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.71	95.40	94.49	98.01	--	95.22	97.57	99.58

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 39 failures:

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.30714160554503664477098007703617845564000442283357561215168357128876905130445
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (18:10:09) Loading:
  (18:10:09) Loading:
  (18:10:09) Loading: 4 packages loaded
  (18:10:10) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (18:10:10) WARNING: Target pattern parsing failed.
  (18:10:10) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (18:10:10) INFO: Elapsed time: 18.631s
  (18:10:10) INFO: 0 processes.
  (18:10:10) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.38962697214390318967009098641875561382454025635794324983155140109015971687893
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:57:43) Loading:
  (16:57:43) Loading:
  (16:57:43) Loading: 4 packages loaded
  (16:57:43) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:57:43) WARNING: Target pattern parsing failed.
  (16:57:43) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:57:43) INFO: Elapsed time: 27.432s
  (16:57:43) INFO: 0 processes.
  (16:57:43) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.11883735027113026691281438548667383710087703333330659643450351920039357452099
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:25:14) Loading:
  (16:25:15) Loading:
  (16:25:15) Loading: 4 packages loaded
  (16:25:15) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:15) WARNING: Target pattern parsing failed.
  (16:25:15) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:15) INFO: Elapsed time: 22.082s
  (16:25:15) INFO: 0 processes.
  (16:25:15) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.10271920796686303129290688082119330732742045027541582028620510086863939417280
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:37:48) Loading:
  (16:37:49) Loading:
  (16:37:49) Loading: 4 packages loaded
  (16:37:49) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:37:49) WARNING: Target pattern parsing failed.
  (16:37:49) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:37:49) INFO: Elapsed time: 22.510s
  (16:37:49) INFO: 0 processes.
  (16:37:49) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.51243503739837624036658349846020892042954921826024638609752538640349784040388
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:25:05) Loading:
  (16:25:06) Loading:
  (16:25:06) Loading: 4 packages loaded
  (16:25:06) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:06) WARNING: Target pattern parsing failed.
  (16:25:06) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:25:06) INFO: Elapsed time: 17.737s
  (16:25:06) INFO: 0 processes.
  (16:25:06) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.61502405098802523086272615969060396250908020461412876021208029043738370362275
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (19:06:52) Loading:
  (19:06:52) Loading:
  (19:06:52) Loading: 4 packages loaded
  (19:06:53) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (19:06:53) WARNING: Target pattern parsing failed.
  (19:06:53) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (19:06:53) INFO: Elapsed time: 21.926s
  (19:06:53) INFO: 0 processes.
  (19:06:53) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.60445930509690341464917239509349829134691458443894252825959939520975456114148
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (16:25:15) Loading:
  (16:25:16) Loading:
  (16:25:16) Loading: 4 packages loaded
  (16:25:16) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:25:16) WARNING: Target pattern parsing failed.
  (16:25:16) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:25:16) INFO: Elapsed time: 20.014s
  (16:25:16) INFO: 0 processes.
  (16:25:16) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.33945436205682829863446166038990097343480223016845061403673046528378875245294
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (17:33:33) Loading:
  (17:33:33) Loading:
  (17:33:33) Loading: 4 packages loaded
  (17:33:34) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (17:33:34) WARNING: Target pattern parsing failed.
  (17:33:34) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (17:33:34) INFO: Elapsed time: 19.749s
  (17:33:34) INFO: 0 processes.
  (17:33:34) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_sw has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.30457767965303856362030240913973931932503891615838930898535235858597223980604
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log

  (17:13:58) Loading:
  (17:13:59) Loading:
  (17:13:59) Loading: 4 packages loaded
  (17:13:59) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (17:13:59) WARNING: Target pattern parsing failed.
  (17:13:59) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (17:13:59) INFO: Elapsed time: 17.584s
  (17:13:59) INFO: 0 processes.
  (17:13:59) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.12614378997879667766101998216951578447889331498695970382061138186916400181305
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log

  (16:38:49) Loading:
  (16:38:50) Loading:
  (16:38:50) Loading: 4 packages loaded
  (16:38:50) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:38:50) WARNING: Target pattern parsing failed.
  (16:38:50) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:38:50) INFO: Elapsed time: 34.382s
  (16:38:50) INFO: 0 processes.
  (16:38:50) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 8 more tests.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 3 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.68030954686758932817019847450438772212773416467687870171123830408908096479698
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:f055c5ea-3421-43fa-aeec-a9d4d5427f53
```
  - 1.chip_sw_uart_tx_rx_bootstrap.101628603142569118375358995568132821640147643908405516876783661985201440489766
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:53dbcfb4-cc93-4206-98ab-6830fa2f8a25
```
  - ... and 1 more failures.
- Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.23763489530650093464354717586213371669721156956555548509374288580901255668942
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  Job ID: smart:e83b62b4-ea26-4a08-87f7-ca299b678a1d
```
  - 1.chip_sw_exit_test_unlocked_bootstrap.101526291357785217642366249060468954098608921959988153161955244736092403711580
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  Job ID: smart:270d8a4f-51c8-4896-b0e2-b7e6cfb4bb7e
```
  - ... and 1 more failures.
- Test chip_sw_flash_rma_unlocked has 2 failures.
  - 0.chip_sw_flash_rma_unlocked.90171318656882801015083022323338650320425755384417274065238122877204342580261
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  Job ID: smart:1aa27d77-79ec-4d2b-bad5-2788681671c8
```
  - 2.chip_sw_flash_rma_unlocked.107650173282515272060096080189202133985930132433762527063999842705251509147992
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_flash_rma_unlocked/latest/run.log
```
  Job ID: smart:c72d14d8-0d19-4282-886e-2e0f2aa5019e
```
- Test chip_sw_lc_walkthrough_dev has 2 failures.
  - 0.chip_sw_lc_walkthrough_dev.10163438599549439983423513747607798132818194179074417216574264504829643153677
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log
```
  Job ID: smart:2fba56ec-08c4-44c8-8fd6-f0cc9bf76860
```
  - 1.chip_sw_lc_walkthrough_dev.104236289147043915388671153375185100226020485207727040190092904765116009022462
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log
```
  Job ID: smart:c0fe9670-7d00-405b-a693-a4e7d594d40f
```
- Test chip_sw_lc_walkthrough_prod has 3 failures.
  - 0.chip_sw_lc_walkthrough_prod.27086383304641208477569024392981113628706058635340168726536523004698858223586
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:5b98bc08-649b-46aa-8dad-1734164a1b5d
```
  - 1.chip_sw_lc_walkthrough_prod.5010504889763650046407806397163813695299464608173625829090954799471622141449
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:2e35c40d-a584-4609-8dde-96d559275592
```
  - ... and 1 more failures.
- ... and 8 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 5 failures:

Test chip_sw_pwrmgr_deep_sleep_por_reset has 3 failures.

0.chip_sw_pwrmgr_deep_sleep_por_reset.76415942999526537157440172357511592154112102828587636099171587640905071025206
Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17783.473816 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17783.473816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_pwrmgr_deep_sleep_por_reset.16466922272134413212764815299190160118877589727018989619562766225874845323644
Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 16234.902575 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16234.902575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_pwrmgr_normal_sleep_por_reset has 2 failures.

0.chip_sw_pwrmgr_normal_sleep_por_reset.16881114745137175188709374596961084197087474336206264949675822106993676357101
Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17951.687813 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17951.687813 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_pwrmgr_normal_sleep_por_reset.68958065632777637463129014010607101611576020746601704309291126250492739442643
Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17575.792368 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17575.792368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.38544248145330544996535113154253650268551413507079325038360188746389392762763
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:8cc28064-7499-4ae0-ab53-a268ad9364c3
```
  - 1.chip_csr_aliasing.103460567607761440637206234866896995382907471211455226573081610257274275353608
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:33ac8129-c3a2-413d-8671-f415bd97b727
```
  - ... and 1 more failures.
- Test chip_csr_bit_bash has 1 failures.
  - 1.chip_csr_bit_bash.114369015271380700761191851221734636825617365724603638766779639643917353226172
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  Job ID: smart:19d46b10-18d3-431e-bef9-28d5b00ebf58
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 4 failures:
- Test chip_sw_all_escalation_resets has 4 failures.
  - 2.chip_sw_all_escalation_resets.38060912201054330503287661155718724927124524004893595601432331359179665251626
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2575.217888 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2575.217888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.chip_sw_all_escalation_resets.60536428602233266156199193656255600229575545292368399502723140351652057615874
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2703.628398 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2703.628398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.70276439060840830289073287589969068942504123347056777026348674007117230407992
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 5592.796840 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 5592.796840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.84292508495846626397078304052574410140441197847100395306240883385766122504385
    Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6045.394958 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 6045.394958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.105551960974304349280212620357572498874411961488704699785165208447181347025947
    Line 803, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 10686.397160 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 10686.397160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.61881499059170040778608968777229448159858931955053310956237935651662094567128
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 10286.464152 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 10286.464152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
- Test chip_sw_pwrmgr_random_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.95247112497475305266996600561721371758533373104087226891412660024559969078412
    Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 7866.366880 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 7866.366880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.6177309809995742698418889736806678310430237965732013403185166798916419889751
    Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 8730.783760 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 8730.783760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.44499266770424510394056579247931729751657787634978926559909566007986532256564
    Line 711, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 1927.767000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1927.767000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.13952933651944966269944393555287936306231403306963426619425859599979078706287
    Line 714, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2023.220000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2023.220000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.56833717692624916514210087408447251875473294186706216670875498033052182075426
    Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2259.387500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2259.387500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.22695350745973593646071493485716369370502057602814402160941090161658765747826
Line 771, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 10229.809568 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 10229.809568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_self_hash.59203752620171515659847491980234443847806059528453197442926341433093153287464
Line 754, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 10140.889000 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 10140.889000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 3 failures.
  - 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.25659459322856830884979002870313223315486679234890662397813189423782969511666
    Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3374.137512 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 3374.137512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.chip_sw_alert_handler_lpg_sleep_mode_alerts.23982237678121698962237281788039649007606240423841992934089132444285904320335
    Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3769.664300 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 3769.664300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.3121944583733171148580423462038719174636404880194216722905683401198668864640
    Line 944, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4682.574712 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 4682.574712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_power_virus.53944987092363575579028904517269806772161361406196630766318345017647411434693
    Line 994, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4620.412995 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 4620.412995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 2 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.90320516199011818505715215772730669282683681495246199857611592365027873348530
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 50966.041597 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50966.041597 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.81967319475798923876644913993840732706671479038036119786239523752422736370994
    Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 50971.100314 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 50971.100314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done. has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.95403909121542739151549307283064796931582029022668375191389962372696109930167
    Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_FATAL @ 13019.834692 us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done.
  UVM_INFO @ 13019.834692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.67085511673613632748833531823178913225433917838323267196824208147051911282971
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  Job ID: smart:e742390a-f3e9-4449-a4bd-f23f045aee5d
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.722532251810203081090521270969756406779898384614112242005649386256612171173
    Line 765, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test chip_plic_all_irqs_10 has 1 failures.
  - 1.chip_plic_all_irqs_10.69917485027579499303600696825855379716304388029090442014571401925711431974117
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_plic_all_irqs_10/latest/run.log
```
  Job ID: smart:685c1b9d-1c89-463a-be60-a13ad934166a
```
Offending 'alert_o' has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 44.chip_sw_all_escalation_resets.10284815892376350344475285032935331810423400307503670843464952707202278368271
    Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest/run.log
```
      Offending 'alert_o'
  UVM_ERROR @ 3031.093656 us: (prim_alert_receiver.sv:313) [ASSERT FAILED] Alert_A
  UVM_INFO @ 3031.093656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test xbar_smoke has 1 failures.
  - 95.xbar_smoke.44695750650863823864311961659724045410430817993632135729751462766205883461113
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/95.xbar_smoke/latest/run.log
```
  Job ID: smart:754370b5-ec25-469f-a496-82807b461a12
```