Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : top_earlgrey
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.51 90.71 59.80 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey 94.75 90.71 93.54 100.00



Module Instance : tb.dut.top_earlgrey

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.75 90.71 93.54 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.59 95.38 94.33 95.75 95.25 97.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.07 76.19 100.00 97.01 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
clk_ctrl_and_main_pd_sva_if 100.00 100.00
u_adc_ctrl_aon 100.00 100.00
u_aes 100.00 100.00
u_alert_handler 99.92 99.92
u_aon_timer_aon 100.00 100.00
u_clkmgr_aon 100.00 100.00
u_csrng 99.72 99.72
u_dft_tap_breakout 100.00 100.00 100.00
u_edn0 99.50 99.50
u_edn1 99.58 99.58
u_entropy_src 99.84 99.84
u_flash_ctrl 99.96 99.96
u_gpio 100.00 100.00
u_hmac 100.00 100.00
u_i2c0 100.00 100.00
u_i2c1 100.00 100.00
u_i2c2 100.00 100.00
u_keymgr 89.68 89.68
u_kmac 99.94 99.94
u_lc_ctrl 92.60 92.60
u_otbn 100.00 100.00
u_otp_ctrl 84.81 84.81
u_pattgen 100.00 100.00
u_pinmux_aon 97.44 96.24 96.25 98.52 97.22 98.95
u_pwm_aon 100.00 100.00
u_pwrmgr_aon 99.78 99.78
u_rom_ctrl 99.96 99.96
u_rstmgr_aon 100.00 100.00
u_rv_core_ibex 96.56 97.60 95.36 98.89 98.13 92.81
u_rv_dm 100.00 100.00
u_rv_plic 95.53 93.81 91.06 100.00 92.78 100.00
u_rv_timer 100.00 100.00
u_sensor_ctrl_aon 93.93 92.46 89.63 93.39 94.18 100.00
u_spi_device 98.40 98.40
u_spi_host0 96.59 96.59
u_spi_host1 96.30 96.30
u_sram_ctrl_main 100.00 100.00
u_sram_ctrl_ret_aon 100.00 100.00
u_sysrst_ctrl_aon 100.00 100.00
u_uart0 100.00 100.00
u_uart1 100.00 100.00
u_uart2 100.00 100.00
u_uart3 100.00 100.00
u_usbdev 94.00 94.00
u_xbar_main 100.00 100.00
u_xbar_peri 100.00 100.00

Line Coverage for Module : top_earlgrey
Line No.TotalCoveredPercent
TOTAL28025490.71
CONT_ASSIGN74711100.00
CONT_ASSIGN74811100.00
CONT_ASSIGN74911100.00
CONT_ASSIGN750100.00
CONT_ASSIGN751100.00
CONT_ASSIGN752100.00
CONT_ASSIGN753100.00
CONT_ASSIGN754100.00
CONT_ASSIGN76711100.00
CONT_ASSIGN768100.00
CONT_ASSIGN769100.00
CONT_ASSIGN770100.00
CONT_ASSIGN771100.00
CONT_ASSIGN772100.00
CONT_ASSIGN773100.00
CONT_ASSIGN774100.00
CONT_ASSIGN78811100.00
CONT_ASSIGN79011100.00
CONT_ASSIGN79211100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN79611100.00
CONT_ASSIGN79811100.00
CONT_ASSIGN80011100.00
CONT_ASSIGN80411100.00
CONT_ASSIGN81311100.00
CONT_ASSIGN81411100.00
CONT_ASSIGN81811100.00
CONT_ASSIGN84211100.00
CONT_ASSIGN84311100.00
CONT_ASSIGN84511100.00
CONT_ASSIGN84611100.00
CONT_ASSIGN84811100.00
CONT_ASSIGN84911100.00
CONT_ASSIGN85111100.00
CONT_ASSIGN85211100.00
CONT_ASSIGN85411100.00
CONT_ASSIGN85511100.00
CONT_ASSIGN85711100.00
CONT_ASSIGN85811100.00
CONT_ASSIGN86011100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN86311100.00
CONT_ASSIGN86411100.00
CONT_ASSIGN86611100.00
CONT_ASSIGN86711100.00
CONT_ASSIGN86911100.00
CONT_ASSIGN87011100.00
CONT_ASSIGN872100.00
CONT_ASSIGN87311100.00
CONT_ASSIGN875100.00
CONT_ASSIGN87611100.00
CONT_ASSIGN87811100.00
CONT_ASSIGN87911100.00
CONT_ASSIGN88111100.00
CONT_ASSIGN88211100.00
CONT_ASSIGN88411100.00
CONT_ASSIGN88511100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN88811100.00
CONT_ASSIGN89011100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89411100.00
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89911100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90211100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN90511100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90811100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN91111100.00
CONT_ASSIGN91211100.00
CONT_ASSIGN91800
CONT_ASSIGN92000
CONT_ASSIGN92200
CONT_ASSIGN92400
CONT_ASSIGN92600
CONT_ASSIGN92800
CONT_ASSIGN93000
CONT_ASSIGN93200
CONT_ASSIGN93400
CONT_ASSIGN93600
CONT_ASSIGN93800
CONT_ASSIGN94000
CONT_ASSIGN94200
CONT_ASSIGN94400
CONT_ASSIGN94600
CONT_ASSIGN94800
CONT_ASSIGN95000
CONT_ASSIGN95200
CONT_ASSIGN95400
CONT_ASSIGN95600
CONT_ASSIGN95800
CONT_ASSIGN96000
CONT_ASSIGN96200
CONT_ASSIGN96400
CONT_ASSIGN96600
CONT_ASSIGN96800
CONT_ASSIGN97000
CONT_ASSIGN97200
CONT_ASSIGN97400
CONT_ASSIGN97600
CONT_ASSIGN97800
CONT_ASSIGN98000
CONT_ASSIGN98200
CONT_ASSIGN98400
CONT_ASSIGN98600
CONT_ASSIGN98800
CONT_ASSIGN99000
CONT_ASSIGN99200
CONT_ASSIGN99400
CONT_ASSIGN99600
CONT_ASSIGN99800
CONT_ASSIGN100000
CONT_ASSIGN100200
CONT_ASSIGN100400
CONT_ASSIGN100600
CONT_ASSIGN100800
CONT_ASSIGN101000
CONT_ASSIGN262811100.00
CONT_ASSIGN302511100.00
CONT_ASSIGN302611100.00
CONT_ASSIGN302711100.00
CONT_ASSIGN302811100.00
CONT_ASSIGN302911100.00
CONT_ASSIGN303011100.00
CONT_ASSIGN303111100.00
CONT_ASSIGN303211100.00
CONT_ASSIGN303311100.00
CONT_ASSIGN303411100.00
CONT_ASSIGN303511100.00
CONT_ASSIGN303611100.00
CONT_ASSIGN303711100.00
CONT_ASSIGN303811100.00
CONT_ASSIGN303911100.00
CONT_ASSIGN304011100.00
CONT_ASSIGN304111100.00
CONT_ASSIGN304211100.00
CONT_ASSIGN304311100.00
CONT_ASSIGN304411100.00
CONT_ASSIGN304511100.00
CONT_ASSIGN304611100.00
CONT_ASSIGN304711100.00
CONT_ASSIGN304811100.00
CONT_ASSIGN304911100.00
CONT_ASSIGN305011100.00
CONT_ASSIGN305111100.00
CONT_ASSIGN305211100.00
CONT_ASSIGN305311100.00
CONT_ASSIGN305411100.00
CONT_ASSIGN305511100.00
CONT_ASSIGN305611100.00
CONT_ASSIGN305711100.00
CONT_ASSIGN305811100.00
CONT_ASSIGN305911100.00
CONT_ASSIGN306011100.00
CONT_ASSIGN306111100.00
CONT_ASSIGN306211100.00
CONT_ASSIGN306311100.00
CONT_ASSIGN306411100.00
CONT_ASSIGN306511100.00
CONT_ASSIGN306611100.00
CONT_ASSIGN306711100.00
CONT_ASSIGN306811100.00
CONT_ASSIGN306911100.00
CONT_ASSIGN307011100.00
CONT_ASSIGN307111100.00
CONT_ASSIGN307211100.00
CONT_ASSIGN307311100.00
CONT_ASSIGN307411100.00
CONT_ASSIGN307511100.00
CONT_ASSIGN307611100.00
CONT_ASSIGN307711100.00
CONT_ASSIGN307811100.00
CONT_ASSIGN307911100.00
CONT_ASSIGN308011100.00
CONT_ASSIGN308111100.00
CONT_ASSIGN308411100.00
CONT_ASSIGN308511100.00
CONT_ASSIGN308611100.00
CONT_ASSIGN308711100.00
CONT_ASSIGN308811100.00
CONT_ASSIGN308911100.00
CONT_ASSIGN309011100.00
CONT_ASSIGN309111100.00
CONT_ASSIGN309211100.00
CONT_ASSIGN309311100.00
CONT_ASSIGN309411100.00
CONT_ASSIGN309511100.00
CONT_ASSIGN309611100.00
CONT_ASSIGN309711100.00
CONT_ASSIGN309811100.00
CONT_ASSIGN309911100.00
CONT_ASSIGN310011100.00
CONT_ASSIGN310111100.00
CONT_ASSIGN310211100.00
CONT_ASSIGN310311100.00
CONT_ASSIGN310411100.00
CONT_ASSIGN310511100.00
CONT_ASSIGN310611100.00
CONT_ASSIGN310711100.00
CONT_ASSIGN310811100.00
CONT_ASSIGN310911100.00
CONT_ASSIGN311011100.00
CONT_ASSIGN311111100.00
CONT_ASSIGN311211100.00
CONT_ASSIGN311311100.00
CONT_ASSIGN311411100.00
CONT_ASSIGN311511100.00
CONT_ASSIGN311600
CONT_ASSIGN311700
CONT_ASSIGN311800
CONT_ASSIGN311900
CONT_ASSIGN312000
CONT_ASSIGN312100
CONT_ASSIGN312211100.00
CONT_ASSIGN3123100.00
CONT_ASSIGN3124100.00
CONT_ASSIGN3125100.00
CONT_ASSIGN312611100.00
CONT_ASSIGN312711100.00
CONT_ASSIGN312811100.00
CONT_ASSIGN312911100.00
CONT_ASSIGN313011100.00
CONT_ASSIGN313111100.00
CONT_ASSIGN313211100.00
CONT_ASSIGN313311100.00
CONT_ASSIGN313411100.00
CONT_ASSIGN313511100.00
CONT_ASSIGN3136100.00
CONT_ASSIGN313700
CONT_ASSIGN313800
CONT_ASSIGN313900
CONT_ASSIGN314000
CONT_ASSIGN314100
CONT_ASSIGN314200
CONT_ASSIGN314300
CONT_ASSIGN314400
CONT_ASSIGN314500
CONT_ASSIGN314611100.00
CONT_ASSIGN314711100.00
CONT_ASSIGN314811100.00
CONT_ASSIGN314911100.00
CONT_ASSIGN315011100.00
CONT_ASSIGN315111100.00
CONT_ASSIGN3152100.00
CONT_ASSIGN315311100.00
CONT_ASSIGN315411100.00
CONT_ASSIGN315511100.00
CONT_ASSIGN315611100.00
CONT_ASSIGN315711100.00
CONT_ASSIGN315811100.00
CONT_ASSIGN316111100.00
CONT_ASSIGN316211100.00
CONT_ASSIGN316311100.00
CONT_ASSIGN316411100.00
CONT_ASSIGN316511100.00
CONT_ASSIGN316611100.00
CONT_ASSIGN316711100.00
CONT_ASSIGN316811100.00
CONT_ASSIGN316911100.00
CONT_ASSIGN317011100.00
CONT_ASSIGN317111100.00
CONT_ASSIGN317211100.00
CONT_ASSIGN317311100.00
CONT_ASSIGN317411100.00
CONT_ASSIGN317511100.00
CONT_ASSIGN317611100.00
CONT_ASSIGN317711100.00
CONT_ASSIGN317811100.00
CONT_ASSIGN317911100.00
CONT_ASSIGN318011100.00
CONT_ASSIGN318111100.00
CONT_ASSIGN318211100.00
CONT_ASSIGN318311100.00
CONT_ASSIGN318411100.00
CONT_ASSIGN318511100.00
CONT_ASSIGN318611100.00
CONT_ASSIGN318711100.00
CONT_ASSIGN318811100.00
CONT_ASSIGN318911100.00
CONT_ASSIGN319011100.00
CONT_ASSIGN319111100.00
CONT_ASSIGN319211100.00
CONT_ASSIGN319311100.00
CONT_ASSIGN319411100.00
CONT_ASSIGN319511100.00
CONT_ASSIGN319611100.00
CONT_ASSIGN319711100.00
CONT_ASSIGN319811100.00
CONT_ASSIGN319911100.00
CONT_ASSIGN3200100.00
CONT_ASSIGN3201100.00
CONT_ASSIGN3202100.00
CONT_ASSIGN320300
CONT_ASSIGN320400
CONT_ASSIGN320500
CONT_ASSIGN320600
CONT_ASSIGN320700
CONT_ASSIGN320800
CONT_ASSIGN320900
CONT_ASSIGN321000
CONT_ASSIGN321111100.00
CONT_ASSIGN321211100.00
CONT_ASSIGN3213100.00
CONT_ASSIGN321400
CONT_ASSIGN321500
CONT_ASSIGN321600
CONT_ASSIGN321700
CONT_ASSIGN321800
CONT_ASSIGN321900
CONT_ASSIGN322000
CONT_ASSIGN322100
CONT_ASSIGN322200
CONT_ASSIGN322300
CONT_ASSIGN322400
CONT_ASSIGN322500
CONT_ASSIGN322600
CONT_ASSIGN322700
CONT_ASSIGN322800
CONT_ASSIGN322911100.00
CONT_ASSIGN323000
CONT_ASSIGN323100
CONT_ASSIGN323200
CONT_ASSIGN323300
CONT_ASSIGN323400
CONT_ASSIGN323500
CONT_ASSIGN323911100.00
CONT_ASSIGN324011100.00
CONT_ASSIGN324111100.00
CONT_ASSIGN324211100.00
CONT_ASSIGN324311100.00
CONT_ASSIGN324411100.00
CONT_ASSIGN324511100.00
CONT_ASSIGN324611100.00
CONT_ASSIGN324711100.00
CONT_ASSIGN324811100.00
CONT_ASSIGN324911100.00
CONT_ASSIGN325011100.00
CONT_ASSIGN325111100.00
CONT_ASSIGN325211100.00
CONT_ASSIGN325311100.00
CONT_ASSIGN325611100.00
CONT_ASSIGN325711100.00
CONT_ASSIGN325811100.00
CONT_ASSIGN325911100.00
CONT_ASSIGN326011100.00
CONT_ASSIGN326111100.00
CONT_ASSIGN326211100.00
CONT_ASSIGN326311100.00
CONT_ASSIGN326411100.00
CONT_ASSIGN326511100.00
CONT_ASSIGN326611100.00
CONT_ASSIGN326711100.00
CONT_ASSIGN327011100.00
CONT_ASSIGN327111100.00
CONT_ASSIGN327411100.00
CONT_ASSIGN327511100.00
CONT_ASSIGN327611100.00
CONT_ASSIGN3277100.00
CONT_ASSIGN3278100.00
CONT_ASSIGN3279100.00
CONT_ASSIGN328011100.00
CONT_ASSIGN328111100.00
CONT_ASSIGN328211100.00
CONT_ASSIGN328311100.00
CONT_ASSIGN328400
CONT_ASSIGN328500
CONT_ASSIGN328811100.00
CONT_ASSIGN328911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
747 1 1
748 1 1
749 1 1
750 0 1
751 0 1
752 0 1
753 0 1
754 0 1
767 1 1
768 0 1
769 0 1
770 0 1
771 0 1
772 0 1
773 0 1
774 0 1
788 1 1
790 1 1
792 1 1
794 1 1
796 1 1
798 1 1
800 1 1
804 1 1
813 1 1
814 1 1
818 1 1
842 1 1
843 1 1
845 1 1
846 1 1
848 1 1
849 1 1
851 1 1
852 1 1
854 1 1
855 1 1
857 1 1
858 1 1
860 1 1
861 1 1
863 1 1
864 1 1
866 1 1
867 1 1
869 1 1
870 1 1
872 0 1
873 1 1
875 0 1
876 1 1
878 1 1
879 1 1
881 1 1
882 1 1
884 1 1
885 1 1
887 1 1
888 1 1
890 1 1
891 1 1
893 1 1
894 1 1
896 1 1
897 1 1
899 1 1
900 1 1
902 1 1
903 1 1
905 1 1
906 1 1
908 1 1
909 1 1
911 1 1
912 1 1
918 unreachable
920 unreachable
922 unreachable
924 unreachable
926 unreachable
928 unreachable
930 unreachable
932 unreachable
934 unreachable
936 unreachable
938 unreachable
940 unreachable
942 unreachable
944 unreachable
946 unreachable
948 unreachable
950 unreachable
952 unreachable
954 unreachable
956 unreachable
958 unreachable
960 unreachable
962 unreachable
964 unreachable
966 unreachable
968 unreachable
970 unreachable
972 unreachable
974 unreachable
976 unreachable
978 unreachable
980 unreachable
982 unreachable
984 unreachable
986 unreachable
988 unreachable
990 unreachable
992 unreachable
994 unreachable
996 unreachable
998 unreachable
1000 unreachable
1002 unreachable
1004 unreachable
1006 unreachable
1008 unreachable
1010 unreachable
2628 1 1
3025 1 1
3026 1 1
3027 1 1
3028 1 1
3029 1 1
3030 1 1
3031 1 1
3032 1 1
3033 1 1
3034 1 1
3035 1 1
3036 1 1
3037 1 1
3038 1 1
3039 1 1
3040 1 1
3041 1 1
3042 1 1
3043 1 1
3044 1 1
3045 1 1
3046 1 1
3047 1 1
3048 1 1
3049 1 1
3050 1 1
3051 1 1
3052 1 1
3053 1 1
3054 1 1
3055 1 1
3056 1 1
3057 1 1
3058 1 1
3059 1 1
3060 1 1
3061 1 1
3062 1 1
3063 1 1
3064 1 1
3065 1 1
3066 1 1
3067 1 1
3068 1 1
3069 1 1
3070 1 1
3071 1 1
3072 1 1
3073 1 1
3074 1 1
3075 1 1
3076 1 1
3077 1 1
3078 1 1
3079 1 1
3080 1 1
3081 1 1
3084 1 1
3085 1 1
3086 1 1
3087 1 1
3088 1 1
3089 1 1
3090 1 1
3091 1 1
3092 1 1
3093 1 1
3094 1 1
3095 1 1
3096 1 1
3097 1 1
3098 1 1
3099 1 1
3100 1 1
3101 1 1
3102 1 1
3103 1 1
3104 1 1
3105 1 1
3106 1 1
3107 1 1
3108 1 1
3109 1 1
3110 1 1
3111 1 1
3112 1 1
3113 1 1
3114 1 1
3115 1 1
3116 unreachable
3117 unreachable
3118 unreachable
3119 unreachable
3120 unreachable
3121 unreachable
3122 1 1
3123 0 1
3124 0 1
3125 0 1
3126 1 1
3127 1 1
3128 1 1
3129 1 1
3130 1 1
3131 1 1
3132 1 1
3133 1 1
3134 1 1
3135 1 1
3136 0 1
3137 unreachable
3138 unreachable
3139 unreachable
3140 unreachable
3141 unreachable
3142 unreachable
3143 unreachable
3144 unreachable
3145 unreachable
3146 1 1
3147 1 1
3148 1 1
3149 1 1
3150 1 1
3151 1 1
3152 0 1
3153 1 1
3154 1 1
3155 1 1
3156 1 1
3157 1 1
3158 1 1
3161 1 1
3162 1 1
3163 1 1
3164 1 1
3165 1 1
3166 1 1
3167 1 1
3168 1 1
3169 1 1
3170 1 1
3171 1 1
3172 1 1
3173 1 1
3174 1 1
3175 1 1
3176 1 1
3177 1 1
3178 1 1
3179 1 1
3180 1 1
3181 1 1
3182 1 1
3183 1 1
3184 1 1
3185 1 1
3186 1 1
3187 1 1
3188 1 1
3189 1 1
3190 1 1
3191 1 1
3192 1 1
3193 1 1
3194 1 1
3195 1 1
3196 1 1
3197 1 1
3198 1 1
3199 1 1
3200 0 1
3201 0 1
3202 0 1
3203 unreachable
3204 unreachable
3205 unreachable
3206 unreachable
3207 unreachable
3208 unreachable
3209 unreachable
3210 unreachable
3211 1 1
3212 1 1
3213 0 1
3214 unreachable
3215 unreachable
3216 unreachable
3217 unreachable
3218 unreachable
3219 unreachable
3220 unreachable
3221 unreachable
3222 unreachable
3223 unreachable
3224 unreachable
3225 unreachable
3226 unreachable
3227 unreachable
3228 unreachable
3229 1 1
3230 unreachable
3231 unreachable
3232 unreachable
3233 unreachable
3234 unreachable
3235 unreachable
3239 1 1
3240 1 1
3241 1 1
3242 1 1
3243 1 1
3244 1 1
3245 1 1
3246 1 1
3247 1 1
3248 1 1
3249 1 1
3250 1 1
3251 1 1
3252 1 1
3253 1 1
3256 1 1
3257 1 1
3258 1 1
3259 1 1
3260 1 1
3261 1 1
3262 1 1
3263 1 1
3264 1 1
3265 1 1
3266 1 1
3267 1 1
3270 1 1
3271 1 1
3274 1 1
3275 1 1
3276 1 1
3277 0 1
3278 0 1
3279 0 1
3280 1 1
3281 1 1
3282 1 1
3283 1 1
3284 unreachable
3285 unreachable
3288 1 1
3289 1 1


Toggle Coverage for Module : top_earlgrey
TotalCoveredPercent
Totals 788 425 53.93
Total Bits 2938 1757 59.80
Total Bits 0->1 1469 882 60.04
Total Bits 1->0 1469 875 59.56

Ports 788 425 53.93
Port Bits 2938 1757 59.80
Port Bits 0->1 1469 882 60.04
Port Bits 1->0 1469 875 59.56

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
mio_in_i[46:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
mio_out_o[46:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_oe_o[46:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_in_i[15:0] Yes Yes T30,T31,T1 Yes T30,T31,T1 INPUT
dio_out_o[11:0] Yes Yes *T30,*T31,T1 Yes T30,T31,T1 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_oe_o[15:0] Yes Yes T30,T31,T1 Yes T30,T31,T1 OUTPUT
mio_attr_o[0].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].keep_en No No No OUTPUT
mio_attr_o[0].schmitt_en No No No OUTPUT
mio_attr_o[0].od_en No No No OUTPUT
mio_attr_o[0].slew_rate[1:0] No No No OUTPUT
mio_attr_o[0].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].drive_strength[3:1] No No No OUTPUT
mio_attr_o[1].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].keep_en No No No OUTPUT
mio_attr_o[1].schmitt_en No No No OUTPUT
mio_attr_o[1].od_en No No No OUTPUT
mio_attr_o[1].slew_rate[1:0] No No No OUTPUT
mio_attr_o[1].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].drive_strength[3:1] No No No OUTPUT
mio_attr_o[2].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].keep_en No No No OUTPUT
mio_attr_o[2].schmitt_en No No No OUTPUT
mio_attr_o[2].od_en No No No OUTPUT
mio_attr_o[2].slew_rate[1:0] No No No OUTPUT
mio_attr_o[2].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].drive_strength[3:1] No No No OUTPUT
mio_attr_o[3].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].keep_en No No No OUTPUT
mio_attr_o[3].schmitt_en No No No OUTPUT
mio_attr_o[3].od_en No No No OUTPUT
mio_attr_o[3].slew_rate[1:0] No No No OUTPUT
mio_attr_o[3].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].drive_strength[3:1] No No No OUTPUT
mio_attr_o[4].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].keep_en No No No OUTPUT
mio_attr_o[4].schmitt_en No No No OUTPUT
mio_attr_o[4].od_en No No No OUTPUT
mio_attr_o[4].slew_rate[1:0] No No No OUTPUT
mio_attr_o[4].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].drive_strength[3:1] No No No OUTPUT
mio_attr_o[5].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].keep_en No No No OUTPUT
mio_attr_o[5].schmitt_en No No No OUTPUT
mio_attr_o[5].od_en No No No OUTPUT
mio_attr_o[5].slew_rate[1:0] No No No OUTPUT
mio_attr_o[5].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].drive_strength[3:1] No No No OUTPUT
mio_attr_o[6].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].keep_en No No No OUTPUT
mio_attr_o[6].schmitt_en No No No OUTPUT
mio_attr_o[6].od_en No No No OUTPUT
mio_attr_o[6].slew_rate[1:0] No No No OUTPUT
mio_attr_o[6].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].drive_strength[3:1] No No No OUTPUT
mio_attr_o[7].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].keep_en No No No OUTPUT
mio_attr_o[7].schmitt_en No No No OUTPUT
mio_attr_o[7].od_en No No No OUTPUT
mio_attr_o[7].slew_rate[1:0] No No No OUTPUT
mio_attr_o[7].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].drive_strength[3:1] No No No OUTPUT
mio_attr_o[8].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].keep_en No No No OUTPUT
mio_attr_o[8].schmitt_en No No No OUTPUT
mio_attr_o[8].od_en No No No OUTPUT
mio_attr_o[8].slew_rate[1:0] No No No OUTPUT
mio_attr_o[8].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].drive_strength[3:1] No No No OUTPUT
mio_attr_o[9].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].keep_en No No No OUTPUT
mio_attr_o[9].schmitt_en No No No OUTPUT
mio_attr_o[9].od_en No No No OUTPUT
mio_attr_o[9].slew_rate[1:0] No No No OUTPUT
mio_attr_o[9].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].drive_strength[3:1] No No No OUTPUT
mio_attr_o[10].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].keep_en No No No OUTPUT
mio_attr_o[10].schmitt_en No No No OUTPUT
mio_attr_o[10].od_en No No No OUTPUT
mio_attr_o[10].slew_rate[1:0] No No No OUTPUT
mio_attr_o[10].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].drive_strength[3:1] No No No OUTPUT
mio_attr_o[11].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].keep_en No No No OUTPUT
mio_attr_o[11].schmitt_en No No No OUTPUT
mio_attr_o[11].od_en No No No OUTPUT
mio_attr_o[11].slew_rate[1:0] No No No OUTPUT
mio_attr_o[11].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].drive_strength[3:1] No No No OUTPUT
mio_attr_o[12].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].keep_en No No No OUTPUT
mio_attr_o[12].schmitt_en No No No OUTPUT
mio_attr_o[12].od_en No No No OUTPUT
mio_attr_o[12].slew_rate[1:0] No No No OUTPUT
mio_attr_o[12].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].drive_strength[3:1] No No No OUTPUT
mio_attr_o[13].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].keep_en No No No OUTPUT
mio_attr_o[13].schmitt_en No No No OUTPUT
mio_attr_o[13].od_en No No No OUTPUT
mio_attr_o[13].slew_rate[1:0] No No No OUTPUT
mio_attr_o[13].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].drive_strength[3:1] No No No OUTPUT
mio_attr_o[14].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].keep_en No No No OUTPUT
mio_attr_o[14].schmitt_en No No No OUTPUT
mio_attr_o[14].od_en No No No OUTPUT
mio_attr_o[14].slew_rate[1:0] No No No OUTPUT
mio_attr_o[14].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].drive_strength[3:1] No No No OUTPUT
mio_attr_o[15].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].keep_en No No No OUTPUT
mio_attr_o[15].schmitt_en No No No OUTPUT
mio_attr_o[15].od_en No No No OUTPUT
mio_attr_o[15].slew_rate[1:0] No No No OUTPUT
mio_attr_o[15].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].drive_strength[3:1] No No No OUTPUT
mio_attr_o[16].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].keep_en No No No OUTPUT
mio_attr_o[16].schmitt_en No No No OUTPUT
mio_attr_o[16].od_en No No No OUTPUT
mio_attr_o[16].slew_rate[1:0] No No No OUTPUT
mio_attr_o[16].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].drive_strength[3:1] No No No OUTPUT
mio_attr_o[17].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].keep_en No No No OUTPUT
mio_attr_o[17].schmitt_en No No No OUTPUT
mio_attr_o[17].od_en No No No OUTPUT
mio_attr_o[17].slew_rate[1:0] No No No OUTPUT
mio_attr_o[17].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].drive_strength[3:1] No No No OUTPUT
mio_attr_o[18].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].keep_en No No No OUTPUT
mio_attr_o[18].schmitt_en No No No OUTPUT
mio_attr_o[18].od_en No No No OUTPUT
mio_attr_o[18].slew_rate[1:0] No No No OUTPUT
mio_attr_o[18].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].drive_strength[3:1] No No No OUTPUT
mio_attr_o[19].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].keep_en No No No OUTPUT
mio_attr_o[19].schmitt_en No No No OUTPUT
mio_attr_o[19].od_en No No No OUTPUT
mio_attr_o[19].slew_rate[1:0] No No No OUTPUT
mio_attr_o[19].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].drive_strength[3:1] No No No OUTPUT
mio_attr_o[20].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].keep_en No No No OUTPUT
mio_attr_o[20].schmitt_en No No No OUTPUT
mio_attr_o[20].od_en No No No OUTPUT
mio_attr_o[20].slew_rate[1:0] No No No OUTPUT
mio_attr_o[20].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].drive_strength[3:1] No No No OUTPUT
mio_attr_o[21].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].keep_en No No No OUTPUT
mio_attr_o[21].schmitt_en No No No OUTPUT
mio_attr_o[21].od_en No No No OUTPUT
mio_attr_o[21].slew_rate[1:0] No No No OUTPUT
mio_attr_o[21].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].drive_strength[3:1] No No No OUTPUT
mio_attr_o[22].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].keep_en No No No OUTPUT
mio_attr_o[22].schmitt_en No No No OUTPUT
mio_attr_o[22].od_en No No No OUTPUT
mio_attr_o[22].slew_rate[1:0] No No No OUTPUT
mio_attr_o[22].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].drive_strength[3:1] No No No OUTPUT
mio_attr_o[23].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].keep_en No No No OUTPUT
mio_attr_o[23].schmitt_en No No No OUTPUT
mio_attr_o[23].od_en No No No OUTPUT
mio_attr_o[23].slew_rate[1:0] No No No OUTPUT
mio_attr_o[23].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].drive_strength[3:1] No No No OUTPUT
mio_attr_o[24].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].keep_en No No No OUTPUT
mio_attr_o[24].schmitt_en No No No OUTPUT
mio_attr_o[24].od_en No No No OUTPUT
mio_attr_o[24].slew_rate[1:0] No No No OUTPUT
mio_attr_o[24].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].drive_strength[3:1] No No No OUTPUT
mio_attr_o[25].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].keep_en No No No OUTPUT
mio_attr_o[25].schmitt_en No No No OUTPUT
mio_attr_o[25].od_en No No No OUTPUT
mio_attr_o[25].slew_rate[1:0] No No No OUTPUT
mio_attr_o[25].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].drive_strength[3:1] No No No OUTPUT
mio_attr_o[26].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].keep_en No No No OUTPUT
mio_attr_o[26].schmitt_en No No No OUTPUT
mio_attr_o[26].od_en No No No OUTPUT
mio_attr_o[26].slew_rate[1:0] No No No OUTPUT
mio_attr_o[26].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].drive_strength[3:1] No No No OUTPUT
mio_attr_o[27].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].keep_en No No No OUTPUT
mio_attr_o[27].schmitt_en No No No OUTPUT
mio_attr_o[27].od_en No No No OUTPUT
mio_attr_o[27].slew_rate[1:0] No No No OUTPUT
mio_attr_o[27].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].drive_strength[3:1] No No No OUTPUT
mio_attr_o[28].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].keep_en No No No OUTPUT
mio_attr_o[28].schmitt_en No No No OUTPUT
mio_attr_o[28].od_en No No No OUTPUT
mio_attr_o[28].slew_rate[1:0] No No No OUTPUT
mio_attr_o[28].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].drive_strength[3:1] No No No OUTPUT
mio_attr_o[29].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].keep_en No No No OUTPUT
mio_attr_o[29].schmitt_en No No No OUTPUT
mio_attr_o[29].od_en No No No OUTPUT
mio_attr_o[29].slew_rate[1:0] No No No OUTPUT
mio_attr_o[29].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].drive_strength[3:1] No No No OUTPUT
mio_attr_o[30].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].keep_en No No No OUTPUT
mio_attr_o[30].schmitt_en No No No OUTPUT
mio_attr_o[30].od_en No No No OUTPUT
mio_attr_o[30].slew_rate[1:0] No No No OUTPUT
mio_attr_o[30].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].drive_strength[3:1] No No No OUTPUT
mio_attr_o[31].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].keep_en No No No OUTPUT
mio_attr_o[31].schmitt_en No No No OUTPUT
mio_attr_o[31].od_en No No No OUTPUT
mio_attr_o[31].slew_rate[1:0] No No No OUTPUT
mio_attr_o[31].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].drive_strength[3:1] No No No OUTPUT
mio_attr_o[32].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].keep_en No No No OUTPUT
mio_attr_o[32].schmitt_en No No No OUTPUT
mio_attr_o[32].od_en No No No OUTPUT
mio_attr_o[32].slew_rate[1:0] No No No OUTPUT
mio_attr_o[32].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].drive_strength[3:1] No No No OUTPUT
mio_attr_o[33].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].keep_en No No No OUTPUT
mio_attr_o[33].schmitt_en No No No OUTPUT
mio_attr_o[33].od_en No No No OUTPUT
mio_attr_o[33].slew_rate[1:0] No No No OUTPUT
mio_attr_o[33].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].drive_strength[3:1] No No No OUTPUT
mio_attr_o[34].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].keep_en No No No OUTPUT
mio_attr_o[34].schmitt_en No No No OUTPUT
mio_attr_o[34].od_en No No No OUTPUT
mio_attr_o[34].slew_rate[1:0] No No No OUTPUT
mio_attr_o[34].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].drive_strength[3:1] No No No OUTPUT
mio_attr_o[35].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].keep_en No No No OUTPUT
mio_attr_o[35].schmitt_en No No No OUTPUT
mio_attr_o[35].od_en No No No OUTPUT
mio_attr_o[35].slew_rate[1:0] No No No OUTPUT
mio_attr_o[35].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].drive_strength[3:1] No No No OUTPUT
mio_attr_o[36].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].keep_en No No No OUTPUT
mio_attr_o[36].schmitt_en No No No OUTPUT
mio_attr_o[36].od_en No No No OUTPUT
mio_attr_o[36].slew_rate[1:0] No No No OUTPUT
mio_attr_o[36].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].drive_strength[3:1] No No No OUTPUT
mio_attr_o[37].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].keep_en No No No OUTPUT
mio_attr_o[37].schmitt_en No No No OUTPUT
mio_attr_o[37].od_en No No No OUTPUT
mio_attr_o[37].slew_rate[1:0] No No No OUTPUT
mio_attr_o[37].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].drive_strength[3:1] No No No OUTPUT
mio_attr_o[38].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].keep_en No No No OUTPUT
mio_attr_o[38].schmitt_en No No No OUTPUT
mio_attr_o[38].od_en No No No OUTPUT
mio_attr_o[38].slew_rate[1:0] No No No OUTPUT
mio_attr_o[38].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].drive_strength[3:1] No No No OUTPUT
mio_attr_o[39].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].keep_en No No No OUTPUT
mio_attr_o[39].schmitt_en No No No OUTPUT
mio_attr_o[39].od_en No No No OUTPUT
mio_attr_o[39].slew_rate[1:0] No No No OUTPUT
mio_attr_o[39].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].drive_strength[3:1] No No No OUTPUT
mio_attr_o[40].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].keep_en No No No OUTPUT
mio_attr_o[40].schmitt_en No No No OUTPUT
mio_attr_o[40].od_en No No No OUTPUT
mio_attr_o[40].slew_rate[1:0] No No No OUTPUT
mio_attr_o[40].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].drive_strength[3:1] No No No OUTPUT
mio_attr_o[41].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].keep_en No No No OUTPUT
mio_attr_o[41].schmitt_en No No No OUTPUT
mio_attr_o[41].od_en No No No OUTPUT
mio_attr_o[41].slew_rate[1:0] No No No OUTPUT
mio_attr_o[41].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].drive_strength[3:1] No No No OUTPUT
mio_attr_o[42].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].keep_en No No No OUTPUT
mio_attr_o[42].schmitt_en No No No OUTPUT
mio_attr_o[42].od_en No No No OUTPUT
mio_attr_o[42].slew_rate[1:0] No No No OUTPUT
mio_attr_o[42].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].drive_strength[3:1] No No No OUTPUT
mio_attr_o[43].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].keep_en No No No OUTPUT
mio_attr_o[43].schmitt_en No No No OUTPUT
mio_attr_o[43].od_en No No No OUTPUT
mio_attr_o[43].slew_rate[1:0] No No No OUTPUT
mio_attr_o[43].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].drive_strength[3:1] No No No OUTPUT
mio_attr_o[44].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].keep_en No No No OUTPUT
mio_attr_o[44].schmitt_en No No No OUTPUT
mio_attr_o[44].od_en No No No OUTPUT
mio_attr_o[44].slew_rate[1:0] No No No OUTPUT
mio_attr_o[44].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].drive_strength[3:1] No No No OUTPUT
mio_attr_o[45].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].keep_en No No No OUTPUT
mio_attr_o[45].schmitt_en No No No OUTPUT
mio_attr_o[45].od_en No No No OUTPUT
mio_attr_o[45].slew_rate[1:0] No No No OUTPUT
mio_attr_o[45].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].drive_strength[3:1] No No No OUTPUT
mio_attr_o[46].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].keep_en No No No OUTPUT
mio_attr_o[46].schmitt_en No No No OUTPUT
mio_attr_o[46].od_en No No No OUTPUT
mio_attr_o[46].slew_rate[1:0] No No No OUTPUT
mio_attr_o[46].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].drive_strength[3:1] No No No OUTPUT
dio_attr_o[0].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T1,*T2,*T7 Yes T1,T2,T7 OUTPUT
dio_attr_o[0].drive_strength[3:1] No No No OUTPUT
dio_attr_o[1].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].keep_en No No No OUTPUT
dio_attr_o[1].schmitt_en No No No OUTPUT
dio_attr_o[1].od_en No No No OUTPUT
dio_attr_o[1].slew_rate[1:0] No No No OUTPUT
dio_attr_o[1].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].drive_strength[3:1] No No No OUTPUT
dio_attr_o[2].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].keep_en No No No OUTPUT
dio_attr_o[2].schmitt_en No No No OUTPUT
dio_attr_o[2].od_en No No No OUTPUT
dio_attr_o[2].slew_rate[1:0] No No No OUTPUT
dio_attr_o[2].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].drive_strength[3:1] No No No OUTPUT
dio_attr_o[3].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].keep_en No No No OUTPUT
dio_attr_o[3].schmitt_en No No No OUTPUT
dio_attr_o[3].od_en No No No OUTPUT
dio_attr_o[3].slew_rate[1:0] No No No OUTPUT
dio_attr_o[3].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].drive_strength[3:1] No No No OUTPUT
dio_attr_o[4].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].keep_en No No No OUTPUT
dio_attr_o[4].schmitt_en No No No OUTPUT
dio_attr_o[4].od_en No No No OUTPUT
dio_attr_o[4].slew_rate[1:0] No No No OUTPUT
dio_attr_o[4].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].drive_strength[3:1] No No No OUTPUT
dio_attr_o[5].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].keep_en No No No OUTPUT
dio_attr_o[5].schmitt_en No No No OUTPUT
dio_attr_o[5].od_en No No No OUTPUT
dio_attr_o[5].slew_rate[1:0] No No No OUTPUT
dio_attr_o[5].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].drive_strength[3:1] No No No OUTPUT
dio_attr_o[6].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].keep_en No No No OUTPUT
dio_attr_o[6].schmitt_en No No No OUTPUT
dio_attr_o[6].od_en No No No OUTPUT
dio_attr_o[6].slew_rate[1:0] No No No OUTPUT
dio_attr_o[6].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].drive_strength[3:1] No No No OUTPUT
dio_attr_o[7].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].keep_en No No No OUTPUT
dio_attr_o[7].schmitt_en No No No OUTPUT
dio_attr_o[7].od_en No No No OUTPUT
dio_attr_o[7].slew_rate[1:0] No No No OUTPUT
dio_attr_o[7].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].drive_strength[3:1] No No No OUTPUT
dio_attr_o[8].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].keep_en No No No OUTPUT
dio_attr_o[8].schmitt_en No No No OUTPUT
dio_attr_o[8].od_en No No No OUTPUT
dio_attr_o[8].slew_rate[1:0] No No No OUTPUT
dio_attr_o[8].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].drive_strength[3:1] No No No OUTPUT
dio_attr_o[9].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].keep_en No No No OUTPUT
dio_attr_o[9].schmitt_en No No No OUTPUT
dio_attr_o[9].od_en No No No OUTPUT
dio_attr_o[9].slew_rate[1:0] No No No OUTPUT
dio_attr_o[9].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].drive_strength[3:1] No No No OUTPUT
dio_attr_o[10].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].keep_en No No No OUTPUT
dio_attr_o[10].schmitt_en No No No OUTPUT
dio_attr_o[10].od_en No No No OUTPUT
dio_attr_o[10].slew_rate[1:0] No No No OUTPUT
dio_attr_o[10].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].drive_strength[3:1] No No No OUTPUT
dio_attr_o[11].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].keep_en No No No OUTPUT
dio_attr_o[11].schmitt_en No No No OUTPUT
dio_attr_o[11].od_en No No No OUTPUT
dio_attr_o[11].slew_rate[1:0] No No No OUTPUT
dio_attr_o[11].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].drive_strength[3:1] No No No OUTPUT
dio_attr_o[12].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[12].virt_od_en No No No OUTPUT
dio_attr_o[12].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[12].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[12].keep_en No No No OUTPUT
dio_attr_o[12].schmitt_en No No No OUTPUT
dio_attr_o[12].od_en No No No OUTPUT
dio_attr_o[12].slew_rate[1:0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:0] No No No OUTPUT
dio_attr_o[13].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[13].virt_od_en No No No OUTPUT
dio_attr_o[13].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[13].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[13].keep_en No No No OUTPUT
dio_attr_o[13].schmitt_en No No No OUTPUT
dio_attr_o[13].od_en No No No OUTPUT
dio_attr_o[13].slew_rate[1:0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:0] No No No OUTPUT
dio_attr_o[14].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].keep_en No No No OUTPUT
dio_attr_o[14].schmitt_en No No No OUTPUT
dio_attr_o[14].od_en No No No OUTPUT
dio_attr_o[14].slew_rate[1:0] No No No OUTPUT
dio_attr_o[14].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].drive_strength[3:1] No No No OUTPUT
dio_attr_o[15].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].keep_en No No No OUTPUT
dio_attr_o[15].schmitt_en No No No OUTPUT
dio_attr_o[15].od_en No No No OUTPUT
dio_attr_o[15].slew_rate[1:0] No No No OUTPUT
dio_attr_o[15].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].drive_strength[3:1] No No No OUTPUT
adc_req_o.pd Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
adc_req_o.channel_sel[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
adc_rsp_i.data_valid Yes Yes T85,T86,T87 Yes T85,T86,T87 INPUT
adc_rsp_i.data[9:0] Yes Yes T85,T86,T88 Yes T85,T86,T88 INPUT
ast_edn_req_i.edn_req Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
ast_edn_rsp_o.edn_bus[31:0] Yes Yes T17,T18,T20 Yes T17,T18,T20 OUTPUT
ast_edn_rsp_o.edn_fips Yes Yes T89,T90,T91 Yes T92,T93,T94 OUTPUT
ast_edn_rsp_o.edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
ast_lc_dft_en_o[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
ram_1p_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_1p_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_1p_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_1p_cfg_i.ram_cfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en No No No INPUT
rom_cfg_i.cfg[3:0] No No No INPUT
rom_cfg_i.cfg_en No No No INPUT
clk_main_jitter_en_o[3:0] Yes Yes T31,T17,T95 Yes T31,T95,T96 OUTPUT
io_clk_byp_req_o[3:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
io_clk_byp_ack_i[3:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 INPUT
all_clk_byp_req_o[3:0] Yes Yes T47,T38,T97 Yes T47,T98,T99 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T47,T38,T97 Yes T47,T98,T99 INPUT
hi_speed_sel_o[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
div_step_down_req_i[3:0] Yes Yes T47,T38,T39 Yes T47,T38,T39 INPUT
calib_rdy_i[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T32,T33,T55 Yes T73,T100,T58 INPUT
flash_power_ready_h_i No No Yes T32,T33,T34 INPUT
flash_test_mode_a_io[1:0] No No Yes T4,T5,T6 INOUT
flash_test_voltage_h_io No No Yes T4,T5,T6 INOUT
flash_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
es_rng_req_o.rng_enable Yes Yes T20,T21,T41 Yes T17,T18,T19 OUTPUT
es_rng_rsp_i.rng_b[3:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
es_rng_rsp_i.rng_valid Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
es_rng_fips_o Yes Yes T81,T101,T102 Yes T80,T81,T103 OUTPUT
ast_tl_req_o.d_ready Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_user.data_intg[6:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_user.instr_type[3:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_data[31:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_mask[3:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_source[5:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_size[1:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_opcode[2:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_valid Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_rsp_i.a_ready Yes Yes T32,T33,T55 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_error Yes Yes T33,T34,T56 Yes T33,T34,T56 INPUT
ast_tl_rsp_i.d_user.data_intg[6:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_data[31:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_sink Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_source[5:0] Yes Yes T33,T34,T56 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_size[1:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_opcode[0] Yes Yes *T32,*T33,*T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_valid Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
dft_strap_test_o.straps[1:0] No No Yes T42,T43,T44 OUTPUT
dft_strap_test_o.valid Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
usb_dp_pullup_en_o Yes Yes T51,T54,T52 Yes T19,T35,T36 OUTPUT
usb_dn_pullup_en_o Yes Yes T51,T52,T53 Yes T51,T52,T53 OUTPUT
pwrmgr_ast_req_o.usb_clk_en Yes Yes T104,T29,T105 Yes T32,T33,T55 OUTPUT
pwrmgr_ast_req_o.io_clk_en Yes Yes T104,T29,T105 Yes T32,T33,T55 OUTPUT
pwrmgr_ast_req_o.core_clk_en Yes Yes T104,T29,T105 Yes T32,T33,T55 OUTPUT
pwrmgr_ast_req_o.slow_clk_en No No No OUTPUT
pwrmgr_ast_req_o.pwr_clamp Yes Yes T32,T33,T55 Yes T104,T29,T105 OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env Yes Yes T32,T33,T55 Yes T104,T29,T105 OUTPUT
pwrmgr_ast_req_o.main_pd_n Yes Yes T73,T100,T58 Yes T73,T100,T58 OUTPUT
pwrmgr_ast_rsp_i.main_pok Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
pwrmgr_ast_rsp_i.usb_clk_val Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
pwrmgr_ast_rsp_i.io_clk_val Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
pwrmgr_ast_rsp_i.core_clk_val Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
pwrmgr_ast_rsp_i.slow_clk_val Yes Yes T47,T38,T106 Yes T32,T33,T34 INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0] No No No OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0] No No No INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1] Yes Yes T32,T33,T55 Yes T73,T100,T58 INPUT
otp_ext_voltage_h_io No No Yes T4,T5,T6 INOUT
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
por_n_i[1:0] Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n Yes Yes T107,T111,T112 Yes T107,T111,T112 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p Yes Yes T107,T111,T112 Yes T107,T111,T112 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n Yes Yes T111,T112,T108 Yes T111,T112,T108 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p Yes Yes T111,T112,T108 Yes T111,T112,T108 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n Yes Yes T113,T108,T109 Yes T113,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p Yes Yes T113,T108,T109 Yes T113,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n Yes Yes T107,T111,T112 Yes T107,T111,T112 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p Yes Yes T107,T111,T112 Yes T107,T111,T112 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n Yes Yes T111,T112,T108 Yes T111,T112,T108 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p Yes Yes T111,T112,T108 Yes T111,T112,T108 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n Yes Yes T113,T108,T109 Yes T113,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p Yes Yes T113,T108,T109 Yes T113,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p Yes Yes T73,T107,T114 Yes T73,T107,T114 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n Yes Yes T107,T111,T112 Yes T107,T111,T112 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p Yes Yes T107,T111,T112 Yes T107,T111,T112 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n Yes Yes T111,T112,T108 Yes T111,T112,T108 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p Yes Yes T111,T112,T108 Yes T111,T112,T108 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n Yes Yes T113,T108,T109 Yes T113,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p Yes Yes T113,T108,T109 Yes T113,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0] Yes Yes T106,T115,T116 Yes T32,T33,T34 INPUT
ast2pinmux_i[8:0] Unreachable Unreachable Unreachable INPUT
ast_init_done_i[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
sck_monitor_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
usbdev_usb_rx_d_i Yes Yes T30,T31,T51 Yes T30,T31,T51 INPUT
usbdev_usb_tx_d_o Yes Yes T30,T31,T62 Yes T30,T31,T62 OUTPUT
usbdev_usb_tx_se0_o Yes Yes T117,T54,T52 Yes T117,T54,T52 OUTPUT
usbdev_usb_tx_use_d_se0_o Yes Yes T30,T31,T118 Yes T30,T31,T118 OUTPUT
usbdev_usb_rx_enable_o Yes Yes T30,T31,T12 Yes T30,T31,T51 OUTPUT
usbdev_usb_ref_val_o Yes Yes T54,T52,T119 Yes T19,T117,T54 OUTPUT
usbdev_usb_ref_pulse_o Yes Yes T19,T117,T54 Yes T19,T117,T54 OUTPUT
clk_main_i Yes Yes T32,T33,T55 Yes T32,T33,T55 INPUT
clk_io_i Yes Yes T32,T33,T55 Yes T32,T33,T55 INPUT
clk_usb_i Yes Yes T32,T33,T55 Yes T32,T33,T55 INPUT
clk_aon_i Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
clks_ast_o.clk_usb_peri Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_peri Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div2_peri Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div4_peri Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div4_timers Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_secure Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div4_secure Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div2_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_usb_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div4_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_otbn Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_kmac Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_hmac Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_aes Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_aon_timers Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
clks_ast_o.clk_aon_peri Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
clks_ast_o.clk_aon_secure Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
clks_ast_o.clk_io_div2_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
clks_ast_o.clk_usb_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
clks_ast_o.clk_io_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
clks_ast_o.clk_main_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
clks_ast_o.clk_aon_powerup Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
clks_ast_o.clk_io_div4_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_i2c2_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c2_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_i2c1_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c1_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_i2c0_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c0_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_usb_aon_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_aon_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_usb_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_spi_host1_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host1_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_spi_host0_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host0_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_spi_device_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_device_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_sys_n[0] No No No OUTPUT
rsts_ast_o.rst_sys_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_io_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_aon_n[0] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_aon_n[1] No No No OUTPUT
rsts_ast_o.rst_lc_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_por_usb_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_usb_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div4_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div2_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_io_div2_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_io_n[1] No No No OUTPUT
rsts_ast_o.rst_por_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_n[1] No No No OUTPUT
rsts_ast_o.rst_por_aon_n[1:0] Yes Yes T104,T29,T105 Yes T32,T33,T55 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : top_earlgrey
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
scanmodeKnown 346967378 346967378 0 0


scanmodeKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 346967378 346967378 0 0
T1 121364 121364 0 0
T2 175767 175767 0 0
T3 196136 196136 0 0
T7 137054 137054 0 0
T60 158417 158417 0 0
T61 175868 175868 0 0
T62 179351 179351 0 0
T63 148543 148543 0 0
T64 135119 135119 0 0
T65 150384 150384 0 0

Line Coverage for Instance : tb.dut.top_earlgrey
Line No.TotalCoveredPercent
TOTAL28025490.71
CONT_ASSIGN74711100.00
CONT_ASSIGN74811100.00
CONT_ASSIGN74911100.00
CONT_ASSIGN750100.00
CONT_ASSIGN751100.00
CONT_ASSIGN752100.00
CONT_ASSIGN753100.00
CONT_ASSIGN754100.00
CONT_ASSIGN76711100.00
CONT_ASSIGN768100.00
CONT_ASSIGN769100.00
CONT_ASSIGN770100.00
CONT_ASSIGN771100.00
CONT_ASSIGN772100.00
CONT_ASSIGN773100.00
CONT_ASSIGN774100.00
CONT_ASSIGN78811100.00
CONT_ASSIGN79011100.00
CONT_ASSIGN79211100.00
CONT_ASSIGN79411100.00
CONT_ASSIGN79611100.00
CONT_ASSIGN79811100.00
CONT_ASSIGN80011100.00
CONT_ASSIGN80411100.00
CONT_ASSIGN81311100.00
CONT_ASSIGN81411100.00
CONT_ASSIGN81811100.00
CONT_ASSIGN84211100.00
CONT_ASSIGN84311100.00
CONT_ASSIGN84511100.00
CONT_ASSIGN84611100.00
CONT_ASSIGN84811100.00
CONT_ASSIGN84911100.00
CONT_ASSIGN85111100.00
CONT_ASSIGN85211100.00
CONT_ASSIGN85411100.00
CONT_ASSIGN85511100.00
CONT_ASSIGN85711100.00
CONT_ASSIGN85811100.00
CONT_ASSIGN86011100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN86311100.00
CONT_ASSIGN86411100.00
CONT_ASSIGN86611100.00
CONT_ASSIGN86711100.00
CONT_ASSIGN86911100.00
CONT_ASSIGN87011100.00
CONT_ASSIGN872100.00
CONT_ASSIGN87311100.00
CONT_ASSIGN875100.00
CONT_ASSIGN87611100.00
CONT_ASSIGN87811100.00
CONT_ASSIGN87911100.00
CONT_ASSIGN88111100.00
CONT_ASSIGN88211100.00
CONT_ASSIGN88411100.00
CONT_ASSIGN88511100.00
CONT_ASSIGN88711100.00
CONT_ASSIGN88811100.00
CONT_ASSIGN89011100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89411100.00
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89911100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90211100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN90511100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90811100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN91111100.00
CONT_ASSIGN91211100.00
CONT_ASSIGN91800
CONT_ASSIGN92000
CONT_ASSIGN92200
CONT_ASSIGN92400
CONT_ASSIGN92600
CONT_ASSIGN92800
CONT_ASSIGN93000
CONT_ASSIGN93200
CONT_ASSIGN93400
CONT_ASSIGN93600
CONT_ASSIGN93800
CONT_ASSIGN94000
CONT_ASSIGN94200
CONT_ASSIGN94400
CONT_ASSIGN94600
CONT_ASSIGN94800
CONT_ASSIGN95000
CONT_ASSIGN95200
CONT_ASSIGN95400
CONT_ASSIGN95600
CONT_ASSIGN95800
CONT_ASSIGN96000
CONT_ASSIGN96200
CONT_ASSIGN96400
CONT_ASSIGN96600
CONT_ASSIGN96800
CONT_ASSIGN97000
CONT_ASSIGN97200
CONT_ASSIGN97400
CONT_ASSIGN97600
CONT_ASSIGN97800
CONT_ASSIGN98000
CONT_ASSIGN98200
CONT_ASSIGN98400
CONT_ASSIGN98600
CONT_ASSIGN98800
CONT_ASSIGN99000
CONT_ASSIGN99200
CONT_ASSIGN99400
CONT_ASSIGN99600
CONT_ASSIGN99800
CONT_ASSIGN100000
CONT_ASSIGN100200
CONT_ASSIGN100400
CONT_ASSIGN100600
CONT_ASSIGN100800
CONT_ASSIGN101000
CONT_ASSIGN262811100.00
CONT_ASSIGN302511100.00
CONT_ASSIGN302611100.00
CONT_ASSIGN302711100.00
CONT_ASSIGN302811100.00
CONT_ASSIGN302911100.00
CONT_ASSIGN303011100.00
CONT_ASSIGN303111100.00
CONT_ASSIGN303211100.00
CONT_ASSIGN303311100.00
CONT_ASSIGN303411100.00
CONT_ASSIGN303511100.00
CONT_ASSIGN303611100.00
CONT_ASSIGN303711100.00
CONT_ASSIGN303811100.00
CONT_ASSIGN303911100.00
CONT_ASSIGN304011100.00
CONT_ASSIGN304111100.00
CONT_ASSIGN304211100.00
CONT_ASSIGN304311100.00
CONT_ASSIGN304411100.00
CONT_ASSIGN304511100.00
CONT_ASSIGN304611100.00
CONT_ASSIGN304711100.00
CONT_ASSIGN304811100.00
CONT_ASSIGN304911100.00
CONT_ASSIGN305011100.00
CONT_ASSIGN305111100.00
CONT_ASSIGN305211100.00
CONT_ASSIGN305311100.00
CONT_ASSIGN305411100.00
CONT_ASSIGN305511100.00
CONT_ASSIGN305611100.00
CONT_ASSIGN305711100.00
CONT_ASSIGN305811100.00
CONT_ASSIGN305911100.00
CONT_ASSIGN306011100.00
CONT_ASSIGN306111100.00
CONT_ASSIGN306211100.00
CONT_ASSIGN306311100.00
CONT_ASSIGN306411100.00
CONT_ASSIGN306511100.00
CONT_ASSIGN306611100.00
CONT_ASSIGN306711100.00
CONT_ASSIGN306811100.00
CONT_ASSIGN306911100.00
CONT_ASSIGN307011100.00
CONT_ASSIGN307111100.00
CONT_ASSIGN307211100.00
CONT_ASSIGN307311100.00
CONT_ASSIGN307411100.00
CONT_ASSIGN307511100.00
CONT_ASSIGN307611100.00
CONT_ASSIGN307711100.00
CONT_ASSIGN307811100.00
CONT_ASSIGN307911100.00
CONT_ASSIGN308011100.00
CONT_ASSIGN308111100.00
CONT_ASSIGN308411100.00
CONT_ASSIGN308511100.00
CONT_ASSIGN308611100.00
CONT_ASSIGN308711100.00
CONT_ASSIGN308811100.00
CONT_ASSIGN308911100.00
CONT_ASSIGN309011100.00
CONT_ASSIGN309111100.00
CONT_ASSIGN309211100.00
CONT_ASSIGN309311100.00
CONT_ASSIGN309411100.00
CONT_ASSIGN309511100.00
CONT_ASSIGN309611100.00
CONT_ASSIGN309711100.00
CONT_ASSIGN309811100.00
CONT_ASSIGN309911100.00
CONT_ASSIGN310011100.00
CONT_ASSIGN310111100.00
CONT_ASSIGN310211100.00
CONT_ASSIGN310311100.00
CONT_ASSIGN310411100.00
CONT_ASSIGN310511100.00
CONT_ASSIGN310611100.00
CONT_ASSIGN310711100.00
CONT_ASSIGN310811100.00
CONT_ASSIGN310911100.00
CONT_ASSIGN311011100.00
CONT_ASSIGN311111100.00
CONT_ASSIGN311211100.00
CONT_ASSIGN311311100.00
CONT_ASSIGN311411100.00
CONT_ASSIGN311511100.00
CONT_ASSIGN311600
CONT_ASSIGN311700
CONT_ASSIGN311800
CONT_ASSIGN311900
CONT_ASSIGN312000
CONT_ASSIGN312100
CONT_ASSIGN312211100.00
CONT_ASSIGN3123100.00
CONT_ASSIGN3124100.00
CONT_ASSIGN3125100.00
CONT_ASSIGN312611100.00
CONT_ASSIGN312711100.00
CONT_ASSIGN312811100.00
CONT_ASSIGN312911100.00
CONT_ASSIGN313011100.00
CONT_ASSIGN313111100.00
CONT_ASSIGN313211100.00
CONT_ASSIGN313311100.00
CONT_ASSIGN313411100.00
CONT_ASSIGN313511100.00
CONT_ASSIGN3136100.00
CONT_ASSIGN313700
CONT_ASSIGN313800
CONT_ASSIGN313900
CONT_ASSIGN314000
CONT_ASSIGN314100
CONT_ASSIGN314200
CONT_ASSIGN314300
CONT_ASSIGN314400
CONT_ASSIGN314500
CONT_ASSIGN314611100.00
CONT_ASSIGN314711100.00
CONT_ASSIGN314811100.00
CONT_ASSIGN314911100.00
CONT_ASSIGN315011100.00
CONT_ASSIGN315111100.00
CONT_ASSIGN3152100.00
CONT_ASSIGN315311100.00
CONT_ASSIGN315411100.00
CONT_ASSIGN315511100.00
CONT_ASSIGN315611100.00
CONT_ASSIGN315711100.00
CONT_ASSIGN315811100.00
CONT_ASSIGN316111100.00
CONT_ASSIGN316211100.00
CONT_ASSIGN316311100.00
CONT_ASSIGN316411100.00
CONT_ASSIGN316511100.00
CONT_ASSIGN316611100.00
CONT_ASSIGN316711100.00
CONT_ASSIGN316811100.00
CONT_ASSIGN316911100.00
CONT_ASSIGN317011100.00
CONT_ASSIGN317111100.00
CONT_ASSIGN317211100.00
CONT_ASSIGN317311100.00
CONT_ASSIGN317411100.00
CONT_ASSIGN317511100.00
CONT_ASSIGN317611100.00
CONT_ASSIGN317711100.00
CONT_ASSIGN317811100.00
CONT_ASSIGN317911100.00
CONT_ASSIGN318011100.00
CONT_ASSIGN318111100.00
CONT_ASSIGN318211100.00
CONT_ASSIGN318311100.00
CONT_ASSIGN318411100.00
CONT_ASSIGN318511100.00
CONT_ASSIGN318611100.00
CONT_ASSIGN318711100.00
CONT_ASSIGN318811100.00
CONT_ASSIGN318911100.00
CONT_ASSIGN319011100.00
CONT_ASSIGN319111100.00
CONT_ASSIGN319211100.00
CONT_ASSIGN319311100.00
CONT_ASSIGN319411100.00
CONT_ASSIGN319511100.00
CONT_ASSIGN319611100.00
CONT_ASSIGN319711100.00
CONT_ASSIGN319811100.00
CONT_ASSIGN319911100.00
CONT_ASSIGN3200100.00
CONT_ASSIGN3201100.00
CONT_ASSIGN3202100.00
CONT_ASSIGN320300
CONT_ASSIGN320400
CONT_ASSIGN320500
CONT_ASSIGN320600
CONT_ASSIGN320700
CONT_ASSIGN320800
CONT_ASSIGN320900
CONT_ASSIGN321000
CONT_ASSIGN321111100.00
CONT_ASSIGN321211100.00
CONT_ASSIGN3213100.00
CONT_ASSIGN321400
CONT_ASSIGN321500
CONT_ASSIGN321600
CONT_ASSIGN321700
CONT_ASSIGN321800
CONT_ASSIGN321900
CONT_ASSIGN322000
CONT_ASSIGN322100
CONT_ASSIGN322200
CONT_ASSIGN322300
CONT_ASSIGN322400
CONT_ASSIGN322500
CONT_ASSIGN322600
CONT_ASSIGN322700
CONT_ASSIGN322800
CONT_ASSIGN322911100.00
CONT_ASSIGN323000
CONT_ASSIGN323100
CONT_ASSIGN323200
CONT_ASSIGN323300
CONT_ASSIGN323400
CONT_ASSIGN323500
CONT_ASSIGN323911100.00
CONT_ASSIGN324011100.00
CONT_ASSIGN324111100.00
CONT_ASSIGN324211100.00
CONT_ASSIGN324311100.00
CONT_ASSIGN324411100.00
CONT_ASSIGN324511100.00
CONT_ASSIGN324611100.00
CONT_ASSIGN324711100.00
CONT_ASSIGN324811100.00
CONT_ASSIGN324911100.00
CONT_ASSIGN325011100.00
CONT_ASSIGN325111100.00
CONT_ASSIGN325211100.00
CONT_ASSIGN325311100.00
CONT_ASSIGN325611100.00
CONT_ASSIGN325711100.00
CONT_ASSIGN325811100.00
CONT_ASSIGN325911100.00
CONT_ASSIGN326011100.00
CONT_ASSIGN326111100.00
CONT_ASSIGN326211100.00
CONT_ASSIGN326311100.00
CONT_ASSIGN326411100.00
CONT_ASSIGN326511100.00
CONT_ASSIGN326611100.00
CONT_ASSIGN326711100.00
CONT_ASSIGN327011100.00
CONT_ASSIGN327111100.00
CONT_ASSIGN327411100.00
CONT_ASSIGN327511100.00
CONT_ASSIGN327611100.00
CONT_ASSIGN3277100.00
CONT_ASSIGN3278100.00
CONT_ASSIGN3279100.00
CONT_ASSIGN328011100.00
CONT_ASSIGN328111100.00
CONT_ASSIGN328211100.00
CONT_ASSIGN328311100.00
CONT_ASSIGN328400
CONT_ASSIGN328500
CONT_ASSIGN328811100.00
CONT_ASSIGN328911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
747 1 1
748 1 1
749 1 1
750 0 1
751 0 1
752 0 1
753 0 1
754 0 1
767 1 1
768 0 1
769 0 1
770 0 1
771 0 1
772 0 1
773 0 1
774 0 1
788 1 1
790 1 1
792 1 1
794 1 1
796 1 1
798 1 1
800 1 1
804 1 1
813 1 1
814 1 1
818 1 1
842 1 1
843 1 1
845 1 1
846 1 1
848 1 1
849 1 1
851 1 1
852 1 1
854 1 1
855 1 1
857 1 1
858 1 1
860 1 1
861 1 1
863 1 1
864 1 1
866 1 1
867 1 1
869 1 1
870 1 1
872 0 1
873 1 1
875 0 1
876 1 1
878 1 1
879 1 1
881 1 1
882 1 1
884 1 1
885 1 1
887 1 1
888 1 1
890 1 1
891 1 1
893 1 1
894 1 1
896 1 1
897 1 1
899 1 1
900 1 1
902 1 1
903 1 1
905 1 1
906 1 1
908 1 1
909 1 1
911 1 1
912 1 1
918 unreachable
920 unreachable
922 unreachable
924 unreachable
926 unreachable
928 unreachable
930 unreachable
932 unreachable
934 unreachable
936 unreachable
938 unreachable
940 unreachable
942 unreachable
944 unreachable
946 unreachable
948 unreachable
950 unreachable
952 unreachable
954 unreachable
956 unreachable
958 unreachable
960 unreachable
962 unreachable
964 unreachable
966 unreachable
968 unreachable
970 unreachable
972 unreachable
974 unreachable
976 unreachable
978 unreachable
980 unreachable
982 unreachable
984 unreachable
986 unreachable
988 unreachable
990 unreachable
992 unreachable
994 unreachable
996 unreachable
998 unreachable
1000 unreachable
1002 unreachable
1004 unreachable
1006 unreachable
1008 unreachable
1010 unreachable
2628 1 1
3025 1 1
3026 1 1
3027 1 1
3028 1 1
3029 1 1
3030 1 1
3031 1 1
3032 1 1
3033 1 1
3034 1 1
3035 1 1
3036 1 1
3037 1 1
3038 1 1
3039 1 1
3040 1 1
3041 1 1
3042 1 1
3043 1 1
3044 1 1
3045 1 1
3046 1 1
3047 1 1
3048 1 1
3049 1 1
3050 1 1
3051 1 1
3052 1 1
3053 1 1
3054 1 1
3055 1 1
3056 1 1
3057 1 1
3058 1 1
3059 1 1
3060 1 1
3061 1 1
3062 1 1
3063 1 1
3064 1 1
3065 1 1
3066 1 1
3067 1 1
3068 1 1
3069 1 1
3070 1 1
3071 1 1
3072 1 1
3073 1 1
3074 1 1
3075 1 1
3076 1 1
3077 1 1
3078 1 1
3079 1 1
3080 1 1
3081 1 1
3084 1 1
3085 1 1
3086 1 1
3087 1 1
3088 1 1
3089 1 1
3090 1 1
3091 1 1
3092 1 1
3093 1 1
3094 1 1
3095 1 1
3096 1 1
3097 1 1
3098 1 1
3099 1 1
3100 1 1
3101 1 1
3102 1 1
3103 1 1
3104 1 1
3105 1 1
3106 1 1
3107 1 1
3108 1 1
3109 1 1
3110 1 1
3111 1 1
3112 1 1
3113 1 1
3114 1 1
3115 1 1
3116 unreachable
3117 unreachable
3118 unreachable
3119 unreachable
3120 unreachable
3121 unreachable
3122 1 1
3123 0 1
3124 0 1
3125 0 1
3126 1 1
3127 1 1
3128 1 1
3129 1 1
3130 1 1
3131 1 1
3132 1 1
3133 1 1
3134 1 1
3135 1 1
3136 0 1
3137 unreachable
3138 unreachable
3139 unreachable
3140 unreachable
3141 unreachable
3142 unreachable
3143 unreachable
3144 unreachable
3145 unreachable
3146 1 1
3147 1 1
3148 1 1
3149 1 1
3150 1 1
3151 1 1
3152 0 1
3153 1 1
3154 1 1
3155 1 1
3156 1 1
3157 1 1
3158 1 1
3161 1 1
3162 1 1
3163 1 1
3164 1 1
3165 1 1
3166 1 1
3167 1 1
3168 1 1
3169 1 1
3170 1 1
3171 1 1
3172 1 1
3173 1 1
3174 1 1
3175 1 1
3176 1 1
3177 1 1
3178 1 1
3179 1 1
3180 1 1
3181 1 1
3182 1 1
3183 1 1
3184 1 1
3185 1 1
3186 1 1
3187 1 1
3188 1 1
3189 1 1
3190 1 1
3191 1 1
3192 1 1
3193 1 1
3194 1 1
3195 1 1
3196 1 1
3197 1 1
3198 1 1
3199 1 1
3200 0 1
3201 0 1
3202 0 1
3203 unreachable
3204 unreachable
3205 unreachable
3206 unreachable
3207 unreachable
3208 unreachable
3209 unreachable
3210 unreachable
3211 1 1
3212 1 1
3213 0 1
3214 unreachable
3215 unreachable
3216 unreachable
3217 unreachable
3218 unreachable
3219 unreachable
3220 unreachable
3221 unreachable
3222 unreachable
3223 unreachable
3224 unreachable
3225 unreachable
3226 unreachable
3227 unreachable
3228 unreachable
3229 1 1
3230 unreachable
3231 unreachable
3232 unreachable
3233 unreachable
3234 unreachable
3235 unreachable
3239 1 1
3240 1 1
3241 1 1
3242 1 1
3243 1 1
3244 1 1
3245 1 1
3246 1 1
3247 1 1
3248 1 1
3249 1 1
3250 1 1
3251 1 1
3252 1 1
3253 1 1
3256 1 1
3257 1 1
3258 1 1
3259 1 1
3260 1 1
3261 1 1
3262 1 1
3263 1 1
3264 1 1
3265 1 1
3266 1 1
3267 1 1
3270 1 1
3271 1 1
3274 1 1
3275 1 1
3276 1 1
3277 0 1
3278 0 1
3279 0 1
3280 1 1
3281 1 1
3282 1 1
3283 1 1
3284 unreachable
3285 unreachable
3288 1 1
3289 1 1


Toggle Coverage for Instance : tb.dut.top_earlgrey
TotalCoveredPercent
Totals 526 486 92.40
Total Bits 1874 1753 93.54
Total Bits 0->1 937 878 93.70
Total Bits 1->0 937 875 93.38

Ports 526 486 92.40
Port Bits 1874 1753 93.54
Port Bits 0->1 937 878 93.70
Port Bits 1->0 937 875 93.38

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
mio_in_i[46:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
mio_out_o[46:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_oe_o[46:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_in_i[15:0] Yes Yes T30,T31,T1 Yes T30,T31,T1 INPUT
dio_out_o[11:0] Yes Yes *T30,*T31,T1 Yes T30,T31,T1 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_oe_o[15:0] Yes Yes T30,T31,T1 Yes T30,T31,T1 OUTPUT
mio_attr_o[0].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[0].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[1].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[2].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[3].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[4].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[5].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[6].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[7].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[8].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[9].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[10].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[11].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[12].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[13].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[14].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[15].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[16].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[17].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[18].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[19].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[20].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[21].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[22].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[23].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[24].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[25].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[26].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[27].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[28].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[29].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[30].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[31].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[32].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[33].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[34].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[35].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[36].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[37].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[38].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[39].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[40].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[41].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[42].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[43].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[44].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[45].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
mio_attr_o[46].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[0].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T1,*T2,*T7 Yes T1,T2,T7 OUTPUT
dio_attr_o[0].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[1].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[2].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[3].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[4].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[5].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[6].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[7].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[8].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[9].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[10].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[11].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[12].virt_od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[12].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[12].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].drive_strength[0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[13].virt_od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[13].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[13].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].drive_strength[0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[14].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].invert Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].pull_en Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].pull_select Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].drive_strength[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
dio_attr_o[15].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
adc_req_o.pd Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
adc_req_o.channel_sel[1:0] Yes Yes T85,T86,T87 Yes T85,T86,T87 OUTPUT
adc_rsp_i.data_valid Yes Yes T85,T86,T87 Yes T85,T86,T87 INPUT
adc_rsp_i.data[9:0] Yes Yes T85,T86,T88 Yes T85,T86,T88 INPUT
ast_edn_req_i.edn_req Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
ast_edn_rsp_o.edn_bus[31:0] Yes Yes T17,T18,T20 Yes T17,T18,T20 OUTPUT
ast_edn_rsp_o.edn_fips Yes Yes T89,T90,T91 Yes T92,T93,T94 OUTPUT
ast_edn_rsp_o.edn_ack Yes Yes T17,T18,T19 Yes T17,T18,T19 OUTPUT
ast_lc_dft_en_o[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
obs_ctrl_i.obmen[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obmsl[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obgsl[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
ram_1p_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en No No No INPUT
rom_cfg_i.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
clk_main_jitter_en_o[3:0] Yes Yes T31,T17,T95 Yes T31,T95,T96 OUTPUT
io_clk_byp_req_o[3:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
io_clk_byp_ack_i[3:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 INPUT
all_clk_byp_req_o[3:0] Yes Yes T47,T38,T97 Yes T47,T98,T99 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T47,T38,T97 Yes T47,T98,T99 INPUT
hi_speed_sel_o[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
div_step_down_req_i[3:0] Yes Yes T47,T38,T39 Yes T47,T38,T39 INPUT
calib_rdy_i[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T32,T33,T55 Yes T73,T100,T58 INPUT
flash_power_ready_h_i No No Yes T32,T33,T34 INPUT
flash_test_mode_a_io[1:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_test_voltage_h_io[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
es_rng_req_o.rng_enable Yes Yes T20,T21,T41 Yes T17,T18,T19 OUTPUT
es_rng_rsp_i.rng_b[3:0] Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
es_rng_rsp_i.rng_valid Yes Yes T17,T18,T19 Yes T17,T18,T19 INPUT
es_rng_fips_o Yes Yes T81,T101,T102 Yes T80,T81,T103 OUTPUT
ast_tl_req_o.d_ready Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_user.data_intg[6:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_user.instr_type[3:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_data[31:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_mask[3:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_source[5:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_size[1:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_opcode[2:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_req_o.a_valid Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
ast_tl_rsp_i.a_ready Yes Yes T32,T33,T55 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_error Yes Yes T33,T34,T56 Yes T33,T34,T56 INPUT
ast_tl_rsp_i.d_user.data_intg[6:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_data[31:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_sink Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_source[5:0] Yes Yes T33,T34,T56 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_size[1:0] Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_opcode[0] Yes Yes *T32,*T33,*T34 Yes T32,T33,T34 INPUT
ast_tl_rsp_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_valid Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
dft_strap_test_o.straps[1:0] No No Yes T42,T43,T44 OUTPUT
dft_strap_test_o.valid Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
usb_dp_pullup_en_o Yes Yes T51,T54,T52 Yes T19,T35,T36 OUTPUT
usb_dn_pullup_en_o Yes Yes T51,T52,T53 Yes T51,T52,T53 OUTPUT
pwrmgr_ast_req_o.usb_clk_en Yes Yes T104,T29,T105 Yes T32,T33,T55 OUTPUT
pwrmgr_ast_req_o.io_clk_en Yes Yes T104,T29,T105 Yes T32,T33,T55 OUTPUT
pwrmgr_ast_req_o.core_clk_en Yes Yes T104,T29,T105 Yes T32,T33,T55 OUTPUT
pwrmgr_ast_req_o.slow_clk_en No No No OUTPUT
pwrmgr_ast_req_o.pwr_clamp Yes Yes T32,T33,T55 Yes T104,T29,T105 OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env Yes Yes T32,T33,T55 Yes T104,T29,T105 OUTPUT
pwrmgr_ast_req_o.main_pd_n Yes Yes T73,T100,T58 Yes T73,T100,T58 OUTPUT
pwrmgr_ast_rsp_i.main_pok Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
pwrmgr_ast_rsp_i.usb_clk_val Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
pwrmgr_ast_rsp_i.io_clk_val Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
pwrmgr_ast_rsp_i.core_clk_val Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
pwrmgr_ast_rsp_i.slow_clk_val Yes Yes T47,T38,T106 Yes T32,T33,T34 INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0] No No No OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0] No No No INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1] Yes Yes T32,T33,T55 Yes T73,T100,T58 INPUT
otp_ext_voltage_h_io[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
por_n_i[1:0] Yes Yes T104,T29,T105 Yes T32,T33,T55 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n Yes Yes T107,T111,T112 Yes T107,T111,T112 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p Yes Yes T107,T111,T112 Yes T107,T111,T112 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p Yes Yes T107,T108,T109 Yes T107,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n Yes Yes T111,T112,T108 Yes T111,T112,T108 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p Yes Yes T111,T112,T108 Yes T111,T112,T108 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n Yes Yes T113,T108,T109 Yes T113,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p Yes Yes T113,T108,T109 Yes T113,T108,T109 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p Yes Yes T108,T109,T110 Yes T108,T109,T110 INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n Yes Yes T107,T111,T112 Yes T107,T111,T112 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p Yes Yes T107,T111,T112 Yes T107,T111,T112 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n Yes Yes T111,T112,T108 Yes T111,T112,T108 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p Yes Yes T111,T112,T108 Yes T111,T112,T108 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n Yes Yes T113,T108,T109 Yes T113,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p Yes Yes T113,T108,T109 Yes T113,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p Yes Yes T73,T107,T114 Yes T73,T107,T114 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n Yes Yes T107,T111,T112 Yes T107,T111,T112 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p Yes Yes T107,T111,T112 Yes T107,T111,T112 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p Yes Yes T107,T108,T109 Yes T107,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n Yes Yes T111,T112,T108 Yes T111,T112,T108 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p Yes Yes T111,T112,T108 Yes T111,T112,T108 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n Yes Yes T113,T108,T109 Yes T113,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p Yes Yes T113,T108,T109 Yes T113,T108,T109 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0] Yes Yes T106,T115,T116 Yes T32,T33,T34 INPUT
ast2pinmux_i[8:0] Unreachable Unreachable Unreachable INPUT
ast_init_done_i[3:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 INPUT
sck_monitor_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
usbdev_usb_rx_d_i Yes Yes T30,T31,T51 Yes T30,T31,T51 INPUT
usbdev_usb_tx_d_o Yes Yes T30,T31,T62 Yes T30,T31,T62 OUTPUT
usbdev_usb_tx_se0_o Yes Yes T117,T54,T52 Yes T117,T54,T52 OUTPUT
usbdev_usb_tx_use_d_se0_o Yes Yes T30,T31,T118 Yes T30,T31,T118 OUTPUT
usbdev_usb_rx_enable_o Yes Yes T30,T31,T12 Yes T30,T31,T51 OUTPUT
usbdev_usb_ref_val_o Yes Yes T54,T52,T119 Yes T19,T117,T54 OUTPUT
usbdev_usb_ref_pulse_o Yes Yes T19,T117,T54 Yes T19,T117,T54 OUTPUT
clk_main_i Yes Yes T32,T33,T55 Yes T32,T33,T55 INPUT
clk_io_i Yes Yes T32,T33,T55 Yes T32,T33,T55 INPUT
clk_usb_i Yes Yes T32,T33,T55 Yes T32,T33,T55 INPUT
clk_aon_i Yes Yes T32,T33,T34 Yes T32,T33,T34 INPUT
clks_ast_o.clk_usb_peri Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_peri Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div2_peri Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div4_peri Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div4_timers Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_secure Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div4_secure Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div2_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_usb_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_io_div4_infra Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_otbn Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_kmac Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_hmac Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_main_aes Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
clks_ast_o.clk_aon_timers Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
clks_ast_o.clk_aon_peri Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
clks_ast_o.clk_aon_secure Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
clks_ast_o.clk_io_div2_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
clks_ast_o.clk_usb_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
clks_ast_o.clk_io_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
clks_ast_o.clk_main_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
clks_ast_o.clk_aon_powerup Yes Yes T32,T33,T34 Yes T32,T33,T34 OUTPUT
clks_ast_o.clk_io_div4_powerup Yes Yes T32,T33,T55 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_i2c2_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c2_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_i2c1_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c1_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_i2c0_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c0_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_usb_aon_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_aon_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_usb_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_spi_host1_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host1_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_spi_host0_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host0_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_spi_device_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_device_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_sys_n[0] No No No OUTPUT
rsts_ast_o.rst_sys_n[1] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_io_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_aon_n[0] Yes Yes *T29,*T30,*T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_aon_n[1] No No No OUTPUT
rsts_ast_o.rst_lc_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0] Yes Yes T29,T30,T31 Yes T29,T30,T31 OUTPUT
rsts_ast_o.rst_por_usb_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_usb_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div4_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div2_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_io_div2_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_io_n[1] No No No OUTPUT
rsts_ast_o.rst_por_n[0] Yes Yes *T104,*T29,*T105 Yes T32,T33,T55 OUTPUT
rsts_ast_o.rst_por_n[1] No No No OUTPUT
rsts_ast_o.rst_por_aon_n[1:0] Yes Yes T104,T29,T105 Yes T32,T33,T55 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Assert Coverage for Instance : tb.dut.top_earlgrey
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
scanmodeKnown 346967378 346967378 0 0


scanmodeKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 346967378 346967378 0 0
T1 121364 121364 0 0
T2 175767 175767 0 0
T3 196136 196136 0 0
T7 137054 137054 0 0
T60 158417 158417 0 0
T61 175868 175868 0 0
T62 179351 179351 0 0
T63 148543 148543 0 0
T64 135119 135119 0 0
T65 150384 150384 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%