Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_cfg_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.77	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T104,T30,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T8
1	1	Covered	T30,T31,T8

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T8
1	-	Covered	T8,T10,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T8
1	1	Covered	T30,T31,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T8
0	0	1	Covered	T30,T31,T8
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T8
0	0	1	Covered	T30,T31,T8
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	97012	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	246	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	97012	0	0
T8	48217	756	0	0
T10	0	660	0	0
T11	0	407	0	0
T12	0	287	0	0
T14	0	773	0	0
T30	79081	693	0	0
T31	671510	6365	0	0
T46	164376	0	0	0
T77	16952	0	0	0
T78	23553	0	0	0
T79	85420	0	0	0
T80	132738	0	0	0
T81	193731	0	0	0
T82	166940	0	0	0
T302	0	1442	0	0
T340	0	436	0	0
T351	0	575	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	246	0	0
T8	48217	2	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	0	2	0	0
T30	79081	2	0	0
T31	671510	16	0	0
T46	164376	0	0	0
T77	16952	0	0	0
T78	23553	0	0	0
T79	85420	0	0	0
T80	132738	0	0	0
T81	193731	0	0	0
T82	166940	0	0	0
T302	0	4	0	0
T340	0	1	0	0
T351	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T30,T31,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T9
1	1	Covered	T30,T31,T9

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T9
1	-	Covered	T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T9
1	1	Covered	T30,T31,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T9
0	0	1	Covered	T30,T31,T9
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T9
0	0	1	Covered	T30,T31,T9
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	78854	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	201	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	78854	0	0
T9	39963	1069	0	0
T11	0	442	0	0
T12	0	304	0	0
T30	79081	667	0	0
T31	671510	5157	0	0
T144	69475	0	0	0
T239	41868	0	0	0
T240	31430	0	0	0
T241	64185	0	0	0
T242	105882	0	0	0
T243	165024	0	0	0
T244	18586	0	0	0
T302	0	3906	0	0
T340	0	456	0	0
T351	0	523	0	0
T352	0	683	0	0
T353	0	748	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	201	0	0
T9	39963	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	79081	2	0	0
T31	671510	13	0	0
T144	69475	0	0	0
T239	41868	0	0	0
T240	31430	0	0	0
T241	64185	0	0	0
T242	105882	0	0	0
T243	165024	0	0	0
T244	18586	0	0	0
T302	0	10	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T11
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	98459	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	251	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	98459	0	0
T11	246504	388	0	0
T12	459143	301	0	0
T30	79081	780	0	0
T31	671510	3384	0	0
T287	97020	0	0	0
T302	0	2856	0	0
T303	0	5813	0	0
T340	0	366	0	0
T351	0	582	0	0
T352	0	661	0	0
T353	0	699	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	251	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T30	79081	2	0	0
T31	671510	9	0	0
T287	97020	0	0	0
T302	0	8	0	0
T303	0	14	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T301,T30,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T11
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	89754	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	226	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	89754	0	0
T11	246504	449	0	0
T12	459143	343	0	0
T30	79081	680	0	0
T31	671510	3510	0	0
T287	97020	0	0	0
T302	0	7303	0	0
T303	0	6259	0	0
T340	0	418	0	0
T351	0	657	0	0
T352	0	742	0	0
T353	0	742	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	226	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T30	79081	2	0	0
T31	671510	9	0	0
T287	97020	0	0	0
T302	0	18	0	0
T303	0	15	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T348,T30,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T11
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	75110	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	193	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	75110	0	0
T11	246504	413	0	0
T12	459143	317	0	0
T30	79081	640	0	0
T31	671510	4118	0	0
T287	97020	0	0	0
T302	0	2154	0	0
T303	0	2365	0	0
T340	0	458	0	0
T351	0	520	0	0
T352	0	764	0	0
T353	0	658	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	193	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T30	79081	2	0	0
T31	671510	11	0	0
T287	97020	0	0	0
T302	0	6	0	0
T303	0	6	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T359,T30,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T11
1	-	Covered	T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	89261	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	226	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	89261	0	0
T11	246504	426	0	0
T12	459143	301	0	0
T15	0	839	0	0
T30	79081	728	0	0
T31	671510	3526	0	0
T287	97020	0	0	0
T302	0	4274	0	0
T340	0	471	0	0
T351	0	591	0	0
T352	0	754	0	0
T353	0	738	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	226	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T15	0	2	0	0
T30	79081	2	0	0
T31	671510	9	0	0
T287	97020	0	0	0
T302	0	11	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T11
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	82488	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	211	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	82488	0	0
T11	246504	450	0	0
T12	459143	288	0	0
T30	79081	722	0	0
T31	671510	3680	0	0
T287	97020	0	0	0
T302	0	886	0	0
T303	0	3805	0	0
T340	0	477	0	0
T351	0	546	0	0
T352	0	718	0	0
T353	0	739	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	211	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T30	79081	2	0	0
T31	671510	10	0	0
T287	97020	0	0	0
T302	0	3	0	0
T303	0	9	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T11
1	-	Covered	T16

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	84253	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	215	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	84253	0	0
T11	246504	371	0	0
T12	459143	281	0	0
T16	0	1005	0	0
T30	79081	754	0	0
T31	671510	2159	0	0
T287	97020	0	0	0
T302	0	4262	0	0
T340	0	454	0	0
T351	0	597	0	0
T352	0	732	0	0
T353	0	683	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	215	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T16	0	2	0	0
T30	79081	2	0	0
T31	671510	6	0	0
T287	97020	0	0	0
T302	0	11	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T105,T30,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T8
1	1	Covered	T30,T31,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T8
1	1	Covered	T30,T31,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T8
0	0	1	Covered	T30,T31,T8
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T8
0	0	1	Covered	T30,T31,T8
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	88956	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	226	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	88956	0	0
T8	48217	261	0	0
T10	0	286	0	0
T11	0	423	0	0
T12	0	344	0	0
T14	0	400	0	0
T30	79081	648	0	0
T31	671510	8397	0	0
T46	164376	0	0	0
T77	16952	0	0	0
T78	23553	0	0	0
T79	85420	0	0	0
T80	132738	0	0	0
T81	193731	0	0	0
T82	166940	0	0	0
T302	0	1724	0	0
T340	0	401	0	0
T351	0	545	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	226	0	0
T8	48217	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	0	1	0	0
T30	79081	2	0	0
T31	671510	20	0	0
T46	164376	0	0	0
T77	16952	0	0	0
T78	23553	0	0	0
T79	85420	0	0	0
T80	132738	0	0	0
T81	193731	0	0	0
T82	166940	0	0	0
T302	0	5	0	0
T340	0	1	0	0
T351	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T56,T30,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T9
1	1	Covered	T30,T31,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T9
1	1	Covered	T30,T31,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T9
0	0	1	Covered	T30,T31,T9
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T9
0	0	1	Covered	T30,T31,T9
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	82060	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	208	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	82060	0	0
T9	39963	410	0	0
T11	0	480	0	0
T12	0	286	0	0
T30	79081	731	0	0
T31	671510	5534	0	0
T144	69475	0	0	0
T239	41868	0	0	0
T240	31430	0	0	0
T241	64185	0	0	0
T242	105882	0	0	0
T243	165024	0	0	0
T244	18586	0	0	0
T302	0	2669	0	0
T340	0	443	0	0
T351	0	685	0	0
T352	0	728	0	0
T353	0	772	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	208	0	0
T9	39963	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T30	79081	2	0	0
T31	671510	14	0	0
T144	69475	0	0	0
T239	41868	0	0	0
T240	31430	0	0	0
T241	64185	0	0	0
T242	105882	0	0	0
T243	165024	0	0	0
T244	18586	0	0	0
T302	0	7	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	89400	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	226	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	89400	0	0
T11	246504	374	0	0
T12	459143	349	0	0
T30	79081	731	0	0
T31	671510	3504	0	0
T287	97020	0	0	0
T302	0	4584	0	0
T303	0	4070	0	0
T340	0	457	0	0
T351	0	551	0	0
T352	0	715	0	0
T353	0	749	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	226	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T30	79081	2	0	0
T31	671510	9	0	0
T287	97020	0	0	0
T302	0	12	0	0
T303	0	10	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	81831	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	209	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	81831	0	0
T11	246504	465	0	0
T12	459143	343	0	0
T30	79081	685	0	0
T31	671510	3800	0	0
T287	97020	0	0	0
T302	0	8165	0	0
T303	0	4084	0	0
T340	0	413	0	0
T351	0	614	0	0
T352	0	799	0	0
T353	0	697	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	209	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T30	79081	2	0	0
T31	671510	10	0	0
T287	97020	0	0	0
T302	0	20	0	0
T303	0	10	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	82902	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	213	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	82902	0	0
T11	246504	371	0	0
T12	459143	243	0	0
T30	79081	699	0	0
T31	671510	6043	0	0
T287	97020	0	0	0
T302	0	4260	0	0
T303	0	1076	0	0
T340	0	414	0	0
T351	0	581	0	0
T352	0	726	0	0
T353	0	711	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	213	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T30	79081	2	0	0
T31	671510	15	0	0
T287	97020	0	0	0
T302	0	11	0	0
T303	0	3	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T360,T30,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	90000	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	228	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	90000	0	0
T11	246504	437	0	0
T12	459143	340	0	0
T15	0	300	0	0
T30	79081	675	0	0
T31	671510	7872	0	0
T287	97020	0	0	0
T302	0	3422	0	0
T340	0	475	0	0
T351	0	612	0	0
T352	0	720	0	0
T353	0	799	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	228	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T15	0	1	0	0
T30	79081	2	0	0
T31	671510	19	0	0
T287	97020	0	0	0
T302	0	9	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	82162	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	208	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	82162	0	0
T11	246504	371	0	0
T12	459143	346	0	0
T30	79081	623	0	0
T31	671510	4201	0	0
T287	97020	0	0	0
T302	0	2190	0	0
T303	0	6315	0	0
T340	0	461	0	0
T351	0	664	0	0
T352	0	762	0	0
T353	0	745	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	208	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T30	79081	2	0	0
T31	671510	11	0	0
T287	97020	0	0	0
T302	0	6	0	0
T303	0	15	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T104,T30,T31

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T11
1	1	Covered	T30,T31,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T30,T31,T11
0	0	1	Covered	T30,T31,T11
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	105754124	86404	0	0
DstReqKnown_A	1322459	1118784	0	0
SrcAckBusyChk_A	105754124	220	0	0
SrcBusyKnown_A	105754124	104982702	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	86404	0	0
T11	246504	470	0	0
T12	459143	340	0	0
T16	0	342	0	0
T30	79081	789	0	0
T31	671510	7425	0	0
T287	97020	0	0	0
T302	0	6738	0	0
T340	0	422	0	0
T351	0	534	0	0
T352	0	758	0	0
T353	0	752	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322459	1118784	0	0
T1	345	122	0	0
T2	465	239	0	0
T3	403	177	0	0
T7	330	105	0	0
T29	630	405	0	0
T30	944	720	0	0
T31	6076	5793	0	0
T60	320	93	0	0
T61	393	168	0	0
T62	470	247	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	220	0	0
T11	246504	1	0	0
T12	459143	1	0	0
T16	0	1	0	0
T30	79081	2	0	0
T31	671510	18	0	0
T287	97020	0	0	0
T302	0	17	0	0
T340	0	1	0	0
T351	0	2	0	0
T352	0	2	0	0
T353	0	2	0	0
T354	211115	0	0	0
T355	54563	0	0	0
T356	117733	0	0	0
T357	156426	0	0	0
T358	51198	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105754124	104982702	0	0
T1	10016	9165	0	0
T2	9882	9318	0	0
T3	9870	9225	0	0
T7	10614	9435	0	0
T29	46767	45750	0	0
T30	79081	78346	0	0
T31	671510	670383	0	0
T60	10452	9202	0	0
T61	9847	9212	0	0
T62	9894	9408	0	0