Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	142689037	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	21110	21110	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	142689037	0	0
T1	265396	10443	0	0
T2	336042	10358	0	0
T3	251568	9453	0	0
T7	226214	4242	0	0
T23	841557	4503	0	0
T24	274812	19374	0	0
T25	1063887	58870	0	0
T26	710601	50690	0	0
T33	262468	439	0	0
T41	789954	58663	0	0
T47	884013	844693	0	0
T55	415702	22674	0	0
T56	328020	15245	0	0
T57	420986	23447	0	0
T58	291320	6722	0	0
T59	343912	9090	0	0
T60	278030	6627	0	0
T85	1469328	134690	0	0
T91	113052	8840	0	0
T158	623139	47132	0	0
T181	734188	62219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1326980	1325340	0	0
T2	1680210	1678530	0	0
T3	1257840	1256160	0	0
T7	1131070	1129430	0	0
T33	1574808	1574742	0	0
T34	1088028	1086612	0	0
T55	2078510	2076760	0	0
T56	1640100	1638420	0	0
T57	2104930	2103290	0	0
T58	1456600	1455000	0	0
T59	687824	687184	0	0
T60	556060	555388	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1326980	1325340	0	0
T2	1680210	1678530	0	0
T3	1257840	1256160	0	0
T7	1131070	1129430	0	0
T33	1574808	1574742	0	0
T34	1088028	1086612	0	0
T55	2078510	2076760	0	0
T56	1640100	1638420	0	0
T57	2104930	2103290	0	0
T58	1456600	1455000	0	0
T59	687824	687184	0	0
T60	556060	555388	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1326980	1325340	0	0
T2	1680210	1678530	0	0
T3	1257840	1256160	0	0
T7	1131070	1129430	0	0
T33	1574808	1574742	0	0
T34	1088028	1086612	0	0
T55	2078510	2076760	0	0
T56	1640100	1638420	0	0
T57	2104930	2103290	0	0
T58	1456600	1455000	0	0
T59	687824	687184	0	0
T60	556060	555388	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	21110	21110	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T7	4	4	0	0
T35	6	6	0	0
T36	6	6	0	0
T37	6	6	0	0
T50	6	6	0	0
T55	4	4	0	0
T56	4	4	0	0
T57	4	4	0	0
T58	4	4	0	0
T59	4	4	0	0
T60	4	4	0	0
T105	6	6	0	0
T169	6	6	0	0
T257	6	6	0	0
T258	6	6	0	0
T259	6	6	0	0
T312	6	6	0	0