Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391480632	45902962	0	0
DepthKnown_A	391480632	391377970	0	0
RvalidKnown_A	391480632	391377970	0	0
WreadyKnown_A	391480632	391377970	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	45902962	0	0
T23	280519	2965	0	0
T24	91604	10875	0	0
T25	354629	31345	0	0
T26	236867	29882	0	0
T41	263318	33972	0	0
T47	294671	436720	0	0
T85	489776	68887	0	0
T91	56526	5318	0	0
T158	207713	25489	0	0
T181	367094	33060	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391480632	35247931	0	0
DepthKnown_A	391480632	391377970	0	0
RvalidKnown_A	391480632	391377970	0	0
WreadyKnown_A	391480632	391377970	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	35247931	0	0
T23	280519	1530	0	0
T24	91604	8486	0	0
T25	354629	27472	0	0
T26	236867	20657	0	0
T41	263318	24542	0	0
T47	294671	407959	0	0
T85	489776	65781	0	0
T91	56526	3522	0	0
T158	207713	21621	0	0
T181	367094	29159	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391480632	33465779	0	0
DepthKnown_A	391480632	391377970	0	0
RvalidKnown_A	391480632	391377970	0	0
WreadyKnown_A	391480632	391377970	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	33465779	0	0
T1	132698	2177	0	0
T2	168021	6600	0	0
T3	125784	2196	0	0
T7	113107	2578	0	0
T55	207851	4785	0	0
T56	164010	3133	0	0
T57	210493	4828	0	0
T58	145660	3786	0	0
T59	171956	5204	0	0
T60	139015	3915	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391480632	27708677	0	0
DepthKnown_A	391480632	391377970	0	0
RvalidKnown_A	391480632	391377970	0	0
WreadyKnown_A	391480632	391377970	0	0
gen_passthru_fifo.paramCheckPass	965	965	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	27708677	0	0
T1	132698	8266	0	0
T2	168021	3758	0	0
T3	125784	7257	0	0
T7	113107	1664	0	0
T55	207851	17889	0	0
T56	164010	12112	0	0
T57	210493	18619	0	0
T58	145660	2936	0	0
T59	171956	3886	0	0
T60	139015	2712	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	391377970	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0
T59	171956	171796	0	0
T60	139015	138847	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478502334	89423	0	0
DepthKnown_A	478502334	478383471	0	0
RvalidKnown_A	478502334	478383471	0	0
WreadyKnown_A	478502334	478383471	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	89423	0	0
T23	280519	8	0	0
T24	91604	13	0	0
T25	354629	53	0	0
T26	236867	151	0	0
T33	262468	439	0	0
T34	181338	50	0	0
T41	263318	149	0	0
T47	294671	14	0	0
T85	489776	22	0	0
T158	207713	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T50	1	1	0	0
T105	1	1	0	0
T169	1	1	0	0
T257	1	1	0	0
T258	1	1	0	0
T259	1	1	0	0
T312	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478502334	92421	0	0
DepthKnown_A	478502334	478383471	0	0
RvalidKnown_A	478502334	478383471	0	0
WreadyKnown_A	478502334	478383471	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	92421	0	0
T23	280519	8	0	0
T24	91604	13	0	0
T25	354629	53	0	0
T26	236867	151	0	0
T33	262468	439	0	0
T34	181338	50	0	0
T41	263318	149	0	0
T47	294671	14	0	0
T85	489776	22	0	0
T158	207713	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T50	1	1	0	0
T105	1	1	0	0
T169	1	1	0	0
T257	1	1	0	0
T258	1	1	0	0
T259	1	1	0	0
T312	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478502334	49028	0	0
DepthKnown_A	478502334	478383471	0	0
RvalidKnown_A	478502334	478383471	0	0
WreadyKnown_A	478502334	478383471	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	49028	0	0
T23	280519	8	0	0
T24	91604	12	0	0
T25	354629	52	0	0
T26	236867	95	0	0
T41	263318	95	0	0
T47	294671	13	0	0
T85	489776	12	0	0
T91	56526	12	0	0
T158	207713	19	0	0
T181	367094	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T50	1	1	0	0
T105	1	1	0	0
T169	1	1	0	0
T257	1	1	0	0
T258	1	1	0	0
T259	1	1	0	0
T312	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478502334	49028	0	0
DepthKnown_A	478502334	478383471	0	0
RvalidKnown_A	478502334	478383471	0	0
WreadyKnown_A	478502334	478383471	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	49028	0	0
T23	280519	8	0	0
T24	91604	12	0	0
T25	354629	52	0	0
T26	236867	95	0	0
T41	263318	95	0	0
T47	294671	13	0	0
T85	489776	12	0	0
T91	56526	12	0	0
T158	207713	19	0	0
T181	367094	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T50	1	1	0	0
T105	1	1	0	0
T169	1	1	0	0
T257	1	1	0	0
T258	1	1	0	0
T259	1	1	0	0
T312	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478502334	40395	0	0
DepthKnown_A	478502334	478383471	0	0
RvalidKnown_A	478502334	478383471	0	0
WreadyKnown_A	478502334	478383471	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	40395	0	0
T24	91604	1	0	0
T25	354629	1	0	0
T26	236867	56	0	0
T33	262468	439	0	0
T34	181338	50	0	0
T41	263318	54	0	0
T47	294671	1	0	0
T85	489776	10	0	0
T91	56526	1	0	0
T158	207713	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T50	1	1	0	0
T105	1	1	0	0
T169	1	1	0	0
T257	1	1	0	0
T258	1	1	0	0
T259	1	1	0	0
T312	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478502334	43393	0	0
DepthKnown_A	478502334	478383471	0	0
RvalidKnown_A	478502334	478383471	0	0
WreadyKnown_A	478502334	478383471	0	0
gen_passthru_fifo.paramCheckPass	2875	2875	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	43393	0	0
T24	91604	1	0	0
T25	354629	1	0	0
T26	236867	56	0	0
T33	262468	439	0	0
T34	181338	50	0	0
T41	263318	54	0	0
T47	294671	1	0	0
T85	489776	10	0	0
T91	56526	1	0	0
T158	207713	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478502334	478383471	0	0
T1	132698	132534	0	0
T2	168021	167853	0	0
T3	125784	125616	0	0
T7	113107	112943	0	0
T33	262468	262457	0	0
T34	181338	181102	0	0
T55	207851	207676	0	0
T56	164010	163842	0	0
T57	210493	210329	0	0
T58	145660	145500	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2875	2875	0	0
T35	1	1	0	0
T36	1	1	0	0
T37	1	1	0	0
T50	1	1	0	0
T105	1	1	0	0
T169	1	1	0	0
T257	1	1	0	0
T258	1	1	0	0
T259	1	1	0	0
T312	1	1	0	0