Unified Coverage Report :: Module :: prim_edn_req

Module : prim_edn_req

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if	96.15	100.00	84.62			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.08	100.00	86.44			94.87	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.44	96.47	89.29	100.00		100.00	71.43	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_packer_fifo	68.93	100.00	90.00			85.71	0.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_edn_req

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
ALWAYS	143	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	163	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
139	1	1
143	1	1
144	1	1
146	1	1
149	1	1
163		unreachable
164		unreachable
165		unreachable
166		unreachable
167		unreachable
168		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_edn_req

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T24,T25

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T25

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T24,T25

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T23,T24,T25
1	1	Covered	T79,T109,T268

---

Branch Coverage for Module : prim_edn_req

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	139	3	3	100.00
IF	143	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((req_i && ack_o)) ? 
-2-:	139	(word_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T23,T24,T25
0	1	Covered	T23,T24,T25
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_edn_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOutputDiffFromPrev_A	390830296	38354234	0	0
DataOutputValid_A	391480632	3808	0	0

DataOutputDiffFromPrev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390830296	38354234	0	0
T26	236867	0	0	0
T41	263318	0	0	0
T42	219051	0	0	0
T47	294671	0	0	0
T77	0	450839	0	0
T79	0	74446	0	0
T85	489776	424867	0	0
T91	56526	0	0	0
T98	0	398371	0	0
T144	0	345230	0	0
T145	0	713004	0	0
T158	207713	0	0	0
T159	0	427397	0	0
T160	0	632783	0	0
T171	134301	0	0	0
T181	367094	0	0	0
T208	362696	0	0	0
T357	0	428479	0	0
T358	0	429714	0	0

DataOutputValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	3808	0	0
T23	280519	1	0	0
T24	91604	1	0	0
T25	354629	1	0	0
T26	236867	4	0	0
T41	263318	4	0	0
T47	294671	1	0	0
T85	489776	9	0	0
T91	56526	1	0	0
T158	207713	2	0	0
T181	367094	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
ALWAYS	143	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	163	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
139	1	1
143	1	1
144	1	1
146	1	1
149	1	1
163		unreachable
164		unreachable
165		unreachable
166		unreachable
167		unreachable
168		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T24,T25

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T25

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T24,T25

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T23,T24,T25
1	1	Covered	T79,T109,T268

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	139	3	3	100.00
IF	143	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((req_i && ack_o)) ? 
-2-:	139	(word_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T23,T24,T25
0	1	Covered	T23,T24,T25
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOutputDiffFromPrev_A	390830296	38354234	0	0
DataOutputValid_A	391480632	3808	0	0

DataOutputDiffFromPrev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390830296	38354234	0	0
T26	236867	0	0	0
T41	263318	0	0	0
T42	219051	0	0	0
T47	294671	0	0	0
T77	0	450839	0	0
T79	0	74446	0	0
T85	489776	424867	0	0
T91	56526	0	0	0
T98	0	398371	0	0
T144	0	345230	0	0
T145	0	713004	0	0
T158	207713	0	0	0
T159	0	427397	0	0
T160	0	632783	0	0
T171	134301	0	0	0
T181	367094	0	0	0
T208	362696	0	0	0
T357	0	428479	0	0
T358	0	429714	0	0

DataOutputValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	3808	0	0
T23	280519	1	0	0
T24	91604	1	0	0
T25	354629	1	0	0
T26	236867	4	0	0
T41	263318	4	0	0
T47	294671	1	0	0
T85	489776	9	0	0
T91	56526	1	0	0
T158	207713	2	0	0
T181	367094	1	0	0