CHIP Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	3.217m	2.055ms	3	3	100.00
		chip_sw_example_rom	2.007m	2.459ms	3	3	100.00
		chip_sw_example_manufacturer	4.412m	2.661ms	3	3	100.00
		chip_sw_example_concurrency	4.616m	2.168ms	3	3	100.00
		chip_sw_uart_smoketest_signed	38.466m	9.575ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset			0	5	0.00
V1	csr_rw	chip_csr_rw			0	20	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	5	0.00
V1	csr_aliasing	chip_csr_aliasing			0	5	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	5	0.00
		chip_csr_rw			0	20	0.00
V1	xbar_smoke	xbar_smoke			0	100	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.734m	4.263ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.734m	4.263ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.734m	4.263ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	20.215m	5.176ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	20.215m	5.176ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	18.387m	5.997ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	17.507m	5.598ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	20.495m	5.400ms	5	5	100.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.207h	23.552ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	51.353m	13.368ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	37.843m	14.182ms	5	5	100.00
V1		TOTAL			68	223	30.49
V2	chip_pin_mux	chip_padctrl_attributes	4.902m	5.242ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.902m	5.242ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.417m	3.271ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	8.670m	5.996ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.023m	3.481ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	30.541m	17.697ms	5	5	100.00
		chip_tap_straps_testunlock0	7.316m	7.984ms	5	5	100.00
		chip_tap_straps_rma	6.143m	3.997ms	5	5	100.00
		chip_tap_straps_prod	15.292m	8.543ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.580m	2.786ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.569m	9.129ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	15.690m	5.775ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	15.690m	5.775ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.309m	6.544ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	19.137m	5.118ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	22.290m	5.611ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.089h	18.891ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.632m	2.696ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.689m	4.993ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.894m	3.804ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.111m	5.083ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	7.116m	3.789ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.413m	5.640ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.812m	2.827ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.665m	3.135ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	17.202m	7.787ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	17.202m	7.787ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.938m	5.328ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.025m	3.336ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.938m	5.328ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	5.989m	2.398ms	3	3	100.00
		chip_sw_aes_smoketest	4.979m	2.548ms	3	3	100.00
		chip_sw_aon_timer_smoketest	7.343m	3.495ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.089m	2.654ms	3	3	100.00
		chip_sw_csrng_smoketest	4.350m	2.633ms	3	3	100.00
		chip_sw_entropy_src_smoketest	9.096m	3.564ms	3	3	100.00
		chip_sw_gpio_smoketest	5.449m	2.691ms	3	3	100.00
		chip_sw_hmac_smoketest	6.520m	3.406ms	3	3	100.00
		chip_sw_kmac_smoketest	6.406m	2.631ms	3	3	100.00
		chip_sw_otbn_smoketest	42.231m	10.132ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.795m	2.818ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.830m	5.303ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.299m	6.370ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.406m	2.956ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.788m	3.432ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.686m	2.901ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.108m	2.649ms	3	3	100.00
		chip_sw_uart_smoketest	6.377m	3.805ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.868m	5.836ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	38.466m	9.575ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.813h	78.963ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	41.617m	8.281ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	38.268m	15.767ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.587m	4.145ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	9.854m	9.932ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.138h	58.507ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.723h	64.715ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	5	0.00
		chip_same_csr_outstanding			0	20	0.00
		chip_csr_hw_reset			0	5	0.00
		chip_csr_rw			0	20	0.00
V2	xbar_base_random_sequence	xbar_random			0	100	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	100	0.00
		xbar_smoke_large_delays			0	100	0.00
		xbar_smoke_slow_rsp			0	100	0.00
		xbar_random_zero_delays			0	100	0.00
		xbar_random_large_delays			0	100	0.00
		xbar_random_slow_rsp			0	100	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_error_cases	xbar_error_random			0	100	0.00
		xbar_error_and_unmapped_addr			0	100	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	100	0.00
		xbar_access_same_device_slow_rsp			0	100	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	100	0.00
V2	xbar_stress_all	xbar_stress_all			0	100	0.00
		xbar_stress_all_with_error			0	100	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	100	0.00
		xbar_stress_all_with_reset_error			0	100	0.00
V2	rom_e2e_smoke	rom_e2e_smoke	41.617m	8.281ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	53.201m	24.813ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	35.431m	8.681ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	22.358m	6.816ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	37.504m	8.813ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	45.219m	8.831ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	38.421m	8.561ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.844m	8.689ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	31.837m	6.677ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	42.082m	8.768ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	35.581m	8.466ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	44.200m	8.784ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	31.599m	8.968ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	50.211m	10.215ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	56.018m	12.570ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	56.824m	12.616ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	51.501m	11.836ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	50.331m	11.140ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	45.553m	10.558ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	55.312m	12.480ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	54.348m	11.967ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	58.012m	11.661ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	53.460m	11.743ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	27.205m	7.031ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	33.231m	8.684ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	33.429m	8.830ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	34.769m	7.769ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	32.037m	8.228ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	30.403m	7.450ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	34.906m	8.346ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	34.590m	7.988ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	32.088m	8.399ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	37.885m	9.227ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.178m	7.066ms	3	3	100.00
		rom_e2e_asm_init_dev	41.103m	8.844ms	3	3	100.00
		rom_e2e_asm_init_prod	33.897m	8.409ms	3	3	100.00
		rom_e2e_asm_init_prod_end	42.286m	9.286ms	3	3	100.00
		rom_e2e_asm_init_rma	37.639m	9.418ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	46.894m	11.232ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.407m	3.065ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.632m	2.696ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.340m	2.570ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.823m	2.572ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.824m	5.331ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	8.612m	19.041ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	8.612m	19.041ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	9.154m	3.626ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.830m	5.303ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	9.154m	3.626ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.325m	8.574ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.325m	8.574ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.910m	7.336ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.591m	6.135ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.623m	6.492ms	3	3	100.00
		chip_sw_aes_idle	3.823m	2.572ms	3	3	100.00
		chip_sw_hmac_enc_idle	4.966m	2.191ms	3	3	100.00
		chip_sw_kmac_idle	5.150m	2.519ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	9.902m	4.725ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	11.132m	5.036ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.955m	4.917ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.436m	4.299ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	29.602m	13.071ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.732m	4.380ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.946m	4.825ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.283m	4.321ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.702m	5.247ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.776m	4.004ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.221m	4.878ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.309m	6.544ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	21.375m	14.115ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.283m	4.321ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.702m	5.247ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	19.137m	5.118ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	22.290m	5.611ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.089h	18.891ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.632m	2.696ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.689m	4.993ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.894m	3.804ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.111m	5.083ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	7.116m	3.789ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.413m	5.640ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.812m	2.827ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.847m	2.618ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	15.824m	6.025ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	20.689m	7.770ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.111h	25.505ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.383m	3.160ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.276m	2.671ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.877m	4.771ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.859m	2.414ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.803m	5.667ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	42.210m	24.455ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	55.734m	15.200ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.309m	6.544ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.510m	5.085ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.257m	4.052ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.794m	5.859ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	26.758m	7.166ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	32.750m	7.484ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.705m	4.950ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	16.148m	10.180ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.461m	2.613ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.102m	8.834ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	31.602m	22.405ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.650m	3.366ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	7.168m	3.793ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.316m	4.342ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	31.602m	22.405ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	31.602m	22.405ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.048h	20.792ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.048h	20.792ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	8.615m	4.975ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	8.612m	19.041ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.190h	18.734ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.374m	2.905ms	3	3	100.00
		chip_sw_edn_entropy_reqs	24.281m	4.941ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.374m	2.905ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	32.750m	7.484ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.019m	2.593ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	35.254m	23.564ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.582m	6.169ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	22.290m	5.611ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	19.087m	5.102ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	19.137m	5.118ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked			0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	35.254m	23.564ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.407m	3.245ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	10.972m	5.208ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.590m	5.082ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked			0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.590m	5.082ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.590m	5.082ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	8.590m	5.082ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.590m	5.082ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.794m	5.859ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	19.107m	5.585ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	11.365m	5.072ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	11.365m	5.072ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.328m	3.244ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.894m	3.804ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.966m	2.191ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.111m	5.787ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	18.278m	5.872ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	16.928m	4.739ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	16.205m	4.584ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	10.972m	5.208ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.111m	5.083ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	11.405m	4.899ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.824m	5.331ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.559h	18.512ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.232m	3.136ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.765m	2.914ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	7.116m	3.789ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	10.972m	5.208ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.581m	8.743ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.752m	2.467ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.187m	3.083ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.150m	2.519ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	9.200m	4.263ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	30.541m	17.697ms	5	5	100.00
		chip_tap_straps_rma	6.143m	3.997ms	5	5	100.00
		chip_tap_straps_prod	15.292m	8.543ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.055m	3.005ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.581m	8.743ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.581m	8.743ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.581m	8.743ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.751m	5.248ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	8.590m	5.082ms	3	3	100.00
		chip_sw_flash_rma_unlocked			0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.021m	7.766ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.307m	6.519ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	22.837m	7.200ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.023m	7.805ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.581m	8.743ms	15	15	100.00
		chip_sw_keymgr_key_derivation	10.972m	5.208ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	10.585m	8.257ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	15.116m	7.099ms	3	3	100.00
		chip_prim_tl_access			0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_lc	21.375m	14.115ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.732m	4.380ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.946m	4.825ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.283m	4.321ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.702m	5.247ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.776m	4.004ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.221m	4.878ms	3	3	100.00
		chip_tap_straps_dev	30.541m	17.697ms	5	5	100.00
		chip_tap_straps_rma	6.143m	3.997ms	5	5	100.00
		chip_tap_straps_prod	15.292m	8.543ms	5	5	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.518m	2.843ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.414m	2.801ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.292m	3.518ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.013m	3.961ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	44.045m	44.013ms	3	3	100.00
		chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev			0	3	0.00
		chip_sw_lc_walkthrough_prod			0	3	0.00
		chip_sw_lc_walkthrough_prodend	23.284m	16.561ms	3	3	100.00
		chip_sw_lc_walkthrough_rma			0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	44.045m	44.013ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	5.189m	6.458ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	6.588m	6.304ms	3	3	100.00
		rom_volatile_raw_unlock	39.005m	15.873ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.581m	8.743ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	35.254m	23.564ms	3	3	100.00
		chip_sw_otbn_mem_scramble	7.953m	3.399ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.972m	5.208ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.702m	5.355ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.399m	3.145ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	35.254m	23.564ms	3	3	100.00
		chip_sw_otbn_mem_scramble	7.953m	3.399ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.972m	5.208ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.702m	5.355ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.399m	3.145ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.581m	8.743ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.771m	5.065ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.055m	3.005ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.021m	7.766ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.307m	6.519ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	22.837m	7.200ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.023m	7.805ms	3	3	100.00
		chip_sw_lc_ctrl_transition	16.581m	8.743ms	15	15	100.00
		chip_prim_tl_access			0	3	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	3	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.702m	8.444ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	29.974m	21.338ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.187m	6.604ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	11.528m	6.715ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	13.405m	6.019ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	40.162m	23.973ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	26.555m	12.158ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	17.325m	8.574ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	28.684m	13.643ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.227m	3.578ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.702m	8.444ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.670m	4.502ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	57.334m	31.636ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.924m	6.155ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	7.413m	4.855ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.154m	22.109ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	20.102m	8.834ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	33.489m	12.271ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	44.976m	21.996ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	6.583m	3.080ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.794m	5.859ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.585m	8.257ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.585m	8.257ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	33.489m	12.271ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.154m	22.109ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	10.227m	3.578ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.830m	5.303ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.863m	4.502ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	9.358m	5.573ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.556m	4.840ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.623m	12.498ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.024m	2.296ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.794m	5.859ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	30.358m	6.670ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	23.210m	6.586ms	3	3	100.00
		chip_plic_all_irqs_10	12.889m	4.231ms	3	3	100.00
		chip_plic_all_irqs_20	15.180m	4.185ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.268m	2.680ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.295m	2.537ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	41.617m	8.281ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.675m	6.415ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	10.078m	4.606ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.542m	3.602ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.924m	3.207ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.702m	5.355ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	9.413m	5.640ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	14.331m	6.650ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	15.580m	6.231ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	15.116m	7.099ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.794m	5.859ms	97	100	97.00
		chip_sw_data_integrity_escalation	15.690m	5.775ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.135m	3.156ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	6.418m	3.059ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup			0	0	--
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	7.379m	4.132ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	0	--
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.607h	31.536ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	55.473m	12.911ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	4.995m	3.381ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	9.200m	4.263ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.794m	5.859ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.622m	3.179ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.623m	12.498ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.508m	5.354ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.938m	4.098ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	27.971m	13.002ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	26.758m	7.166ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	30.358m	6.670ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.476h	253.993ms	2	3	66.67
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	40.803m	18.767ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	26.153m	13.296ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.863m	4.502ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	7.629m	4.869ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.679m	5.798ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.143m	3.997ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	3	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			833	2655	31.37
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.148m	2.948ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.958m	5.016ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.650m	1.838ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.529m	2.169ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.633m	1.961ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.107h	47.497ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.127h	53.638ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.037h	47.496ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	43.191m	10.473ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	6.909m	3.430ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.727m	2.658ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	32.852m	6.251ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	28.443m	7.868ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.476m	3.479ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	19.820m	6.009ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.348m	3.257ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.997m	4.682ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.379m	5.649ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.028m	4.604ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	33.489m	12.271ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.794m	5.859ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	20.215m	5.176ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.210h	18.496ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.650m	1.838ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.529m	2.169ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.633m	1.961ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.896m	5.020ms	3	3	100.00
V3		TOTAL			32	48	66.67
	Unmapped tests	chip_sival_flash_info_access	11.117m	7.257ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	14.258m	6.069ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.098h	16.872ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	17.166m	5.201ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	13.745m	5.458ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.428m	5.181ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.352m	2.960ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	2.929m	2.828ms	2	3	66.67
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			959	2956	32.44

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	7	77.78
V1	19	19	13	68.42
V2	288	274	229	79.51
V2S	1	1	1	100.00
V3	91	22	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.20	90.98	80.72	90.17	--	92.41	78.28	84.62

Failure Buckets

launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.16112256725408330014133716636941762741334763002302538964642176491714163912381
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
  - 2.chip_csr_bit_bash.31182301425747688965041978854738960771517730493130651415792265478708986023193
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.5622138336596031027306235153252104462557596151802428645890449608274812232070
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
  - 2.chip_same_csr_outstanding.27513096741180339102840700348840393443772439048534478299691492048251200733987
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
  - ... and 1 more failures.
- Test chip_prim_tl_access has 2 failures.
  - 0.chip_prim_tl_access.54950090793533250437437956813014143104204694710173097498808253576696646364434
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
  - 2.chip_prim_tl_access.61198565068772992320374486243753538004053548349708863104972434960574223479935
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
- Test xbar_smoke has 8 failures.
  - 0.xbar_smoke.15925831726236430543102597220765678299387865056082882871797148833216470123945
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
  - 2.xbar_smoke.91324324237693918439233107733457121523745403199673855165322298701713153967198
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_large_delays has 8 failures.
  - 0.xbar_smoke_large_delays.9499913132513062700233647673185170336501053553436591677530740666889313695185
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
  - 2.xbar_smoke_large_delays.49574867902068306713479185915929636890430794385153271353123582654392959415440
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.28108313598853335334533939756574774062018168016309958642254273616018090436793
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
  - 2.chip_csr_aliasing.24090033288982884840695907454650291307761531347778942853501701309812979963089
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
  - ... and 1 more failures.
- Test chip_tl_errors has 8 failures.
  - 0.chip_tl_errors.24509576416758724239831091410242252147349736526737070294687808643436565697407
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
  - 2.chip_tl_errors.97027985974320016260341204636800671293032273004617033353150185149578412638927
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
  - ... and 6 more failures.
- Test chip_rv_dm_lc_disabled has 2 failures.
  - 0.chip_rv_dm_lc_disabled.106039650306889716752565040201306765160622456276550916107353345197639643521596
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
  - 2.chip_rv_dm_lc_disabled.17362386766493238453919803563176785653790753977051874812939356620080483144947
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
- Test xbar_smoke_zero_delays has 8 failures.
  - 0.xbar_smoke_zero_delays.5379377943552973552031079000570950115129790009092838777404421813449198930107
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
  - 2.xbar_smoke_zero_delays.92081381664349147095419431679430946580608109977752381284324275784512579205028
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
  - ... and 6 more failures.
- Test xbar_smoke_slow_rsp has 8 failures.
  - 0.xbar_smoke_slow_rsp.26810444017464152050936022840520601889645879690131198882528497481671117988993
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
  - 2.xbar_smoke_slow_rsp.80671062854161494108381336859924891319431731931690653261534273034545868944197
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
  - ... and 6 more failures.
- ... and 22 more tests.

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.82236396563808632181512881380325967255896724482202023133760270365799408920811
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:33:22) Loading:
  (15:33:23) Loading:
  (15:33:23) Loading: 4 packages loaded
  (15:33:23) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:33:23) WARNING: Target pattern parsing failed.
  (15:33:23) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:33:23) INFO: Elapsed time: 22.176s
  (15:33:23) INFO: 0 processes.
  (15:33:23) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.41072790473400687523149194759679089855826845299533849657741025984029889815495
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:48:51) Loading:
  (15:48:52) Loading:
  (15:48:52) Loading: 4 packages loaded
  (15:48:52) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:48:52) WARNING: Target pattern parsing failed.
  (15:48:52) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:48:52) INFO: Elapsed time: 20.616s
  (15:48:52) INFO: 0 processes.
  (15:48:52) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.58765441719759722313500954995736260383869508189728384680223345302645561649256
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:33:39) Loading:
  (15:33:39) Loading:
  (15:33:39) Loading: 4 packages loaded
  (15:33:39) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:33:39) WARNING: Target pattern parsing failed.
  (15:33:39) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:33:39) INFO: Elapsed time: 19.071s
  (15:33:39) INFO: 0 processes.
  (15:33:39) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.100419600554098390958071931399344689501105265601674060804289448869437242089356
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:49:35) Loading:
  (15:49:36) Loading:
  (15:49:36) Loading: 4 packages loaded
  (15:49:36) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:36) WARNING: Target pattern parsing failed.
  (15:49:36) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:36) INFO: Elapsed time: 17.988s
  (15:49:36) INFO: 0 processes.
  (15:49:36) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.50487105385139569877181886600740314905455045789446452267895478347093238715945
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:33:47) Loading:
  (15:33:48) Loading:
  (15:33:48) Loading: 4 packages loaded
  (15:33:48) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:33:48) WARNING: Target pattern parsing failed.
  (15:33:48) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:33:48) INFO: Elapsed time: 18.916s
  (15:33:48) INFO: 0 processes.
  (15:33:48) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.63852776382490228182555654540742411434502772005414874327369568822738737739805
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:49:41) Loading:
  (15:49:42) Loading:
  (15:49:42) Loading: 4 packages loaded
  (15:49:42) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:42) WARNING: Target pattern parsing failed.
  (15:49:42) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:42) INFO: Elapsed time: 19.334s
  (15:49:42) INFO: 0 processes.
  (15:49:42) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.101307885235291692985094555399525660003526189706611324443941188769210895252337
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:33:51) Loading:
  (15:33:51) Loading:
  (15:33:51) Loading: 4 packages loaded
  (15:33:51) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:33:51) WARNING: Target pattern parsing failed.
  (15:33:51) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:33:52) INFO: Elapsed time: 28.978s
  (15:33:52) INFO: 0 processes.
  (15:33:52) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.60780951100585639774829225671605868661523249389395239377149835412626609490729
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:49:39) Loading:
  (15:49:40) Loading:
  (15:49:40) Loading: 4 packages loaded
  (15:49:40) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:40) WARNING: Target pattern parsing failed.
  (15:49:40) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:40) INFO: Elapsed time: 19.195s
  (15:49:40) INFO: 0 processes.
  (15:49:40) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.57923567588382110254486292470102689934157226529245377962539443428517086472300
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:33:38) Loading:
  (15:33:39) Loading:
  (15:33:39) Loading: 4 packages loaded
  (15:33:39) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:33:39) WARNING: Target pattern parsing failed.
  (15:33:39) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:33:39) INFO: Elapsed time: 20.737s
  (15:33:39) INFO: 0 processes.
  (15:33:39) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.13626764615871010965543681967174385225075289903913320922972133255663701013026
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:49:42) Loading:
  (15:49:43) Loading:
  (15:49:43) Loading: 4 packages loaded
  (15:49:43) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:49:43) WARNING: Target pattern parsing failed.
  (15:49:43) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:49:43) INFO: Elapsed time: 23.138s
  (15:49:43) INFO: 0 processes.
  (15:49:43) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.99497925465111647486163256292865041566423439167100542985353339119779071407139
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  Job ID: smart:dd27f0d9-2048-4dac-b561-4c924415d585
```
  - 1.chip_sw_flash_rma_unlocked.80899892511502956248629750517340447597119188213967172516762554610464430851731
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  Job ID: smart:aed2b794-1377-40d9-ade7-7f887040b362
```
  - ... and 1 more failures.
- Test chip_sw_lc_walkthrough_dev has 3 failures.
  - 0.chip_sw_lc_walkthrough_dev.96093000969903056034239822755041745794584817941050667166437195377583519227193
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log
```
  Job ID: smart:23548314-6b83-4a07-854b-c770940ba561
```
  - 1.chip_sw_lc_walkthrough_dev.77429638468490156866410976636706666252278271254327933285804895426823000123664
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log
```
  Job ID: smart:6ff553ab-0874-4c66-9b7b-fb3a4c97c2b9
```
  - ... and 1 more failures.
- Test chip_sw_lc_walkthrough_prod has 3 failures.
  - 0.chip_sw_lc_walkthrough_prod.78951001776125695275481161352582880266141321103798471944399805725134752247097
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:3c17c78d-b77f-4baf-a57c-5d8ae939a7fc
```
  - 1.chip_sw_lc_walkthrough_prod.4858857427979117012218664491824614281248164615405357956024180401262247169714
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:dbe8ce0e-2e2c-45b6-b834-8b98cad9eaa2
```
  - ... and 1 more failures.
- Test chip_sw_lc_walkthrough_rma has 3 failures.
  - 0.chip_sw_lc_walkthrough_rma.73992962412085550807573983781746316839816827660229920913149147232653052588405
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log
```
  Job ID: smart:d89929fb-bc8f-479e-86ae-ef00ebd5bbd1
```
  - 1.chip_sw_lc_walkthrough_rma.86791968931372094300478932377528518806523527718642014863676298742544325147415
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log
```
  Job ID: smart:6e23a76d-db53-4e79-8721-d2c916460e04
```
  - ... and 1 more failures.
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.42186933332006485554592201321534909853145046326034502809388813433341734653417
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:28458ee8-fb9b-4aac-9c14-0397b9a2a7d7
```
  - 1.chip_sw_rv_timer_systick_test.30239571660256559525336743524326769069367577803293834974540722094787626608257
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:4b0894cc-7e77-4c03-b02c-bc87c5248fc9
```
  - ... and 1 more failures.
- ... and 5 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_pwrmgr_deep_sleep_por_reset has 2 failures.

0.chip_sw_pwrmgr_deep_sleep_por_reset.2025599724961026871537085777283915511649721311605309878509766802659697175007
Line 805, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17627.517662 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17627.517662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_pwrmgr_deep_sleep_por_reset.15993796776708353949089964506963750072057266139646958450032875940802043289991
Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 16543.657188 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16543.657188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_pwrmgr_normal_sleep_por_reset has 2 failures.

0.chip_sw_pwrmgr_normal_sleep_por_reset.96236705770108036927591036036563353892576152430108303523877557191642740658697
Line 793, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17604.514515 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17604.514515 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_pwrmgr_normal_sleep_por_reset.57269528692142457601423344535500038132595766236040369626190565654817033376017
Line 741, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 15928.128569 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15928.128569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.62435161465899739544722323189829403708050444520197086739518524527933468890925
    Line 822, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 1838.128000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1838.128000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.99828894235209837034445084913847896759890430055685330590763488622798072184247
    Line 813, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2169.265000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2169.265000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.24390311854499990321185761434507281899552337417067649322845671425655864686694
    Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 1961.043500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1961.043500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.64134498128643867260073496659816302432735662956670971086193732583785571835579
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 47496.922684 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 47496.922684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.90330712409548389054942737345023185145207607924428317120464632683108154927333
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 53637.651406 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 53637.651406 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.103834372491852767572062672007911837651330586547878157769862107690982022711254
    Line 844, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 47496.382141 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 47496.382141 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.83531498590349342996787638468484026474122483939097150400558704524722031698039
Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 10472.692932 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 10472.692932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_self_hash.103914911562486305263225214878497019992448792523901384208931694051869395540634
Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 9147.672240 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 9147.672240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 22.chip_sw_all_escalation_resets.33892052959775947202461379097356753931243013683649884045532180999788491889736
    Line 797, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2572.920130 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2572.920130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.chip_sw_all_escalation_resets.102330357686842889652500192460756681461303284768184292963045560015700537865151
    Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/45.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3053.126630 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3053.126630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 1.chip_sw_power_virus.96429752568046999181315301000692087052253939263031245937156234164410622294242
    Line 929, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5015.890051 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5015.890051 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_power_virus.61521302220684520221811281620665963438846155463996317713173108114468944854807
    Line 939, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5069.997119 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5069.997119 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 16.chip_sw_alert_handler_lpg_sleep_mode_alerts.61654723080116461618328655947662991214630265639140697963085007140089821379990
    Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4097.930586 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 4097.930586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 83.chip_sw_alert_handler_lpg_sleep_mode_alerts.7457710196824811197412372645115189443941968751919414619354187272064072887477
    Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3602.370920 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 3602.370920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))' has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.13026797108750155453970294241957295415662010189873681765050432129496423339125
    Line 734, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
      Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))'
  UVM_ERROR @ 2828.340540 us: (tlul_assert.sv:253) [ASSERT FAILED] respOpcode_M
  UVM_INFO @ 2828.340540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```