17d5a97c3b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.488m | 2.805ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.125m | 2.810ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 5.030m | 2.344ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.212m | 3.212ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 45.416m | 8.429ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 5.752m | 7.667ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 13.060m | 5.669ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.810h | 51.358ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.961h | 51.752ms | 3 | 5 | 60.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 7.474m | 7.335ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.961h | 51.752ms | 3 | 5 | 60.00 |
| chip_csr_rw | 13.060m | 5.669ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 11.550s | 244.459us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 10.204m | 4.547ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 10.204m | 4.547ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 10.204m | 4.547ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 18.337m | 5.456ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 18.337m | 5.456ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 19.845m | 5.926ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 19.839m | 6.103ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 20.940m | 5.739ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 1.618h | 22.746ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 1.667h | 23.082ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 44.218m | 14.061ms | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 220 | 223 | 98.65 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.450m | 5.286ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.450m | 5.286ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 7.425m | 3.081ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.475m | 5.075ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 8.356m | 4.436ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 33.001m | 14.535ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 16.859m | 8.970ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 16.192m | 7.350ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 15.256m | 7.545ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 6.663m | 3.007ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 27.590m | 8.798ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 16.144m | 6.728ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 16.144m | 6.728ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 18.619m | 7.375ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | ||
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 18.032m | 5.011ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.906m | 6.640ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.357h | 18.467ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.514m | 2.809ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 16.067m | 5.193ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 6.005m | 3.522ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 9.552m | 5.205ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.390m | 3.405ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.128m | 5.404ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.019m | 3.136ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.069m | 2.354ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 20.971m | 9.763ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 20.971m | 9.763ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.052m | 5.132ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.852m | 2.988ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.052m | 5.132ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.135m | 2.784ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.914m | 3.212ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.650m | 3.616ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.331m | 2.346ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 5.436m | 2.866ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.827m | 3.849ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 6.192m | 3.047ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.851m | 3.542ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 7.237m | 2.867ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 38.231m | 9.545ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 6.000m | 2.506ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 10.093m | 5.080ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 7.871m | 5.256ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 5.565m | 3.036ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 5.462m | 3.055ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.282m | 2.487ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 5.011m | 3.331ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 6.296m | 3.350ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 11.323m | 4.324ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 45.416m | 8.429ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 0 | 3 | 0.00 | ||
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 42.581m | 9.490ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 44.011m | 15.799ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 11.396m | 4.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 9.051m | 10.860ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 0 | 3 | 0.00 | ||
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 4.668h | 66.835ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 9.827m | 4.412ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 9.827m | 4.412ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.961h | 51.752ms | 3 | 5 | 60.00 |
| chip_same_csr_outstanding | 1.295h | 28.245ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.752m | 7.667ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 13.060m | 5.669ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.961h | 51.752ms | 3 | 5 | 60.00 |
| chip_same_csr_outstanding | 1.295h | 28.245ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 5.752m | 7.667ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 13.060m | 5.669ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.914m | 2.678ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.670s | 61.065us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.069m | 10.023ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.008m | 6.591ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.102m | 594.071us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 22.388m | 112.005ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 23.170m | 71.801ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.135m | 1.385ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.095m | 1.311ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.735m | 2.589ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.095m | 1.311ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.684m | 3.692ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 49.165m | 156.748ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.519m | 2.480ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 13.992m | 19.758ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 15.154m | 22.350ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 21.196m | 26.490ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 14.732m | 19.293ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 42.581m | 9.490ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.050h | 28.094ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 37.129m | 8.468ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 29.392m | 7.070ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 35.769m | 8.036ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 42.090m | 9.163ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 32.503m | 8.554ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 40.027m | 8.691ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 33.078m | 6.233ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 44.644m | 8.604ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 38.141m | 8.342ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 25.146m | 9.095ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 46.006m | 8.449ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 51.397m | 9.937ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 53.010m | 12.286ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.027h | 11.681ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 57.474m | 12.699ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.017h | 11.986ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 50.529m | 9.753ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.060h | 12.057ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.006h | 11.976ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.004h | 11.122ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.004h | 12.041ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 27.226m | 7.172ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 34.348m | 9.297ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 44.781m | 8.451ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 30.109m | 8.337ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 43.271m | 8.042ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 30.087m | 7.207ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 37.535m | 8.370ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 31.853m | 8.781ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 34.928m | 8.449ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 37.126m | 8.437ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_dev_otbn | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_dev_sw | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_prod_otbn | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_prod_sw | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_rma_otbn | 0 | 3 | 0.00 | ||||
| rom_e2e_sigverify_mod_exp_rma_sw | 0 | 3 | 0.00 | ||||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 31.814m | 7.131ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 42.279m | 9.220ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 46.514m | 9.151ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 44.477m | 9.266ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 40.645m | 8.323ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 0 | 3 | 0.00 | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 0 | 3 | 0.00 | ||||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0 | 3 | 0.00 | ||||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 53.045m | 10.261ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.614m | 3.069ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 4.514m | 2.809ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.077m | 3.260ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.902m | 3.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 12.057m | 4.706ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.998m | 18.803ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.998m | 18.803ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 9.522m | 4.703ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 10.093m | 5.080ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 9.522m | 4.703ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 18.474m | 9.222ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 18.474m | 9.222ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 9.169m | 6.301ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.102m | 5.692ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 19.163m | 5.959ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.902m | 3.376ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.397m | 3.129ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.574m | 2.964ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 9.562m | 5.745ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 10.271m | 4.497ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 10.060m | 5.318ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 9.323m | 3.948ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 28.052m | 13.660ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 14.419m | 4.371ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.527m | 5.462ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.798m | 3.861ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.222m | 4.358ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.991m | 3.822ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.264m | 4.450ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 18.619m | 7.375ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 9.175m | 6.940ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.798m | 3.861ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.222m | 4.358ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 18.032m | 5.011ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.906m | 6.640ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.357h | 18.467ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.514m | 2.809ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 16.067m | 5.193ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 6.005m | 3.522ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 9.552m | 5.205ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.390m | 3.405ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.128m | 5.404ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.019m | 3.136ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.218m | 2.354ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 19.154m | 6.427ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 22.519m | 7.713ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.620h | 24.952ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 5.750m | 2.917ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.213m | 3.095ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 7.669m | 3.345ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.333m | 3.184ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 12.604m | 5.036ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 43.985m | 23.218ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 1.284h | 20.143ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 18.619m | 7.375ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.829m | 4.545ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.584m | 3.226ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 15.331m | 5.260ms | 99 | 100 | 99.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 28.458m | 7.621ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 32.738m | 7.772ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 10.626m | 4.635ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 14.599m | 6.450ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.977m | 2.207ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 23.850m | 8.096ms | 2 | 3 | 66.67 |
| chip_sw_sysrst_ctrl_reset | 34.489m | 23.396ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 7.150m | 3.608ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 5.859m | 3.896ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 10.619m | 4.443ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 34.489m | 23.396ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 34.489m | 23.396ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.239h | 20.400ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.239h | 20.400ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 9.890m | 5.147ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.998m | 18.803ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.084h | 22.182ms | 3 | 3 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.021m | 2.903ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 20.871m | 5.556ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.021m | 2.903ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 32.738m | 7.772ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 11.646m | 4.292ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 5.779m | 2.846ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 47.445m | 22.842ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.780m | 5.722ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.906m | 6.640ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 17.197m | 5.123ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 18.032m | 5.011ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.592h | 45.138ms | 1 | 3 | 33.33 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 47.445m | 22.842ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.408m | 4.089ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 10.019m | 3.557ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.518m | 4.267ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.592h | 45.138ms | 1 | 3 | 33.33 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.518m | 4.267ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.518m | 4.267ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.518m | 4.267ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.518m | 4.267ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 15.331m | 5.260ms | 99 | 100 | 99.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 6.406m | 11.044ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 19.813m | 5.948ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 13.125m | 5.064ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 6.496m | 3.011ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 6.005m | 3.522ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.397m | 3.129ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 16.119m | 5.623ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 17.269m | 4.645ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 19.258m | 6.119ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 12.077m | 4.323ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 10.019m | 3.557ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 9.552m | 5.205ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 11.846m | 4.422ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 12.057m | 4.706ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.894h | 19.079ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.513m | 3.219ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.431m | 2.950ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.390m | 3.405ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 10.019m | 3.557ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 24.963m | 9.758ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.819m | 3.351ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 6.264m | 3.544ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.574m | 2.964ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.585m | 4.901ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 33.001m | 14.535ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 16.192m | 7.350ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 15.256m | 7.545ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 3.814m | 3.594ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 24.963m | 9.758ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 24.963m | 9.758ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 24.963m | 9.758ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 10.091m | 3.508ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.518m | 4.267ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.592h | 45.138ms | 1 | 3 | 33.33 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.299m | 4.398ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 25.414m | 7.311ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 18.505m | 6.560ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.021m | 8.930ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 24.963m | 9.758ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 10.019m | 3.557ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 9.923m | 9.329ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 18.767m | 8.876ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 6.406m | 11.044ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 9.175m | 6.940ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 14.419m | 4.371ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.527m | 5.462ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.798m | 3.861ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.222m | 4.358ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.991m | 3.822ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.264m | 4.450ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 33.001m | 14.535ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 16.192m | 7.350ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 15.256m | 7.545ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 6.974m | 10.364ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 2.739m | 2.417ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.141m | 2.542ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.984m | 3.987ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.273m | 3.633ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 52.054m | 25.192ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 6.974m | 10.364ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 0 | 3 | 0.00 | ||
| chip_sw_lc_walkthrough_prod | 0 | 3 | 0.00 | ||||
| chip_sw_lc_walkthrough_prodend | 19.639m | 9.358ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 0 | 3 | 0.00 | ||||
| chip_sw_lc_walkthrough_testunlocks | 52.054m | 25.192ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 6.829m | 3.979ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 6.320m | 5.449ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 37.341m | 8.902ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 24.963m | 9.758ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 47.445m | 22.842ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.618m | 3.677ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 10.019m | 3.557ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.657m | 4.019ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.249m | 2.656ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 47.445m | 22.842ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.618m | 3.677ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 10.019m | 3.557ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 12.657m | 4.019ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.249m | 2.656ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 24.963m | 9.758ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 11.136m | 5.712ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 3.814m | 3.594ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.299m | 4.398ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 25.414m | 7.311ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 18.505m | 6.560ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.021m | 8.930ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 24.963m | 9.758ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 6.406m | 11.044ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 6.406m | 11.044ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 9.265m | 9.042ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 13.236m | 8.308ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.463m | 6.235ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 12.527m | 6.514ms | 1 | 3 | 33.33 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 15.618m | 7.482ms | 2 | 3 | 66.67 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 15.496m | 10.491ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 28.515m | 12.993ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 18.474m | 9.222ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 26.257m | 13.696ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 13.608m | 5.684ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 9.265m | 9.042ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.610m | 4.140ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1.218h | 39.170ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.616m | 5.596ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 9.563m | 6.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 50.946m | 27.189ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 23.850m | 8.096ms | 2 | 3 | 66.67 |
| chip_sw_pwrmgr_all_reset_reqs | 35.326m | 10.771ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 57.202m | 21.618ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.307m | 3.511ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 15.331m | 5.260ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 9.923m | 9.329ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 9.923m | 9.329ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 35.326m | 10.771ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 50.946m | 27.189ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 13.608m | 5.684ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 10.093m | 5.080ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 7.142m | 4.686ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 12.715m | 5.845ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 9.794m | 4.928ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 34.809m | 15.070ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.600m | 3.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 15.331m | 5.260ms | 99 | 100 | 99.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 33.729m | 7.808ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 20.764m | 5.845ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 8.971m | 4.400ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 15.956m | 4.453ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.650m | 2.486ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.982m | 3.179ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 0 | 3 | 0.00 | ||
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 15.273m | 6.406ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.300m | 3.735ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 7.975m | 3.607ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.220m | 2.838ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 12.657m | 4.019ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.128m | 5.404ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 10.774m | 7.446ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 12.933m | 6.147ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 18.767m | 8.876ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 15.331m | 5.260ms | 99 | 100 | 99.00 |
| chip_sw_data_integrity_escalation | 16.144m | 6.728ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 3.169m | 2.742ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 5.243m | 2.877ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.601m | 4.331ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.589h | 30.918ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 58.400m | 11.984ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.168m | 3.082ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.585m | 4.901ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 15.331m | 5.260ms | 99 | 100 | 99.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.335m | 4.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 34.809m | 15.070ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 9.589m | 4.022ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.333m | 3.353ms | 89 | 90 | 98.89 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 31.921m | 12.462ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 28.458m | 7.621ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 33.729m | 7.808ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.126h | 254.572ms | 1 | 3 | 33.33 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 39.957m | 21.629ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 26.004m | 13.059ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 7.142m | 4.686ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 10.115m | 5.684ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 9.551m | 5.088ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 16.192m | 7.350ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 6.974m | 10.364ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2582 | 2658 | 97.14 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.825m | 3.391ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 3 | 0.00 | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 1.629m | 2.175ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 2.005m | 2.279ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 1.712m | 2.057ms | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.698h | 50.474ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_inject_dev | 55.773m | 41.145ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_rma | 59.248m | 40.984ms | 0 | 1 | 0.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 52.600m | 9.759ms | 0 | 3 | 0.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.294m | 3.847ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 10.060m | 2.845ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 34.499m | 6.616ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 48.485m | 10.500ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 11.012m | 3.361ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 21.542m | 6.165ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.959m | 3.439ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 19.689m | 12.291ms | 0 | 1 | 0.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 7.841m | 5.790ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 10.946m | 5.496ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 35.326m | 10.771ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 15.331m | 5.260ms | 99 | 100 | 99.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | chip_sw_spi_host_pass_through | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 18.337m | 5.456ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.616h | 18.886ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 1.629m | 2.175ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 2.005m | 2.279ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 1.712m | 2.057ms | 0 | 1 | 0.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 11.323m | 6.209ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 31 | 48 | 64.58 | |||
| Unmapped tests | chip_sival_flash_info_access | 9.351m | 3.965ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 12.261m | 6.182ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.339h | 16.928ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 20.149m | 6.018ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 15.300m | 4.947ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.528m | 2.940ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.397m | 2.639ms | 3 | 3 | 100.00 | ||
| TOTAL | 2857 | 2953 | 96.75 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 7 | 7 | 7 | 100.00 |
| V1 | 19 | 19 | 17 | 89.47 |
| V2 | 289 | 275 | 246 | 85.12 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 91 | 22 | 11 | 12.09 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.41 | 95.44 | 94.71 | 95.74 | -- | 95.42 | 97.57 | 99.57 |
Exit reason: Error: User command failed Job returned non-zero exit code has 39 failures:
0.rom_e2e_keymgr_init_rom_ext_meas.24214862598813210398346783828719201145025537148198425566227325123095255500402
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log
(00:11:43) Loading:
(00:11:44) Loading:
(00:11:44) Loading: 4 packages loaded
(00:11:44) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(00:11:44) WARNING: Target pattern parsing failed.
(00:11:44) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(00:11:44) INFO: Elapsed time: 21.936s
(00:11:44) INFO: 0 processes.
(00:11:44) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.rom_e2e_keymgr_init_rom_ext_meas.55822422751394123690481715810053099771962981441678245785496232603127632805903
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log
(03:06:00) Loading:
(03:06:01) Loading:
(03:06:01) Loading: 4 packages loaded
(03:06:01) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(03:06:01) WARNING: Target pattern parsing failed.
(03:06:01) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(03:06:01) INFO: Elapsed time: 18.315s
(03:06:01) INFO: 0 processes.
(03:06:01) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.rom_e2e_keymgr_init_rom_ext_no_meas.64811643271675927627537330176674677519875389883483557210904035170487790215808
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log
(00:11:37) Loading:
(00:11:38) Loading:
(00:11:38) Loading: 4 packages loaded
(00:11:38) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(00:11:38) WARNING: Target pattern parsing failed.
(00:11:38) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(00:11:38) INFO: Elapsed time: 20.449s
(00:11:38) INFO: 0 processes.
(00:11:38) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.rom_e2e_keymgr_init_rom_ext_no_meas.64952676651152786473341255012479797504232190009472482882836313967220255076160
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log
(00:36:59) Loading:
(00:37:00) Loading:
(00:37:00) Loading: 4 packages loaded
(00:37:00) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(00:37:00) WARNING: Target pattern parsing failed.
(00:37:00) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(00:37:00) INFO: Elapsed time: 26.291s
(00:37:00) INFO: 0 processes.
(00:37:00) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.rom_e2e_keymgr_init_rom_ext_invalid_meas.21160057963659499235643846904505374248532272161761799362575201725946635112745
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log
(00:11:39) Loading:
(00:11:40) Loading:
(00:11:40) Loading: 4 packages loaded
(00:11:40) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(00:11:40) WARNING: Target pattern parsing failed.
(00:11:40) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(00:11:40) INFO: Elapsed time: 19.319s
(00:11:40) INFO: 0 processes.
(00:11:40) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.rom_e2e_keymgr_init_rom_ext_invalid_meas.74550681548935183662410103634236346060472058023342400603547234038195488141186
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log
(02:18:32) Loading:
(02:18:33) Loading:
(02:18:33) Loading: 4 packages loaded
(02:18:33) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(02:18:33) WARNING: Target pattern parsing failed.
(02:18:33) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
(02:18:33) INFO: Elapsed time: 23.929s
(02:18:33) INFO: 0 processes.
(02:18:33) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.48429836217418012261842207802508358268239580091659783650346481781713962160536
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log
(00:11:39) Loading:
(00:11:40) Loading:
(00:11:40) Loading: 4 packages loaded
(00:11:40) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
(00:11:40) WARNING: Target pattern parsing failed.
(00:11:40) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
(00:11:40) INFO: Elapsed time: 19.135s
(00:11:40) INFO: 0 processes.
(00:11:40) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.25415248165720738732965146672024543478237415844831084006449577545019854357501
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log
(00:37:12) Loading:
(00:37:13) Loading:
(00:37:13) Loading: 4 packages loaded
(00:37:13) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
(00:37:13) WARNING: Target pattern parsing failed.
(00:37:13) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
(00:37:13) INFO: Elapsed time: 18.434s
(00:37:13) INFO: 0 processes.
(00:37:13) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.97907120808913555683893542513125470248823274600570059637944104846838425702715
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log
(00:11:42) Loading:
(00:11:43) Loading:
(00:11:43) Loading: 4 packages loaded
(00:11:43) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
(00:11:43) WARNING: Target pattern parsing failed.
(00:11:43) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
(00:11:43) INFO: Elapsed time: 20.654s
(00:11:43) INFO: 0 processes.
(00:11:43) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.68038928201927700686365368013675014961485971399380615062235490883348764603147
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log
(06:47:27) Loading:
(06:47:27) Loading:
(06:47:27) Loading: 4 packages loaded
(06:47:27) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
(06:47:27) WARNING: Target pattern parsing failed.
(06:47:27) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
(06:47:27) INFO: Elapsed time: 17.304s
(06:47:27) INFO: 0 processes.
(06:47:27) FAILED: Build did NOT complete successfully (5 packages loaded)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
... and 1 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 31 failures:
0.chip_sw_uart_tx_rx_bootstrap.85688561763953197420978179051874001459702617861147744902778792848307559758993
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
Job ID: smart:4852569a-3bc2-4bc8-ad1a-788ad8731b79
1.chip_sw_uart_tx_rx_bootstrap.100209664447888536218950975140347026961554143152486737939849873504053208565757
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
Job ID: smart:e0204af2-4ed2-49cc-9bd4-4fc02088bd81
... and 1 more failures.
0.chip_sw_exit_test_unlocked_bootstrap.43642528939990447988152492797217294201637942132208778518058826417196413271753
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job ID: smart:2aea9bfb-cea4-4645-80cc-bcee6698a9a5
1.chip_sw_exit_test_unlocked_bootstrap.104856203735117582233119917240609100543179725728930717722735613103242984791890
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job ID: smart:70ec9c06-a41b-43be-9d3a-9937c7acf682
... and 1 more failures.
0.chip_sw_lc_walkthrough_dev.28492957615226390226956849548148655602885820330470710098831030019363986909932
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log
Job ID: smart:c709f6b0-a0bf-464a-a686-7dc90a4e9114
1.chip_sw_lc_walkthrough_dev.96255814031596555291268277073060633065565234081408612782051279667653357879441
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log
Job ID: smart:d0246ba9-703e-48d7-9d01-e62af146639f
... and 1 more failures.
0.chip_sw_lc_walkthrough_prod.111137201526251845206308014022361711036569367537731959767224663707383038451150
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log
Job ID: smart:0e07bf9e-a52d-4fd5-a55f-f70971629d3e
1.chip_sw_lc_walkthrough_prod.93834502007131797151506888196338776758072688691300736956966466675556745485244
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log
Job ID: smart:e836b1ea-2b59-4ffc-a0e4-2a6c7fb91226
... and 1 more failures.
0.chip_sw_lc_walkthrough_rma.1604953612495318811489205185282157594185991899658492995221624974946748274175
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log
Job ID: smart:3ba40d83-7271-47c1-ad26-9d0f99ab29f2
1.chip_sw_lc_walkthrough_rma.77196231696239014553276828877991750973814603240235768794011801854073347314327
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log
Job ID: smart:5a5466cb-e679-41b5-89e2-ded7b3ca45b0
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:
Test chip_sw_pwrmgr_deep_sleep_por_reset has 2 failures.
0.chip_sw_pwrmgr_deep_sleep_por_reset.22088995547012531928740056659801597669475668854925131475793961505246912590636
Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
UVM_ERROR @ 16960.528527 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
UVM_INFO @ 16960.528527 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_deep_sleep_por_reset.41781888572535391251363199906534956191816873355819026930047264302361465143278
Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
UVM_ERROR @ 17830.696596 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
UVM_INFO @ 17830.696596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_pwrmgr_normal_sleep_por_reset has 1 failures.
2.chip_sw_pwrmgr_normal_sleep_por_reset.106007426291247678163755069609115677239745851463945580880025987828397978480800
Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log
UVM_ERROR @ 16981.623758 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
UVM_INFO @ 16981.623758 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.111988563894801597090704420356822808647248793283012355407783379011964005073750
Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
UVM_ERROR @ 6435.641426 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
UVM_INFO @ 6435.641426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.66978270691341205910588768649246936898044026717396279453285124593019668000574
Line 835, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
UVM_ERROR @ 6048.217826 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
UVM_INFO @ 6048.217826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.113778790656964537887261788842604310271129903981425948080228849080902362215285
Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log
UVM_ERROR @ 8913.036536 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
UVM_INFO @ 8913.036536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.115293047223775516906432728174236288762425955368229245469374849077206180923971
Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log
UVM_ERROR @ 10491.434872 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
UVM_INFO @ 10491.434872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
0.chip_sw_pwrmgr_random_sleep_all_wake_ups.18440532995642815621892227949566156446338598468669012544754549211840568057911
Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log
UVM_ERROR @ 9333.861514 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
UVM_INFO @ 9333.861514 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_random_sleep_all_wake_ups.96159934069056039498224069655354345768101790821281443898671452658306908835082
Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log
UVM_ERROR @ 8307.763240 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
UVM_INFO @ 8307.763240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_debug_test_unlocked0.112137631444962642561021117874698853518551273272765840599656407167464519365266
Line 708, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
UVM_FATAL @ 2174.540000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
UVM_INFO @ 2174.540000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_dev has 1 failures.
0.rom_e2e_jtag_debug_dev.107528361309191785010143041651849993132823880216909888982151535678619225704162
Line 724, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
UVM_FATAL @ 2279.082000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
UVM_INFO @ 2279.082000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_rma has 1 failures.
0.rom_e2e_jtag_debug_rma.59317819957098584660226925720172910081397985801899597374183080653619643824268
Line 698, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
UVM_FATAL @ 2056.677500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
UVM_INFO @ 2056.677500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_inject_test_unlocked0.94242478130133263222269539279877521325784334986569122228889859741954683208564
Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
UVM_FATAL @ 50474.273873 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 50474.273873 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_dev has 1 failures.
0.rom_e2e_jtag_inject_dev.34663873169558619608326401064097219535537152086593960983790452859046344924287
Line 753, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
UVM_FATAL @ 41144.590190 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 41144.590190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_rma has 1 failures.
0.rom_e2e_jtag_inject_rma.91018478923303719919600184701782050059435649974240090737550841852670714239621
Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
UVM_FATAL @ 40984.187218 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 40984.187218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:
0.rom_e2e_self_hash.97786624368973341119791049054290321893005291242416550476073045336042200128009
Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log
UVM_ERROR @ 9997.735080 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
UVM_INFO @ 9997.735080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_self_hash.26257526061750410309997427855485093841240696652344133830587958047061802637540
Line 755, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log
UVM_ERROR @ 9758.748460 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
UVM_INFO @ 9758.748460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
2.chip_csr_aliasing.84516878568098277932722902239930817302034772578892550391084587367046893586450
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
Job ID: smart:061edda2-8bad-421b-a34f-2fdc46a9d85e
4.chip_csr_aliasing.49579721039032041696886385091718281322078801943596296114436319396836664019337
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_csr_aliasing/latest/run.log
Job ID: smart:c94dc247-592d-4498-a751-d2f304088be9
UVM_FATAL @ * us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done. has 1 failures:
0.chip_sw_otp_ctrl_escalation.81606333257428975403650329819817773443825957991941731538112102191355179851116
Line 755, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
UVM_FATAL @ 12291.312360 us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done.
UVM_INFO @ 12291.312360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
13.chip_sw_all_escalation_resets.11910788933287620220455228285712337707644631144243529164402923658709218107694
Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2803.287426 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2803.287426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
31.chip_sw_alert_handler_lpg_sleep_mode_alerts.10177371066393106988831720517669037176973031300196738412886258185853761878061
Line 815, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3664.549324 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
UVM_INFO @ 3664.549324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---