| T208 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.738728297 |
|
|
Mar 03 03:46:56 PM PST 24 |
Mar 03 05:20:53 PM PST 24 |
47412536047 ps |
| T736 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3949958194 |
|
|
Mar 03 04:07:21 PM PST 24 |
Mar 03 04:16:17 PM PST 24 |
4670738952 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3413242707 |
|
|
Mar 03 03:47:13 PM PST 24 |
Mar 03 03:56:16 PM PST 24 |
5606814436 ps |
| T242 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1694526492 |
|
|
Mar 03 04:05:18 PM PST 24 |
Mar 03 04:17:48 PM PST 24 |
6109959840 ps |
| T117 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.719141496 |
|
|
Mar 03 04:09:06 PM PST 24 |
Mar 03 04:15:23 PM PST 24 |
4217829240 ps |
| T961 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1446113667 |
|
|
Mar 03 03:44:37 PM PST 24 |
Mar 03 03:55:15 PM PST 24 |
5860272258 ps |
| T288 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3300603137 |
|
|
Mar 03 03:43:16 PM PST 24 |
Mar 03 03:47:31 PM PST 24 |
3041119640 ps |
| T750 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1516868605 |
|
|
Mar 03 04:11:13 PM PST 24 |
Mar 03 04:17:13 PM PST 24 |
2873592540 ps |
| T741 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3411279622 |
|
|
Mar 03 04:08:58 PM PST 24 |
Mar 03 04:15:37 PM PST 24 |
3293143150 ps |
| T962 |
/workspace/coverage/default/4.chip_tap_straps_prod.3063456537 |
|
|
Mar 03 04:06:01 PM PST 24 |
Mar 03 04:09:43 PM PST 24 |
3022134381 ps |
| T963 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3172845676 |
|
|
Mar 03 03:47:20 PM PST 24 |
Mar 03 03:51:20 PM PST 24 |
2677272789 ps |
| T157 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.729801776 |
|
|
Mar 03 03:46:20 PM PST 24 |
Mar 03 03:54:21 PM PST 24 |
6018272456 ps |
| T964 |
/workspace/coverage/default/0.chip_sw_aes_entropy.1972953427 |
|
|
Mar 03 03:45:39 PM PST 24 |
Mar 03 03:49:10 PM PST 24 |
2565311362 ps |
| T77 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3263936383 |
|
|
Mar 03 03:47:43 PM PST 24 |
Mar 03 04:08:10 PM PST 24 |
9118152646 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3066578923 |
|
|
Mar 03 03:44:16 PM PST 24 |
Mar 03 03:52:01 PM PST 24 |
4256506000 ps |
| T244 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3360311689 |
|
|
Mar 03 04:04:33 PM PST 24 |
Mar 03 04:14:33 PM PST 24 |
5608977334 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1715671004 |
|
|
Mar 03 03:59:36 PM PST 24 |
Mar 03 04:07:41 PM PST 24 |
3493953288 ps |
| T965 |
/workspace/coverage/default/2.rom_keymgr_functest.4056719 |
|
|
Mar 03 04:03:14 PM PST 24 |
Mar 03 04:11:55 PM PST 24 |
4547723520 ps |
| T216 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.123606474 |
|
|
Mar 03 03:44:12 PM PST 24 |
Mar 03 03:55:09 PM PST 24 |
4670938024 ps |
| T966 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.4260272286 |
|
|
Mar 03 03:56:58 PM PST 24 |
Mar 03 04:16:52 PM PST 24 |
10503772106 ps |
| T194 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.904731387 |
|
|
Mar 03 03:45:59 PM PST 24 |
Mar 03 03:52:17 PM PST 24 |
3929388160 ps |
| T183 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.3049323878 |
|
|
Mar 03 03:44:45 PM PST 24 |
Mar 03 03:49:36 PM PST 24 |
3297633040 ps |
| T65 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.1302169747 |
|
|
Mar 03 03:48:50 PM PST 24 |
Mar 03 03:56:07 PM PST 24 |
4786439550 ps |
| T967 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2912697122 |
|
|
Mar 03 04:01:33 PM PST 24 |
Mar 03 04:04:54 PM PST 24 |
3117889076 ps |
| T968 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2054378577 |
|
|
Mar 03 04:08:21 PM PST 24 |
Mar 03 04:19:00 PM PST 24 |
6012131212 ps |
| T969 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3192633029 |
|
|
Mar 03 03:51:11 PM PST 24 |
Mar 03 04:01:53 PM PST 24 |
4916220590 ps |
| T138 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.2231561683 |
|
|
Mar 03 03:49:53 PM PST 24 |
Mar 03 03:57:37 PM PST 24 |
5040482034 ps |
| T970 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2095644445 |
|
|
Mar 03 03:57:42 PM PST 24 |
Mar 03 04:08:08 PM PST 24 |
4748785008 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2874176045 |
|
|
Mar 03 03:50:53 PM PST 24 |
Mar 03 03:58:13 PM PST 24 |
3775312400 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2031639664 |
|
|
Mar 03 03:48:03 PM PST 24 |
Mar 03 03:58:21 PM PST 24 |
17642102058 ps |
| T972 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3293795055 |
|
|
Mar 03 03:58:09 PM PST 24 |
Mar 03 04:06:09 PM PST 24 |
6644715692 ps |
| T285 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3788500238 |
|
|
Mar 03 03:46:12 PM PST 24 |
Mar 03 03:54:52 PM PST 24 |
19978589272 ps |
| T788 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3111857642 |
|
|
Mar 03 04:10:29 PM PST 24 |
Mar 03 04:16:40 PM PST 24 |
4038720820 ps |
| T78 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1779565905 |
|
|
Mar 03 03:44:44 PM PST 24 |
Mar 03 07:32:00 PM PST 24 |
256110806296 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.920948139 |
|
|
Mar 03 04:01:45 PM PST 24 |
Mar 03 04:07:02 PM PST 24 |
2765828706 ps |
| T265 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2556065788 |
|
|
Mar 03 03:45:46 PM PST 24 |
Mar 03 04:06:06 PM PST 24 |
6325071176 ps |
| T779 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2983572857 |
|
|
Mar 03 04:08:35 PM PST 24 |
Mar 03 04:18:33 PM PST 24 |
5115329988 ps |
| T728 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2736847041 |
|
|
Mar 03 04:04:31 PM PST 24 |
Mar 03 04:14:52 PM PST 24 |
5461603400 ps |
| T974 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2210282373 |
|
|
Mar 03 03:49:07 PM PST 24 |
Mar 03 04:22:04 PM PST 24 |
8663918560 ps |
| T746 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.1132114560 |
|
|
Mar 03 04:06:00 PM PST 24 |
Mar 03 04:15:46 PM PST 24 |
4574963208 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3171510463 |
|
|
Mar 03 03:53:15 PM PST 24 |
Mar 03 04:05:30 PM PST 24 |
5890046700 ps |
| T173 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.357502073 |
|
|
Mar 03 03:46:51 PM PST 24 |
Mar 03 03:56:48 PM PST 24 |
4956928188 ps |
| T687 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.2498665118 |
|
|
Mar 03 04:06:10 PM PST 24 |
Mar 03 04:14:45 PM PST 24 |
4813899844 ps |
| T174 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1756017860 |
|
|
Mar 03 03:55:49 PM PST 24 |
Mar 03 04:09:52 PM PST 24 |
7704804505 ps |
| T976 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3635810715 |
|
|
Mar 03 03:43:06 PM PST 24 |
Mar 03 03:46:23 PM PST 24 |
3073266589 ps |
| T977 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2890147289 |
|
|
Mar 03 03:50:09 PM PST 24 |
Mar 03 04:24:47 PM PST 24 |
9580121240 ps |
| T978 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4083171607 |
|
|
Mar 03 04:04:00 PM PST 24 |
Mar 03 04:13:45 PM PST 24 |
8198789536 ps |
| T749 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.56579930 |
|
|
Mar 03 04:10:29 PM PST 24 |
Mar 03 04:17:09 PM PST 24 |
3444194752 ps |
| T979 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3003978415 |
|
|
Mar 03 03:46:11 PM PST 24 |
Mar 03 03:52:49 PM PST 24 |
3886018478 ps |
| T980 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3799370612 |
|
|
Mar 03 04:01:00 PM PST 24 |
Mar 03 04:04:34 PM PST 24 |
2608553341 ps |
| T739 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2164488432 |
|
|
Mar 03 04:05:03 PM PST 24 |
Mar 03 04:12:46 PM PST 24 |
3272662516 ps |
| T7 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4109126382 |
|
|
Mar 03 03:44:02 PM PST 24 |
Mar 03 03:48:12 PM PST 24 |
3369576248 ps |
| T814 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011329337 |
|
|
Mar 03 04:10:27 PM PST 24 |
Mar 03 04:16:30 PM PST 24 |
3888500026 ps |
| T314 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.834316167 |
|
|
Mar 03 03:59:37 PM PST 24 |
Mar 03 04:06:54 PM PST 24 |
3979947580 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.367461668 |
|
|
Mar 03 04:05:24 PM PST 24 |
Mar 03 04:10:09 PM PST 24 |
2570709424 ps |
| T982 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3489309867 |
|
|
Mar 03 03:59:14 PM PST 24 |
Mar 03 04:03:52 PM PST 24 |
3031614402 ps |
| T307 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1641646166 |
|
|
Mar 03 03:48:08 PM PST 24 |
Mar 03 03:57:06 PM PST 24 |
3000590340 ps |
| T983 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2614483298 |
|
|
Mar 03 03:50:38 PM PST 24 |
Mar 03 04:23:11 PM PST 24 |
8176377208 ps |
| T774 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3193048796 |
|
|
Mar 03 04:08:06 PM PST 24 |
Mar 03 04:13:29 PM PST 24 |
4231163696 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2329944971 |
|
|
Mar 03 04:02:00 PM PST 24 |
Mar 03 04:08:47 PM PST 24 |
3322314936 ps |
| T985 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.227352835 |
|
|
Mar 03 03:45:14 PM PST 24 |
Mar 03 03:48:33 PM PST 24 |
2195643098 ps |
| T217 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3312283353 |
|
|
Mar 03 03:57:52 PM PST 24 |
Mar 03 04:09:50 PM PST 24 |
5930727260 ps |
| T812 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.878188611 |
|
|
Mar 03 04:07:53 PM PST 24 |
Mar 03 04:13:33 PM PST 24 |
3469459276 ps |
| T225 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.3211803182 |
|
|
Mar 03 03:44:36 PM PST 24 |
Mar 03 03:49:38 PM PST 24 |
2580629632 ps |
| T816 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3334681278 |
|
|
Mar 03 04:05:48 PM PST 24 |
Mar 03 04:13:01 PM PST 24 |
3498507792 ps |
| T266 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2291476725 |
|
|
Mar 03 03:47:00 PM PST 24 |
Mar 03 04:00:28 PM PST 24 |
5060658622 ps |
| T323 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.129646071 |
|
|
Mar 03 03:50:13 PM PST 24 |
Mar 03 04:44:35 PM PST 24 |
11908464676 ps |
| T263 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2997901588 |
|
|
Mar 03 03:44:02 PM PST 24 |
Mar 03 04:13:02 PM PST 24 |
13514709328 ps |
| T986 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3772288375 |
|
|
Mar 03 04:10:04 PM PST 24 |
Mar 03 04:22:48 PM PST 24 |
5464890069 ps |
| T747 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1433415351 |
|
|
Mar 03 04:08:13 PM PST 24 |
Mar 03 04:15:31 PM PST 24 |
3800636148 ps |
| T987 |
/workspace/coverage/default/1.chip_sw_hmac_enc.2219945514 |
|
|
Mar 03 03:47:36 PM PST 24 |
Mar 03 03:51:38 PM PST 24 |
3073590260 ps |
| T786 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1574039842 |
|
|
Mar 03 04:07:13 PM PST 24 |
Mar 03 04:14:52 PM PST 24 |
3804270488 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3061716547 |
|
|
Mar 03 03:57:16 PM PST 24 |
Mar 03 04:17:41 PM PST 24 |
7882439870 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.799319599 |
|
|
Mar 03 04:02:12 PM PST 24 |
Mar 03 04:13:30 PM PST 24 |
4643473274 ps |
| T810 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1626853187 |
|
|
Mar 03 04:08:16 PM PST 24 |
Mar 03 04:14:38 PM PST 24 |
3868700912 ps |
| T990 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3208061446 |
|
|
Mar 03 03:46:15 PM PST 24 |
Mar 03 03:51:13 PM PST 24 |
3225724824 ps |
| T683 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4009683367 |
|
|
Mar 03 03:44:43 PM PST 24 |
Mar 03 03:47:17 PM PST 24 |
2922583337 ps |
| T991 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4228268224 |
|
|
Mar 03 04:04:38 PM PST 24 |
Mar 03 05:08:41 PM PST 24 |
23209837944 ps |
| T789 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3054675320 |
|
|
Mar 03 04:06:50 PM PST 24 |
Mar 03 04:12:44 PM PST 24 |
3587519272 ps |
| T992 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3464095327 |
|
|
Mar 03 04:01:01 PM PST 24 |
Mar 03 04:06:25 PM PST 24 |
3050639734 ps |
| T143 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.261676033 |
|
|
Mar 03 03:49:51 PM PST 24 |
Mar 03 04:46:35 PM PST 24 |
25624869816 ps |
| T27 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.1946495413 |
|
|
Mar 03 04:04:07 PM PST 24 |
Mar 03 04:08:29 PM PST 24 |
2981837181 ps |
| T229 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3810819391 |
|
|
Mar 03 04:10:54 PM PST 24 |
Mar 03 04:22:07 PM PST 24 |
5364249704 ps |
| T188 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3533518343 |
|
|
Mar 03 03:46:30 PM PST 24 |
Mar 03 07:27:35 PM PST 24 |
78464480659 ps |
| T993 |
/workspace/coverage/default/1.chip_sw_example_concurrency.1481178374 |
|
|
Mar 03 03:47:09 PM PST 24 |
Mar 03 03:51:39 PM PST 24 |
3088958946 ps |
| T994 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1600202233 |
|
|
Mar 03 03:44:01 PM PST 24 |
Mar 03 03:48:21 PM PST 24 |
3001933738 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3887946054 |
|
|
Mar 03 03:47:33 PM PST 24 |
Mar 03 04:01:42 PM PST 24 |
4942861200 ps |
| T996 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1598738271 |
|
|
Mar 03 03:45:00 PM PST 24 |
Mar 03 03:55:29 PM PST 24 |
4124726340 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.990760758 |
|
|
Mar 03 03:56:10 PM PST 24 |
Mar 03 04:14:36 PM PST 24 |
5695440472 ps |
| T819 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1946416191 |
|
|
Mar 03 04:09:29 PM PST 24 |
Mar 03 04:18:31 PM PST 24 |
5241200546 ps |
| T673 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.647213550 |
|
|
Mar 03 04:02:38 PM PST 24 |
Mar 03 05:13:08 PM PST 24 |
25429572766 ps |
| T796 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.93091194 |
|
|
Mar 03 04:09:41 PM PST 24 |
Mar 03 04:18:58 PM PST 24 |
5059600380 ps |
| T298 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2155946149 |
|
|
Mar 03 03:48:15 PM PST 24 |
Mar 03 03:54:20 PM PST 24 |
3311390154 ps |
| T998 |
/workspace/coverage/default/1.chip_sw_aes_idle.2391806979 |
|
|
Mar 03 03:47:48 PM PST 24 |
Mar 03 03:51:24 PM PST 24 |
2405195848 ps |
| T999 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3307422728 |
|
|
Mar 03 03:46:57 PM PST 24 |
Mar 03 04:29:28 PM PST 24 |
24104427338 ps |
| T678 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2377648285 |
|
|
Mar 03 04:09:59 PM PST 24 |
Mar 03 04:16:55 PM PST 24 |
4270115392 ps |
| T1000 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.3379748155 |
|
|
Mar 03 04:08:12 PM PST 24 |
Mar 03 04:40:17 PM PST 24 |
8303784007 ps |
| T700 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1033038518 |
|
|
Mar 03 04:11:04 PM PST 24 |
Mar 03 04:18:06 PM PST 24 |
3837214988 ps |
| T201 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3720692260 |
|
|
Mar 03 04:00:35 PM PST 24 |
Mar 03 04:09:52 PM PST 24 |
5614769720 ps |
| T726 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2114997883 |
|
|
Mar 03 04:06:47 PM PST 24 |
Mar 03 04:17:55 PM PST 24 |
5184883916 ps |
| T820 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2140683929 |
|
|
Mar 03 04:06:36 PM PST 24 |
Mar 03 04:11:31 PM PST 24 |
3355786680 ps |
| T164 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1998070444 |
|
|
Mar 03 03:59:27 PM PST 24 |
Mar 03 04:02:47 PM PST 24 |
2128113829 ps |
| T1001 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.719540680 |
|
|
Mar 03 03:48:02 PM PST 24 |
Mar 03 04:21:09 PM PST 24 |
7930933513 ps |
| T176 |
/workspace/coverage/default/2.chip_jtag_csr_rw.520937995 |
|
|
Mar 03 03:53:42 PM PST 24 |
Mar 03 04:28:55 PM PST 24 |
19495140144 ps |
| T801 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3332163805 |
|
|
Mar 03 04:05:57 PM PST 24 |
Mar 03 04:14:24 PM PST 24 |
4866634312 ps |
| T147 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.913301445 |
|
|
Mar 03 03:48:54 PM PST 24 |
Mar 03 03:57:19 PM PST 24 |
4591292470 ps |
| T8 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.405914685 |
|
|
Mar 03 03:53:46 PM PST 24 |
Mar 03 03:58:55 PM PST 24 |
3475401529 ps |
| T1002 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1032279425 |
|
|
Mar 03 03:51:24 PM PST 24 |
Mar 03 04:19:11 PM PST 24 |
6312066034 ps |
| T109 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.1449774423 |
|
|
Mar 03 03:46:31 PM PST 24 |
Mar 03 03:55:52 PM PST 24 |
4013585820 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.4141061773 |
|
|
Mar 03 03:50:34 PM PST 24 |
Mar 03 03:55:08 PM PST 24 |
2620484352 ps |
| T1003 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.2142393295 |
|
|
Mar 03 04:03:39 PM PST 24 |
Mar 03 04:08:13 PM PST 24 |
2602203888 ps |
| T1004 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.603225175 |
|
|
Mar 03 03:43:10 PM PST 24 |
Mar 03 03:52:08 PM PST 24 |
6222305232 ps |
| T1005 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1266671194 |
|
|
Mar 03 03:47:35 PM PST 24 |
Mar 03 04:04:37 PM PST 24 |
5491824560 ps |
| T1006 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.761315941 |
|
|
Mar 03 03:59:08 PM PST 24 |
Mar 03 04:02:58 PM PST 24 |
2640550716 ps |
| T148 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2050844479 |
|
|
Mar 03 03:49:22 PM PST 24 |
Mar 03 03:59:05 PM PST 24 |
4137362430 ps |
| T1007 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3528149887 |
|
|
Mar 03 03:52:19 PM PST 24 |
Mar 03 03:58:20 PM PST 24 |
3638259577 ps |
| T679 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.304941732 |
|
|
Mar 03 03:48:01 PM PST 24 |
Mar 03 03:54:34 PM PST 24 |
4390757060 ps |
| T21 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2285705106 |
|
|
Mar 03 04:01:17 PM PST 24 |
Mar 03 04:57:41 PM PST 24 |
20477883256 ps |
| T1008 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.274247924 |
|
|
Mar 03 04:06:06 PM PST 24 |
Mar 03 04:53:08 PM PST 24 |
27470609755 ps |
| T374 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3812398448 |
|
|
Mar 03 03:45:47 PM PST 24 |
Mar 03 03:54:12 PM PST 24 |
4208098004 ps |
| T315 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2677557403 |
|
|
Mar 03 03:47:13 PM PST 24 |
Mar 03 03:55:52 PM PST 24 |
4718189872 ps |
| T1009 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.4279670106 |
|
|
Mar 03 03:48:05 PM PST 24 |
Mar 03 03:52:26 PM PST 24 |
2661876360 ps |
| T1010 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2540761143 |
|
|
Mar 03 03:45:25 PM PST 24 |
Mar 03 04:04:50 PM PST 24 |
7756085908 ps |
| T38 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.4102818487 |
|
|
Mar 03 03:55:21 PM PST 24 |
Mar 03 04:01:01 PM PST 24 |
3237260150 ps |
| T112 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2718676618 |
|
|
Mar 03 03:46:17 PM PST 24 |
Mar 03 04:13:08 PM PST 24 |
12697452080 ps |
| T136 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3151917616 |
|
|
Mar 03 04:02:02 PM PST 24 |
Mar 03 04:05:58 PM PST 24 |
2807692439 ps |
| T684 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.2836178688 |
|
|
Mar 03 03:47:04 PM PST 24 |
Mar 03 03:48:44 PM PST 24 |
2234058574 ps |
| T331 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.1404750717 |
|
|
Mar 03 03:45:21 PM PST 24 |
Mar 03 03:48:50 PM PST 24 |
2670542112 ps |
| T731 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3343351261 |
|
|
Mar 03 03:46:15 PM PST 24 |
Mar 03 03:53:34 PM PST 24 |
4042239984 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2649520380 |
|
|
Mar 03 03:55:58 PM PST 24 |
Mar 03 04:02:30 PM PST 24 |
3316026852 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.154904581 |
|
|
Mar 03 03:47:31 PM PST 24 |
Mar 03 04:39:50 PM PST 24 |
20155265130 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2470297704 |
|
|
Mar 03 03:49:50 PM PST 24 |
Mar 03 03:53:58 PM PST 24 |
2817864284 ps |
| T350 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3851141879 |
|
|
Mar 03 03:45:26 PM PST 24 |
Mar 03 03:53:10 PM PST 24 |
9538821360 ps |
| T274 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.680461187 |
|
|
Mar 03 03:55:59 PM PST 24 |
Mar 03 04:08:13 PM PST 24 |
5073663440 ps |
| T1012 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2095867760 |
|
|
Mar 03 03:45:43 PM PST 24 |
Mar 03 04:07:19 PM PST 24 |
8386167688 ps |
| T1013 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.684102289 |
|
|
Mar 03 03:52:53 PM PST 24 |
Mar 03 04:46:06 PM PST 24 |
11988685084 ps |
| T743 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3063498508 |
|
|
Mar 03 04:05:54 PM PST 24 |
Mar 03 04:18:48 PM PST 24 |
4330648368 ps |
| T822 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.947887350 |
|
|
Mar 03 04:05:56 PM PST 24 |
Mar 03 04:11:30 PM PST 24 |
3543758842 ps |
| T1014 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3872769462 |
|
|
Mar 03 03:57:13 PM PST 24 |
Mar 03 04:00:48 PM PST 24 |
2253446228 ps |
| T815 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.3390343490 |
|
|
Mar 03 04:08:15 PM PST 24 |
Mar 03 04:20:20 PM PST 24 |
5390380652 ps |
| T823 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1979919364 |
|
|
Mar 03 04:08:40 PM PST 24 |
Mar 03 04:21:00 PM PST 24 |
5508526512 ps |
| T1015 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2752533976 |
|
|
Mar 03 04:02:36 PM PST 24 |
Mar 03 04:07:40 PM PST 24 |
3970159142 ps |
| T295 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3539692743 |
|
|
Mar 03 04:11:05 PM PST 24 |
Mar 03 04:21:14 PM PST 24 |
4972818422 ps |
| T1016 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.286845708 |
|
|
Mar 03 04:06:36 PM PST 24 |
Mar 03 04:21:16 PM PST 24 |
5233219520 ps |
| T1017 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1085485587 |
|
|
Mar 03 03:47:26 PM PST 24 |
Mar 03 03:52:04 PM PST 24 |
2725719772 ps |
| T51 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3685110582 |
|
|
Mar 03 03:47:53 PM PST 24 |
Mar 03 04:21:43 PM PST 24 |
20598490740 ps |
| T1018 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.864361953 |
|
|
Mar 03 03:47:13 PM PST 24 |
Mar 03 03:59:33 PM PST 24 |
5056472790 ps |
| T1019 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.3004932242 |
|
|
Mar 03 03:49:06 PM PST 24 |
Mar 03 04:24:55 PM PST 24 |
8545676715 ps |
| T1020 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2242666890 |
|
|
Mar 03 03:51:27 PM PST 24 |
Mar 03 04:26:23 PM PST 24 |
8884324192 ps |
| T1021 |
/workspace/coverage/default/0.chip_sw_aes_enc.2038301499 |
|
|
Mar 03 03:47:40 PM PST 24 |
Mar 03 03:54:35 PM PST 24 |
3356929952 ps |
| T1022 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.470543201 |
|
|
Mar 03 03:48:22 PM PST 24 |
Mar 03 04:07:18 PM PST 24 |
6209102426 ps |
| T1023 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1113225380 |
|
|
Mar 03 03:51:30 PM PST 24 |
Mar 03 04:22:28 PM PST 24 |
6915336328 ps |
| T1024 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.6155082 |
|
|
Mar 03 03:56:35 PM PST 24 |
Mar 03 04:01:44 PM PST 24 |
3454555828 ps |
| T1025 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.775804078 |
|
|
Mar 03 04:04:25 PM PST 24 |
Mar 03 04:16:54 PM PST 24 |
9442732148 ps |
| T1026 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2699050812 |
|
|
Mar 03 03:57:39 PM PST 24 |
Mar 03 04:11:35 PM PST 24 |
9057840921 ps |
| T1027 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3510914052 |
|
|
Mar 03 03:59:53 PM PST 24 |
Mar 03 04:06:27 PM PST 24 |
4483045864 ps |
| T742 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1666403209 |
|
|
Mar 03 04:09:15 PM PST 24 |
Mar 03 04:14:28 PM PST 24 |
3920460720 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2558361773 |
|
|
Mar 03 03:49:31 PM PST 24 |
Mar 03 03:55:28 PM PST 24 |
4513569854 ps |
| T324 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.735810658 |
|
|
Mar 03 03:53:51 PM PST 24 |
Mar 03 04:55:07 PM PST 24 |
12562112524 ps |
| T206 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3391981640 |
|
|
Mar 03 03:48:00 PM PST 24 |
Mar 03 05:26:49 PM PST 24 |
47416334728 ps |
| T757 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3827518571 |
|
|
Mar 03 04:07:15 PM PST 24 |
Mar 03 04:20:46 PM PST 24 |
5615835664 ps |
| T780 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2058739350 |
|
|
Mar 03 04:07:26 PM PST 24 |
Mar 03 04:13:16 PM PST 24 |
3800998308 ps |
| T1029 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4017693869 |
|
|
Mar 03 03:57:33 PM PST 24 |
Mar 03 04:19:44 PM PST 24 |
11904805896 ps |
| T1030 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3270198981 |
|
|
Mar 03 03:49:40 PM PST 24 |
Mar 03 03:52:52 PM PST 24 |
2628773968 ps |
| T278 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.471512448 |
|
|
Mar 03 03:55:20 PM PST 24 |
Mar 03 04:09:39 PM PST 24 |
5289863400 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.3384467868 |
|
|
Mar 03 03:46:31 PM PST 24 |
Mar 03 04:18:12 PM PST 24 |
17354922757 ps |
| T803 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2613256558 |
|
|
Mar 03 04:14:31 PM PST 24 |
Mar 03 04:22:08 PM PST 24 |
3986433064 ps |
| T468 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1031523802 |
|
|
Mar 03 03:44:55 PM PST 24 |
Mar 03 04:16:02 PM PST 24 |
13818752520 ps |
| T1032 |
/workspace/coverage/default/1.chip_sw_example_flash.193745586 |
|
|
Mar 03 03:47:16 PM PST 24 |
Mar 03 03:51:21 PM PST 24 |
3018402660 ps |
| T177 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.60374906 |
|
|
Mar 03 03:58:57 PM PST 24 |
Mar 03 04:26:26 PM PST 24 |
21156177882 ps |
| T140 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.558690159 |
|
|
Mar 03 04:02:47 PM PST 24 |
Mar 03 04:48:00 PM PST 24 |
12710692636 ps |
| T207 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1598876998 |
|
|
Mar 03 04:00:00 PM PST 24 |
Mar 03 04:27:56 PM PST 24 |
20374051518 ps |
| T1033 |
/workspace/coverage/default/1.chip_sw_aes_enc.261362921 |
|
|
Mar 03 03:47:05 PM PST 24 |
Mar 03 03:52:32 PM PST 24 |
2830401300 ps |
| T245 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1338090110 |
|
|
Mar 03 03:59:02 PM PST 24 |
Mar 03 04:09:37 PM PST 24 |
4205282104 ps |
| T744 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1807773263 |
|
|
Mar 03 04:09:05 PM PST 24 |
Mar 03 04:19:38 PM PST 24 |
4926775840 ps |
| T1034 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.1502892118 |
|
|
Mar 03 04:00:36 PM PST 24 |
Mar 03 04:04:09 PM PST 24 |
3143501432 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2407988256 |
|
|
Mar 03 03:59:44 PM PST 24 |
Mar 03 04:18:24 PM PST 24 |
5533033152 ps |
| T158 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.209745068 |
|
|
Mar 03 04:00:57 PM PST 24 |
Mar 03 04:09:10 PM PST 24 |
5103374936 ps |
| T202 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2859595059 |
|
|
Mar 03 03:45:33 PM PST 24 |
Mar 03 03:53:45 PM PST 24 |
5089905704 ps |
| T308 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.873109933 |
|
|
Mar 03 03:59:42 PM PST 24 |
Mar 03 04:08:50 PM PST 24 |
2491122916 ps |
| T1036 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2104518604 |
|
|
Mar 03 03:47:34 PM PST 24 |
Mar 03 03:58:10 PM PST 24 |
4855027048 ps |
| T269 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3696749693 |
|
|
Mar 03 03:45:31 PM PST 24 |
Mar 03 03:56:45 PM PST 24 |
4157024813 ps |
| T1037 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2683258088 |
|
|
Mar 03 04:04:03 PM PST 24 |
Mar 03 04:21:51 PM PST 24 |
5968933512 ps |
| T1038 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2413270731 |
|
|
Mar 03 03:47:46 PM PST 24 |
Mar 03 03:53:03 PM PST 24 |
3395755236 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1817936589 |
|
|
Mar 03 04:02:07 PM PST 24 |
Mar 03 04:29:18 PM PST 24 |
21295165536 ps |
| T1039 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.659435864 |
|
|
Mar 03 03:58:05 PM PST 24 |
Mar 03 04:45:57 PM PST 24 |
17154307018 ps |
| T1040 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2853691796 |
|
|
Mar 03 04:05:36 PM PST 24 |
Mar 03 04:12:42 PM PST 24 |
3048792372 ps |
| T1041 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1018881253 |
|
|
Mar 03 04:06:40 PM PST 24 |
Mar 03 04:15:58 PM PST 24 |
5998256507 ps |
| T798 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1578280594 |
|
|
Mar 03 04:10:41 PM PST 24 |
Mar 03 04:21:40 PM PST 24 |
5720257752 ps |
| T1042 |
/workspace/coverage/default/0.chip_tap_straps_rma.2185162922 |
|
|
Mar 03 03:42:20 PM PST 24 |
Mar 03 03:46:12 PM PST 24 |
3543275750 ps |
| T776 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1884451648 |
|
|
Mar 03 04:07:12 PM PST 24 |
Mar 03 04:17:19 PM PST 24 |
4558613440 ps |
| T160 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1877595036 |
|
|
Mar 03 04:04:34 PM PST 24 |
Mar 03 04:20:29 PM PST 24 |
7877885820 ps |
| T1043 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2072899767 |
|
|
Mar 03 03:47:51 PM PST 24 |
Mar 03 03:58:36 PM PST 24 |
4393816250 ps |
| T243 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1347712020 |
|
|
Mar 03 04:03:25 PM PST 24 |
Mar 03 04:19:36 PM PST 24 |
5134076332 ps |
| T685 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4137371833 |
|
|
Mar 03 03:57:08 PM PST 24 |
Mar 03 04:01:17 PM PST 24 |
3066277951 ps |
| T758 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1204926299 |
|
|
Mar 03 04:08:13 PM PST 24 |
Mar 03 04:17:54 PM PST 24 |
4725746032 ps |
| T1044 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1588757002 |
|
|
Mar 03 04:00:32 PM PST 24 |
Mar 03 04:19:57 PM PST 24 |
11135772790 ps |
| T1045 |
/workspace/coverage/default/1.rom_e2e_static_critical.3807390356 |
|
|
Mar 03 03:56:25 PM PST 24 |
Mar 03 04:38:58 PM PST 24 |
10927157000 ps |
| T1046 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2811164493 |
|
|
Mar 03 04:02:04 PM PST 24 |
Mar 03 04:13:45 PM PST 24 |
5105387308 ps |
| T806 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1408971914 |
|
|
Mar 03 04:08:54 PM PST 24 |
Mar 03 04:16:00 PM PST 24 |
3870188524 ps |
| T1047 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.690136652 |
|
|
Mar 03 03:48:21 PM PST 24 |
Mar 03 03:56:11 PM PST 24 |
5328290600 ps |
| T1048 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.69707527 |
|
|
Mar 03 04:04:25 PM PST 24 |
Mar 03 04:08:51 PM PST 24 |
2983422624 ps |
| T1049 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3597658935 |
|
|
Mar 03 03:49:10 PM PST 24 |
Mar 03 03:52:08 PM PST 24 |
2502734600 ps |
| T272 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.3859098711 |
|
|
Mar 03 03:45:14 PM PST 24 |
Mar 03 04:07:54 PM PST 24 |
6091359202 ps |
| T777 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.472833089 |
|
|
Mar 03 04:10:27 PM PST 24 |
Mar 03 04:16:24 PM PST 24 |
3239962760 ps |
| T1050 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1036680346 |
|
|
Mar 03 03:54:44 PM PST 24 |
Mar 03 04:42:03 PM PST 24 |
13199105348 ps |
| T299 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3321413331 |
|
|
Mar 03 03:46:01 PM PST 24 |
Mar 03 03:52:58 PM PST 24 |
3362941872 ps |
| T178 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2962662795 |
|
|
Mar 03 03:46:52 PM PST 24 |
Mar 03 03:57:16 PM PST 24 |
4811988537 ps |
| T787 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2169532384 |
|
|
Mar 03 04:07:03 PM PST 24 |
Mar 03 04:16:34 PM PST 24 |
3857031084 ps |
| T230 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3618656097 |
|
|
Mar 03 04:11:36 PM PST 24 |
Mar 03 04:23:25 PM PST 24 |
6148507306 ps |
| T1051 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1201488219 |
|
|
Mar 03 03:49:49 PM PST 24 |
Mar 03 04:22:32 PM PST 24 |
9199804162 ps |
| T327 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.682788836 |
|
|
Mar 03 04:02:06 PM PST 24 |
Mar 03 04:04:43 PM PST 24 |
2289781232 ps |
| T1052 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.3025758551 |
|
|
Mar 03 04:07:13 PM PST 24 |
Mar 03 04:37:40 PM PST 24 |
8978486196 ps |
| T784 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.237648739 |
|
|
Mar 03 04:09:58 PM PST 24 |
Mar 03 04:20:29 PM PST 24 |
5199046752 ps |
| T686 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.2382188564 |
|
|
Mar 03 04:02:38 PM PST 24 |
Mar 03 04:04:23 PM PST 24 |
2824187827 ps |
| T1053 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2176597495 |
|
|
Mar 03 03:59:21 PM PST 24 |
Mar 03 04:12:29 PM PST 24 |
8107422868 ps |
| T316 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.501508962 |
|
|
Mar 03 03:59:40 PM PST 24 |
Mar 03 04:11:33 PM PST 24 |
5478298920 ps |
| T724 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.767736869 |
|
|
Mar 03 04:11:59 PM PST 24 |
Mar 03 04:18:46 PM PST 24 |
3898565452 ps |
| T769 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1229645814 |
|
|
Mar 03 04:10:51 PM PST 24 |
Mar 03 04:18:40 PM PST 24 |
3691630872 ps |
| T36 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1349420800 |
|
|
Mar 03 03:45:31 PM PST 24 |
Mar 03 03:49:45 PM PST 24 |
2899344480 ps |
| T121 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1839070387 |
|
|
Mar 03 03:46:30 PM PST 24 |
Mar 03 03:50:17 PM PST 24 |
2273414141 ps |
| T766 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3185248903 |
|
|
Mar 03 04:11:41 PM PST 24 |
Mar 03 04:19:23 PM PST 24 |
5004316402 ps |
| T92 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2225871547 |
|
|
Mar 03 03:48:04 PM PST 24 |
Mar 03 03:54:11 PM PST 24 |
7093370136 ps |
| T125 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3953607471 |
|
|
Mar 03 04:11:29 PM PST 24 |
Mar 03 04:22:20 PM PST 24 |
4994623688 ps |
| T1054 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3635781856 |
|
|
Mar 03 03:46:39 PM PST 24 |
Mar 03 04:17:10 PM PST 24 |
7396643928 ps |
| T729 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1840862477 |
|
|
Mar 03 04:06:13 PM PST 24 |
Mar 03 04:12:19 PM PST 24 |
3582302006 ps |
| T1055 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2048775637 |
|
|
Mar 03 03:56:07 PM PST 24 |
Mar 03 04:17:32 PM PST 24 |
6865202020 ps |
| T1056 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.155583281 |
|
|
Mar 03 03:47:55 PM PST 24 |
Mar 03 04:04:55 PM PST 24 |
5911286628 ps |
| T1057 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1796404729 |
|
|
Mar 03 03:47:32 PM PST 24 |
Mar 03 04:17:43 PM PST 24 |
8599076935 ps |
| T1058 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2001492257 |
|
|
Mar 03 03:49:02 PM PST 24 |
Mar 03 04:00:29 PM PST 24 |
6401955057 ps |
| T1059 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1654851045 |
|
|
Mar 03 04:01:03 PM PST 24 |
Mar 03 04:11:46 PM PST 24 |
5216859000 ps |
| T1060 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1672269975 |
|
|
Mar 03 03:46:34 PM PST 24 |
Mar 03 03:50:43 PM PST 24 |
3360562442 ps |
| T246 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3085920367 |
|
|
Mar 03 03:44:53 PM PST 24 |
Mar 03 03:55:24 PM PST 24 |
4555128859 ps |
| T1061 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1159785032 |
|
|
Mar 03 03:45:37 PM PST 24 |
Mar 03 03:50:10 PM PST 24 |
3149640436 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3559402523 |
|
|
Mar 03 03:46:49 PM PST 24 |
Mar 03 04:03:32 PM PST 24 |
7501357508 ps |
| T1063 |
/workspace/coverage/default/0.chip_sw_aes_idle.612836629 |
|
|
Mar 03 03:48:21 PM PST 24 |
Mar 03 03:53:56 PM PST 24 |
2900581750 ps |
| T1064 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3807732603 |
|
|
Mar 03 03:50:43 PM PST 24 |
Mar 03 03:55:07 PM PST 24 |
3332928987 ps |
| T818 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4176830044 |
|
|
Mar 03 04:06:38 PM PST 24 |
Mar 03 04:13:58 PM PST 24 |
3913510056 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.4029819715 |
|
|
Mar 03 04:09:03 PM PST 24 |
Mar 03 04:42:24 PM PST 24 |
8755142920 ps |
| T794 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1561422294 |
|
|
Mar 03 04:06:44 PM PST 24 |
Mar 03 04:15:58 PM PST 24 |
5019163444 ps |
| T1066 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3355717486 |
|
|
Mar 03 03:59:01 PM PST 24 |
Mar 03 04:20:23 PM PST 24 |
6258681000 ps |
| T1067 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1248875198 |
|
|
Mar 03 03:50:49 PM PST 24 |
Mar 03 04:24:55 PM PST 24 |
9051986024 ps |
| T28 |
/workspace/coverage/default/1.chip_sw_gpio.3047487375 |
|
|
Mar 03 03:44:35 PM PST 24 |
Mar 03 03:52:10 PM PST 24 |
4043969854 ps |
| T722 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.145232668 |
|
|
Mar 03 04:06:52 PM PST 24 |
Mar 03 04:12:47 PM PST 24 |
3172409268 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2117936443 |
|
|
Mar 03 04:02:22 PM PST 24 |
Mar 03 04:07:49 PM PST 24 |
3151536216 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2123648991 |
|
|
Mar 03 03:43:27 PM PST 24 |
Mar 03 05:22:16 PM PST 24 |
47664788275 ps |
| T1068 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3072975184 |
|
|
Mar 03 04:02:29 PM PST 24 |
Mar 03 04:40:04 PM PST 24 |
14824972770 ps |
| T1069 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3709293049 |
|
|
Mar 03 03:47:19 PM PST 24 |
Mar 03 03:52:29 PM PST 24 |
3554067568 ps |
| T81 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1594248789 |
|
|
Mar 03 04:09:03 PM PST 24 |
Mar 03 04:15:18 PM PST 24 |
2922805854 ps |
| T83 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2710371105 |
|
|
Mar 03 04:08:01 PM PST 24 |
Mar 03 04:12:28 PM PST 24 |
3014372296 ps |