| T84 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.986526515 |
|
|
Mar 03 03:42:53 PM PST 24 |
Mar 03 03:52:55 PM PST 24 |
5213901292 ps |
| T85 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4004021774 |
|
|
Mar 03 03:56:45 PM PST 24 |
Mar 03 04:15:49 PM PST 24 |
6292099976 ps |
| T86 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.244716372 |
|
|
Mar 03 03:44:56 PM PST 24 |
Mar 03 03:54:17 PM PST 24 |
4232021175 ps |
| T87 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.1171814964 |
|
|
Mar 03 03:47:00 PM PST 24 |
Mar 03 03:52:13 PM PST 24 |
3477830455 ps |
| T88 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3983798307 |
|
|
Mar 03 03:49:47 PM PST 24 |
Mar 03 04:25:54 PM PST 24 |
9069447500 ps |
| T89 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3560013343 |
|
|
Mar 03 03:47:05 PM PST 24 |
Mar 03 06:28:16 PM PST 24 |
58753345516 ps |
| T90 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.775583698 |
|
|
Mar 03 03:45:50 PM PST 24 |
Mar 03 03:52:49 PM PST 24 |
3679609188 ps |
| T91 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.1966895844 |
|
|
Mar 03 04:01:28 PM PST 24 |
Mar 03 04:05:56 PM PST 24 |
2615993750 ps |
| T1070 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1940153958 |
|
|
Mar 03 03:47:55 PM PST 24 |
Mar 03 04:03:14 PM PST 24 |
10946922515 ps |
| T466 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1032766720 |
|
|
Mar 03 03:47:56 PM PST 24 |
Mar 03 04:00:17 PM PST 24 |
5143555400 ps |
| T1071 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.3887472132 |
|
|
Mar 03 03:48:49 PM PST 24 |
Mar 03 04:26:08 PM PST 24 |
8812893200 ps |
| T1072 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.1216416090 |
|
|
Mar 03 04:03:20 PM PST 24 |
Mar 03 04:05:35 PM PST 24 |
2947527738 ps |
| T1073 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.3681561143 |
|
|
Mar 03 03:47:55 PM PST 24 |
Mar 03 03:53:46 PM PST 24 |
3536560579 ps |
| T1074 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.618158295 |
|
|
Mar 03 03:44:58 PM PST 24 |
Mar 03 03:48:41 PM PST 24 |
2207710784 ps |
| T1075 |
/workspace/coverage/default/2.chip_sw_flash_init.1345873600 |
|
|
Mar 03 03:55:40 PM PST 24 |
Mar 03 04:34:41 PM PST 24 |
24998255620 ps |
| T1076 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.382524277 |
|
|
Mar 03 04:06:09 PM PST 24 |
Mar 03 04:13:49 PM PST 24 |
3780974848 ps |
| T1077 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1434687033 |
|
|
Mar 03 03:48:12 PM PST 24 |
Mar 03 03:52:52 PM PST 24 |
3284120680 ps |
| T1078 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2002849843 |
|
|
Mar 03 03:45:57 PM PST 24 |
Mar 03 04:31:18 PM PST 24 |
20794923962 ps |
| T802 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.4206529095 |
|
|
Mar 03 04:04:43 PM PST 24 |
Mar 03 04:15:47 PM PST 24 |
4855083040 ps |
| T1079 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.822620919 |
|
|
Mar 03 03:55:00 PM PST 24 |
Mar 03 04:11:08 PM PST 24 |
5283009426 ps |
| T1080 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.2946387255 |
|
|
Mar 03 04:02:29 PM PST 24 |
Mar 03 04:06:33 PM PST 24 |
3304986640 ps |
| T831 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3854222883 |
|
|
Mar 03 04:10:59 PM PST 24 |
Mar 03 04:21:03 PM PST 24 |
5263397268 ps |
| T1081 |
/workspace/coverage/default/2.chip_sw_power_idle_load.3476110878 |
|
|
Mar 03 04:02:19 PM PST 24 |
Mar 03 04:13:38 PM PST 24 |
4424383978 ps |
| T1082 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2051719666 |
|
|
Mar 03 03:47:43 PM PST 24 |
Mar 03 03:57:57 PM PST 24 |
4306675864 ps |
| T39 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.3433954773 |
|
|
Mar 03 03:46:47 PM PST 24 |
Mar 03 03:52:27 PM PST 24 |
3282059905 ps |
| T1083 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1005504902 |
|
|
Mar 03 03:45:12 PM PST 24 |
Mar 03 03:49:59 PM PST 24 |
3073152216 ps |
| T1084 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3978953230 |
|
|
Mar 03 03:48:01 PM PST 24 |
Mar 03 03:51:03 PM PST 24 |
2416761160 ps |
| T1085 |
/workspace/coverage/default/0.chip_sw_example_flash.2364174663 |
|
|
Mar 03 03:44:01 PM PST 24 |
Mar 03 03:47:06 PM PST 24 |
2891524138 ps |
| T1086 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.1620052680 |
|
|
Mar 03 03:48:51 PM PST 24 |
Mar 03 03:54:09 PM PST 24 |
2829751400 ps |
| T1087 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.883490287 |
|
|
Mar 03 03:59:39 PM PST 24 |
Mar 03 04:06:05 PM PST 24 |
3725466828 ps |
| T1088 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.567964351 |
|
|
Mar 03 03:46:58 PM PST 24 |
Mar 03 03:51:05 PM PST 24 |
2979983600 ps |
| T725 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.259397703 |
|
|
Mar 03 04:12:56 PM PST 24 |
Mar 03 04:19:18 PM PST 24 |
3296120200 ps |
| T1089 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3956325982 |
|
|
Mar 03 04:03:59 PM PST 24 |
Mar 03 04:09:53 PM PST 24 |
4774336795 ps |
| T1090 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1692990484 |
|
|
Mar 03 03:52:14 PM PST 24 |
Mar 03 04:07:03 PM PST 24 |
4839376568 ps |
| T1091 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2963034330 |
|
|
Mar 03 03:48:09 PM PST 24 |
Mar 03 07:22:34 PM PST 24 |
65332566345 ps |
| T1092 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3835778328 |
|
|
Mar 03 03:48:03 PM PST 24 |
Mar 03 03:52:26 PM PST 24 |
3010912917 ps |
| T1093 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2767688540 |
|
|
Mar 03 03:45:08 PM PST 24 |
Mar 03 03:50:25 PM PST 24 |
3870016280 ps |
| T1094 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1700716047 |
|
|
Mar 03 03:50:47 PM PST 24 |
Mar 03 04:18:52 PM PST 24 |
7318164096 ps |
| T1095 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.561929533 |
|
|
Mar 03 03:57:40 PM PST 24 |
Mar 03 05:22:24 PM PST 24 |
48436317664 ps |
| T301 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1601787922 |
|
|
Mar 03 03:55:09 PM PST 24 |
Mar 03 04:09:13 PM PST 24 |
4037210056 ps |
| T716 |
/workspace/coverage/default/0.rom_raw_unlock.2589529922 |
|
|
Mar 03 03:46:14 PM PST 24 |
Mar 03 04:24:04 PM PST 24 |
14903946627 ps |
| T1096 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.354145670 |
|
|
Mar 03 03:51:50 PM PST 24 |
Mar 03 03:57:40 PM PST 24 |
3355005744 ps |
| T247 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3705425061 |
|
|
Mar 03 03:46:05 PM PST 24 |
Mar 03 03:57:16 PM PST 24 |
4671607928 ps |
| T1097 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1621125552 |
|
|
Mar 03 04:03:31 PM PST 24 |
Mar 03 05:21:53 PM PST 24 |
23699887953 ps |
| T320 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2301583249 |
|
|
Mar 03 04:08:42 PM PST 24 |
Mar 03 04:14:43 PM PST 24 |
4185491160 ps |
| T1098 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.4175331309 |
|
|
Mar 03 03:52:39 PM PST 24 |
Mar 03 03:54:12 PM PST 24 |
1717384020 ps |
| T764 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.884141994 |
|
|
Mar 03 04:07:11 PM PST 24 |
Mar 03 04:17:03 PM PST 24 |
4183853376 ps |
| T1099 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2715881996 |
|
|
Mar 03 04:04:00 PM PST 24 |
Mar 03 04:12:17 PM PST 24 |
7370574077 ps |
| T273 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2076881899 |
|
|
Mar 03 04:00:36 PM PST 24 |
Mar 03 04:20:08 PM PST 24 |
5892915548 ps |
| T353 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2108957158 |
|
|
Mar 03 04:09:09 PM PST 24 |
Mar 03 04:19:29 PM PST 24 |
4517490928 ps |
| T1100 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.672451112 |
|
|
Mar 03 03:57:20 PM PST 24 |
Mar 03 05:33:31 PM PST 24 |
47068093394 ps |
| T1101 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.55175899 |
|
|
Mar 03 03:59:21 PM PST 24 |
Mar 03 04:04:56 PM PST 24 |
2901531334 ps |
| T279 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.1684584464 |
|
|
Mar 03 03:59:58 PM PST 24 |
Mar 03 04:10:41 PM PST 24 |
4063928420 ps |
| T1102 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3349539212 |
|
|
Mar 03 03:57:42 PM PST 24 |
Mar 03 04:05:01 PM PST 24 |
4289790554 ps |
| T1103 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.244917571 |
|
|
Mar 03 04:00:35 PM PST 24 |
Mar 03 04:45:29 PM PST 24 |
12927556174 ps |
| T286 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3496472467 |
|
|
Mar 03 03:42:20 PM PST 24 |
Mar 03 03:45:10 PM PST 24 |
2873952167 ps |
| T1104 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2171176638 |
|
|
Mar 03 04:04:19 PM PST 24 |
Mar 03 04:11:21 PM PST 24 |
3199482150 ps |
| T1105 |
/workspace/coverage/default/0.chip_sw_edn_kat.1019195924 |
|
|
Mar 03 03:43:44 PM PST 24 |
Mar 03 03:54:24 PM PST 24 |
3304429200 ps |
| T1106 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.792448567 |
|
|
Mar 03 03:54:51 PM PST 24 |
Mar 03 04:41:55 PM PST 24 |
23077905754 ps |
| T1107 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3168797225 |
|
|
Mar 03 03:51:55 PM PST 24 |
Mar 03 04:23:46 PM PST 24 |
9060279670 ps |
| T1108 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1447777719 |
|
|
Mar 03 03:52:27 PM PST 24 |
Mar 03 03:56:12 PM PST 24 |
2259002856 ps |
| T325 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2483184651 |
|
|
Mar 03 03:48:13 PM PST 24 |
Mar 03 03:50:16 PM PST 24 |
1876386430 ps |
| T718 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4097737952 |
|
|
Mar 03 03:46:40 PM PST 24 |
Mar 03 04:11:51 PM PST 24 |
21404996100 ps |
| T1109 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.466381800 |
|
|
Mar 03 04:01:08 PM PST 24 |
Mar 03 04:09:06 PM PST 24 |
3818261590 ps |
| T1110 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1883820161 |
|
|
Mar 03 03:50:49 PM PST 24 |
Mar 03 03:59:06 PM PST 24 |
4608948973 ps |
| T1111 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2771395024 |
|
|
Mar 03 03:53:13 PM PST 24 |
Mar 03 03:56:59 PM PST 24 |
2658930220 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1256350049 |
|
|
Mar 03 03:47:18 PM PST 24 |
Mar 03 03:51:25 PM PST 24 |
3417196520 ps |
| T1112 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2948099512 |
|
|
Mar 03 04:01:53 PM PST 24 |
Mar 03 04:08:28 PM PST 24 |
3866806707 ps |
| T1113 |
/workspace/coverage/default/1.rom_keymgr_functest.1163152738 |
|
|
Mar 03 03:53:44 PM PST 24 |
Mar 03 04:03:50 PM PST 24 |
4689439192 ps |
| T1114 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1345824518 |
|
|
Mar 03 04:03:26 PM PST 24 |
Mar 03 04:08:23 PM PST 24 |
2282995536 ps |
| T1115 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4264472244 |
|
|
Mar 03 03:53:17 PM PST 24 |
Mar 03 04:36:35 PM PST 24 |
9721512292 ps |
| T1116 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1583688371 |
|
|
Mar 03 03:53:40 PM PST 24 |
Mar 03 03:59:02 PM PST 24 |
5101521136 ps |
| T1117 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.313542799 |
|
|
Mar 03 04:03:34 PM PST 24 |
Mar 03 04:08:22 PM PST 24 |
3376384030 ps |
| T1118 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2960566128 |
|
|
Mar 03 04:04:24 PM PST 24 |
Mar 03 04:11:22 PM PST 24 |
6508691166 ps |
| T1119 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3781486379 |
|
|
Mar 03 04:02:35 PM PST 24 |
Mar 03 04:47:51 PM PST 24 |
23027477720 ps |
| T1120 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3290517461 |
|
|
Mar 03 04:04:39 PM PST 24 |
Mar 03 04:20:50 PM PST 24 |
6218772424 ps |
| T1121 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2594047283 |
|
|
Mar 03 03:56:14 PM PST 24 |
Mar 03 05:35:50 PM PST 24 |
47771037280 ps |
| T1122 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3558963717 |
|
|
Mar 03 03:47:02 PM PST 24 |
Mar 03 03:59:19 PM PST 24 |
5532314674 ps |
| T740 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3079172075 |
|
|
Mar 03 04:08:59 PM PST 24 |
Mar 03 04:14:56 PM PST 24 |
3480147450 ps |
| T1123 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1886314054 |
|
|
Mar 03 04:01:16 PM PST 24 |
Mar 03 04:13:00 PM PST 24 |
7903607980 ps |
| T271 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1386173420 |
|
|
Mar 03 03:46:39 PM PST 24 |
Mar 03 03:57:17 PM PST 24 |
3709756900 ps |
| T723 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1017209471 |
|
|
Mar 03 04:10:53 PM PST 24 |
Mar 03 04:19:52 PM PST 24 |
4746299956 ps |
| T680 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2536380561 |
|
|
Mar 03 03:51:39 PM PST 24 |
Mar 03 03:59:58 PM PST 24 |
5054441949 ps |
| T1124 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.995030767 |
|
|
Mar 03 03:43:43 PM PST 24 |
Mar 03 03:48:24 PM PST 24 |
2543662832 ps |
| T1125 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1171677726 |
|
|
Mar 03 03:46:16 PM PST 24 |
Mar 03 03:56:44 PM PST 24 |
7233456010 ps |
| T1126 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3481174374 |
|
|
Mar 03 03:47:39 PM PST 24 |
Mar 03 04:07:55 PM PST 24 |
9427279813 ps |
| T1127 |
/workspace/coverage/default/4.chip_tap_straps_rma.3068380584 |
|
|
Mar 03 04:09:24 PM PST 24 |
Mar 03 04:12:38 PM PST 24 |
2761080620 ps |
| T122 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2579538853 |
|
|
Mar 03 03:56:28 PM PST 24 |
Mar 03 03:58:36 PM PST 24 |
2112611470 ps |
| T1128 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1972672079 |
|
|
Mar 03 04:04:16 PM PST 24 |
Mar 03 04:40:33 PM PST 24 |
12986991960 ps |
| T1129 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.168356879 |
|
|
Mar 03 03:44:29 PM PST 24 |
Mar 03 07:32:25 PM PST 24 |
78153300995 ps |
| T1130 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.964956189 |
|
|
Mar 03 04:01:27 PM PST 24 |
Mar 03 04:10:08 PM PST 24 |
4207163816 ps |
| T93 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2551335030 |
|
|
Mar 03 04:02:44 PM PST 24 |
Mar 03 04:10:07 PM PST 24 |
7125174188 ps |
| T354 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677029953 |
|
|
Mar 03 04:09:45 PM PST 24 |
Mar 03 04:15:03 PM PST 24 |
3243149200 ps |
| T1131 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2760186415 |
|
|
Mar 03 03:51:10 PM PST 24 |
Mar 03 03:59:50 PM PST 24 |
4663371076 ps |
| T1132 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3779235131 |
|
|
Mar 03 03:45:45 PM PST 24 |
Mar 03 03:50:21 PM PST 24 |
3004098738 ps |
| T1133 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.4073897869 |
|
|
Mar 03 03:53:57 PM PST 24 |
Mar 03 04:24:34 PM PST 24 |
8693619378 ps |
| T69 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.1674321855 |
|
|
Mar 03 03:46:17 PM PST 24 |
Mar 03 03:51:33 PM PST 24 |
3608259314 ps |
| T1134 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1069787956 |
|
|
Mar 03 03:52:44 PM PST 24 |
Mar 03 03:56:52 PM PST 24 |
2789420236 ps |
| T1135 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.954392534 |
|
|
Mar 03 03:45:06 PM PST 24 |
Mar 03 03:52:57 PM PST 24 |
7659102188 ps |
| T275 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3560760778 |
|
|
Mar 03 03:47:32 PM PST 24 |
Mar 03 04:19:21 PM PST 24 |
7473894076 ps |
| T674 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.477270203 |
|
|
Mar 03 03:44:02 PM PST 24 |
Mar 03 04:47:38 PM PST 24 |
25185647539 ps |
| T1136 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2742843387 |
|
|
Mar 03 03:58:39 PM PST 24 |
Mar 03 04:39:16 PM PST 24 |
27582800576 ps |
| T1137 |
/workspace/coverage/default/2.chip_tap_straps_rma.3769063342 |
|
|
Mar 03 04:03:28 PM PST 24 |
Mar 03 04:11:54 PM PST 24 |
5130051166 ps |
| T248 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3768366211 |
|
|
Mar 03 03:59:58 PM PST 24 |
Mar 03 04:10:12 PM PST 24 |
5312220303 ps |
| T1138 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3807410545 |
|
|
Mar 03 04:02:16 PM PST 24 |
Mar 03 05:01:43 PM PST 24 |
18242888016 ps |
| T745 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3331993287 |
|
|
Mar 03 04:07:21 PM PST 24 |
Mar 03 04:14:12 PM PST 24 |
3431947256 ps |
| T790 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.303726617 |
|
|
Mar 03 04:07:09 PM PST 24 |
Mar 03 04:14:14 PM PST 24 |
3893838728 ps |
| T1139 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1122638258 |
|
|
Mar 03 04:00:09 PM PST 24 |
Mar 03 04:08:01 PM PST 24 |
3908209232 ps |
| T1140 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.1102293249 |
|
|
Mar 03 04:01:54 PM PST 24 |
Mar 03 04:17:22 PM PST 24 |
5470778398 ps |
| T1141 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.4109658136 |
|
|
Mar 03 03:48:29 PM PST 24 |
Mar 03 03:53:06 PM PST 24 |
2541577240 ps |
| T1142 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1493992150 |
|
|
Mar 03 03:46:30 PM PST 24 |
Mar 03 04:05:29 PM PST 24 |
5325631190 ps |
| T1143 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2934968038 |
|
|
Mar 03 03:42:17 PM PST 24 |
Mar 03 03:58:48 PM PST 24 |
8264794276 ps |
| T1144 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.100279498 |
|
|
Mar 03 03:49:23 PM PST 24 |
Mar 03 03:55:56 PM PST 24 |
5395413433 ps |
| T40 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.3254937529 |
|
|
Mar 03 03:43:56 PM PST 24 |
Mar 03 03:50:23 PM PST 24 |
3510305029 ps |
| T1145 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.2969746108 |
|
|
Mar 03 04:05:45 PM PST 24 |
Mar 03 04:15:15 PM PST 24 |
4485722088 ps |
| T1146 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.614627887 |
|
|
Mar 03 03:43:55 PM PST 24 |
Mar 03 03:51:20 PM PST 24 |
3989993591 ps |
| T1147 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.955533586 |
|
|
Mar 03 03:43:00 PM PST 24 |
Mar 03 04:03:44 PM PST 24 |
5470401925 ps |
| T1148 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2869619098 |
|
|
Mar 03 03:44:00 PM PST 24 |
Mar 03 03:54:20 PM PST 24 |
4758844832 ps |
| T1149 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3104057991 |
|
|
Mar 03 03:53:38 PM PST 24 |
Mar 03 03:57:24 PM PST 24 |
2221143772 ps |
| T1150 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.463653141 |
|
|
Mar 03 03:46:44 PM PST 24 |
Mar 03 03:52:53 PM PST 24 |
4538789656 ps |
| T1151 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.674393354 |
|
|
Mar 03 04:03:12 PM PST 24 |
Mar 03 04:08:17 PM PST 24 |
2534825720 ps |
| T199 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3633571861 |
|
|
Mar 03 03:35:48 PM PST 24 |
Mar 03 03:57:12 PM PST 24 |
10192989304 ps |
| T717 |
/workspace/coverage/default/2.rom_raw_unlock.2332134635 |
|
|
Mar 03 04:06:01 PM PST 24 |
Mar 03 04:38:47 PM PST 24 |
16543492978 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.869032967 |
|
|
Mar 03 03:45:19 PM PST 24 |
Mar 03 03:52:45 PM PST 24 |
4726710784 ps |
| T1153 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3939576664 |
|
|
Mar 03 04:11:11 PM PST 24 |
Mar 03 04:21:08 PM PST 24 |
5379310000 ps |
| T53 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.688581670 |
|
|
Mar 03 04:01:35 PM PST 24 |
Mar 03 04:23:25 PM PST 24 |
19395848466 ps |
| T1154 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.563597453 |
|
|
Mar 03 03:53:53 PM PST 24 |
Mar 03 03:57:51 PM PST 24 |
3338613200 ps |
| T1155 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1460712502 |
|
|
Mar 03 04:00:05 PM PST 24 |
Mar 03 04:11:06 PM PST 24 |
5406975000 ps |
| T1156 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3623128065 |
|
|
Mar 03 03:44:28 PM PST 24 |
Mar 03 03:54:36 PM PST 24 |
4545065688 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1611394924 |
|
|
Mar 03 03:49:33 PM PST 24 |
Mar 03 03:55:26 PM PST 24 |
3292460119 ps |
| T29 |
/workspace/coverage/default/2.chip_sw_gpio.1220315533 |
|
|
Mar 03 03:54:57 PM PST 24 |
Mar 03 04:02:14 PM PST 24 |
4198632916 ps |
| T249 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1813833645 |
|
|
Mar 03 04:00:12 PM PST 24 |
Mar 03 04:11:33 PM PST 24 |
4406799146 ps |
| T732 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2330360944 |
|
|
Mar 03 04:07:33 PM PST 24 |
Mar 03 04:19:05 PM PST 24 |
6113885320 ps |
| T1158 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2012427344 |
|
|
Mar 03 03:58:27 PM PST 24 |
Mar 03 04:03:10 PM PST 24 |
2393964956 ps |
| T339 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3570465290 |
|
|
Mar 03 03:48:30 PM PST 24 |
Mar 03 04:12:21 PM PST 24 |
21177156650 ps |
| T1159 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3312799555 |
|
|
Mar 03 03:47:04 PM PST 24 |
Mar 03 03:55:21 PM PST 24 |
4211787279 ps |
| T340 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3132008995 |
|
|
Mar 03 03:50:00 PM PST 24 |
Mar 03 03:56:57 PM PST 24 |
6974282150 ps |
| T734 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.928704978 |
|
|
Mar 03 04:11:11 PM PST 24 |
Mar 03 04:18:33 PM PST 24 |
3921351844 ps |
| T1160 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.2850474340 |
|
|
Mar 03 03:46:04 PM PST 24 |
Mar 03 03:49:43 PM PST 24 |
2290288280 ps |
| T1161 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2735828814 |
|
|
Mar 03 03:46:28 PM PST 24 |
Mar 03 04:03:48 PM PST 24 |
7156526088 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.712471999 |
|
|
Mar 03 03:47:05 PM PST 24 |
Mar 03 03:56:54 PM PST 24 |
4803572925 ps |
| T721 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2414968247 |
|
|
Mar 03 03:47:42 PM PST 24 |
Mar 03 04:40:37 PM PST 24 |
19917812761 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4182925199 |
|
|
Mar 03 04:03:55 PM PST 24 |
Mar 03 04:13:36 PM PST 24 |
4608768236 ps |
| T1163 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3033573008 |
|
|
Mar 03 03:46:36 PM PST 24 |
Mar 03 03:50:55 PM PST 24 |
3249612696 ps |
| T753 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382125971 |
|
|
Mar 03 04:08:32 PM PST 24 |
Mar 03 04:15:56 PM PST 24 |
3728501550 ps |
| T772 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3546782856 |
|
|
Mar 03 04:06:45 PM PST 24 |
Mar 03 04:14:00 PM PST 24 |
3901220400 ps |
| T735 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2761443892 |
|
|
Mar 03 04:10:50 PM PST 24 |
Mar 03 04:18:52 PM PST 24 |
5572079678 ps |
| T261 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3480267460 |
|
|
Mar 03 03:44:19 PM PST 24 |
Mar 03 03:47:36 PM PST 24 |
2789240164 ps |
| T1164 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2753308069 |
|
|
Mar 03 03:47:04 PM PST 24 |
Mar 03 04:30:59 PM PST 24 |
14750151548 ps |
| T344 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3398617546 |
|
|
Mar 03 03:43:10 PM PST 24 |
Mar 03 04:08:59 PM PST 24 |
22495084840 ps |
| T1165 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2771275033 |
|
|
Mar 03 04:02:29 PM PST 24 |
Mar 03 04:20:06 PM PST 24 |
7680757012 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2388283905 |
|
|
Mar 03 03:59:56 PM PST 24 |
Mar 03 04:26:52 PM PST 24 |
7377700888 ps |
| T1167 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1001178113 |
|
|
Mar 03 03:50:44 PM PST 24 |
Mar 03 03:58:25 PM PST 24 |
3024440248 ps |
| T30 |
/workspace/coverage/default/0.chip_sw_gpio.3118569137 |
|
|
Mar 03 03:44:30 PM PST 24 |
Mar 03 03:51:27 PM PST 24 |
3549660286 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1185712091 |
|
|
Mar 03 03:47:43 PM PST 24 |
Mar 03 04:11:42 PM PST 24 |
7635957874 ps |
| T70 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.541939450 |
|
|
Mar 03 03:43:51 PM PST 24 |
Mar 03 03:51:52 PM PST 24 |
3907895500 ps |
| T1169 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.564721113 |
|
|
Mar 03 03:47:48 PM PST 24 |
Mar 03 03:52:37 PM PST 24 |
3326603344 ps |
| T281 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3410036922 |
|
|
Mar 03 03:43:26 PM PST 24 |
Mar 03 03:52:33 PM PST 24 |
4305197592 ps |
| T1170 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.55041015 |
|
|
Mar 03 03:54:45 PM PST 24 |
Mar 03 04:11:48 PM PST 24 |
5559888092 ps |
| T775 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.245916726 |
|
|
Mar 03 04:14:07 PM PST 24 |
Mar 03 04:24:10 PM PST 24 |
6058050212 ps |
| T830 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.208023732 |
|
|
Mar 03 04:12:15 PM PST 24 |
Mar 03 04:19:20 PM PST 24 |
3602488910 ps |
| T1171 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2280309973 |
|
|
Mar 03 03:59:58 PM PST 24 |
Mar 03 04:08:21 PM PST 24 |
4292237058 ps |
| T1172 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2779349239 |
|
|
Mar 03 04:00:28 PM PST 24 |
Mar 03 04:14:11 PM PST 24 |
3631142184 ps |
| T1173 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3426737601 |
|
|
Mar 03 03:57:23 PM PST 24 |
Mar 03 04:01:51 PM PST 24 |
3493701620 ps |
| T1174 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4026131062 |
|
|
Mar 03 03:47:26 PM PST 24 |
Mar 03 04:12:50 PM PST 24 |
15794419408 ps |
| T1175 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3789485567 |
|
|
Mar 03 04:01:34 PM PST 24 |
Mar 03 04:15:33 PM PST 24 |
4644863400 ps |
| T1176 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1969927844 |
|
|
Mar 03 03:50:39 PM PST 24 |
Mar 03 04:39:37 PM PST 24 |
11736111288 ps |
| T832 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1542781806 |
|
|
Mar 03 04:06:16 PM PST 24 |
Mar 03 04:16:29 PM PST 24 |
4176863232 ps |
| T291 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1307515270 |
|
|
Mar 03 03:49:17 PM PST 24 |
Mar 03 03:59:11 PM PST 24 |
4184635752 ps |
| T369 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1033499840 |
|
|
Mar 03 03:43:50 PM PST 24 |
Mar 03 03:58:47 PM PST 24 |
4869866872 ps |
| T141 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3202080396 |
|
|
Mar 03 03:48:06 PM PST 24 |
Mar 03 04:40:12 PM PST 24 |
16047359372 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2838696076 |
|
|
Mar 03 04:02:53 PM PST 24 |
Mar 03 04:06:24 PM PST 24 |
3098823960 ps |
| T1178 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3698192844 |
|
|
Mar 03 04:10:42 PM PST 24 |
Mar 03 04:23:27 PM PST 24 |
5335906960 ps |
| T1179 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.240848908 |
|
|
Mar 03 03:58:11 PM PST 24 |
Mar 03 04:28:27 PM PST 24 |
11841077059 ps |
| T1180 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.272916231 |
|
|
Mar 03 03:45:25 PM PST 24 |
Mar 03 03:51:07 PM PST 24 |
3154141545 ps |
| T1181 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1607486732 |
|
|
Mar 03 03:47:19 PM PST 24 |
Mar 03 04:11:37 PM PST 24 |
6414174184 ps |
| T357 |
/workspace/coverage/default/1.chip_jtag_mem_access.1708515067 |
|
|
Mar 03 03:38:10 PM PST 24 |
Mar 03 04:00:51 PM PST 24 |
12855032056 ps |
| T1182 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.1386031809 |
|
|
Mar 03 03:52:47 PM PST 24 |
Mar 03 03:58:34 PM PST 24 |
3312327020 ps |
| T1183 |
/workspace/coverage/default/2.chip_tap_straps_prod.693821498 |
|
|
Mar 03 04:00:30 PM PST 24 |
Mar 03 04:12:03 PM PST 24 |
6304059770 ps |
| T829 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.763723328 |
|
|
Mar 03 04:09:03 PM PST 24 |
Mar 03 04:18:12 PM PST 24 |
4431355456 ps |
| T1184 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.4092176555 |
|
|
Mar 03 03:49:22 PM PST 24 |
Mar 03 04:08:53 PM PST 24 |
8938470088 ps |
| T56 |
/workspace/coverage/default/0.chip_sw_alert_test.1565582770 |
|
|
Mar 03 03:46:45 PM PST 24 |
Mar 03 03:50:48 PM PST 24 |
3296091420 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.1413232252 |
|
|
Mar 03 03:50:09 PM PST 24 |
Mar 03 04:52:37 PM PST 24 |
18713891320 ps |
| T1185 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1463040985 |
|
|
Mar 03 03:44:03 PM PST 24 |
Mar 03 03:48:46 PM PST 24 |
3314964844 ps |
| T1186 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1755868954 |
|
|
Mar 03 03:45:02 PM PST 24 |
Mar 03 03:54:42 PM PST 24 |
3724427320 ps |
| T309 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2148829821 |
|
|
Mar 03 03:44:45 PM PST 24 |
Mar 03 03:52:44 PM PST 24 |
3133075460 ps |
| T1187 |
/workspace/coverage/default/2.chip_sival_flash_info_access.275088156 |
|
|
Mar 03 03:53:00 PM PST 24 |
Mar 03 03:56:57 PM PST 24 |
2766567060 ps |
| T1188 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.173935392 |
|
|
Mar 03 03:57:32 PM PST 24 |
Mar 03 03:59:46 PM PST 24 |
2721901775 ps |
| T760 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.4009785566 |
|
|
Mar 03 04:08:31 PM PST 24 |
Mar 03 04:18:42 PM PST 24 |
4812439444 ps |
| T1189 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.688407666 |
|
|
Mar 03 03:49:09 PM PST 24 |
Mar 03 03:56:49 PM PST 24 |
3171193080 ps |
| T168 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.3878388425 |
|
|
Mar 03 03:45:37 PM PST 24 |
Mar 03 04:34:45 PM PST 24 |
11889826200 ps |
| T71 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3298665146 |
|
|
Mar 03 03:45:08 PM PST 24 |
Mar 03 05:40:52 PM PST 24 |
30942421240 ps |
| T1190 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1648694929 |
|
|
Mar 03 03:46:28 PM PST 24 |
Mar 03 04:41:01 PM PST 24 |
41462383250 ps |
| T277 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2456413704 |
|
|
Mar 03 03:46:18 PM PST 24 |
Mar 03 04:01:34 PM PST 24 |
5411038392 ps |
| T1191 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2594098701 |
|
|
Mar 03 03:48:00 PM PST 24 |
Mar 03 04:27:25 PM PST 24 |
8264495505 ps |
| T773 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3129668060 |
|
|
Mar 03 04:12:37 PM PST 24 |
Mar 03 04:20:44 PM PST 24 |
4366428338 ps |
| T1192 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1713444903 |
|
|
Mar 03 03:47:16 PM PST 24 |
Mar 03 03:51:07 PM PST 24 |
3122301660 ps |
| T1193 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2715552565 |
|
|
Mar 03 03:46:42 PM PST 24 |
Mar 03 03:58:13 PM PST 24 |
10825339032 ps |
| T688 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.443539379 |
|
|
Mar 03 04:04:36 PM PST 24 |
Mar 03 04:16:29 PM PST 24 |
6272560944 ps |
| T1194 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.627893835 |
|
|
Mar 03 03:47:53 PM PST 24 |
Mar 03 03:55:01 PM PST 24 |
4729501736 ps |
| T1195 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1926115692 |
|
|
Mar 03 04:01:29 PM PST 24 |
Mar 03 04:10:16 PM PST 24 |
4814619328 ps |
| T1196 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2076360767 |
|
|
Mar 03 03:47:08 PM PST 24 |
Mar 03 04:20:25 PM PST 24 |
8299530607 ps |
| T1197 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.761841182 |
|
|
Mar 03 04:05:24 PM PST 24 |
Mar 03 04:22:04 PM PST 24 |
5184086248 ps |
| T321 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2795552033 |
|
|
Mar 03 03:59:02 PM PST 24 |
Mar 03 04:08:04 PM PST 24 |
4181149472 ps |
| T754 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1017939033 |
|
|
Mar 03 04:09:16 PM PST 24 |
Mar 03 04:17:00 PM PST 24 |
3433170978 ps |
| T785 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.179385580 |
|
|
Mar 03 04:06:22 PM PST 24 |
Mar 03 04:12:55 PM PST 24 |
3993613400 ps |
| T811 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2948970588 |
|
|
Mar 03 04:09:42 PM PST 24 |
Mar 03 04:18:31 PM PST 24 |
4418871940 ps |
| T825 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2941554340 |
|
|
Mar 03 04:09:33 PM PST 24 |
Mar 03 04:20:18 PM PST 24 |
5635251616 ps |
| T805 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2958399445 |
|
|
Mar 03 04:09:48 PM PST 24 |
Mar 03 04:19:24 PM PST 24 |
4790430970 ps |
| T817 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909736852 |
|
|
Mar 03 04:05:59 PM PST 24 |
Mar 03 04:12:37 PM PST 24 |
3165744984 ps |
| T1198 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.4139067161 |
|
|
Mar 03 03:53:40 PM PST 24 |
Mar 03 04:30:52 PM PST 24 |
8533931401 ps |
| T1199 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2240436135 |
|
|
Mar 03 04:07:29 PM PST 24 |
Mar 03 04:19:14 PM PST 24 |
6307347008 ps |
| T1200 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1624499320 |
|
|
Mar 03 04:00:57 PM PST 24 |
Mar 03 04:22:59 PM PST 24 |
6645122228 ps |
| T1201 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2558673132 |
|
|
Mar 03 03:49:27 PM PST 24 |
Mar 03 03:54:14 PM PST 24 |
2848792844 ps |
| T1202 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1078811127 |
|
|
Mar 03 03:43:58 PM PST 24 |
Mar 03 03:45:41 PM PST 24 |
3065933661 ps |
| T355 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2187544931 |
|
|
Mar 03 04:08:17 PM PST 24 |
Mar 03 04:14:30 PM PST 24 |
3386305080 ps |
| T765 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3952881568 |
|
|
Mar 03 04:08:33 PM PST 24 |
Mar 03 04:16:29 PM PST 24 |
4111741496 ps |
| T1203 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1061936637 |
|
|
Mar 03 04:00:50 PM PST 24 |
Mar 03 04:10:02 PM PST 24 |
5741952443 ps |
| T1204 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2837771650 |
|
|
Mar 03 03:49:24 PM PST 24 |
Mar 03 03:57:43 PM PST 24 |
4006848020 ps |
| T1205 |
/workspace/coverage/default/2.chip_sw_aes_entropy.1544506973 |
|
|
Mar 03 04:03:12 PM PST 24 |
Mar 03 04:08:28 PM PST 24 |
3188676860 ps |
| T1206 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2312965409 |
|
|
Mar 03 03:49:03 PM PST 24 |
Mar 03 04:22:28 PM PST 24 |
9115589073 ps |
| T37 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.630152952 |
|
|
Mar 03 03:55:37 PM PST 24 |
Mar 03 04:00:29 PM PST 24 |
3406118536 ps |
| T48 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3602822403 |
|
|
Mar 03 04:01:15 PM PST 24 |
Mar 03 04:07:17 PM PST 24 |
3286457400 ps |
| T1207 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1862323902 |
|
|
Mar 03 04:05:34 PM PST 24 |
Mar 03 04:20:02 PM PST 24 |
5975440900 ps |
| T1208 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1614999251 |
|
|
Mar 03 03:46:04 PM PST 24 |
Mar 03 04:01:12 PM PST 24 |
10113110084 ps |
| T205 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3202307271 |
|
|
Mar 03 04:01:56 PM PST 24 |
Mar 03 04:55:32 PM PST 24 |
14118974852 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.1490964958 |
|
|
Mar 03 03:45:00 PM PST 24 |
Mar 03 04:07:22 PM PST 24 |
5953028760 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2764456243 |
|
|
Mar 03 03:49:41 PM PST 24 |
Mar 03 04:01:41 PM PST 24 |
4448681158 ps |
| T1211 |
/workspace/coverage/default/4.chip_tap_straps_dev.546949607 |
|
|
Mar 03 04:09:35 PM PST 24 |
Mar 03 04:12:16 PM PST 24 |
2921818515 ps |
| T1212 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3979724057 |
|
|
Mar 03 04:06:27 PM PST 24 |
Mar 03 04:34:44 PM PST 24 |
8535805803 ps |
| T110 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.3624800109 |
|
|
Mar 03 04:00:01 PM PST 24 |
Mar 03 04:10:19 PM PST 24 |
3906154872 ps |
| T1213 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.136413971 |
|
|
Mar 03 04:01:30 PM PST 24 |
Mar 03 04:08:27 PM PST 24 |
4549999342 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2251287090 |
|
|
Mar 03 03:46:21 PM PST 24 |
Mar 03 03:54:27 PM PST 24 |
4415046792 ps |
| T1215 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1255501733 |
|
|
Mar 03 04:05:23 PM PST 24 |
Mar 03 05:05:14 PM PST 24 |
23315668588 ps |
| T1216 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.95684166 |
|
|
Mar 03 03:47:39 PM PST 24 |
Mar 03 03:53:34 PM PST 24 |
3503340628 ps |
| T1217 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2529827358 |
|
|
Mar 03 03:57:56 PM PST 24 |
Mar 03 04:12:33 PM PST 24 |
5964350012 ps |
| T276 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2686886324 |
|
|
Mar 03 04:00:56 PM PST 24 |
Mar 03 04:29:57 PM PST 24 |
7605133986 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.1650259545 |
|
|
Mar 03 03:57:18 PM PST 24 |
Mar 03 04:32:51 PM PST 24 |
9145054924 ps |
| T1219 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1120140302 |
|
|
Mar 03 03:48:32 PM PST 24 |
Mar 03 04:15:36 PM PST 24 |
13164659868 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1762272487 |
|
|
Mar 03 03:44:49 PM PST 24 |
Mar 03 03:57:43 PM PST 24 |
5299344205 ps |
| T1221 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2403643890 |
|
|
Mar 03 04:10:51 PM PST 24 |
Mar 03 04:24:35 PM PST 24 |
5448699260 ps |
| T1222 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3403543022 |
|
|
Mar 03 03:53:09 PM PST 24 |
Mar 03 03:58:00 PM PST 24 |
2542678466 ps |
| T727 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3441736762 |
|
|
Mar 03 04:07:02 PM PST 24 |
Mar 03 04:16:11 PM PST 24 |
4638029112 ps |
| T1223 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2727721722 |
|
|
Mar 03 04:04:20 PM PST 24 |
Mar 03 04:11:38 PM PST 24 |
4325596350 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.140857305 |
|
|
Mar 03 03:45:41 PM PST 24 |
Mar 03 04:19:12 PM PST 24 |
15103241976 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.10991600 |
|
|
Mar 03 03:46:33 PM PST 24 |
Mar 03 03:54:56 PM PST 24 |
5367208860 ps |
| T1226 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3594623293 |
|
|
Mar 03 03:59:02 PM PST 24 |
Mar 03 04:08:02 PM PST 24 |
6465807128 ps |
| T159 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1656765878 |
|
|
Mar 03 03:46:28 PM PST 24 |
Mar 03 03:52:54 PM PST 24 |
5525486312 ps |
| T1227 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1473798959 |
|
|
Mar 03 03:48:33 PM PST 24 |
Mar 03 03:55:57 PM PST 24 |
8901811916 ps |
| T782 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.778599357 |
|
|
Mar 03 04:10:26 PM PST 24 |
Mar 03 04:16:10 PM PST 24 |
3564896500 ps |