| T1228 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2904051372 |
|
|
Mar 03 04:04:41 PM PST 24 |
Mar 03 04:13:49 PM PST 24 |
6067627961 ps |
| T1229 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2591050564 |
|
|
Mar 03 03:43:23 PM PST 24 |
Mar 03 04:11:13 PM PST 24 |
32155343338 ps |
| T778 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.1715338601 |
|
|
Mar 03 04:05:49 PM PST 24 |
Mar 03 04:17:11 PM PST 24 |
4473731848 ps |
| T1230 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.670317191 |
|
|
Mar 03 04:02:28 PM PST 24 |
Mar 03 04:05:56 PM PST 24 |
3159680391 ps |
| T111 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.627859908 |
|
|
Mar 03 03:51:29 PM PST 24 |
Mar 03 03:59:48 PM PST 24 |
3582153072 ps |
| T1231 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2195028962 |
|
|
Mar 03 03:48:26 PM PST 24 |
Mar 03 04:17:19 PM PST 24 |
7824368716 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3795521843 |
|
|
Mar 03 03:57:21 PM PST 24 |
Mar 03 04:06:52 PM PST 24 |
4083722055 ps |
| T1233 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1946417973 |
|
|
Mar 03 04:04:52 PM PST 24 |
Mar 03 04:13:09 PM PST 24 |
3306083626 ps |
| T1234 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.4250579539 |
|
|
Mar 03 03:48:00 PM PST 24 |
Mar 03 04:04:09 PM PST 24 |
6084846589 ps |
| T1235 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.820446616 |
|
|
Mar 03 03:56:48 PM PST 24 |
Mar 03 04:29:57 PM PST 24 |
25235690605 ps |
| T1236 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1822699852 |
|
|
Mar 03 03:54:52 PM PST 24 |
Mar 03 04:34:18 PM PST 24 |
14854717997 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3999390084 |
|
|
Mar 03 03:45:34 PM PST 24 |
Mar 03 06:50:18 PM PST 24 |
65367421882 ps |
| T1238 |
/workspace/coverage/default/1.chip_sw_example_rom.2597917649 |
|
|
Mar 03 03:45:14 PM PST 24 |
Mar 03 03:47:05 PM PST 24 |
2619700200 ps |
| T1239 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3533788741 |
|
|
Mar 03 03:44:32 PM PST 24 |
Mar 03 04:00:44 PM PST 24 |
5671928348 ps |
| T804 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3042040739 |
|
|
Mar 03 04:08:27 PM PST 24 |
Mar 03 04:21:49 PM PST 24 |
6044926192 ps |
| T1240 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3825268061 |
|
|
Mar 03 03:46:20 PM PST 24 |
Mar 03 03:51:20 PM PST 24 |
2884141320 ps |
| T49 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2289155541 |
|
|
Mar 03 03:46:14 PM PST 24 |
Mar 03 03:50:39 PM PST 24 |
3509847912 ps |
| T1241 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.4143890250 |
|
|
Mar 03 03:45:02 PM PST 24 |
Mar 03 03:52:42 PM PST 24 |
6263776263 ps |
| T1242 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2630757695 |
|
|
Mar 03 03:46:54 PM PST 24 |
Mar 03 04:46:04 PM PST 24 |
18651299727 ps |
| T1243 |
/workspace/coverage/default/1.chip_sw_aes_entropy.1183130454 |
|
|
Mar 03 03:47:17 PM PST 24 |
Mar 03 03:51:10 PM PST 24 |
2853950052 ps |
| T1244 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.266503858 |
|
|
Mar 03 04:06:46 PM PST 24 |
Mar 03 04:43:17 PM PST 24 |
13590243208 ps |
| T1245 |
/workspace/coverage/default/1.chip_sw_kmac_idle.317915549 |
|
|
Mar 03 03:46:21 PM PST 24 |
Mar 03 03:50:54 PM PST 24 |
3533788120 ps |
| T730 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1499654994 |
|
|
Mar 03 04:07:20 PM PST 24 |
Mar 03 04:14:51 PM PST 24 |
3285159592 ps |
| T1246 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2247181469 |
|
|
Mar 03 03:46:10 PM PST 24 |
Mar 03 04:26:53 PM PST 24 |
24607943360 ps |
| T1247 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2899524879 |
|
|
Mar 03 03:48:16 PM PST 24 |
Mar 03 03:55:15 PM PST 24 |
5192024960 ps |
| T82 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.1633040880 |
|
|
Mar 03 04:10:10 PM PST 24 |
Mar 03 04:22:53 PM PST 24 |
6219047260 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.4015646307 |
|
|
Mar 03 03:46:28 PM PST 24 |
Mar 03 03:49:03 PM PST 24 |
1909305190 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1065163796 |
|
|
Mar 03 03:45:04 PM PST 24 |
Mar 03 03:52:55 PM PST 24 |
6598227952 ps |
| T368 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2743249589 |
|
|
Mar 03 03:56:01 PM PST 24 |
Mar 03 04:11:30 PM PST 24 |
4744487974 ps |
| T1249 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2836433690 |
|
|
Mar 03 03:49:10 PM PST 24 |
Mar 03 03:55:34 PM PST 24 |
4667622375 ps |
| T1250 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2520493760 |
|
|
Mar 03 03:42:16 PM PST 24 |
Mar 03 03:45:55 PM PST 24 |
4004964454 ps |
| T1251 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3090516203 |
|
|
Mar 03 03:47:18 PM PST 24 |
Mar 03 03:51:54 PM PST 24 |
2707937288 ps |
| T1252 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.169472757 |
|
|
Mar 03 03:48:39 PM PST 24 |
Mar 03 03:52:49 PM PST 24 |
2685882650 ps |
| T826 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.131225521 |
|
|
Mar 03 04:07:19 PM PST 24 |
Mar 03 04:17:36 PM PST 24 |
4567483538 ps |
| T1253 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.618986420 |
|
|
Mar 03 03:45:16 PM PST 24 |
Mar 03 04:22:30 PM PST 24 |
21238616247 ps |
| T1254 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1493495596 |
|
|
Mar 03 03:50:13 PM PST 24 |
Mar 03 03:56:47 PM PST 24 |
3854570591 ps |
| T1255 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.799105692 |
|
|
Mar 03 03:45:12 PM PST 24 |
Mar 03 03:59:53 PM PST 24 |
5636414144 ps |
| T761 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1699426252 |
|
|
Mar 03 04:07:03 PM PST 24 |
Mar 03 04:17:26 PM PST 24 |
5904975240 ps |
| T1256 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.242907904 |
|
|
Mar 03 03:58:30 PM PST 24 |
Mar 03 04:03:07 PM PST 24 |
3129050287 ps |
| T1257 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1686685860 |
|
|
Mar 03 03:54:47 PM PST 24 |
Mar 03 06:50:50 PM PST 24 |
58077006528 ps |
| T1258 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1487862717 |
|
|
Mar 03 03:58:27 PM PST 24 |
Mar 03 04:12:14 PM PST 24 |
5951916764 ps |
| T1259 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1170110305 |
|
|
Mar 03 04:07:32 PM PST 24 |
Mar 03 04:37:39 PM PST 24 |
8583731360 ps |
| T1260 |
/workspace/coverage/default/1.chip_sw_power_idle_load.3604943410 |
|
|
Mar 03 03:51:12 PM PST 24 |
Mar 03 04:03:56 PM PST 24 |
3859755904 ps |
| T231 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.3999652739 |
|
|
Mar 03 04:05:28 PM PST 24 |
Mar 03 04:14:28 PM PST 24 |
5298202056 ps |
| T1261 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3675751837 |
|
|
Mar 03 04:09:02 PM PST 24 |
Mar 03 04:22:00 PM PST 24 |
5838511596 ps |
| T1262 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3607564191 |
|
|
Mar 03 03:48:28 PM PST 24 |
Mar 03 04:16:50 PM PST 24 |
7087136120 ps |
| T1263 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.2705591069 |
|
|
Mar 03 03:54:48 PM PST 24 |
Mar 03 03:58:48 PM PST 24 |
2614589680 ps |
| T1264 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3764967266 |
|
|
Mar 03 03:45:07 PM PST 24 |
Mar 03 03:52:03 PM PST 24 |
4787979288 ps |
| T1265 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3905965620 |
|
|
Mar 03 03:43:52 PM PST 24 |
Mar 03 03:52:01 PM PST 24 |
3881019252 ps |
| T1266 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.672282596 |
|
|
Mar 03 04:11:21 PM PST 24 |
Mar 03 04:17:34 PM PST 24 |
3754564354 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.4104086402 |
|
|
Mar 03 03:59:32 PM PST 24 |
Mar 03 04:17:14 PM PST 24 |
6076060032 ps |
| T1268 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3764050226 |
|
|
Mar 03 03:46:30 PM PST 24 |
Mar 03 03:49:32 PM PST 24 |
2661817980 ps |
| T809 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2824410226 |
|
|
Mar 03 04:10:22 PM PST 24 |
Mar 03 04:25:42 PM PST 24 |
5337018904 ps |
| T770 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1317176470 |
|
|
Mar 03 04:09:21 PM PST 24 |
Mar 03 04:16:48 PM PST 24 |
3847426088 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2643847945 |
|
|
Mar 03 03:46:01 PM PST 24 |
Mar 03 04:00:25 PM PST 24 |
10733648382 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4165453669 |
|
|
Mar 03 03:55:41 PM PST 24 |
Mar 03 04:06:24 PM PST 24 |
3908196856 ps |
| T799 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.836235739 |
|
|
Mar 03 04:06:45 PM PST 24 |
Mar 03 04:18:47 PM PST 24 |
5194876288 ps |
| T1271 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3782529199 |
|
|
Mar 03 03:42:56 PM PST 24 |
Mar 03 03:51:08 PM PST 24 |
5176785208 ps |
| T1272 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.87137445 |
|
|
Mar 03 03:46:40 PM PST 24 |
Mar 03 03:51:53 PM PST 24 |
2945967686 ps |
| T767 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1363321612 |
|
|
Mar 03 04:09:28 PM PST 24 |
Mar 03 04:22:27 PM PST 24 |
4747267400 ps |
| T1273 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1972609099 |
|
|
Mar 03 04:05:00 PM PST 24 |
Mar 03 04:43:26 PM PST 24 |
14376713682 ps |
| T227 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3449512505 |
|
|
Mar 03 03:43:52 PM PST 24 |
Mar 03 03:50:45 PM PST 24 |
5057312568 ps |
| T348 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3788133037 |
|
|
Mar 03 03:46:30 PM PST 24 |
Mar 03 03:51:40 PM PST 24 |
3627699320 ps |
| T821 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.351000823 |
|
|
Mar 03 04:07:37 PM PST 24 |
Mar 03 04:16:22 PM PST 24 |
4882847464 ps |
| T1274 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1269478688 |
|
|
Mar 03 04:05:08 PM PST 24 |
Mar 03 04:19:12 PM PST 24 |
11690958644 ps |
| T1275 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2801424956 |
|
|
Mar 03 04:10:53 PM PST 24 |
Mar 03 04:22:33 PM PST 24 |
6149032180 ps |
| T1276 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2230826416 |
|
|
Mar 03 04:07:13 PM PST 24 |
Mar 03 04:21:41 PM PST 24 |
5885410838 ps |
| T771 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3888527765 |
|
|
Mar 03 04:06:49 PM PST 24 |
Mar 03 04:12:59 PM PST 24 |
3965434816 ps |
| T1277 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.788946633 |
|
|
Mar 03 04:06:38 PM PST 24 |
Mar 03 04:30:53 PM PST 24 |
7091257840 ps |
| T1278 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1648323331 |
|
|
Mar 03 03:57:04 PM PST 24 |
Mar 03 04:09:27 PM PST 24 |
4109782355 ps |
| T1279 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.3877508284 |
|
|
Mar 03 03:54:34 PM PST 24 |
Mar 03 04:32:45 PM PST 24 |
9300261923 ps |
| T1280 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.404732123 |
|
|
Mar 03 03:49:03 PM PST 24 |
Mar 03 03:57:10 PM PST 24 |
4452863564 ps |
| T1281 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.275212181 |
|
|
Mar 03 03:47:23 PM PST 24 |
Mar 03 03:53:45 PM PST 24 |
4923005060 ps |
| T1282 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1630866751 |
|
|
Mar 03 04:08:35 PM PST 24 |
Mar 03 04:16:20 PM PST 24 |
4122634290 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_flash_init.3426102416 |
|
|
Mar 03 03:47:15 PM PST 24 |
Mar 03 04:20:15 PM PST 24 |
15555235160 ps |
| T1284 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.178142887 |
|
|
Mar 03 03:45:20 PM PST 24 |
Mar 03 04:33:04 PM PST 24 |
12079927602 ps |
| T1285 |
/workspace/coverage/default/0.chip_tap_straps_prod.2759045850 |
|
|
Mar 03 03:49:13 PM PST 24 |
Mar 03 03:51:38 PM PST 24 |
1877174007 ps |
| T1286 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1358854370 |
|
|
Mar 03 03:45:57 PM PST 24 |
Mar 03 04:03:04 PM PST 24 |
5121703048 ps |
| T1287 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.815045199 |
|
|
Mar 03 04:06:14 PM PST 24 |
Mar 03 04:12:04 PM PST 24 |
3521043440 ps |
| T1288 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.1889526007 |
|
|
Mar 03 03:47:24 PM PST 24 |
Mar 03 03:51:34 PM PST 24 |
2824521192 ps |
| T1289 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3049926720 |
|
|
Mar 03 03:58:36 PM PST 24 |
Mar 03 04:08:39 PM PST 24 |
3948310004 ps |
| T1290 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1636978677 |
|
|
Mar 03 03:45:00 PM PST 24 |
Mar 03 03:50:24 PM PST 24 |
2905774549 ps |
| T1291 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1435065647 |
|
|
Mar 03 04:01:30 PM PST 24 |
Mar 03 04:12:02 PM PST 24 |
4176438392 ps |
| T1292 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.230048813 |
|
|
Mar 03 03:55:51 PM PST 24 |
Mar 03 04:19:15 PM PST 24 |
8290084272 ps |
| T1293 |
/workspace/coverage/default/2.chip_sw_kmac_idle.948601831 |
|
|
Mar 03 03:59:48 PM PST 24 |
Mar 03 04:04:04 PM PST 24 |
2680516692 ps |
| T1294 |
/workspace/coverage/default/3.chip_tap_straps_dev.1915273070 |
|
|
Mar 03 04:03:04 PM PST 24 |
Mar 03 04:07:42 PM PST 24 |
3140020725 ps |
| T1295 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.2187894555 |
|
|
Mar 03 03:43:04 PM PST 24 |
Mar 03 03:47:36 PM PST 24 |
2804666512 ps |
| T1296 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2476068835 |
|
|
Mar 03 03:49:34 PM PST 24 |
Mar 03 03:53:35 PM PST 24 |
2507091038 ps |
| T759 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1075039809 |
|
|
Mar 03 04:10:08 PM PST 24 |
Mar 03 04:22:59 PM PST 24 |
5088120288 ps |
| T1297 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1317001843 |
|
|
Mar 03 03:54:59 PM PST 24 |
Mar 03 07:01:08 PM PST 24 |
66108663614 ps |
| T1298 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2341646720 |
|
|
Mar 03 03:50:55 PM PST 24 |
Mar 03 04:06:54 PM PST 24 |
9156600880 ps |
| T1299 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.967890949 |
|
|
Mar 03 04:12:16 PM PST 24 |
Mar 03 04:19:38 PM PST 24 |
4046607504 ps |
| T1300 |
/workspace/coverage/default/2.chip_sw_example_rom.3484583028 |
|
|
Mar 03 03:52:03 PM PST 24 |
Mar 03 03:53:59 PM PST 24 |
2502978552 ps |
| T807 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2661254729 |
|
|
Mar 03 04:09:03 PM PST 24 |
Mar 03 04:19:05 PM PST 24 |
5018010220 ps |
| T1301 |
/workspace/coverage/default/2.chip_tap_straps_dev.3449952846 |
|
|
Mar 03 04:00:45 PM PST 24 |
Mar 03 04:03:16 PM PST 24 |
2408448083 ps |
| T827 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2420032924 |
|
|
Mar 03 04:05:31 PM PST 24 |
Mar 03 04:13:16 PM PST 24 |
3037713626 ps |
| T1302 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2231003332 |
|
|
Mar 03 03:47:00 PM PST 24 |
Mar 03 04:06:50 PM PST 24 |
5256105944 ps |
| T768 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.1370606691 |
|
|
Mar 03 04:06:06 PM PST 24 |
Mar 03 04:18:45 PM PST 24 |
5329388944 ps |
| T1303 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.2747561117 |
|
|
Mar 03 03:47:54 PM PST 24 |
Mar 03 03:51:27 PM PST 24 |
2329880648 ps |
| T793 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.4098049518 |
|
|
Mar 03 04:05:51 PM PST 24 |
Mar 03 04:14:38 PM PST 24 |
5033401384 ps |
| T1304 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1440397216 |
|
|
Mar 03 03:49:32 PM PST 24 |
Mar 03 04:26:47 PM PST 24 |
9166100020 ps |
| T1305 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3126179612 |
|
|
Mar 03 03:46:22 PM PST 24 |
Mar 03 04:10:10 PM PST 24 |
8924679722 ps |
| T681 |
/workspace/coverage/default/0.chip_tap_straps_dev.3600279157 |
|
|
Mar 03 03:45:01 PM PST 24 |
Mar 03 04:00:09 PM PST 24 |
7828701855 ps |
| T1306 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.301617033 |
|
|
Mar 03 03:46:39 PM PST 24 |
Mar 03 03:59:21 PM PST 24 |
5577934004 ps |
| T50 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3970038706 |
|
|
Mar 03 03:54:53 PM PST 24 |
Mar 03 03:59:20 PM PST 24 |
3027492970 ps |
| T1307 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1645286868 |
|
|
Mar 03 03:46:07 PM PST 24 |
Mar 03 03:54:45 PM PST 24 |
4665155020 ps |
| T232 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.654336168 |
|
|
Mar 03 03:46:24 PM PST 24 |
Mar 03 03:54:05 PM PST 24 |
4170751154 ps |
| T1308 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.4262679152 |
|
|
Mar 03 03:48:33 PM PST 24 |
Mar 03 04:08:24 PM PST 24 |
4908800250 ps |
| T1309 |
/workspace/coverage/default/2.rom_e2e_static_critical.3022763667 |
|
|
Mar 03 04:05:17 PM PST 24 |
Mar 03 04:43:47 PM PST 24 |
11305124796 ps |
| T1310 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1565756975 |
|
|
Mar 03 03:47:38 PM PST 24 |
Mar 03 04:10:23 PM PST 24 |
8448641260 ps |
| T813 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.432751531 |
|
|
Mar 03 04:10:37 PM PST 24 |
Mar 03 04:20:25 PM PST 24 |
5461912556 ps |
| T219 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.782408984 |
|
|
Mar 03 04:05:28 PM PST 24 |
Mar 03 04:15:13 PM PST 24 |
5401224844 ps |
| T251 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.656512297 |
|
|
Mar 03 03:51:26 PM PST 24 |
Mar 03 03:56:00 PM PST 24 |
2404477169 ps |
| T252 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3526017788 |
|
|
Mar 03 04:10:51 PM PST 24 |
Mar 03 04:21:14 PM PST 24 |
5371738456 ps |
| T253 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2383744954 |
|
|
Mar 03 03:51:26 PM PST 24 |
Mar 03 04:01:26 PM PST 24 |
4625071833 ps |
| T254 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.364515456 |
|
|
Mar 03 03:50:24 PM PST 24 |
Mar 03 04:04:08 PM PST 24 |
4828932470 ps |
| T255 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1818119472 |
|
|
Mar 03 03:58:07 PM PST 24 |
Mar 03 04:09:30 PM PST 24 |
5105778736 ps |
| T256 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2065163406 |
|
|
Mar 03 03:49:30 PM PST 24 |
Mar 03 03:59:01 PM PST 24 |
4852503496 ps |
| T257 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2469480259 |
|
|
Mar 03 03:45:55 PM PST 24 |
Mar 03 03:57:05 PM PST 24 |
4878879080 ps |
| T258 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1054961906 |
|
|
Mar 03 03:52:16 PM PST 24 |
Mar 03 04:38:04 PM PST 24 |
16115344836 ps |
| T259 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1853335470 |
|
|
Mar 03 04:04:38 PM PST 24 |
Mar 03 04:12:17 PM PST 24 |
3771313672 ps |
| T1311 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1072400129 |
|
|
Mar 03 03:50:17 PM PST 24 |
Mar 03 04:04:56 PM PST 24 |
6014556878 ps |
| T1312 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1450814353 |
|
|
Mar 03 03:53:26 PM PST 24 |
Mar 03 03:58:18 PM PST 24 |
2849673884 ps |
| T719 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2599897755 |
|
|
Mar 03 03:46:08 PM PST 24 |
Mar 03 04:11:02 PM PST 24 |
21442393528 ps |
| T1313 |
/workspace/coverage/default/0.rom_e2e_smoke.4233212601 |
|
|
Mar 03 03:47:21 PM PST 24 |
Mar 03 04:25:33 PM PST 24 |
9235407396 ps |
| T1314 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3495871831 |
|
|
Mar 03 03:51:48 PM PST 24 |
Mar 03 03:57:41 PM PST 24 |
3690235194 ps |
| T1315 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2603241746 |
|
|
Mar 03 04:06:47 PM PST 24 |
Mar 03 04:22:47 PM PST 24 |
10248960185 ps |
| T800 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2529915755 |
|
|
Mar 03 04:12:58 PM PST 24 |
Mar 03 04:21:43 PM PST 24 |
4182785318 ps |
| T57 |
/workspace/coverage/default/1.chip_sw_alert_test.1063276460 |
|
|
Mar 03 03:47:28 PM PST 24 |
Mar 03 03:53:36 PM PST 24 |
2964157852 ps |
| T1316 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.495425372 |
|
|
Mar 03 03:48:16 PM PST 24 |
Mar 03 04:26:41 PM PST 24 |
22542445596 ps |
| T220 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.2212123549 |
|
|
Mar 03 03:55:09 PM PST 24 |
Mar 03 04:05:23 PM PST 24 |
5039235270 ps |
| T1317 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2974725693 |
|
|
Mar 03 04:05:33 PM PST 24 |
Mar 03 04:19:45 PM PST 24 |
11420636301 ps |
| T1318 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2199059832 |
|
|
Mar 03 03:42:17 PM PST 24 |
Mar 03 03:47:52 PM PST 24 |
8926772872 ps |
| T1319 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2552391252 |
|
|
Mar 03 03:44:42 PM PST 24 |
Mar 03 03:48:45 PM PST 24 |
3262323824 ps |
| T1320 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2640136777 |
|
|
Mar 03 03:47:57 PM PST 24 |
Mar 03 04:20:19 PM PST 24 |
9421166478 ps |
| T783 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3678830805 |
|
|
Mar 03 04:06:40 PM PST 24 |
Mar 03 04:17:15 PM PST 24 |
4848584376 ps |
| T1321 |
/workspace/coverage/default/1.chip_tap_straps_prod.3869667512 |
|
|
Mar 03 03:52:55 PM PST 24 |
Mar 03 04:18:43 PM PST 24 |
12374289449 ps |
| T1322 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.327897833 |
|
|
Mar 03 03:55:12 PM PST 24 |
Mar 03 04:02:53 PM PST 24 |
3850387692 ps |
| T1323 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.4294051789 |
|
|
Mar 03 03:45:12 PM PST 24 |
Mar 03 04:54:32 PM PST 24 |
17039481514 ps |
| T1324 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.2693946151 |
|
|
Mar 03 03:46:45 PM PST 24 |
Mar 03 04:00:01 PM PST 24 |
6385257192 ps |
| T317 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2475622947 |
|
|
Mar 03 03:45:21 PM PST 24 |
Mar 03 03:53:05 PM PST 24 |
6518448430 ps |
| T1325 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3464115008 |
|
|
Mar 03 04:04:56 PM PST 24 |
Mar 03 04:11:26 PM PST 24 |
3391075612 ps |
| T1326 |
/workspace/coverage/default/2.chip_sw_aes_idle.1850793178 |
|
|
Mar 03 04:00:05 PM PST 24 |
Mar 03 04:03:59 PM PST 24 |
3237901256 ps |
| T795 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1531771304 |
|
|
Mar 03 04:07:07 PM PST 24 |
Mar 03 04:16:35 PM PST 24 |
4029802992 ps |
| T1327 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1254805905 |
|
|
Mar 03 04:01:07 PM PST 24 |
Mar 03 04:11:26 PM PST 24 |
3956355384 ps |
| T1328 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.645502328 |
|
|
Mar 03 03:47:34 PM PST 24 |
Mar 03 03:53:34 PM PST 24 |
3450582120 ps |
| T1329 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.64896942 |
|
|
Mar 03 03:59:40 PM PST 24 |
Mar 03 04:05:10 PM PST 24 |
2820032877 ps |
| T1330 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.247927957 |
|
|
Mar 03 03:56:35 PM PST 24 |
Mar 03 04:01:48 PM PST 24 |
3872185170 ps |
| T755 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2974713561 |
|
|
Mar 03 04:09:55 PM PST 24 |
Mar 03 04:19:46 PM PST 24 |
5136442618 ps |
| T1331 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.1518954323 |
|
|
Mar 03 04:06:56 PM PST 24 |
Mar 03 04:16:14 PM PST 24 |
5343083694 ps |
| T1332 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1753301637 |
|
|
Mar 03 03:49:23 PM PST 24 |
Mar 03 04:05:48 PM PST 24 |
5714634200 ps |
| T1333 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.3156161455 |
|
|
Mar 03 03:52:33 PM PST 24 |
Mar 03 03:57:50 PM PST 24 |
3254593720 ps |
| T1334 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4159466590 |
|
|
Mar 03 03:47:57 PM PST 24 |
Mar 03 03:54:07 PM PST 24 |
3087278760 ps |
| T1335 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1664579983 |
|
|
Mar 03 04:02:15 PM PST 24 |
Mar 03 04:12:45 PM PST 24 |
5582719673 ps |
| T1336 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.867217381 |
|
|
Mar 03 03:54:00 PM PST 24 |
Mar 03 04:10:05 PM PST 24 |
5797060398 ps |
| T1337 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1978382274 |
|
|
Mar 03 03:52:18 PM PST 24 |
Mar 03 03:56:01 PM PST 24 |
2572659644 ps |
| T318 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1198895442 |
|
|
Mar 03 04:04:44 PM PST 24 |
Mar 03 04:14:35 PM PST 24 |
6482285174 ps |
| T1338 |
/workspace/coverage/default/0.chip_sival_flash_info_access.3155715426 |
|
|
Mar 03 03:49:24 PM PST 24 |
Mar 03 03:53:38 PM PST 24 |
3057352540 ps |
| T1339 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.121585663 |
|
|
Mar 03 03:44:00 PM PST 24 |
Mar 03 04:36:06 PM PST 24 |
39574665406 ps |
| T1340 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.2030755297 |
|
|
Mar 03 03:47:06 PM PST 24 |
Mar 03 03:51:24 PM PST 24 |
3343411400 ps |
| T467 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.392238109 |
|
|
Mar 03 03:44:55 PM PST 24 |
Mar 03 03:59:31 PM PST 24 |
5290368476 ps |
| T1341 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.4250286948 |
|
|
Mar 03 04:07:10 PM PST 24 |
Mar 03 04:16:25 PM PST 24 |
5028015184 ps |
| T1342 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2424417126 |
|
|
Mar 03 03:44:11 PM PST 24 |
Mar 03 03:55:23 PM PST 24 |
4126756460 ps |
| T1343 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3861473836 |
|
|
Mar 03 04:00:04 PM PST 24 |
Mar 03 04:04:07 PM PST 24 |
2173161507 ps |
| T1344 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.55015625 |
|
|
Mar 03 03:48:59 PM PST 24 |
Mar 03 04:44:11 PM PST 24 |
22204625528 ps |
| T1345 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.4263556514 |
|
|
Mar 03 03:49:05 PM PST 24 |
Mar 03 03:54:28 PM PST 24 |
3449831328 ps |
| T1346 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1598970787 |
|
|
Mar 03 04:06:16 PM PST 24 |
Mar 03 04:15:39 PM PST 24 |
4075220088 ps |
| T1347 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1242287560 |
|
|
Mar 03 04:02:20 PM PST 24 |
Mar 03 04:13:42 PM PST 24 |
4303545258 ps |
| T781 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3974316263 |
|
|
Mar 03 04:08:47 PM PST 24 |
Mar 03 04:19:40 PM PST 24 |
4284498980 ps |
| T1348 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.604423714 |
|
|
Mar 03 03:49:47 PM PST 24 |
Mar 03 04:13:28 PM PST 24 |
8403691453 ps |
| T1349 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1721653521 |
|
|
Mar 03 03:48:32 PM PST 24 |
Mar 03 03:54:28 PM PST 24 |
3639755320 ps |
| T1350 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.2932360613 |
|
|
Mar 03 03:56:08 PM PST 24 |
Mar 03 04:01:26 PM PST 24 |
3202559610 ps |
| T1351 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1826918224 |
|
|
Mar 03 04:09:14 PM PST 24 |
Mar 03 04:21:34 PM PST 24 |
5112621692 ps |
| T1352 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1770478094 |
|
|
Mar 03 03:50:51 PM PST 24 |
Mar 03 03:59:23 PM PST 24 |
4282146686 ps |
| T733 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3459690042 |
|
|
Mar 03 04:04:04 PM PST 24 |
Mar 03 04:18:18 PM PST 24 |
6008231462 ps |
| T1353 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2127424129 |
|
|
Mar 03 03:47:31 PM PST 24 |
Mar 03 04:21:33 PM PST 24 |
8189511616 ps |
| T1354 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2225412056 |
|
|
Mar 03 04:04:22 PM PST 24 |
Mar 03 04:45:22 PM PST 24 |
12938654928 ps |
| T689 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.146856214 |
|
|
Mar 03 04:09:57 PM PST 24 |
Mar 03 04:18:43 PM PST 24 |
4797401144 ps |
| T1355 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3584826206 |
|
|
Mar 03 03:45:35 PM PST 24 |
Mar 03 04:56:38 PM PST 24 |
22869597142 ps |
| T1356 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2160683542 |
|
|
Mar 03 04:06:06 PM PST 24 |
Mar 03 04:10:48 PM PST 24 |
3704040770 ps |
| T1357 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.666545695 |
|
|
Mar 03 03:44:49 PM PST 24 |
Mar 03 03:46:56 PM PST 24 |
3074076483 ps |
| T1358 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3745326023 |
|
|
Mar 03 03:47:45 PM PST 24 |
Mar 03 03:56:44 PM PST 24 |
2819957908 ps |
| T1359 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1950035639 |
|
|
Mar 03 03:43:50 PM PST 24 |
Mar 03 04:06:15 PM PST 24 |
16442545242 ps |
| T267 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1698065190 |
|
|
Mar 03 03:46:34 PM PST 24 |
Mar 03 04:14:03 PM PST 24 |
10274885010 ps |
| T1360 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2382103847 |
|
|
Mar 03 04:01:29 PM PST 24 |
Mar 03 04:05:47 PM PST 24 |
3115295019 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3505429295 |
|
|
Mar 03 03:46:46 PM PST 24 |
Mar 03 04:02:53 PM PST 24 |
5200628690 ps |
| T791 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3765897532 |
|
|
Mar 03 04:12:09 PM PST 24 |
Mar 03 04:21:17 PM PST 24 |
4020847200 ps |
| T1361 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3161326921 |
|
|
Mar 03 03:57:07 PM PST 24 |
Mar 03 04:23:15 PM PST 24 |
7225975992 ps |
| T1362 |
/workspace/coverage/default/0.chip_sw_example_rom.1567490028 |
|
|
Mar 03 03:42:39 PM PST 24 |
Mar 03 03:44:37 PM PST 24 |
2865323044 ps |
| T756 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2822144622 |
|
|
Mar 03 04:06:53 PM PST 24 |
Mar 03 04:13:04 PM PST 24 |
3670572120 ps |
| T1363 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2719629434 |
|
|
Mar 03 03:45:00 PM PST 24 |
Mar 03 03:55:09 PM PST 24 |
4123329608 ps |
| T1364 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.3654695089 |
|
|
Mar 03 03:47:54 PM PST 24 |
Mar 03 04:19:43 PM PST 24 |
8933026348 ps |
| T797 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3849906520 |
|
|
Mar 03 04:05:13 PM PST 24 |
Mar 03 04:11:32 PM PST 24 |
3364010000 ps |
| T1365 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2548200249 |
|
|
Mar 03 03:46:08 PM PST 24 |
Mar 03 03:50:43 PM PST 24 |
3597081237 ps |
| T1366 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3725638632 |
|
|
Mar 03 03:49:16 PM PST 24 |
Mar 03 04:00:28 PM PST 24 |
4400246000 ps |
| T1367 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3977360261 |
|
|
Mar 03 03:47:52 PM PST 24 |
Mar 03 03:55:24 PM PST 24 |
3445373480 ps |
| T1368 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1324426382 |
|
|
Mar 03 04:06:05 PM PST 24 |
Mar 03 04:12:01 PM PST 24 |
3751114072 ps |
| T1369 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.21874869 |
|
|
Mar 03 03:52:31 PM PST 24 |
Mar 03 04:31:14 PM PST 24 |
8479268328 ps |
| T1370 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2234357696 |
|
|
Mar 03 03:50:18 PM PST 24 |
Mar 03 04:29:47 PM PST 24 |
9097383660 ps |
| T72 |
/workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.1943742452 |
|
|
Mar 03 03:24:50 PM PST 24 |
Mar 03 03:36:46 PM PST 24 |
41994491458 ps |
| T73 |
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.491090079 |
|
|
Mar 03 03:09:22 PM PST 24 |
Mar 03 03:28:47 PM PST 24 |
65485404427 ps |
| T74 |
/workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.583714467 |
|
|
Mar 03 03:24:43 PM PST 24 |
Mar 03 03:24:49 PM PST 24 |
46427342 ps |
| T75 |
/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.3288755902 |
|
|
Mar 03 03:08:18 PM PST 24 |
Mar 03 03:08:59 PM PST 24 |
560417956 ps |
| T105 |
/workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3357011655 |
|
|
Mar 03 03:10:39 PM PST 24 |
Mar 03 03:11:21 PM PST 24 |
427786154 ps |
| T221 |
/workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1253799273 |
|
|
Mar 03 03:10:33 PM PST 24 |
Mar 03 03:12:07 PM PST 24 |
8072215056 ps |
| T223 |
/workspace/coverage/cover_reg_top/71.xbar_random_large_delays.1510901950 |
|
|
Mar 03 03:20:16 PM PST 24 |
Mar 03 03:26:02 PM PST 24 |
33520406413 ps |
| T384 |
/workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2480197134 |
|
|
Mar 03 03:14:14 PM PST 24 |
Mar 03 03:27:29 PM PST 24 |
72922014173 ps |
| T222 |
/workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1368809758 |
|
|
Mar 03 03:22:56 PM PST 24 |
Mar 03 03:23:15 PM PST 24 |
426480735 ps |
| T372 |
/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3306928950 |
|
|
Mar 03 03:24:51 PM PST 24 |
Mar 03 04:00:59 PM PST 24 |
111419015476 ps |
| T469 |
/workspace/coverage/cover_reg_top/35.xbar_random_large_delays.2055404450 |
|
|
Mar 03 03:13:27 PM PST 24 |
Mar 03 03:21:18 PM PST 24 |
43492107482 ps |
| T367 |
/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3778778962 |
|
|
Mar 03 03:11:45 PM PST 24 |
Mar 03 03:15:39 PM PST 24 |
6506509649 ps |
| T471 |
/workspace/coverage/cover_reg_top/31.xbar_random_large_delays.848007825 |
|
|
Mar 03 03:12:43 PM PST 24 |
Mar 03 03:15:51 PM PST 24 |
16324941105 ps |
| T345 |
/workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3832623269 |
|
|
Mar 03 03:12:40 PM PST 24 |
Mar 03 03:13:34 PM PST 24 |
618744703 ps |
| T475 |
/workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.380559815 |
|
|
Mar 03 03:18:13 PM PST 24 |
Mar 03 03:18:31 PM PST 24 |
408457749 ps |
| T477 |
/workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3036368107 |
|
|
Mar 03 03:11:03 PM PST 24 |
Mar 03 03:11:25 PM PST 24 |
146147779 ps |
| T470 |
/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.2727137483 |
|
|
Mar 03 03:08:23 PM PST 24 |
Mar 03 03:12:31 PM PST 24 |
6378206735 ps |
| T473 |
/workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.56650764 |
|
|
Mar 03 03:24:45 PM PST 24 |
Mar 03 03:25:16 PM PST 24 |
292244565 ps |
| T479 |
/workspace/coverage/cover_reg_top/96.xbar_error_random.4294540522 |
|
|
Mar 03 03:24:44 PM PST 24 |
Mar 03 03:25:02 PM PST 24 |
468839541 ps |
| T390 |
/workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2911596370 |
|
|
Mar 03 03:08:09 PM PST 24 |
Mar 03 03:08:36 PM PST 24 |
309337004 ps |
| T347 |
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.32443209 |
|
|
Mar 03 03:07:55 PM PST 24 |
Mar 03 03:59:22 PM PST 24 |
166793688426 ps |
| T404 |
/workspace/coverage/cover_reg_top/72.xbar_random.690418596 |
|
|
Mar 03 03:20:28 PM PST 24 |
Mar 03 03:21:20 PM PST 24 |
552640148 ps |
| T476 |
/workspace/coverage/cover_reg_top/1.xbar_error_random.3251917799 |
|
|
Mar 03 03:07:56 PM PST 24 |
Mar 03 03:08:23 PM PST 24 |
331784562 ps |
| T482 |
/workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3035896782 |
|
|
Mar 03 03:21:06 PM PST 24 |
Mar 03 03:21:12 PM PST 24 |
51286326 ps |
| T483 |
/workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1864493312 |
|
|
Mar 03 03:08:02 PM PST 24 |
Mar 03 03:25:49 PM PST 24 |
11024465388 ps |
| T478 |
/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3461752085 |
|
|
Mar 03 03:14:50 PM PST 24 |
Mar 03 03:19:02 PM PST 24 |
7527661378 ps |
| T472 |
/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.222305156 |
|
|
Mar 03 03:23:56 PM PST 24 |
Mar 03 03:27:54 PM PST 24 |
6086074089 ps |
| T503 |
/workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3087751226 |
|
|
Mar 03 03:22:17 PM PST 24 |
Mar 03 03:22:24 PM PST 24 |
55695026 ps |
| T419 |
/workspace/coverage/cover_reg_top/88.xbar_same_source.3769276804 |
|
|
Mar 03 03:23:19 PM PST 24 |
Mar 03 03:23:54 PM PST 24 |
1320265513 ps |
| T474 |
/workspace/coverage/cover_reg_top/23.xbar_stress_all.702487910 |
|
|
Mar 03 03:11:18 PM PST 24 |
Mar 03 03:14:25 PM PST 24 |
5269361495 ps |
| T601 |
/workspace/coverage/cover_reg_top/69.xbar_random.3635982564 |
|
|
Mar 03 03:19:59 PM PST 24 |
Mar 03 03:20:12 PM PST 24 |
123934157 ps |
| T343 |
/workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1085470585 |
|
|
Mar 03 03:12:58 PM PST 24 |
Mar 03 03:13:37 PM PST 24 |
854866085 ps |
| T566 |
/workspace/coverage/cover_reg_top/40.xbar_smoke.3927221039 |
|
|
Mar 03 03:14:22 PM PST 24 |
Mar 03 03:14:28 PM PST 24 |
50647561 ps |
| T511 |
/workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.4021483989 |
|
|
Mar 03 03:24:27 PM PST 24 |
Mar 03 03:25:08 PM PST 24 |
903998112 ps |
| T506 |
/workspace/coverage/cover_reg_top/22.xbar_error_random.3658920161 |
|
|
Mar 03 03:11:04 PM PST 24 |
Mar 03 03:12:04 PM PST 24 |
1709013531 ps |
| T1371 |
/workspace/coverage/cover_reg_top/96.xbar_smoke.3179239500 |
|
|
Mar 03 03:24:35 PM PST 24 |
Mar 03 03:24:44 PM PST 24 |
151114811 ps |
| T427 |
/workspace/coverage/cover_reg_top/21.xbar_random.3649104526 |
|
|
Mar 03 03:10:47 PM PST 24 |
Mar 03 03:11:05 PM PST 24 |
183948143 ps |
| T611 |
/workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.4077066248 |
|
|
Mar 03 03:23:11 PM PST 24 |
Mar 03 03:24:11 PM PST 24 |
5665885660 ps |
| T481 |
/workspace/coverage/cover_reg_top/7.xbar_same_source.585462693 |
|
|
Mar 03 03:08:20 PM PST 24 |
Mar 03 03:08:45 PM PST 24 |
348022515 ps |
| T835 |
/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3687462167 |
|
|
Mar 03 03:08:07 PM PST 24 |
Mar 03 03:33:58 PM PST 24 |
88124181618 ps |
| T576 |
/workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1260979743 |
|
|
Mar 03 03:17:22 PM PST 24 |
Mar 03 03:17:31 PM PST 24 |
51648995 ps |
| T532 |
/workspace/coverage/cover_reg_top/74.xbar_random.1370561513 |
|
|
Mar 03 03:20:51 PM PST 24 |
Mar 03 03:21:47 PM PST 24 |
1620168773 ps |
| T165 |
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1602511397 |
|
|
Mar 03 03:07:52 PM PST 24 |
Mar 03 04:21:39 PM PST 24 |
28974599172 ps |
| T480 |
/workspace/coverage/cover_reg_top/41.xbar_same_source.3368685032 |
|
|
Mar 03 03:14:36 PM PST 24 |
Mar 03 03:15:16 PM PST 24 |
547244278 ps |
| T631 |
/workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1009162355 |
|
|
Mar 03 03:24:50 PM PST 24 |
Mar 03 03:26:17 PM PST 24 |
4919079977 ps |
| T1372 |
/workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.819974329 |
|
|
Mar 03 03:08:13 PM PST 24 |
Mar 03 03:09:36 PM PST 24 |
8037378025 ps |
| T373 |
/workspace/coverage/cover_reg_top/43.xbar_stress_all.923306788 |
|
|
Mar 03 03:15:07 PM PST 24 |
Mar 03 03:22:42 PM PST 24 |
11548915932 ps |
| T666 |
/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1419303778 |
|
|
Mar 03 03:20:10 PM PST 24 |
Mar 03 03:23:39 PM PST 24 |
5745725558 ps |
| T560 |
/workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1620492167 |
|
|
Mar 03 03:24:36 PM PST 24 |
Mar 03 03:33:19 PM PST 24 |
30042764687 ps |
| T847 |
/workspace/coverage/cover_reg_top/65.xbar_access_same_device.2239153066 |
|
|
Mar 03 03:19:15 PM PST 24 |
Mar 03 03:19:45 PM PST 24 |
511609794 ps |
| T1373 |
/workspace/coverage/cover_reg_top/62.xbar_smoke.1858886475 |
|
|
Mar 03 03:18:36 PM PST 24 |
Mar 03 03:18:44 PM PST 24 |
155338250 ps |