Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_cfg_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.26	99.82	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T54,T55,T51

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T54,T55,T51
1	1	Covered	T54,T55,T51

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T54,T55,T51
1	-	Covered	T54,T55,T56

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T54,T55,T51

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T55,T51
1	1	Covered	T54,T55,T51

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T54,T55,T51
0	0	1	Covered	T54,T55,T51
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T54,T55,T51
0	0	1	Covered	T54,T55,T51
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	86849	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	217	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	86849	0	0
T51	0	335	0	0
T54	42359	790	0	0
T55	0	647	0	0
T56	0	948	0	0
T126	9829	0	0	0
T167	0	655	0	0
T168	0	615	0	0
T169	0	6261	0	0
T201	36140	0	0	0
T215	102034	0	0	0
T233	20411	0	0	0
T348	0	476	0	0
T350	0	443	0	0
T374	0	1398	0	0
T376	132333	0	0	0
T377	27668	0	0	0
T378	47280	0	0	0
T379	35098	0	0	0
T380	53080	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	217	0	0
T51	0	1	0	0
T54	42359	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T126	9829	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	16	0	0
T201	36140	0	0	0
T215	102034	0	0	0
T233	20411	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	4	0	0
T376	132333	0	0	0
T377	27668	0	0	0
T378	47280	0	0	0
T379	35098	0	0	0
T380	53080	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T57,T347

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T57,T347
1	1	Covered	T51,T57,T347

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T51,T57,T347
1	-	Covered	T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T57,T347

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T57,T347
1	1	Covered	T51,T57,T347

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T57,T347
0	0	1	Covered	T51,T57,T347
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T57,T347
0	0	1	Covered	T51,T57,T347
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	79652	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	199	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	79652	0	0
T51	426138	246	0	0
T57	0	895	0	0
T167	0	624	0	0
T168	0	597	0	0
T169	0	5613	0	0
T303	63454	0	0	0
T348	0	404	0	0
T349	43970	0	0	0
T350	0	410	0	0
T369	0	299	0	0
T374	0	3370	0	0
T375	0	809	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	199	0	0
T51	426138	1	0	0
T57	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T51,T347

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T51,T347
1	1	Covered	T52,T51,T347

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T52,T51,T347
1	-	Covered	T52

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T51,T347

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T51,T347
1	1	Covered	T52,T51,T347

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T51,T347
0	0	1	Covered	T52,T51,T347
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T51,T347
0	0	1	Covered	T52,T51,T347
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	88675	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	222	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	88675	0	0
T51	0	297	0	0
T52	47584	903	0	0
T167	0	603	0	0
T168	0	600	0	0
T169	0	1143	0	0
T268	35974	0	0	0
T348	0	371	0	0
T350	0	462	0	0
T369	0	337	0	0
T374	0	3010	0	0
T375	0	886	0	0
T388	68974	0	0	0
T389	53942	0	0	0
T390	15769	0	0	0
T391	54726	0	0	0
T392	36985	0	0	0
T393	149250	0	0	0
T394	62029	0	0	0
T395	17551	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	222	0	0
T51	0	1	0	0
T52	47584	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	3	0	0
T268	35974	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	8	0	0
T375	0	2	0	0
T388	68974	0	0	0
T389	53942	0	0	0
T390	15769	0	0	0
T391	54726	0	0	0
T392	36985	0	0	0
T393	149250	0	0	0
T394	62029	0	0	0
T395	17551	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T396,T347

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T51,T347,T167
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	82792	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	207	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	82792	0	0
T51	426138	354	0	0
T167	0	522	0	0
T168	0	636	0	0
T169	0	4301	0	0
T303	63454	0	0	0
T348	0	443	0	0
T349	43970	0	0	0
T350	0	446	0	0
T369	0	335	0	0
T374	0	2191	0	0
T375	0	891	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	320	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	207	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	11	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T167

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T51,T347,T167
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	70217	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	175	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	70217	0	0
T51	426138	289	0	0
T167	0	620	0	0
T168	0	595	0	0
T169	0	2229	0	0
T303	63454	0	0	0
T348	0	426	0	0
T349	43970	0	0	0
T350	0	443	0	0
T369	0	322	0	0
T374	0	3429	0	0
T375	0	824	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	254	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	175	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T16,T19,T46

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T19,T46
1	1	Covered	T16,T19,T46

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T16,T19,T46
1	-	Covered	T16,T19,T46

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T16,T19,T46

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T19,T46
1	1	Covered	T16,T19,T46

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T16,T19,T46
0	0	1	Covered	T16,T19,T46
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T16,T19,T46
0	0	1	Covered	T16,T19,T46
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	85552	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	218	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	85552	0	0
T16	49927	625	0	0
T19	0	1647	0	0
T44	166989	0	0	0
T46	0	886	0	0
T50	0	1275	0	0
T51	0	310	0	0
T58	0	1314	0	0
T67	55206	0	0	0
T68	60328	0	0	0
T104	0	871	0	0
T105	0	875	0	0
T106	0	623	0	0
T107	124989	0	0	0
T108	42647	0	0	0
T109	57592	0	0	0
T110	36955	0	0	0
T111	55936	0	0	0
T112	508996	0	0	0
T398	0	643	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	218	0	0
T16	49927	2	0	0
T19	0	4	0	0
T44	166989	0	0	0
T46	0	2	0	0
T50	0	4	0	0
T51	0	1	0	0
T58	0	4	0	0
T67	55206	0	0	0
T68	60328	0	0	0
T104	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	124989	0	0	0
T108	42647	0	0	0
T109	57592	0	0	0
T110	36955	0	0	0
T111	55936	0	0	0
T112	508996	0	0	0
T398	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T77,T347

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T51,T347,T167
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	76508	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	193	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	76508	0	0
T51	426138	327	0	0
T167	0	619	0	0
T168	0	503	0	0
T169	0	5638	0	0
T303	63454	0	0	0
T348	0	458	0	0
T349	43970	0	0	0
T350	0	466	0	0
T369	0	247	0	0
T374	0	289	0	0
T375	0	806	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	247	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	193	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	1	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T53,T399

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T53,T347
1	1	Covered	T51,T53,T347

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T51,T53,T347
1	-	Covered	T53

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T53,T347

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T347
1	1	Covered	T51,T53,T347

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T53,T347
0	0	1	Covered	T51,T53,T347
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T53,T347
0	0	1	Covered	T51,T53,T347
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	67344	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	169	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	67344	0	0
T51	426138	355	0	0
T53	0	1059	0	0
T167	0	639	0	0
T168	0	598	0	0
T169	0	2273	0	0
T303	63454	0	0	0
T348	0	388	0	0
T349	43970	0	0	0
T350	0	471	0	0
T369	0	307	0	0
T374	0	3779	0	0
T375	0	891	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	169	0	0
T51	426138	1	0	0
T53	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T54,T55,T51

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T54,T55,T51
1	1	Covered	T54,T55,T51

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T54,T55,T51

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T55,T51
1	1	Covered	T54,T55,T51

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T54,T55,T51
0	0	1	Covered	T54,T55,T51
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T54,T55,T51
0	0	1	Covered	T54,T55,T51
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	84618	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	212	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	84618	0	0
T51	0	313	0	0
T54	42359	293	0	0
T55	0	274	0	0
T56	0	454	0	0
T126	9829	0	0	0
T167	0	550	0	0
T168	0	515	0	0
T169	0	3511	0	0
T201	36140	0	0	0
T215	102034	0	0	0
T233	20411	0	0	0
T348	0	443	0	0
T350	0	478	0	0
T374	0	3419	0	0
T376	132333	0	0	0
T377	27668	0	0	0
T378	47280	0	0	0
T379	35098	0	0	0
T380	53080	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	212	0	0
T51	0	1	0	0
T54	42359	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T126	9829	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T201	36140	0	0	0
T215	102034	0	0	0
T233	20411	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	9	0	0
T376	132333	0	0	0
T377	27668	0	0	0
T378	47280	0	0	0
T379	35098	0	0	0
T380	53080	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T57,T347

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T57,T347
1	1	Covered	T51,T57,T347

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T57,T347

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T57,T347
1	1	Covered	T51,T57,T347

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T57,T347
0	0	1	Covered	T51,T57,T347
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T57,T347
0	0	1	Covered	T51,T57,T347
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	67263	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	172	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	67263	0	0
T51	426138	278	0	0
T57	0	477	0	0
T167	0	617	0	0
T168	0	693	0	0
T169	0	3397	0	0
T303	63454	0	0	0
T348	0	383	0	0
T349	43970	0	0	0
T350	0	441	0	0
T369	0	287	0	0
T374	0	1404	0	0
T375	0	866	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	172	0	0
T51	426138	1	0	0
T57	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T51,T347

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T52,T51,T347
1	1	Covered	T52,T51,T347

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T52,T51,T347

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T52,T51,T347
1	1	Covered	T52,T51,T347

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T51,T347
0	0	1	Covered	T52,T51,T347
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T52,T51,T347
0	0	1	Covered	T52,T51,T347
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	85724	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	215	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	85724	0	0
T51	0	316	0	0
T52	47584	244	0	0
T167	0	646	0	0
T168	0	553	0	0
T169	0	4744	0	0
T268	35974	0	0	0
T348	0	370	0	0
T350	0	462	0	0
T369	0	292	0	0
T374	0	4213	0	0
T375	0	804	0	0
T388	68974	0	0	0
T389	53942	0	0	0
T390	15769	0	0	0
T391	54726	0	0	0
T392	36985	0	0	0
T393	149250	0	0	0
T394	62029	0	0	0
T395	17551	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	215	0	0
T51	0	1	0	0
T52	47584	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	12	0	0
T268	35974	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	11	0	0
T375	0	2	0	0
T388	68974	0	0	0
T389	53942	0	0	0
T390	15769	0	0	0
T391	54726	0	0	0
T392	36985	0	0	0
T393	149250	0	0	0
T394	62029	0	0	0
T395	17551	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T400

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	83281	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	211	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	83281	0	0
T51	426138	298	0	0
T167	0	641	0	0
T168	0	543	0	0
T169	0	8608	0	0
T303	63454	0	0	0
T348	0	404	0	0
T349	43970	0	0	0
T350	0	431	0	0
T369	0	352	0	0
T374	0	2189	0	0
T375	0	881	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	328	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	211	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	22	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T401

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	84638	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	213	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	84638	0	0
T51	426138	289	0	0
T167	0	623	0	0
T168	0	534	0	0
T169	0	3991	0	0
T303	63454	0	0	0
T348	0	416	0	0
T349	43970	0	0	0
T350	0	392	0	0
T369	0	286	0	0
T374	0	3766	0	0
T375	0	889	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	352	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	213	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	10	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T16,T19,T46

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T19,T46
1	1	Covered	T16,T19,T46

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T16,T19,T46

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T19,T46
1	1	Covered	T16,T19,T46

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T16,T19,T46
0	0	1	Covered	T16,T19,T46
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T16,T19,T46
0	0	1	Covered	T16,T19,T46
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	91544	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	232	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	91544	0	0
T16	49927	250	0	0
T19	0	782	0	0
T44	166989	0	0	0
T46	0	391	0	0
T50	0	527	0	0
T51	0	247	0	0
T58	0	566	0	0
T67	55206	0	0	0
T68	60328	0	0	0
T104	0	376	0	0
T105	0	379	0	0
T106	0	247	0	0
T107	124989	0	0	0
T108	42647	0	0	0
T109	57592	0	0	0
T110	36955	0	0	0
T111	55936	0	0	0
T112	508996	0	0	0
T398	0	267	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	232	0	0
T16	49927	1	0	0
T19	0	2	0	0
T44	166989	0	0	0
T46	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T58	0	2	0	0
T67	55206	0	0	0
T68	60328	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	124989	0	0	0
T108	42647	0	0	0
T109	57592	0	0	0
T110	36955	0	0	0
T111	55936	0	0	0
T112	508996	0	0	0
T398	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T402

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T347,T167
1	1	Covered	T51,T347,T167

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T347,T167
0	0	1	Covered	T51,T347,T167
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	61817	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	159	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	61817	0	0
T51	426138	262	0	0
T167	0	578	0	0
T168	0	641	0	0
T169	0	2621	0	0
T303	63454	0	0	0
T348	0	419	0	0
T349	43970	0	0	0
T350	0	437	0	0
T369	0	324	0	0
T374	0	2194	0	0
T375	0	832	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	294	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	159	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	7	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T53,T77

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T51,T53,T347
1	1	Covered	T51,T53,T347

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T51,T53,T347

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T53,T347
1	1	Covered	T51,T53,T347

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T53,T347
0	0	1	Covered	T51,T53,T347
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T51,T53,T347
0	0	1	Covered	T51,T53,T347
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121500719	80808	0	0
DstReqKnown_A	1541566	1344381	0	0
SrcAckBusyChk_A	121500719	203	0	0
SrcBusyKnown_A	121500719	120755741	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	80808	0	0
T51	426138	290	0	0
T53	0	396	0	0
T167	0	667	0	0
T168	0	661	0	0
T169	0	2964	0	0
T303	63454	0	0	0
T348	0	418	0	0
T349	43970	0	0	0
T350	0	450	0	0
T369	0	297	0	0
T374	0	1361	0	0
T375	0	789	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	1344381	0	0
T1	546	384	0	0
T2	345	181	0	0
T3	372	208	0	0
T32	906	743	0	0
T43	1622	1458	0	0
T59	468	306	0	0
T60	708	546	0	0
T86	768	606	0	0
T87	360	196	0	0
T88	365	204	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	203	0	0
T51	426138	1	0	0
T53	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	8	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	120755741	0	0
T1	42420	41795	0	0
T2	17858	17243	0	0
T3	16536	16064	0	0
T32	52169	51798	0	0
T43	162050	161675	0	0
T59	29930	29412	0	0
T60	61478	60872	0	0
T86	65803	65298	0	0
T87	25705	24689	0	0
T88	23085	22442	0	0