CHIP Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.127m	2.507ms	3	3	100.00
		chip_sw_example_rom	2.478m	2.379ms	3	3	100.00
		chip_sw_example_manufacturer	4.106m	2.584ms	3	3	100.00
		chip_sw_example_concurrency	4.569m	3.019ms	3	3	100.00
		chip_sw_uart_smoketest_signed	36.022m	8.659ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.133m	7.480ms	5	5	100.00
V1	csr_rw	chip_csr_rw	12.556m	6.210ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.115h	36.449ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.450h	52.258ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.139m	2.649ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.450h	52.258ms	5	5	100.00
		chip_csr_rw	12.556m	6.210ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.990s	267.946us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.942m	3.845ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.942m	3.845ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.942m	3.845ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	17.684m	5.840ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	17.684m	5.840ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	18.215m	5.479ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	17.219m	5.298ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	16.139m	5.217ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.126h	22.887ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.410h	23.060ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	25.038m	12.847ms	4	5	80.00
V1		TOTAL			202	223	90.58
V2	chip_pin_mux	chip_padctrl_attributes	5.932m	5.321ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.932m	5.321ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.423m	3.150ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	8.749m	5.533ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.740m	3.866ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	17.132m	9.173ms	5	5	100.00
		chip_tap_straps_testunlock0	11.204m	7.521ms	5	5	100.00
		chip_tap_straps_rma	9.161m	6.428ms	5	5	100.00
		chip_tap_straps_prod	30.640m	18.734ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.286m	2.699ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.735m	9.286ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	16.451m	6.417ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	16.451m	6.417ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	22.285m	8.141ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.778m	4.397ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.811m	5.861ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.216h	18.366ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.539m	3.355ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	17.175m	5.136ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.998m	3.078ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.004m	5.401ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.464m	3.056ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.861m	4.584ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.762m	2.019ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.739m	2.430ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	16.756m	6.680ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	16.756m	6.680ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.864m	5.741ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	6.004m	3.528ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.864m	5.741ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	5.066m	3.446ms	3	3	100.00
		chip_sw_aes_smoketest	5.218m	2.717ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.186m	3.747ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.614m	2.571ms	3	3	100.00
		chip_sw_csrng_smoketest	3.866m	3.181ms	3	3	100.00
		chip_sw_entropy_src_smoketest	13.095m	3.650ms	3	3	100.00
		chip_sw_gpio_smoketest	5.493m	2.554ms	3	3	100.00
		chip_sw_hmac_smoketest	6.218m	3.299ms	3	3	100.00
		chip_sw_kmac_smoketest	6.540m	2.625ms	3	3	100.00
		chip_sw_otbn_smoketest	33.456m	9.355ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.441m	3.086ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.119m	5.692ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.749m	4.640ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.925m	2.536ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.338m	2.798ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.337m	2.760ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.799m	2.645ms	3	3	100.00
		chip_sw_uart_smoketest	5.755m	3.017ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.488m	4.409ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	36.022m	8.659ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.751h	78.634ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	35.624m	8.963ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	38.466m	14.801ms	2	3	66.67
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.589m	3.808ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	7.555m	9.187ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.422h	59.792ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.798h	64.864ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.890m	4.920ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.890m	4.920ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.450h	52.258ms	5	5	100.00
		chip_same_csr_outstanding	1.341h	30.807ms	20	20	100.00
		chip_csr_hw_reset	7.133m	7.480ms	5	5	100.00
		chip_csr_rw	12.556m	6.210ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.450h	52.258ms	5	5	100.00
		chip_same_csr_outstanding	1.341h	30.807ms	20	20	100.00
		chip_csr_hw_reset	7.133m	7.480ms	5	5	100.00
		chip_csr_rw	12.556m	6.210ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.667m	2.544ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.420s	57.757us	100	100	100.00
		xbar_smoke_large_delays	2.077m	11.368ms	100	100	100.00
		xbar_smoke_slow_rsp	2.135m	6.803ms	100	100	100.00
		xbar_random_zero_delays	54.260s	543.309us	100	100	100.00
		xbar_random_large_delays	23.465m	109.769ms	100	100	100.00
		xbar_random_slow_rsp	22.886m	67.370ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.103m	1.441ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.082m	1.295ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.608m	2.559ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.082m	1.295ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.987m	3.776ms	100	100	100.00
		xbar_access_same_device_slow_rsp	51.898m	169.599ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.480m	2.677ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.877m	20.870ms	100	100	100.00
		xbar_stress_all_with_error	9.520m	14.137ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	23.993m	29.013ms	100	100	100.00
		xbar_stress_all_with_reset_error	20.551m	12.351ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	35.624m	8.963ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	52.960m	25.717ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	35.614m	8.773ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	25.717m	7.051ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.836m	8.392ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	34.536m	8.659ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	38.038m	9.200ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	36.346m	8.811ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	23.938m	6.405ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	37.689m	8.947ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	39.725m	8.412ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	37.943m	9.051ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	34.534m	9.350ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	42.630m	9.678ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	56.126m	11.846ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	50.711m	11.521ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	50.412m	12.382ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	47.190m	12.315ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	52.320m	10.865ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	51.907m	11.812ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	51.206m	11.583ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	42.297m	11.763ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	50.877m	12.080ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	27.888m	7.291ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	38.491m	8.375ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	29.907m	8.390ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	35.185m	9.358ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	32.476m	9.064ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	30.113m	7.232ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	34.462m	8.793ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	38.634m	8.956ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	36.564m	8.099ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	36.366m	8.901ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	26.789m	6.945ms	3	3	100.00
		rom_e2e_asm_init_dev	45.688m	8.572ms	3	3	100.00
		rom_e2e_asm_init_prod	35.898m	8.491ms	3	3	100.00
		rom_e2e_asm_init_prod_end	33.856m	8.973ms	3	3	100.00
		rom_e2e_asm_init_rma	37.535m	9.394ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.668m	10.699ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.948m	2.880ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.539m	3.355ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.700m	3.109ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.380m	3.048ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.159m	4.643ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.112m	19.735ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.112m	19.735ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.322m	4.632ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.119m	5.692ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.322m	4.632ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.180m	7.609ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.180m	7.609ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.124m	6.715ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.530m	4.636ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.768m	5.636ms	3	3	100.00
		chip_sw_aes_idle	5.380m	3.048ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.409m	3.136ms	3	3	100.00
		chip_sw_kmac_idle	5.014m	3.173ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.026m	5.246ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.156m	4.489ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	7.322m	4.592ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	8.839m	4.669ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	25.854m	12.113ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.317m	4.030ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.448m	5.131ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.857m	3.844ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.247m	4.452ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.261m	4.600ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.297m	4.838ms	3	3	100.00
		chip_sw_ast_clk_outputs	22.285m	8.141ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	16.797m	10.563ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.857m	3.844ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.247m	4.452ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.778m	4.397ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.811m	5.861ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.216h	18.366ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.539m	3.355ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	17.175m	5.136ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.998m	3.078ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.004m	5.401ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.464m	3.056ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.861m	4.584ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.762m	2.019ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.908m	3.134ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.302m	5.451ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	20.393m	7.271ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.031h	25.593ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.748m	3.885ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.035m	2.443ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.907m	4.091ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.503m	3.188ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.383m	5.794ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	35.632m	19.273ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.162h	20.811ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	22.285m	8.141ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.077m	4.430ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	9.915m	3.436ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.754m	4.785ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	28.251m	8.158ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	30.372m	8.244ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.300m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	21.325m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.799m	2.392ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.553m	7.393ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	32.283m	21.689ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.703m	2.934ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	41.740s	10.160us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.578m	5.231ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	32.283m	21.689ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	32.283m	21.689ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.100h	20.870ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.100h	20.870ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	8.675m	5.951ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.112m	19.735ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.125h	16.563ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.353m	3.091ms	3	3	100.00
		chip_sw_edn_entropy_reqs	22.546m	5.219ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.353m	3.091ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	30.372m	8.244ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	5.015m	2.863ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	37.270m	24.864ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	17.991m	5.935ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.811m	5.861ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.888m	4.617ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.778m	4.397ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	9.104m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	37.270m	24.864ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.025m	3.274ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	8.045m	5.365ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.437m	5.719ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	9.104m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.437m	5.719ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.437m	5.719ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	9.437m	5.719ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.437m	5.719ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.754m	4.785ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	12.704m	13.599ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	21.165m	6.029ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.172m	5.803ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.172m	5.803ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.496m	2.666ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.998m	3.078ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.409m	3.136ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.641m	5.603ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	17.625m	6.072ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.668m	5.857ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.241m	4.729ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	8.045m	5.365ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.004m	5.401ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.940m	5.429ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.159m	4.643ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.082h	15.402ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.131m	2.761ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.512m	2.791ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.464m	3.056ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	8.045m	5.365ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	17.860m	12.714ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.872m	2.433ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.603m	3.436ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.014m	3.173ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.212m	5.269ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	17.132m	9.173ms	5	5	100.00
		chip_tap_straps_rma	9.161m	6.428ms	5	5	100.00
		chip_tap_straps_prod	30.640m	18.734ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.588m	3.682ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	17.860m	12.714ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	17.860m	12.714ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	17.860m	12.714ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.639m	4.047ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	9.437m	5.719ms	3	3	100.00
		chip_sw_flash_rma_unlocked	9.104m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.583m	4.522ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.324m	7.316ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.423m	7.916ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.333m	9.237ms	3	3	100.00
		chip_sw_lc_ctrl_transition	17.860m	12.714ms	15	15	100.00
		chip_sw_keymgr_key_derivation	8.045m	5.365ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.644m	10.043ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	8.375m	10.020ms	0	3	0.00
		chip_prim_tl_access	12.704m	13.599ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	16.797m	10.563ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.317m	4.030ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.448m	5.131ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.857m	3.844ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.247m	4.452ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.261m	4.600ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.297m	4.838ms	3	3	100.00
		chip_tap_straps_dev	17.132m	9.173ms	5	5	100.00
		chip_tap_straps_rma	9.161m	6.428ms	5	5	100.00
		chip_tap_straps_prod	30.640m	18.734ms	5	5	100.00
		chip_rv_dm_lc_disabled	11.451m	16.319ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.331m	4.127ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.465m	3.507ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.721m	2.611ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.425m	2.959ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	41.407m	27.523ms	3	3	100.00
		chip_rv_dm_lc_disabled	11.451m	16.319ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.579h	50.320ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.583h	48.027ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	19.093m	10.873ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.593h	48.383ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	41.407m	27.523ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.930m	1.911ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.980m	2.836ms	3	3	100.00
		rom_volatile_raw_unlock	1.813m	2.016ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	17.860m	12.714ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	37.270m	24.864ms	3	3	100.00
		chip_sw_otbn_mem_scramble	11.334m	3.909ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.045m	5.365ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.954m	4.227ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.323m	2.997ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	37.270m	24.864ms	3	3	100.00
		chip_sw_otbn_mem_scramble	11.334m	3.909ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.045m	5.365ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.954m	4.227ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.323m	2.997ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	17.860m	12.714ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	19.771m	14.467ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.588m	3.682ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.583m	4.522ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.324m	7.316ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.423m	7.916ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.333m	9.237ms	3	3	100.00
		chip_sw_lc_ctrl_transition	17.860m	12.714ms	15	15	100.00
		chip_prim_tl_access	12.704m	13.599ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	12.704m	13.599ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.146m	6.269ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	29.532m	19.084ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	8.460m	7.861ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	9.047m	16.915ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.784m	17.177ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	27.979m	20.434ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	28.505m	13.034ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	17.180m	7.609ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	21.310m	11.654ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.301m	4.140ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.146m	6.269ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.102m	5.014ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.013h	35.153ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.095m	6.644ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.710m	5.082ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	40.633m	21.689ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.553m	7.393ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	27.883m	13.215ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	45.900m	25.085ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	6.192m	3.023ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.754m	4.785ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.644m	10.043ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.644m	10.043ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	27.883m	13.215ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	40.633m	21.689ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	12.301m	4.140ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.119m	5.692ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.725m	3.658ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	13.026m	7.760ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.534m	4.137ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	36.024m	15.355ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.503m	3.378ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.754m	4.785ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	27.806m	6.057ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.331m	6.271ms	3	3	100.00
		chip_plic_all_irqs_10	11.671m	4.400ms	3	3	100.00
		chip_plic_all_irqs_20	15.537m	4.982ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.062m	3.088ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.255m	2.798ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	35.624m	8.963ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.915m	7.257ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.251m	4.859ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.972m	3.703ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.174m	3.162ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.954m	4.227ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.861m	4.584ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.427m	6.685ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	16.095m	7.608ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.375m	10.020ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.754m	4.785ms	97	100	97.00
		chip_sw_data_integrity_escalation	16.451m	6.417ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.031m	2.736ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.263m	2.856ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.319m	3.594ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	8.490m	3.556ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	30.201m	8.274ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.231h	31.685ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	45.833m	11.991ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.829m	3.232ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.212m	5.269ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.754m	4.785ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.945m	3.847ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	36.024m	15.355ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	6.416m	2.835ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.302m	4.078ms	87	90	96.67
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	25.674m	11.061ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	28.251m	8.158ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	27.806m	6.057ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.802h	255.466ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	45.130m	19.832ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	24.483m	12.860ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.725m	3.658ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.458m	5.138ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	8.508m	6.320ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	9.161m	6.428ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	11.451m	16.319ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2583	2657	97.21
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.765m	2.723ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.774h	50.322ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.792m	1.928ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.787m	2.293ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.584m	2.479ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.028h	54.225ms	0	1	0.00
		rom_e2e_jtag_inject_dev	59.446m	40.449ms	0	1	0.00
		rom_e2e_jtag_inject_rma	56.778m	38.869ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	43.546m	10.232ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.358m	4.010ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.969m	3.102ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	18.975m	4.469ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	30.390m	8.644ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	14.543m	2.983ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.889m	5.969ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.673m	3.255ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	12.302m	6.070ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	6.970m	6.065ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.705m	5.321ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	27.883m	13.215ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.754m	4.785ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	17.684m	5.840ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.180h	18.298ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.792m	1.928ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.787m	2.293ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.584m	2.479ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.543m	5.005ms	3	3	100.00
V3		TOTAL			33	48	68.75
	Unmapped tests	chip_sival_flash_info_access	6.623m	3.394ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	13.572m	4.975ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.077h	16.400ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	20.202m	6.036ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.892m	4.827ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.752m	6.668ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.192m	2.194ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.675m	2.607ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2845	2958	96.18

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	17	89.47
V2	290	276	250	86.21
V2S	1	1	1	100.00
V3	91	22	13	14.29

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	95.45	94.14	95.17	--	94.70	97.38	99.55

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.98197741832061141087823969263965324296935323833650878819067237764900110481957
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:45:04) Loading:
  (15:45:05) Loading:
  (15:45:05) Loading: 4 packages loaded
  (15:45:05) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:45:05) WARNING: Target pattern parsing failed.
  (15:45:05) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:45:05) INFO: Elapsed time: 42.592s
  (15:45:05) INFO: 0 processes.
  (15:45:05) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.25275855108972362298821956562183323083903693740108898848683745415735806577862
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:56:36) Loading:
  (15:56:36) Loading:
  (15:56:36) Loading: 4 packages loaded
  (15:56:36) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:56:36) WARNING: Target pattern parsing failed.
  (15:56:37) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:56:37) INFO: Elapsed time: 20.778s
  (15:56:37) INFO: 0 processes.
  (15:56:37) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.112495203469046863763645867946636633475633219021819547222245179000798616446062
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:46:25) Loading:
  (15:46:26) Loading:
  (15:46:26) Loading: 4 packages loaded
  (15:46:26) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:46:26) WARNING: Target pattern parsing failed.
  (15:46:26) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:46:27) INFO: Elapsed time: 32.392s
  (15:46:27) INFO: 0 processes.
  (15:46:27) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.93696538456280252799190770003465213080970047758536569462248388809676015695949
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:57:32) Loading:
  (15:57:33) Loading:
  (15:57:33) Loading: 4 packages loaded
  (15:57:33) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:33) WARNING: Target pattern parsing failed.
  (15:57:33) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:33) INFO: Elapsed time: 17.936s
  (15:57:33) INFO: 0 processes.
  (15:57:33) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.56879262782576304273120481677801560181409713381756670225282112110212118515043
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:46:47) Loading:
  (15:46:48) Loading:
  (15:46:48) Loading: 4 packages loaded
  (15:46:48) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:46:48) WARNING: Target pattern parsing failed.
  (15:46:48) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:46:49) INFO: Elapsed time: 27.137s
  (15:46:49) INFO: 0 processes.
  (15:46:49) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.77477557170623092503915953341140816098181937780372188099601875313125396605366
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:57:36) Loading:
  (15:57:37) Loading:
  (15:57:37) Loading: 4 packages loaded
  (15:57:37) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:37) WARNING: Target pattern parsing failed.
  (15:57:37) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:37) INFO: Elapsed time: 18.357s
  (15:57:37) INFO: 0 processes.
  (15:57:37) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.113735680671086102197982792730609148670103923296656950684204120484677763015578
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:47:03) Loading:
  (15:47:04) Loading:
  (15:47:04) Loading: 4 packages loaded
  (15:47:04) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:47:04) WARNING: Target pattern parsing failed.
  (15:47:04) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:47:04) INFO: Elapsed time: 39.772s
  (15:47:04) INFO: 0 processes.
  (15:47:04) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.56816993425076915308767965017483385693901257610739236581366481561328399036260
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:57:36) Loading:
  (15:57:36) Loading:
  (15:57:36) Loading: 4 packages loaded
  (15:57:36) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:36) WARNING: Target pattern parsing failed.
  (15:57:36) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:57:36) INFO: Elapsed time: 17.207s
  (15:57:36) INFO: 0 processes.
  (15:57:36) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.74808520143271004234304718960984755580221865094816006548299812095906544996748
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:46:45) Loading:
  (15:46:45) Loading:
  (15:46:45) Loading: 4 packages loaded
  (15:46:45) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:46:45) WARNING: Target pattern parsing failed.
  (15:46:45) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:46:45) INFO: Elapsed time: 25.914s
  (15:46:45) INFO: 0 processes.
  (15:46:45) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.97083656084766114896177932198861980506145418955236345115306540287402274788082
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:57:34) Loading:
  (15:57:35) Loading:
  (15:57:35) Loading: 4 packages loaded
  (15:57:35) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:57:35) WARNING: Target pattern parsing failed.
  (15:57:35) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:57:35) INFO: Elapsed time: 18.489s
  (15:57:35) INFO: 0 processes.
  (15:57:35) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:827) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.86026218240735212024750467768130342868356163812244979585517303468946430965342
    Line 361, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2200.577583 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2200.577583 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.59336514263613025108064071747750131592063583044082028597215272321309335164321
    Line 366, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2269.697821 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2269.697821 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 13 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.23997088761284839327880196128436298776804355514740148670552686322052885387078
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:6ff10d27-78c0-4a6d-ba7d-7d8cda452e84
```
  - 1.chip_sw_rv_timer_systick_test.87577463393781623582044314027928587945863274526748784294377416295514858563776
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:8b35d82f-935d-4c1f-aec3-772e606979e4
```
  - ... and 1 more failures.
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.17124635920800233314803900792524486713292609289728243913788832957921633719544
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:ed311626-e5f4-4dba-bce6-c2bcb2c915f3
```
  - 1.chip_sw_ast_clk_rst_inputs.2646217268775316273931112771261785281353630155891472752434668485473622556151
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:1ccbcd08-3b55-424b-a986-eebcc2652728
```
  - ... and 1 more failures.
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.32785595342292348379223444020791960248586377075584910143112604027538984708598
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:7f26d698-82dd-4ed9-8b8d-717b74fc4a1e
```
  - 1.chip_sw_power_virus.66626224923408971437798635974650820881873306197559471480132921311823259862159
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:f62ae87d-1630-45e3-b119-3df7c156f132
```
  - ... and 1 more failures.
- Test rom_raw_unlock has 1 failures.
  - 0.rom_raw_unlock.110935699129538697290277485978611637402650686419538632388568993016351194078423
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
```
  Job ID: smart:75cd712b-491a-45f7-8bba-c789820187d5
```
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 1.chip_sw_uart_tx_rx_bootstrap.59035649793097827345651714148787693265217092998755590763399753104353873161430
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:31e5e0ee-7713-4b6d-921e-7d9ec4ad7749
```
  - 2.chip_sw_uart_tx_rx_bootstrap.14598300429855917830045758138086044161471496922401318992489091098358709012578
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:5ed69d3b-9c3d-4b05-aedb-b6c49025c62b
```
- ... and 1 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 5 failures:

Test chip_sw_pwrmgr_deep_sleep_por_reset has 3 failures.

0.chip_sw_pwrmgr_deep_sleep_por_reset.49602800815996750257293671117366710120581613312587343293529070750829455815518
Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 16705.475181 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16705.475181 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_pwrmgr_deep_sleep_por_reset.62787002531076946058246866217051842023975156458039955836466841094100268503036
Line 740, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17086.754108 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17086.754108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_pwrmgr_normal_sleep_por_reset has 2 failures.

0.chip_sw_pwrmgr_normal_sleep_por_reset.5852792458284217377662490236627218020891005059788669612613374630193585400788
Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17177.012933 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17177.012933 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_pwrmgr_normal_sleep_por_reset.45970231953148026950350876415341931180132858929657612338689307713502596425704
Line 821, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17111.623329 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17111.623329 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.34773469095953347438290550614811497072889620881366747553204854447358950613263
    Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.340001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.81589707275313768302528150553067818563449277656185536943970422449407673187529
    Line 689, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.260001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.87402642552011980538620301862743346961312685010242203360876325877929915050436
    Line 715, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.70588589852499280985909298356400396970472641659673306530679113770095171377352
    Line 714, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:
- Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.
  - 0.chip_sw_csrng_lc_hw_debug_en_test.18013915850440792931886622106219926273574157453315494808796108164340205221539
    Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.120001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_lc_hw_debug_en_test.32681134366589009777060635006400839349716126677804667988899685094315648849182
    Line 809, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.220001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:33) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.80124827605706922286476457812842273066332742160933409321878635086635177123340
    Line 723, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.260001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_fuse_en_sw_app_read_test.16782341116459073829726996263415651784782624067672653118352298452632065531663
    Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.140001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_sram_ctrl_execution_main has 3 failures.
  - 0.chip_sw_sram_ctrl_execution_main.96635309508151116143534425566462497594555023801368273631407157223745733125668
    Line 722, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.500001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.500001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sram_ctrl_execution_main.12708693072704363573394162113562603943444024778513617879954478580404054007411
    Line 723, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.380001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.98783073441733865382894771842624386335581440914581910820559093824207002918856
    Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14466.573936 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14466.573936 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.51027617001400401675114497045773814092154453990804062919776843579510045337824
    Line 721, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14923.101560 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14923.101560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.53976049845293303686318069196607950654350840579765491583146919558994853079888
    Line 716, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 1928.357000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1928.357000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.53154062183401434798302589806435423238318620887650350275405547520929162437732
    Line 685, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2293.447500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2293.447500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.89615127216642960983227537129110982707396458111428003366421236504829055805474
    Line 688, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2479.320000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2479.320000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.103120176393925145161442106013687056516342007952848801133582125165134469995166
    Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 54225.264711 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 54225.264711 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.992555995748116638525307065485552644478226612396801813806343773361418608699
    Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 40449.438185 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40449.438185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.115065291322629090418260390129551724682085395011058877384848058019042671659953
    Line 742, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 38869.333035 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 38869.333035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.81939603094647373430633511218168720810076898191884317551783878189370674579262
Line 731, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 9533.716464 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 9533.716464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_self_hash.6709311402721171958405561882514499719694549126135823104642456515888399164627
Line 742, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 10232.141870 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 10232.141870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 3 failures.
  - 28.chip_sw_alert_handler_lpg_sleep_mode_alerts.74235682203161045794290685952409070791590504149664556989724050750270285978285
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3646.570720 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a36 MTVAL=40600800
  UVM_INFO @ 3646.570720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.chip_sw_alert_handler_lpg_sleep_mode_alerts.89016256693334661525772048008713300410411222902062011444738506958335598449799
    Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4004.244636 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a36 MTVAL=40600800
  UVM_INFO @ 4004.244636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 30.chip_sw_all_escalation_resets.2208175894291342903894162938018243065381109908807014829454675487040339060298
    Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/30.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3055.237188 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3055.237188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 50.chip_sw_all_escalation_resets.69938608704289189542074002193428694439562760390307259228614162190722523438408
    Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/50.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2909.647672 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2909.647672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.