CHIP Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.983m	2.926ms	3	3	100.00
		chip_sw_example_rom	1.914m	2.765ms	3	3	100.00
		chip_sw_example_manufacturer	3.626m	2.211ms	3	3	100.00
		chip_sw_example_concurrency	5.425m	3.280ms	3	3	100.00
		chip_sw_uart_smoketest_signed	38.834m	8.928ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.811m	7.357ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.399m	5.927ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.171h	36.995ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.952h	71.130ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.618m	2.502ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.952h	71.130ms	5	5	100.00
		chip_csr_rw	11.399m	5.927ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.930s	278.481us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.091m	4.273ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.091m	4.273ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.091m	4.273ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	18.317m	5.778ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	18.317m	5.778ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	18.509m	5.186ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	16.420m	5.572ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	20.526m	5.092ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.112h	23.092ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.117h	23.339ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	34.678m	13.455ms	4	5	80.00
V1		TOTAL			202	223	90.58
V2	chip_pin_mux	chip_padctrl_attributes	4.691m	4.944ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.691m	4.944ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.513m	2.743ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.397m	5.040ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.634m	3.836ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	32.499m	16.067ms	5	5	100.00
		chip_tap_straps_testunlock0	12.955m	7.141ms	5	5	100.00
		chip_tap_straps_rma	25.289m	12.388ms	5	5	100.00
		chip_tap_straps_prod	32.725m	18.770ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.500m	2.690ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.063m	9.462ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	15.207m	5.553ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	15.207m	5.553ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	17.405m	7.333ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.060m	4.162ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.682m	6.452ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.096h	18.878ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.752m	2.631ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	17.155m	4.667ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.746m	2.939ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.915m	5.014ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.463m	3.674ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.706m	5.461ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.261m	2.721ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.466m	3.252ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	15.175m	6.099ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	15.175m	6.099ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.103m	5.356ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.827m	3.105ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.103m	5.356ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.774m	3.251ms	3	3	100.00
		chip_sw_aes_smoketest	4.720m	2.939ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.293m	3.103ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.646m	2.908ms	3	3	100.00
		chip_sw_csrng_smoketest	6.150m	2.982ms	3	3	100.00
		chip_sw_entropy_src_smoketest	10.886m	2.860ms	3	3	100.00
		chip_sw_gpio_smoketest	4.917m	2.696ms	3	3	100.00
		chip_sw_hmac_smoketest	6.113m	2.996ms	3	3	100.00
		chip_sw_kmac_smoketest	7.027m	2.986ms	3	3	100.00
		chip_sw_otbn_smoketest	40.699m	9.534ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	6.348m	2.954ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.087m	5.714ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.042m	5.620ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.134m	3.304ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.850m	3.461ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.112m	2.438ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.771m	3.387ms	3	3	100.00
		chip_sw_uart_smoketest	4.428m	3.426ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	10.759m	4.633ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	38.834m	8.928ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.645h	79.562ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	40.857m	9.353ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	41.913m	15.428ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.649m	4.131ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.949m	11.183ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.022h	58.763ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.645h	64.457ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.155m	4.630ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.155m	4.630ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.952h	71.130ms	5	5	100.00
		chip_same_csr_outstanding	1.114h	31.677ms	20	20	100.00
		chip_csr_hw_reset	6.811m	7.357ms	5	5	100.00
		chip_csr_rw	11.399m	5.927ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.952h	71.130ms	5	5	100.00
		chip_same_csr_outstanding	1.114h	31.677ms	20	20	100.00
		chip_csr_hw_reset	6.811m	7.357ms	5	5	100.00
		chip_csr_rw	11.399m	5.927ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.949m	2.772ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.990s	60.746us	100	100	100.00
		xbar_smoke_large_delays	2.105m	11.392ms	100	100	100.00
		xbar_smoke_slow_rsp	2.212m	7.102ms	100	100	100.00
		xbar_random_zero_delays	1.076m	623.661us	100	100	100.00
		xbar_random_large_delays	21.339m	108.270ms	100	100	100.00
		xbar_random_slow_rsp	21.896m	72.359ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.122m	1.366ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.017m	1.347ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.740m	2.598ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.017m	1.347ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.589m	3.528ms	100	100	100.00
		xbar_access_same_device_slow_rsp	49.410m	169.345ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.585m	2.660ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	13.277m	16.169ms	100	100	100.00
		xbar_stress_all_with_error	11.521m	14.674ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	14.958m	6.692ms	100	100	100.00
		xbar_stress_all_with_reset_error	18.176m	12.570ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.857m	9.353ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	56.860m	22.996ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.513m	9.228ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	26.871m	6.624ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	35.556m	9.016ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	35.533m	9.077ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	36.697m	9.257ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.502m	8.482ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	26.838m	7.184ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	38.704m	8.399ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	39.984m	8.840ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	39.024m	7.883ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	30.439m	8.382ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	46.294m	10.129ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	59.133m	12.671ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	59.373m	12.003ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	52.100m	12.099ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	51.002m	12.108ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	45.643m	10.026ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	48.506m	11.562ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	53.180m	11.477ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	48.004m	12.087ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	53.129m	11.498ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	27.860m	6.991ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	37.400m	8.298ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	34.854m	7.712ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	31.022m	8.311ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	35.387m	8.096ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	24.168m	6.800ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	32.469m	8.815ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	38.967m	8.320ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	39.914m	8.183ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	34.878m	8.728ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	25.155m	7.210ms	3	3	100.00
		rom_e2e_asm_init_dev	38.871m	8.429ms	3	3	100.00
		rom_e2e_asm_init_prod	36.378m	8.740ms	3	3	100.00
		rom_e2e_asm_init_prod_end	36.569m	8.920ms	3	3	100.00
		rom_e2e_asm_init_rma	37.648m	9.051ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	45.690m	10.601ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.391m	2.880ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.752m	2.631ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.262m	2.844ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.442m	2.427ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.054m	5.074ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.056m	19.278ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.056m	19.278ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	6.756m	3.571ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.087m	5.714ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	6.756m	3.571ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.361m	6.982ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.361m	6.982ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.582m	7.225ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.524m	5.619ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	17.667m	5.804ms	3	3	100.00
		chip_sw_aes_idle	4.442m	2.427ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.864m	2.840ms	3	3	100.00
		chip_sw_kmac_idle	6.366m	3.264ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.659m	4.702ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.368m	5.033ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	10.571m	5.628ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	7.539m	3.868ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	22.123m	10.650ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.872m	4.141ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.014m	4.306ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.900m	3.915ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.292m	4.812ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.131m	4.001ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.261m	4.523ms	3	3	100.00
		chip_sw_ast_clk_outputs	17.405m	7.333ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.029m	9.426ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.900m	3.915ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.292m	4.812ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	13.060m	4.162ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.682m	6.452ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.096h	18.878ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.752m	2.631ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	17.155m	4.667ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.746m	2.939ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.915m	5.014ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.463m	3.674ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.706m	5.461ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.261m	2.721ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.287m	2.905ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	14.167m	4.623ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.951m	7.473ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.211h	25.319ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.097m	3.652ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.119m	3.429ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.720m	5.831ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.004m	3.066ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.253m	4.010ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	34.719m	24.789ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.055h	19.464ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	17.405m	7.333ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.284m	4.596ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.692m	3.215ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	16.213m	5.795ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	36.028m	9.175ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	32.575m	7.699ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.457m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	28.603m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.868m	2.378ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.682m	8.604ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	31.670m	21.873ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.116m	3.515ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	41.950s	10.280us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	11.183m	4.921ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	31.670m	21.873ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	31.670m	21.873ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.088h	20.670ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.088h	20.670ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	8.612m	5.132ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	13.056m	19.278ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.397h	20.886ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.109m	2.655ms	3	3	100.00
		chip_sw_edn_entropy_reqs	20.884m	5.922ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.109m	2.655ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	32.575m	7.699ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.912m	2.198ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	39.633m	22.769ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.286m	5.700ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.682m	6.452ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	10.576m	4.407ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	13.060m	4.162ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	13.158m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	39.633m	22.769ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.539m	3.490ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	8.284m	3.516ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.420m	5.415ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	13.158m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	11.420m	5.415ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.420m	5.415ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	11.420m	5.415ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	11.420m	5.415ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	16.213m	5.795ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.175m	8.037ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.279m	5.561ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.055m	5.631ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.055m	5.631ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.032m	2.805ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.746m	2.939ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.864m	2.840ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.338m	6.005ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	16.757m	5.678ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	17.462m	5.596ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.308m	4.242ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	8.284m	3.516ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	8.915m	5.014ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.457m	4.921ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.054m	5.074ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.278h	18.085ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.055m	2.798ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.384m	2.987ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.463m	3.674ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	8.284m	3.516ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.805m	13.747ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.769m	3.046ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.246m	2.795ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	6.366m	3.264ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.431m	5.164ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	32.499m	16.067ms	5	5	100.00
		chip_tap_straps_rma	25.289m	12.388ms	5	5	100.00
		chip_tap_straps_prod	32.725m	18.770ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.309m	2.576ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.805m	13.747ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.805m	13.747ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.805m	13.747ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.489m	4.620ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	11.420m	5.415ms	3	3	100.00
		chip_sw_flash_rma_unlocked	13.158m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.856m	4.050ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.499m	9.083ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.942m	9.266ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	25.448m	7.617ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.805m	13.747ms	15	15	100.00
		chip_sw_keymgr_key_derivation	8.284m	3.516ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.256m	8.880ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	10.816m	10.021ms	0	3	0.00
		chip_prim_tl_access	5.175m	8.037ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.029m	9.426ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.872m	4.141ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.014m	4.306ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.900m	3.915ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.292m	4.812ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.131m	4.001ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.261m	4.523ms	3	3	100.00
		chip_tap_straps_dev	32.499m	16.067ms	5	5	100.00
		chip_tap_straps_rma	25.289m	12.388ms	5	5	100.00
		chip_tap_straps_prod	32.725m	18.770ms	5	5	100.00
		chip_rv_dm_lc_disabled	12.954m	18.902ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.567m	3.521ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.260m	2.663ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.196m	3.555ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.865m	3.161ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	42.746m	29.235ms	3	3	100.00
		chip_rv_dm_lc_disabled	12.954m	18.902ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.745h	49.658ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.749h	49.816ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	19.871m	9.639ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.566h	49.751ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	42.746m	29.235ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.867m	2.715ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.898m	2.448ms	3	3	100.00
		rom_volatile_raw_unlock	1.925m	1.795ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.805m	13.747ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	39.633m	22.769ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.359m	3.295ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.284m	3.516ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.902m	5.491ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.691m	3.370ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	39.633m	22.769ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.359m	3.295ms	3	3	100.00
		chip_sw_keymgr_key_derivation	8.284m	3.516ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.902m	5.491ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.691m	3.370ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.805m	13.747ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.874m	14.776ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.309m	2.576ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.856m	4.050ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	25.499m	9.083ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.942m	9.266ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	25.448m	7.617ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.805m	13.747ms	15	15	100.00
		chip_prim_tl_access	5.175m	8.037ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.175m	8.037ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.485m	6.716ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	11.804m	9.060ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.843m	5.774ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	14.835m	10.180ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.421m	5.988ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.088m	9.777ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	29.235m	16.765ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	13.361m	6.982ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	25.583m	9.446ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.625m	4.966ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.485m	6.716ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.047m	4.704ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	54.462m	38.883ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.329m	7.085ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	8.487m	4.316ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	46.355m	25.972ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.682m	8.604ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	31.784m	13.076ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	51.285m	23.401ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.670m	3.537ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	16.213m	5.795ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.256m	8.880ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.256m	8.880ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	31.784m	13.076ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	46.355m	25.972ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	10.625m	4.966ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.087m	5.714ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.673m	5.144ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	12.630m	6.125ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.653m	3.604ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	35.808m	11.840ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.474m	2.738ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	16.213m	5.795ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	29.265m	8.398ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	23.116m	6.734ms	3	3	100.00
		chip_plic_all_irqs_10	11.044m	4.027ms	3	3	100.00
		chip_plic_all_irqs_20	16.792m	4.244ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.097m	2.511ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.238m	3.171ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.857m	9.353ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	16.751m	7.766ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.192m	5.065ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.601m	3.594ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.332m	3.182ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.902m	5.491ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.706m	5.461ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	12.749m	8.390ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	15.783m	8.431ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.816m	10.021ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	16.213m	5.795ms	99	100	99.00
		chip_sw_data_integrity_escalation	15.207m	5.553ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	5.067m	3.020ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	6.098m	2.965ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	9.553m	3.176ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	11.155m	3.329ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	35.023m	7.587ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.860h	30.923ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	48.775m	11.963ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.368m	3.059ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.431m	5.164ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	16.213m	5.795ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.000m	3.159ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	35.808m	11.840ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	7.978m	4.685ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.325m	4.434ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	29.253m	12.750ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	36.028m	9.175ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	29.265m	8.398ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.606h	255.102ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	52.137m	20.280ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.330m	13.176ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.673m	5.144ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.131m	5.481ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.246m	5.302ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	25.289m	12.388ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.954m	18.902ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2583	2657	97.21
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.606m	3.555ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.361m	5.933ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.759m	1.818ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.695m	2.291ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.852m	2.657ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.056h	48.873ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.419h	40.282ms	0	1	0.00
		rom_e2e_jtag_inject_rma	52.925m	41.356ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	41.850m	9.514ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.802m	3.730ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.765m	2.941ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	21.536m	5.200ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	43.448m	9.931ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.884m	3.302ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.893m	5.620ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.370m	3.096ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.542m	5.635ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.763m	4.668ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	8.157m	4.697ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	31.784m	13.076ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	16.213m	5.795ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	18.317m	5.778ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.216h	18.859ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.759m	1.818ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.695m	2.291ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.852m	2.657ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.395m	4.582ms	3	3	100.00
V3		TOTAL			32	48	66.67
	Unmapped tests	chip_sival_flash_info_access	6.739m	3.622ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	15.438m	5.946ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.054h	17.236ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	20.194m	5.380ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.501m	4.384ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.899m	5.943ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.675m	2.582ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	5.355m	2.862ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2844	2958	96.15

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	17	89.47
V2	290	276	250	86.21
V2S	1	1	1	100.00
V3	91	22	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.22	95.37	94.53	95.15	--	95.35	97.38	99.53

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.66554934101701167226871461398390405247952146290407882204689921914451543999910
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:30:06) Loading:
  (15:30:06) Loading:
  (15:30:06) Loading: 4 packages loaded
  (15:30:06) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:30:06) WARNING: Target pattern parsing failed.
  (15:30:06) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:30:06) INFO: Elapsed time: 22.470s
  (15:30:06) INFO: 0 processes.
  (15:30:06) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.7921175054369761804620678137118245117167559500343717612385767328031154473039
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:42:09) Loading:
  (15:42:10) Loading:
  (15:42:10) Loading: 4 packages loaded
  (15:42:10) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:42:10) WARNING: Target pattern parsing failed.
  (15:42:10) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:42:10) INFO: Elapsed time: 18.038s
  (15:42:10) INFO: 0 processes.
  (15:42:10) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.60078721775948169881653819153295243231358121088507341178692847124167514516775
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:30:10) Loading:
  (15:30:11) Loading:
  (15:30:11) Loading: 4 packages loaded
  (15:30:11) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:11) WARNING: Target pattern parsing failed.
  (15:30:11) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:11) INFO: Elapsed time: 18.901s
  (15:30:11) INFO: 0 processes.
  (15:30:11) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.32225518218089677435727737613176414426941895194655188320543882555058068423336
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:43:22) Loading:
  (15:43:23) Loading:
  (15:43:23) Loading: 4 packages loaded
  (15:43:23) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:43:23) WARNING: Target pattern parsing failed.
  (15:43:23) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:43:23) INFO: Elapsed time: 17.637s
  (15:43:23) INFO: 0 processes.
  (15:43:23) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.32859725963785900153243189612049375788628768548896459745123097659480529309143
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:30:12) Loading:
  (15:30:13) Loading:
  (15:30:13) Loading: 4 packages loaded
  (15:30:13) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:13) WARNING: Target pattern parsing failed.
  (15:30:13) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:13) INFO: Elapsed time: 24.410s
  (15:30:13) INFO: 0 processes.
  (15:30:13) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.34163665128561569927763008333879059084467973658259540853941828075212493482726
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:43:29) Loading:
  (15:43:30) Loading:
  (15:43:30) Loading: 4 packages loaded
  (15:43:30) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:43:30) WARNING: Target pattern parsing failed.
  (15:43:30) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:43:30) INFO: Elapsed time: 17.436s
  (15:43:30) INFO: 0 processes.
  (15:43:30) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.63889755226545165535051121006354019800548580390110245707735499552968277448418
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:30:16) Loading:
  (15:30:17) Loading:
  (15:30:17) Loading: 4 packages loaded
  (15:30:17) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:17) WARNING: Target pattern parsing failed.
  (15:30:17) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:30:17) INFO: Elapsed time: 21.411s
  (15:30:17) INFO: 0 processes.
  (15:30:17) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.102404348305391961398445155606452668717157573086702884525251148322317716940265
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:43:28) Loading:
  (15:43:29) Loading:
  (15:43:29) Loading: 4 packages loaded
  (15:43:29) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:43:29) WARNING: Target pattern parsing failed.
  (15:43:29) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:43:29) INFO: Elapsed time: 17.051s
  (15:43:29) INFO: 0 processes.
  (15:43:29) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.15374947646543133784449745499168225678410452523469796237121301734557684661123
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:30:20) Loading:
  (15:30:21) Loading:
  (15:30:21) Loading: 4 packages loaded
  (15:30:21) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:30:21) WARNING: Target pattern parsing failed.
  (15:30:21) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:30:21) INFO: Elapsed time: 21.006s
  (15:30:21) INFO: 0 processes.
  (15:30:21) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.28907582485233018779646490411471304266477774446101205852662386391389208599307
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:43:32) Loading:
  (15:43:33) Loading:
  (15:43:33) Loading: 4 packages loaded
  (15:43:33) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:43:33) WARNING: Target pattern parsing failed.
  (15:43:33) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:43:33) INFO: Elapsed time: 16.698s
  (15:43:33) INFO: 0 processes.
  (15:43:33) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:827) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.36919727861644263167159462380993398295162251174562132413800449719296615171755
    Line 395, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2475.687577 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2475.687577 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.76253084872462048552292827250518361785824015040745395633723263224330660236882
    Line 430, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2501.990206 us: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2501.990206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.85859636039174024545565427345724293717936422333911892300126492350858158549696
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:d3707e87-df99-4be7-a3f3-104ee465b2f0
```
  - 1.chip_sw_uart_tx_rx_bootstrap.72590778407475874720395723134024214052923442555431388858746347026168959307642
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:988fb945-6ca8-48f4-8d0b-43bec59cf01f
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.35611293268002223383899211357927847886405164072298410603744169542384580375771
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:1c3530a3-06b1-480a-a4b0-560dc44c3fdf
```
  - 1.chip_sw_rv_timer_systick_test.41172529248921086101514709560451610926088216889320045630192146756068063044228
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:39dbb2c7-c441-49e5-ae3a-3e253cc0a6b3
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.54701563789398229624052032608808908089454721617346177463158228981228130111007
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:3b4467cb-778a-4260-a810-19f2da738453
```
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.95853826517410659121807038986774041111168917541542057563046734360575215225871
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:5eb39990-9005-4dbc-b75f-e39dd59e527e
```
  - 1.chip_sw_ast_clk_rst_inputs.80327113762923420002559062436471440949920012008289946992824817327087048532569
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:f8d82615-5463-4bf1-8d8c-3b0d2d3e27a7
```
  - ... and 1 more failures.
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.71548199867403783582271290250726768472007958262467621981477835708985610722127
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:6821d474-6db9-483b-a7aa-a954338d607e
```
  - 2.chip_sw_power_virus.26726781848402404697450949519187022837499451264104968003805736311984627726756
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:22c174de-4d7e-4a19-9d4c-9733a5c3d29d
```
- ... and 1 more tests.
UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.87271787294745107220438119864570412032447015701548430180583375733939744643108
    Line 857, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.340001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.25272812478951761397153358357864944838043898900691666523091387601544978761514
    Line 720, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.160001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.108571633548285853383356282958632700524974589923132047289836583481889546875872
    Line 719, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.1891859185184722939762195291074125078667858870318103849983637091041257006911
    Line 720, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:
- Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.
  - 0.chip_sw_csrng_lc_hw_debug_en_test.45456018868521357606384913317417693697994511483611264691644504482506321255935
    Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.220001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_lc_hw_debug_en_test.40874172422137084127739985187753567394044241690820006481129300567338679005355
    Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.360001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:33) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.37184830651875628947930772747995298815705497005272163213017579130731710000598
    Line 905, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.140001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_fuse_en_sw_app_read_test.2097593230917112715034814293628534847906117348009801531200641494542046414840
    Line 721, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.400001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_sram_ctrl_execution_main has 3 failures.
  - 0.chip_sw_sram_ctrl_execution_main.100828639567920188829351338371308515114727271641664549222773784728853454766502
    Line 740, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.700001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.700001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sram_ctrl_execution_main.31287675106368139024958045050426608142120548128365739623473391195042451701122
    Line 708, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.440001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.440001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.70227110406462165433549154431814001270645944227943256704516072988785671789266
    Line 862, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15177.127632 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15177.127632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.31255853425993767397540273785539481669523794625482678446475965526103114210236
    Line 732, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14775.852984 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14775.852984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.34743377749252181543619368291993780982796035321857542559808968436667238176934
    Line 833, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 5773.771704 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 5773.771704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.99880211539128874446421199271261650526397385023694505062405300528876913801951
    Line 722, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 5671.949388 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 5671.949388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.84572697166798788228322950565580303259249209408707375396428483161745218641059
    Line 940, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 9777.113568 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 9777.113568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2416493841724948158955136594589201286894780024127677056436031658020055207294
    Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 10214.337902 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 10214.337902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
- Test chip_sw_pwrmgr_random_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.8870628066294235942020329489591105366329015901976917321408419064493087096207
    Line 837, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 9059.681204 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 9059.681204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.102030421471380912616195946214722238922068764880095378355471174530165935282646
    Line 742, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 7624.987340 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:248)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 7624.987340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.73988729794267853828628861948994802541445613003533993741345631676279353455192
    Line 716, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 1817.756000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1817.756000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.19271367638673135642266689091471283802381769019099546762121792835531641268629
    Line 738, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2290.740500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2290.740500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.1074132308199144606123951392386719681123822835476986515903662499728653960494
    Line 721, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2657.117500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2657.117500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.57304811350072455261836564173057074820431513461236523996533875508166255586337
    Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 48872.972972 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 48872.972972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.108796169710395647154777951947552230394802433580032651099463267732861876272894
    Line 743, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 40281.651364 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40281.651364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.36293681368155810748362485088961088032035339636845978617960229426497613635975
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 41355.595020 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 41355.595020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns * has 3 failures:
- Test rom_e2e_self_hash has 3 failures.
  - 0.rom_e2e_self_hash.81025361166149335463689779641886011648735629319649599223188872884754044393974
    Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 9514.402070 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 9514.402070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_e2e_self_hash.82849452441315305109179571428754072766085866674484526340872210959872198684993
    Line 717, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log
```
  UVM_ERROR @ 8759.676808 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(w/device/lib/testing/test_framework/ottf_isrs.c:159)] DIF-fail: dif_rv_plic_irq_claim(&ottf_plic, kPlicTarget, &plic_irq_id) returns 536901151
  UVM_INFO @ 8759.676808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 74.chip_sw_alert_handler_lpg_sleep_mode_alerts.52461002465897723768386518321652214616267003516136011418984737547599857786392
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4434.383070 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a36 MTVAL=40600800
  UVM_INFO @ 4434.383070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 77.chip_sw_alert_handler_lpg_sleep_mode_alerts.6758937726081302126621285657636922230635958716515535811272977894523280004820
    Line 754, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3996.267760 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a36 MTVAL=40600800
  UVM_INFO @ 3996.267760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 1.chip_sw_power_virus.85910824577353663381661870931049035130080719580786305249674910988165519809203
    Line 928, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5932.823855 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5932.823855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 15.chip_sw_all_escalation_resets.84536224102750945038845569670755463900074492138519021292576258652040463889407
    Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/15.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2640.295396 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2640.295396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```