Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.24			90.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	90.12			90.12
tb.dut.top_earlgrey.u_i2c1	90.18			90.18
tb.dut.top_earlgrey.u_i2c2	90.18			90.18

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12			90.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12			90.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.02	90.65		91.41			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.18			90.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.18			90.18

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.02	90.65		91.41			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.18			90.18

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.18			90.18

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.02	90.65		91.41			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	48	40	83.33
Total Bits	328	296	90.24
Total Bits 0->1	164	148	90.24
Total Bits 1->0	164	148	90.24

Ports	48	40	83.33
Port Bits	328	296	90.24
Port Bits 0->1	164	148	90.24
Port Bits 1->0	164	148	90.24

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T70,*T52,*T44	Yes	T70,T52,T44	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	INPUT
tl_o.a_ready	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T119,*T123,T124	Yes	T51,T238,T243	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T51,*T238,*T243	Yes	T51,T238,T243	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T119,T123,T124	Yes	T51,T238,T243	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T51,*T238,*T243	Yes	T51,T238,T243	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T325,T326,T123	Yes	T325,T326,T123	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T327	Yes	T78,T79,T327	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T327	Yes	T78,T79,T327	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T325,T326,T123	Yes	T325,T326,T123	OUTPUT
cio_scl_i	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T51,T238,T245	Yes	T51,T238,T245	OUTPUT
cio_sda_i	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T51,T238,T245	Yes	T51,T238,T245	OUTPUT
intr_rx_threshold_o	Yes	Yes	T51,T238,T245	Yes	T51,T238,T245	OUTPUT
intr_acq_threshold_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_rx_overflow_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_nak_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_scl_interference_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_sda_interference_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_sda_unstable_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_cmd_complete_o	Yes	Yes	T51,T238,T243	Yes	T51,T238,T243	OUTPUT
intr_tx_stretch_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_tx_threshold_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_acq_full_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_unexp_stop_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_host_timeout_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	48	40	83.33
Total Bits	324	292	90.12
Total Bits 0->1	162	146	90.12
Total Bits 1->0	162	146	90.12

Ports	48	40	83.33
Port Bits	324	292	90.12
Port Bits 0->1	162	146	90.12
Port Bits 1->0	162	146	90.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T238,T119,T239	Yes	T238,T119,T239	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T238,T119,T239	Yes	T238,T119,T239	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T70,*T52,*T44	Yes	T70,T52,T44	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T238,T119,T239	Yes	T238,T119,T239	INPUT
tl_o.a_ready	Yes	Yes	T238,T119,T239	Yes	T238,T119,T239	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T238,T239,T310	Yes	T238,T239,T310	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T238,T119,T239	Yes	T238,T119,T239	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T119,*T123,T124	Yes	T238,T119,T239	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T238,T119,T239	Yes	T238,T119,T239	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T238,*T119,*T239	Yes	T238,T119,T239	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T119,T123,T124	Yes	T238,T119,T239	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T238,*T119,*T239	Yes	T238,T119,T239	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T238,T119,T239	Yes	T238,T119,T239	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T326,T123,T328	Yes	T326,T123,T328	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T327	Yes	T78,T79,T327	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T327	Yes	T78,T79,T327	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T326,T123,T328	Yes	T326,T123,T328	OUTPUT
cio_scl_i	Yes	Yes	T238,T239,T310	Yes	T238,T239,T310	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T238,T310,T329	Yes	T238,T310,T329	OUTPUT
cio_sda_i	Yes	Yes	T238,T239,T310	Yes	T238,T239,T310	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T238,T239,T310	Yes	T238,T239,T310	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T238,T310,T213	Yes	T238,T310,T213	OUTPUT
intr_rx_threshold_o	Yes	Yes	T238,T310,T213	Yes	T238,T310,T213	OUTPUT
intr_acq_threshold_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_rx_overflow_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_nak_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_scl_interference_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_sda_interference_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_sda_unstable_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_cmd_complete_o	Yes	Yes	T238,T239,T310	Yes	T238,T239,T310	OUTPUT
intr_tx_stretch_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_tx_threshold_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_acq_full_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_unexp_stop_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_host_timeout_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	48	40	83.33
Total Bits	326	294	90.18
Total Bits 0->1	163	147	90.18
Total Bits 1->0	163	147	90.18

Ports	48	40	83.33
Port Bits	326	294	90.18
Port Bits 0->1	163	147	90.18
Port Bits 1->0	163	147	90.18

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T243,T119,T124	Yes	T243,T119,T124	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T243,T119,T124	Yes	T243,T119,T124	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T70,*T52,*T44	Yes	T70,T52,T44	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T243,T119,T123	Yes	T243,T119,T123	INPUT
tl_o.a_ready	Yes	Yes	T243,T119,T123	Yes	T243,T119,T123	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T243,T119,T124	Yes	T243,T119,T124	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T243,T119,T123	Yes	T243,T119,T123	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T119,*T123,T124	Yes	T243,T119,T123	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T243,T119,T123	Yes	T243,T119,T123	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T243,*T119,*T123	Yes	T243,T119,T123	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T119,T123,T124	Yes	T243,T119,T123	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T243,*T119,*T124	Yes	T243,T119,T124	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T243,T119,T123	Yes	T243,T119,T123	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T325,T123,T78	Yes	T325,T123,T78	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T327	Yes	T78,T79,T327	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T327	Yes	T78,T79,T327	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T325,T123,T78	Yes	T325,T123,T78	OUTPUT
cio_scl_i	Yes	Yes	T243,T245,T330	Yes	T243,T245,T330	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T245,T330,T331	Yes	T245,T330,T331	OUTPUT
cio_sda_i	Yes	Yes	T243,T245,T330	Yes	T243,T245,T330	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T243,T245,T330	Yes	T243,T245,T330	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T245,T330,T213	Yes	T245,T330,T213	OUTPUT
intr_rx_threshold_o	Yes	Yes	T245,T330,T213	Yes	T245,T330,T213	OUTPUT
intr_acq_threshold_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_rx_overflow_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_nak_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_scl_interference_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_sda_interference_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_sda_unstable_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_cmd_complete_o	Yes	Yes	T243,T245,T330	Yes	T243,T245,T330	OUTPUT
intr_tx_stretch_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_tx_threshold_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_acq_full_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_unexp_stop_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_host_timeout_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	48	40	83.33
Total Bits	326	294	90.18
Total Bits 0->1	163	147	90.18
Total Bits 1->0	163	147	90.18

Ports	48	40	83.33
Port Bits	326	294	90.18
Port Bits 0->1	163	147	90.18
Port Bits 1->0	163	147	90.18

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T20	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T51,T119,T124	Yes	T51,T119,T124	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T51,T119,T124	Yes	T51,T119,T124	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T69,*T70,*T76	Yes	T69,T70,T76	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T30,T31,T32	Yes	T30,T31,T32	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T70,*T52,*T44	Yes	T70,T52,T44	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T51,T119,T123	Yes	T51,T119,T123	INPUT
tl_o.a_ready	Yes	Yes	T51,T119,T123	Yes	T51,T119,T123	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T51,T311,T213	Yes	T51,T311,T213	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T51,T119,T123	Yes	T51,T119,T123	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T119,*T123,T124	Yes	T51,T119,T123	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T51,T119,T123	Yes	T51,T119,T123	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T51,*T119,*T123	Yes	T51,T119,T123	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T119,T123,T124	Yes	T51,T119,T123	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T51,*T119,*T124	Yes	T51,T119,T124	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T51,T119,T123	Yes	T51,T119,T123	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T123,T78,T54	Yes	T123,T78,T54	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T327	Yes	T78,T79,T327	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T327	Yes	T78,T79,T327	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T123,T78,T54	Yes	T123,T78,T54	OUTPUT
cio_scl_i	Yes	Yes	T51,T311,T332	Yes	T51,T311,T332	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T51,T311,T332	Yes	T51,T311,T332	OUTPUT
cio_sda_i	Yes	Yes	T51,T311,T332	Yes	T51,T311,T332	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T51,T311,T332	Yes	T51,T311,T332	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T51,T311,T213	Yes	T51,T311,T213	OUTPUT
intr_rx_threshold_o	Yes	Yes	T51,T311,T213	Yes	T51,T311,T213	OUTPUT
intr_acq_threshold_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_rx_overflow_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_nak_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_scl_interference_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_sda_interference_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_sda_unstable_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_cmd_complete_o	Yes	Yes	T51,T311,T213	Yes	T51,T311,T213	OUTPUT
intr_tx_stretch_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_tx_threshold_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_acq_full_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_unexp_stop_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT
intr_host_timeout_o	Yes	Yes	T213,T214,T215	Yes	T213,T214,T215	OUTPUT

*Tests covering at least one bit in the range