Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.30 94.30

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main 93.98 93.98
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 94.89 94.89


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.98 93.98


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.98 93.98


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.02 90.65 91.41 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.89 94.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.89 94.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.02 90.65 91.41 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 64 46 71.88
Total Bits 1158 1092 94.30
Total Bits 0->1 579 546 94.30
Total Bits 1->0 579 546 94.30

Ports 64 46 71.88
Port Bits 1158 1092 94.30
Port Bits 0->1 579 546 94.30
Port Bits 1->0 579 546 94.30

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T20 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T3,T4,T20 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T3,T4,T20 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T6,*T38,*T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T69,*T70,*T76 Yes T69,T70,T76 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T70,*T52,*T44 Yes T70,T52,T44 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_o.a_ready Yes Yes T6,T38,T40 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T144,T146,T147 Yes T144,T146,T147 OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T6,T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes *T6,*T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T6,T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T53,*T144,*T39 Yes T53,T40,T144 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T6,T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T144,*T146,*T147 Yes T144,T145,T146 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T6,T38,T40 Yes T6,T38,T40 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T141,T78,T54 Yes T141,T78,T54 INPUT
alert_rx_i[0].ping_n Yes Yes T141,T78,T79 Yes T141,T78,T79 INPUT
alert_rx_i[0].ping_p Yes Yes T141,T78,T79 Yes T141,T78,T79 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T141,T78,T54 Yes T141,T78,T54 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T33,T62,T63 Yes T33,T62,T63 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T3,T4,T20 Yes T2,T3,T4 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T3,T4,T20 INPUT
sram_otp_key_o.req Yes Yes T6,T38,T40 Yes T6,T38,T40 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T3,T20,T33 Yes T2,T3,T50 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T3,T4,T50 Yes T2,T3,T4 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T50,T81 Yes T4,T81,T33 INPUT
sram_otp_key_i.ack Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 60 40 66.67
Total Bits 1130 1062 93.98
Total Bits 0->1 565 531 93.98
Total Bits 1->0 565 531 93.98

Ports 60 40 66.67
Port Bits 1130 1062 93.98
Port Bits 0->1 565 531 93.98
Port Bits 1->0 565 531 93.98

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T4,T20 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T3,T4,T20 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[16:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[5] No No No INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[0] No No No INPUT
ram_tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T3,T4,T20 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[5] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T3,T4,T20 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_user.cmd_intg[0] Yes Yes *T6,*T38,*T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_user.cmd_intg[1] No No No INPUT
regs_tl_i.a_user.cmd_intg[6:2] Yes Yes T144,T145,T146 Yes T144,T145,T146 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T6,*T38,*T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes *T6,*T38,*T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_address[17:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T6,*T38,*T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T6,*T38,*T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[1:0] Yes Yes *T53,*T144,*T145 Yes T53,T144,T145 INPUT
regs_tl_i.a_source[5:2] No No No INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[0] No No No INPUT
regs_tl_i.a_size[1] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[1:0] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T144,T145,T146 Yes T144,T145,T146 INPUT
regs_tl_i.a_valid Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_o.a_ready Yes Yes T6,T38,T40 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[3:0] Yes Yes *T53,*T144,*T146 Yes T53,T144,T146 OUTPUT
regs_tl_o.d_user.data_intg[4] No No No OUTPUT
regs_tl_o.d_user.data_intg[5] Yes Yes *T144,*T146,*T147 Yes T144,T146,T147 OUTPUT
regs_tl_o.d_user.data_intg[6] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T6,T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes *T6,*T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T6,T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T53,*T144,*T146 Yes T53,T144,T145 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T6,T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T144,*T146,*T147 Yes T144,T145,T146 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T6,T38,T40 Yes T6,T38,T40 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T78,T54,T79 Yes T78,T54,T79 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T78,T54,T79 Yes T78,T54,T79 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T33,T62,T63 Yes T33,T62,T63 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T3,T4,T20 Yes T2,T3,T4 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T3,T4,T20 INPUT
sram_otp_key_o.req Yes Yes T6,T38,T40 Yes T6,T38,T40 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T3,T20,T33 Yes T2,T3,T50 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T3,T4,T50 Yes T2,T3,T4 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T50,T81 Yes T4,T81,T33 INPUT
sram_otp_key_i.ack Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 58 43 74.14
Total Bits 1096 1040 94.89
Total Bits 0->1 548 520 94.89
Total Bits 1->0 548 520 94.89

Ports 58 43 74.14
Port Bits 1096 1040 94.89
Port Bits 0->1 548 520 94.89
Port Bits 1->0 548 520 94.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T20,T33 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T4,T20,T33 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T3,T20,T33 Yes T3,T20,T33 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[2:1] No No No INPUT
ram_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[1:0] No No No INPUT
ram_tl_i.a_address[11:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T69,*T70,*T76 Yes T69,T70,T76 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[0] Yes Yes *T70,*T52,*T44 Yes T70,T52,T44 INPUT
ram_tl_i.a_opcode[1] No No No INPUT
ram_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T4,T20,T33 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T3,T20,T33 Yes T3,T20,T33 OUTPUT
ram_tl_o.d_user.rsp_intg[2:0] Yes Yes T3,T4,T20 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[3] No No No OUTPUT
ram_tl_o.d_user.rsp_intg[5:4] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
ram_tl_o.d_user.rsp_intg[6] No No No OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T3,T20,T33 Yes T3,T20,T33 OUTPUT
ram_tl_o.d_sink No No No OUTPUT
ram_tl_o.d_source[1:0] Yes Yes *T70,*T107,*T108 Yes T70,T107,T108 OUTPUT
ram_tl_o.d_source[5:2] No No No OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[0] No No No OUTPUT
ram_tl_o.d_size[1] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[2:1] No No No INPUT
regs_tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[1:0] No No No INPUT
regs_tl_i.a_address[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[19:5] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T69,*T70,*T76 Yes T69,T70,T76 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T30,T31,T32 Yes T30,T31,T32 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[0] Yes Yes *T70,*T52,*T44 Yes T70,T52,T44 INPUT
regs_tl_i.a_opcode[1] No No No INPUT
regs_tl_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_valid Yes Yes T6,T38,T40 Yes T6,T38,T40 INPUT
regs_tl_o.a_ready Yes Yes T6,T38,T40 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_error No No No OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T144,T146,T147 Yes T144,T146,T147 OUTPUT
regs_tl_o.d_user.rsp_intg[1:0] Yes Yes T6,T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
regs_tl_o.d_user.rsp_intg[5:4] Yes Yes *T6,*T38,*T39 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T6,T38,T144 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_sink No No No OUTPUT
regs_tl_o.d_source[1:0] Yes Yes *T53,*T144,*T39 Yes T53,T40,T144 OUTPUT
regs_tl_o.d_source[5:2] No No No OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[0] No No No OUTPUT
regs_tl_o.d_size[1] Yes Yes T6,T38,T39 Yes T6,T38,T40 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T144,*T146,*T147 Yes T144,T145,T146 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T6,T38,T40 Yes T6,T38,T40 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T141,T78,T54 Yes T141,T78,T54 INPUT
alert_rx_i[0].ping_n Yes Yes T141,T78,T79 Yes T141,T79,T80 INPUT
alert_rx_i[0].ping_p Yes Yes T141,T79,T80 Yes T141,T78,T79 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T141,T78,T54 Yes T141,T78,T54 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T33,T62,T63 Yes T33,T62,T63 INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T144,T146,T147 Yes T144,T146,T147 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T3,T20,T33 Yes T2,T3,T50 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T3,T4,T50 Yes T2,T3,T4 INPUT
sram_otp_key_i.key[127:0] Yes Yes T4,T50,T81 Yes T4,T81,T33 INPUT
sram_otp_key_i.ack Yes Yes T144,T146,T147 Yes T144,T146,T147 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%